3
Pin Descr iption
PIN TYPE SYMBOL DESCRIPTION
1V
CC †Positive Voltage Supply
2 NC No Connec tion
3 GND Ground
4 I RRD A high l evel on REC EIVER RE GISTER DISAB LE
fo rces t he rece i v e r ho l ding ou t-pu t s RBR 1-RBR8
to high i m pedance stat e.
5 O RBR8 The contents of the RE CEI V ER BUFFER REG IS-
TER appear o n t he s e three-state ou t puts . Word f or-
mats less than 8 characters are right justified to
RBR1.
6 O RBR7 See Pin 5-RBR8
7 O RBR6 See Pin 5-RBR8
8 O RBR5 See Pin 5-RBR8
9 O RBR4 See Pin 5-RBR8
10 O RBR3 See Pin 5-RBR8
11 O RBR2 See Pin 5-RBR8
12 O RBR1 See Pin 5-RBR8
13 O PE A high level on PA RITY ERROR in dicates received
parity does n ot m atch parity p rogra mmed by c ontrol
bits. W hen parit y is i nh ibi ted thi s out put i s l ow.
14 O FE A high level on FRAMING ERROR indicates the
first stop bit was invalid.
15 O OE A high level on OVERRUN ERROR indicates the
data rec eive d flag was not cle are d befo re the las t
character was transferred to the receiver buffer
register.
16 I SFD A high leve l on STATUS FLAGS DI SABLE forc es
the outputs PE, FE, OE, DR, TBRE to a high im-
pedance state.
17 I RRC The Rece i ver regist er clock is 16X the rece iver
data rate.
18 I DRR A low level on DATA RECEIVED RESET clears
the dat a received out put DR to a lo w l evel .
19 O DR A high level on DATA RECE IVED indicates a
character has been received and transferred to
the receiver buffer register.
20 I RRI Serial data on RECEIVER REGISTER INPUT is
cl ock ed i nto the receiver regist er.
21 I MR A high level on MASTER RESET clears PE, FE,
OE and DR to a low level and sets the transmitter
register empty (TRE) to a high level 18 clock cycles
after MR falling edge. MR does not clear the receiv-
er buffer register. This input must be pulsed at least
once after power up. The HD-6402 must be master
reset after power up. The reset pulse should meet
VIH and tMR. Wait 18 cl ock cycles a fter the fal li n g
edge of MR before beginning operation.
22 O TBRE A high level on TRANSMITTER BUFFER REGIS-
TER EMPTY indicates the transmitter buffer register
has tran s ferred it s dat a t o the tran s mit ter regis ter
and is ready for new data .
23 I TBRL A low level on TRANSMIT TER BUFFER REGIS-
TER LOAD transfers data from inputs TBR1-
TBR8 into the transmitter buffer register. A low to
hig h transit i o n on T BRL initiates data transfer to
the transmitter register. If busy, transfer is auto-
matically delayed so that the two characters are
trans m i tt ed end to en d.
24 O TRE A high leve l on TRAN SMITTER REGIS TER E MP-
TY indicates completed transmission of a charac-
ter incl udi ng st op bi t s.
25 O TRO Character data, start data and stop bits appear se-
rially at the TRANSMITTER REGISTER OUTPUT.
26 I TRB1 Character data is loaded into the TRANSMITTER
BUFFER REGISTER via i n puts T BR 1-T BR 8. For
character formats less than 8 bits the TBR8, 7 and
6 in puts are ig nored corr esponding to the i r pro-
gram m ed word le ngt h.
27 I TBR2 See Pin 26-TBR1.
28 I TBR3 See Pin 26-TBR1.
29 I TBR4 See Pin 26-TBR1.
30 I TBR5 See Pin 26-TBR1.
31 I TBR6 See Pin 26-TBR1.
32 I TBR7 See Pin 26-TBR1.
33 I TBR8 See Pin 26-TBR1.
34 I CRL A high level on CONTROL REGISTER LOAD
loads the control register with the control word. The
control word is latched on the falling edge of CRL.
CRL may be tied high.
35 I PI A high level on PARITY INHIBIT inhibits parity gen-
eration, parity checking and forces PE output low.
36 I SBS A high level on STOP BIT SELECT selects 1.5
stop bits for 5 character format and 2 stop bits for
other lengths.
37 I CLS2 T hese inputs pr ogram the CH ARACTER
LENGTH SELECTED (CLS1 low CLS2 low 5 bits)
(CLS 1 hi gh CLS2 low 6 bi t s) (CLS1 lo w CLS 2
hi gh 7 bit s) (C LS1 high CLS2 hi gh 8 bits.)
38 I CLS1 See Pin 37-CLS2.
39 I EPE When PI is low, a high level on EVEN PARITY
ENAB LE gene rates and checks ev en parity . A low
level selects odd parity.
40 I TRC The TRANSMITTER REGISTER CLOCK is 16X
the transmit data rate.
†A 0. 1 µF decoupling capacitor from the VCC pin to the G ND is r ec-
ommended.
PIN TYPE SYMBOL DESCRIPTION
HD-6402