SMCP-67206HV-15SCC - Atmel Corporation

Rev. 4143J–AERO–04/07

Features

•

First-in First-out Dual Port Memory

•

16384 bits x 9 Organization

•

Fast Flag and Access Times: 15, 30 ns

•

Wide Temperature Range: - 55°C to + 125°C

•

Fully Expandable by Word Width or Depth

•

Asynchronous Read/Write Operations

•

Empty, Full and Half Flags in Single Device Mode

•

Retransmit Capability

•

Bi-directional Applications

•

Battery Back-up Operation: 2V Data Retention

•

TTL Compatible

•

Single 5V ± 10% Power Supply

•

No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm

•

Tested up to a Total Dose of 30 krads (Si) according to MIL STD 883 Method 1019

•

Quality grades: QML Q and V with SMD 5962-93177 and ESCC with specification

9301/048

Description

The M67206H implements a first-in first-out algorithm, featuring asynchronous

read/write operations. The FULL and EMPTY flags prevent data overflow and under-

flow. The Expansion logic allows unlimited expansion in word size and depth with no

timing penalties. Twin address pointers automatically generate internal read and write

addresses, and no external address information is required. Address pointers are

automatically incremented with the write pin and read pin. The 9 bits wide data are

used in data communications applications where a parity bit for error checking is nec-

essary. The Retransmit pin resets the Read pointer to zero without affecting the write

pointer. This is very useful for retransmitting data when an error is detected in the

system.

Using an array of eight transistors (8T) memory cell, the M67206H combines an

extremely low standby supply current (typ = 0.1 µA) with a fast access time at 15 ns

over the full temperature range. All versions offer battery backup data retention capa-

bility with a typical power consumption at less than 2 µW.

The M67206H is processed according to the methods of the latest revision of the MIL

PRF 38535 (Q and V) or ESCC 9000.

Rad. Tolerant

High Speed

16 Kb x 9

Parallel FIFO

M67206H

4143J–AERO–04/07

Block Diagram

Pin Configuration

DIL ceramic 28-pin 300 mils

FP 28-pin 400 mils

M67206H

4143J–AERO–04/07

Pin Description

Data In (I

- I

)

Data inputs for 9-bit data

Reset (RS)

Reset occurs whenever the Reset (RS) input is taken to a low state. Reset returns both

internal read and write pointers to the first location. A reset is required after power-up

before a write operation can be enabled. Both the Read Enable (R) and Write Enable

(W) inputs must be in the high state during the period shown in Figure 1 (i.e. t

RSS

before

the rising edge of RS) and should not change until t

RSR

after the rising edge of RS. The

Half-Full Flag (HF) will be reset to high After Reset (RS)

Figure 1. Reset

Notes: 1. EF, FF and HF may change status during reset, but flags will be valid at t

RSC

2. W and R = VIH around the rising edge of RS.

Names Description

I0-8 Inputs

Q0-8 Outputs

W Write Enable

R Read Enable

RS Reset

EF Empty Flag

FF Full Flag

XO/HF Expansion Out/Half-Full Flag

XI Expansion IN

FL/RT First Load/Retransmit

VCC Power Supply

GND Ground

M67206H

4143J–AERO–04/07

Write Enable (W)

A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

Data set-up and hold times must be maintained in the rise time of the leading edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) will be set to low and remain in this state until the difference

between the write and read pointers is less than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high after TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked from W, so that external changes to W will have no effect on the full FIFO stack.

Read Enable (R)

A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empty Flag (EF) is not set. The data is accessed on a first-in/first-out basis, not includ-

ing any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0

- Q8) will return to a high impedance state until the next Read operation. When all the

data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the

“final” read cycle, but inhibiting further read operations while the data outputs remain in

a high impedance state. Once a valid write operation has been completed, the Empty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

First Load/Retransmit

(FL/RT)

This pin is a dual-purpose input. In the Depth Expansion Mode, this pin is connected to

ground to indicate that it is the first loaded (see Operating Modes). In the Single Device

Mode, this pin acts as the retransmit input. The Single Device Mode is initiated by con-

necting the Expansion In (XI) to ground.

The M67206H can be set to retransmit data when the Retransmit Enable Control (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

number of writes are equal to or less than the depth of the FIFO has occurred since the

last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (HF), in accordance with the relative locations of the

read and write pointers.

Expansion In (XI)

The XI input is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an

operation in the single device mode. Expansion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Daisy Chain modes.

Full Flag (FF)

The Full Flag (FF) will go low, inhibiting further write operations when the write pointer is

one location less than the read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.

Empty Flag (EF)

The Empty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating that the device is empty.

M67206H

4143J–AERO–04/07

Expansion Out/Half-Full

Flag (XO/HF)

The XO/HF pin is a dual-purpose output. In the single device mode, when Expansion In

(XI) is connected to ground, this output acts as an indication of a half-full memory.

After half the memory is filled and on the falling edge of the next write operation, the

Half-Full Flag (HF) will be set to low and will remain set until the difference between the

write and read pointers is less than or equal to half of the total memory of the device.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion Out (XO) of

the previous device. This output acts as a signal to the next device in the Daisy Chain by

providing a pulse to the next device when the previous device reaches the last memory

location.

Data Output (Q

- Q

)

DATA output for 9-bit wide data. This data is in a high impedance condition whenever

Read (R) is in a high state.

M67206H

4143J–AERO–04/07

Functional Description

Single Device Mode

A single M67206H may be used when the application requirements are for 16384 words

or less. The M67206H is in a Single Device Configuration when the Expansion In (XI) control

input is grounded (see Figure 2). In this mode the Half-Full Flag (HF), which is an active low

output, is shared with Expansion Out (XO).

Figure 2. Block Diagram of Single 16384 bits × 9

Width Expansion Mode

Word width may be increased simply by connecting the corresponding input control sig-

nals of multiple devices. Status flags (EF, FF and HF) can be detected from any device.

Figure 3 demonstrates an 18-bit word width by using two M67206H. Any word width can be

attained by adding additional M67206H.

Figure 3. Block Diagram of 16384 bits x 18 FIFO Memory Used in Width Expansion Mode

Note: Flag detection is accomplished by monitoring the FF, EF and the HF signals on either (any) device used in the width expansion

configuration. Do not connect any output control signals together.

(HALF-FULL FLAG)

WRITE (W) (R) READ

DATAIN

(I) DATAOUT

(Q)

FULL FLAG

RESET

(FF)

(RS)

EMPTY FLAG

RETRANSMIT

(EF)

(RT)

EXPANSION IN (XI)

M67206H

4143J–AERO–04/07

Note: 1. Pointer will increment if flag is high.

Note: 1. XI is connected to XO of previous device.

See Figure 4.

Depth Expansion (Daisy

Chain) Mode

The M67206H can be easily adapted for applications which require more than 16384

words. Figure 4 demonstrates Depth Expansion using three M67206Hs. Any depth can

be achieved by adding an additional M67206H.

The M67206H operates in the Depth Expansion configuration if the following conditions

are met:

1. The first device must be designated by connecting the First Load (FL) control

input to ground.

2. All other devices must have FL in the high state.

3. The Expansion Out (XO) pin of each device must be connected to the Expansion In

(XI) pin of the next device. See Figure 4

4. External logic is needed to generate a composite Full Flag (FF) and Empty Flag

(EF). This requires that all EF’s and all FFs be ORed (i.e. all must be set to generate the

correct composite FF or EF). See Figure 4.

5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in the Depth

Expansion Mode.

Compound Expansion

Module

It is quite simple to apply the two expansion techniques described above together to cre-

ate large FIFO arrays (see Figure 5).

Table 1. Reset and Retransmit

Single Device Configuration/Width Expansion Mode

Mode

Inputs Internal Status Outputs

RS RT XI Read Pointer Write Pointer EF FF HF

Reset

0 X 0

Location Zero Location Zero

0 1 1

Retransmit

1 0 0

Location Zero Unchanged

X X X

Read/Write

1 1 0

Increment

(1)

Increment

(1)

X X X

Table 2. Reset and First Load Truth Table

Depth Expansion/Compound Expansion Mode

Mode

Inputs Internal Status Outputs

RS FL XI Read Pointer Write Pointer EF FF

Reset First Device

0 0 (1)

Location Zero Location Zero

0 1

Reset All Other

Devices

0 1 (1)

Location Zero Location Zero

0 1

Read/Write

1 X (1)

X X

M67206H

4143J–AERO–04/07

Bi-directional Mode

Applications which require data buffering between two systems (each system being

capable of Read and Write operations) can be created by coupling M67206H as shown

in Figure 6. Care must be taken to ensure that the appropriate flag is monitored by each

system (i.e. FF is monitored on the device on which W is in use; EF is monitored on the device

on which R is in use). Both Depth Expansion and Width Expansion may be used in this mode.

Data Flow – Through

Modes

Two types of flow-through modes are permitted: a read flow-through and a write flow-

through mode. In the read flow-through mode (Figure 17) the FIFO stack allows a single

word to be read after one word has been written to an empty FIFO stack. The data is

enabled on the bus at (tWEF + tA) ns after the leading edge of W which is known as the

first write edge and remains on the bus until the R line is raised from low to high, after which the

bus will go into a three-state mode after tRHZ ns. The EF line will show a pulse indicating tem-

porary reset and then will be set. In the interval in which R is low, more words may be written to

the FIFO stack (the subsequent writes after the first write edge will reset the Empty Flag); how-

ever, the same word (written on the first write edge) presented to the output bus as the read

pointer will not be incremented if R is low. On toggling R, the remaining words written to the

FIFO will appear on the output bus in accordance with the read cycle timings.

In the write flow-through mode (Figure 18), the FIFO stack allows a single word of data

to be written immediately after a single word of data has been read from a full FIFO

stack. The R line causes the FF to be reset, but the W line, being low, causes it to be set again

in anticipation of a new data word. The new word is loaded into the FIFO stack on the leading

edge of W. The W line must be toggled when FF is not set in order to write new data into the

FIFO stack and to increment the write pointer.

Figure 4. Block Diagram of 49152 bits × 9 FIFO Memory (Depth Expansion)

67206H

M67206H

4143J–AERO–04/07

Figure 5. Compound FIFO Expansion

Notes: 1. For depth expansion block see section on Depth Expansion and Figure 4.

2. For Flag detection see section on Width Expansion and Figure 3.

Figure 6. Bi-directional FIFO Mode



I0- I

8

I0- I8I9- I17

I9 17

- I

R W RS





Q - Q

0 8

Q - Q

0 8

Q - Q

9 17

Q - Q

9 17



(N-8) - IN

I(N-8) -

I

N

Q(N-8) - QN

M67206H M67206H

67206H

M67206H

4143J–AERO–04/07

Electrical Characteristics

Absolute Maximum Ratings

DC Parameters

Supply voltage (VCC - GND):.............................- 0.5V to 7.0V

Input or Output voltage applied: (GND - 0.3V) to (Vcc + 0.3V)

Storage temperature:................................. - 65 °C to + 150 °C

*NOTICE:

Stresses beyond those listed under "Absolute Maxi-

mum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional oper-

ation of the device at these or any other conditions

beyond those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect device reliability.

DC Test Conditions

TA = -55°C to + 125°C; Vss = 0V; Vcc = 4.5V to 5.5V

Parameter Description M67206H-30 M67206H-15 Unit Value

ICCOP (1)

Operating

supply current

110 120 mA Max

ICCSB (2)

Standby

supply current

5 5 mA Max

ICCPD (3)

Power down

current

400 400 µA Max

1. Icc measurements are made with outputs open.

2. R = W = RS = FL/RT = VIH.

3. All input = Vcc.

Parameter Description M67206H Unit Value

ILI (1)

Input leakage current

± 1 µA Max

ILO (2)

Output leakage current

± 1 µA Max

VIL (3)

Input low voltage

0.8 V Max

VIH(3)

Input high voltage

2.2 V Min

VOL (4)

Output low voltage

0.4 V Max

VOH(4)

Output high voltage

2.4 V Min

C IN (5)

Input capacitance

8 pF Max

C OUT(5)

Output capacitance

8 pF Max

1. 0.4 ≤ Vin ≤ Vcc.

2. R = VIH, 0.4 ≤ VOUT ≤ VCC.

3. VIH max = Vcc + 0.3 V. VIL min = -0.3V or -1V pulse width 50 ns. For XI input, VIH = 2.8V

4. Vcc min, IOL = 8 mA, IOH = -2 mA.

5. Guaranteed but not tested.

M67206H

4143J–AERO–04/07

AC Test Conditions

Figure 7. Output Load

Input pulse levels: Gnd to 3.0V Output reference levels: 1.5V

Input rise/Fall times: 5 ns Output load: See Figure 7

Input timing reference levels: 1.5V

Table 3. AC Test Conditions

Symbol

(1)

Symbol

(2)

Parameter

(3)

(4)

M67206H- 15 M67206H- 30 Unit

Min Max Min Max

Read Cycle

TRLRL tRC

Read cycle time

25 – 40 – ns

TRLQV tA

Access time

– 15 – 30 ns

TRHRL tRR

Read recovery time

10 – 10 – ns

TRLRH tRPW

Read pulse width

(5)

15 – 30 – ns

TRLQX tRLZ

Read low to data low Z

(6)

0 – 0 – ns

TWHQX tWLZ

Write low to data low Z

(6) (7)

3 – 5 – ns

TRHQX tDV

Data valid from read high

5 – 5 – ns

TRHQZ tRHZ

Read high to data high Z

(6)

– 15 – 20 ns

Write Cycle

TWLWL tWC

Write cycle time

25 – 40 – ns

TWLWH tWPW

Write pulse width

(5)

15 – 30 – ns

TWHWL tWR

Write recovery time

10 – 10 – ns

TDVWH tDS

Data set-up time

9 – 18 – ns

TWHDX tDH

Data hold time

0 – 0 – ns

Reset Cycle

TRSLWL tRSC

Reset cycle time

25 – 40 – ns

TRSLRSH tRS

Reset pulse width

(5)

15 – 30 – ns

M67206H

4143J–AERO–04/07

TWHRSH tRSS

Reset set-up time

20 – 30 – ns

TRSHWL tRSR

Reset recovery time

10 – 10 – ns

Retransmit Cycle

TRTLWL tRTC

Retransmit cycle time

25 – 40 – ns

TRTLRTH tRT

Retransmit pulse width

(5)

15 – 30 – ns

TWHRTH tRTS

Retransmit set-up time

(6)

15 – 30 – ns

TRTHWL tRTR

Retransmit recovery time

10 – 10 – ns

Flags

TRSLEFL tEFL

Reset to EF low

– 25 – 30 ns

TRSLFFH tHFH, tFFH

Reset to HF/FF high

– 25 – 30 ns

TRLEFL tREF

Read low to EF low

– 25 – 30 ns

TRHFFH tRFF

Read high to FF high

– 25 – 30 ns

TEFHRH tRPE

Read width after EF high

15 – 30 – ns

TWHEFH tWEF

Write high to EF high

– 15 – 30 ns

TWLFFL tWFF

Write low to FF low

– 20 – 30 ns

TWLHFL tWHF

Write low to HF low

– 30 – 30 ns

TRHHFH tRHF

Read high to HF high

– 30 – 30 ns

TFFHWH tWPF

Write width after FF high

15 – 30 – ns

Expansion

TWLXOL tXOL

Read/Write to XO low

– 15 – 30 ns

TWHXOH tXOH

Read/Write to XO high

– 15 – 30 ns

TXILXIH tXI

XI pulse width

15 – 30 – ns

TXIHXIL tXIR

XI recovery time

10 – 10 – ns

TXILRL tXIS

XI set-up time

10 – 10 – ns

1. STD symbol.

2. ALT symbol.

3. Timings referenced as in AC test conditions.

4. All parameters tested only.

5. Pulse widths less than minimum value are not allowed.

6. Values guaranteed by design, not currently tested.

7. Only applies to read data flow-through mode.

Table 3. AC Test Conditions (Continued)

Symbol

(1)

Symbol

(2)

Parameter

(3)

(4)

M67206H- 15 M67206H- 30 Unit

Min Max Min Max

M67206H

4143J–AERO–04/07

Figure 8. Asynchronous Write and Read Operation

Figure 9. Full Flag from Last Write to First Read

Figure 10. Empty Flag from Last Read to First Write

M67206H

4143J–AERO–04/07

Figure 11. Retransmit

Figure 12. Empty Flag Timing

Figure 13. Full Flag Timing

M67206H

4143J–AERO–04/07

Figure 14. Half Full Flag Timing

Figure 15. Expansion Out

Figure 16. Expansion In

M67206H

4143J–AERO–04/07

Figure 17. Read Data Flow

–

Through Mode

Figure 18. Write Data Flow

–

Through Mode

M67206H

4143J–AERO–04/07

Ordering Information

Note: 1. Contact Atmel for availability.

Part Number

Temperature

Range Speed Package Quality Flow

MMCP-67206HV-15-E

(1)

25°C 15 ns SB28.3 Engineering Samples

SMCP-67206HV-15SCC

-55 to +125°C 15 ns SB28.3 ESCC

SMCP-67206HV-30SCC

-55 to +125°C 30 ns SB28.3 ESCC

5962-9317708QTC

-55 to +125°C 15 ns SB28.3 QML Q

5962-9317707QTC

-55 to +125°C 30 ns SB28.3 QML Q

5962-9317708VTC

-55 to +125°C 15 ns SB28.3 QML V

5962D9317708VTC

-55 to +125°C 15 ns SB28.3 QML V RHA

5962D9317707VTC

-55 to +125°C 30 ns SB28.3 QML V RHA

5962-9317707VTC

-55 to +125°C 30 ns SB28.3 QML V

MMDP-67206HV-15-E

25°C 15 ns FP28.4 Engineering Samples

SMDP-67206HV-15SCC

-55 to +125°C 15 ns FP28.4 ESCC

SMDP-67206HV-30SCC

-55 to +125°C 30 ns FP28.4 ESCC

5962-9317708QNC

-55 to +125°C 15 ns FP28.4 QML Q

5962-9317707QNC

-55 to +125°C 30 ns FP28.4 QML Q

5962-9317708VNC

-55 to +125°C 15 ns FP28.4 QML V

5962-9317707VNC

-55 to +125°C 30 ns FP28.4 QML V

5962D9317708VNC

-55 to +125°C 15 ns FP28.4 QML V RHA

5962D9317707VNC

-55 to +125°C 30 ns FP28.4 QML V RHA

MM0 -67206HV-15SV

(1)

-55 to +125°C 15 ns Die QML V

MM067206HV-15-E

(1)

25°C 15 ns Die Engineering Samples

M67206H

4143J–AERO–04/07

Package Drawings

28-lead Side Braze (300 Mils)

M67206H

4143J–AERO–04/07

28-lead Flat Pack (400 Mils)

tered trademarks, of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

Atmel Headquarters Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

TEL (41) 26-426-5555

FAX (41) 26-426-5500

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

Memory

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

TEL (33) 4-42-53-60-00

FAX (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Data-

com

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

TEL (33) 4-76-58-30-00

FAX (33) 4-76-58-34-80

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

4143J–AERO–04/07 /xM