5V994PFGI8 - Integrated Device Technology

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

AUGUST 2002

2002 Integrated Device Technology, Inc. DSC 5828/3c

INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

• Ref input is 5V tolerant

• 4 pairs of programmable skew outputs

• Low skew: 200ps same pair, 250ps all outputs

• Selectable positive or negative edge synchronization:

Excellent for DSP applications

• Synchronous output enable

• Input frequency: 17.5MHz to 133MHz

• Output frequency: 17.5MHz to 133MHz

• 2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)

• 3-level inputs for skew control

• PLL bypass for DC testing

• External feedback, internal loop filter

• 12mA balanced drive outputs

• Low Jitter: <200ps cycle-to-cycle

• Available in PLCC and TQFP packages

FUNCTIONAL BLOCK DIAGRAM

sOE

1Q0

Skew

Select 1Q1

1F1:0

2Q0

Skew

Select 2Q1

2F1:0

REF PLL

3Q0

Skew

Select 3Q1

3F1:0

4Q0

4Q1

Skew

Select

4F1:0

PE TEST

IDT5V994

3.3V PROGRAMMABLE

SKEW PLL CLOCK DRIVER

TURBOCLOCK™ PLUS

DESCRIPTION

The IDT5V994 is a high fanout 3.3V PLL based clock driver intended for

high performance computing and data-communications applications. A key

feature of the programmable skew is the ability of outputs to lead or lag the

REF input signal. The IDT5V994 has eight programmable skew outputs in

four banks of 2. Skew is controlled by 3-level input signals that may be hard-

wired to appropriate HIGH-MID-LOW levels.

When the sOE pin is held low, all the outputs are synchronously enabled.

However, if sOE is held high, all the outputs except 3Q0 and 3Q1 are

synchronously disabled.

Furthermore, when the PE is held high, all the outputs are synchronized

with the positive edge of the REF clock input. When PE is held low, all the

outputs are synchronized with the negative edge of REF. The IDT5V994

has LVTTL outputs with 12mA balanced drive outputs.

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

PIN CONFIGURATIONS

NOTE:

1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute-

maximum-rated conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Description Max Unit

VDDQ, VDD Supply Voltage to Ground–0.5 to +4.6 V

VIDC Input Voltage –0.5 to VDD+0.5 V

REF Input Voltage –0.5 to +5.5 V

Maximum Power Dissipation, TA = 85°C 0.8 W

TSTG Storage Temperature Range –65 to +150 °C

NOTE:

1. Capacitance applies to all inputs except TEST, FS, and nF[1:0].

CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)

Parameter Description Typ. Max. Unit

CIN Input Capacitance 5 7 pF

TQFP

TOP VIEW

3F1

4F0

4F1

VDDQ

4Q1

4Q0

GND

2F0

sOE

1F1

1F0

1Q0

1Q1

GND

4 3 2 1 32 31 30

14 15 16 17 18 19 20

3F0

REF

GND

TEST

2F1

3Q1

3Q0

2Q1

2Q0

DDQ

VDDQ

PROGRAMMABLE SKEW

Output skew with respect to the REF input is adjustable to compensate

for PCB trace delays, backplane propagation delays or to accommodate

requirements for special timing relationships between clocked compo-

nents. Skew is selectable as a multiple of a time unit tU which is of the

order of a nanosecond (see PLL Programmable Skew Range and Resolution

Table). There are nine skew configurations available for each output

pair. These configurations are chosen by the nF1:0 control pins. In order

to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)

are used, they are intended for but not restricted to hard-wiring. Undriven

3-level inputs default to the MID level. Where programmable skew is

not a requirement, the control pins can be left open for the zero skew

default setting. The Control Summary Table shows how to select specific

skew taps by using the nF1:0 control pins.

PLCC

TOP VIEW

3F0

REF

2F1

28 27

GND

TEST

2F0

3Q1

3Q0

DDQ

2Q0

13 14

2Q1

DDQ

GND

3F1

4F0

4F1

VDDQ

4Q1

4Q0

GND

sOE

1F1

1F0

1Q0

1Q1

GND

VDDQ

GND

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

NOTE:

1. When TEST = MID and sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in

effect unless nF[1:0] = LL.

PIN DESCRIPTION

Pin Name Type Description

REF IN Reference Clock Input

FB IN Feedback Input

TEST (1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary

Table) remain in effect. Set LOW for normal operation.

sOE(1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1 may be used as

the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable

controls for individual banks when nF[1:0] = LL. Set sOE LOW for normal operation.

PE IN Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference

clock.

nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions

nQ[1:0] OUT Four banks of two outputs with programmable skew

VDDQ PWR Power supply for output buffers

VDD PWR Power supply for phase locked loop and other internal circuitry

GND PWR Ground

EXTERNAL FEEDBACK

By providing external feedback, the IDT5V994 gives users flexibility

with regard to skew adjustment. The FB signal is compared with the

input REF signal at the phase detector in order to drive the VCO. Phase

differences cause the VCO of the PLL to adjust upwards or downwards

accordingly.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to

provide minimal jitter (or frequency variation) while still providing accu-

rate responses to input frequency changes.

NOTES:

1 . The VCO frequency always appears at 1Q1:0, 2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs

will be FNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication

by using a divided output as the FB input. Using the nF[1:0] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals).

2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example

if a 4tU skewed output is used for feedback, all other outputs will be skewed –4tU in addition to whatever skew value is programmed for those outputs. ‘Max adjustment’ range

applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.

Comments

Timing Unit Calculation (tU) 1/(16 x FNOM)

VCO Frequency Range (FNOM)(1,2) 70 to 133MHz

Skew Adjustment Range(2)

Max Adjustment: ±5.36ns ns

±135° Phase Degrees

±37.5% % of Cycle Time

Example 1, FNOM = 80MHz tU = 0.78ns

Example 2, FNOM = 100MHz tU = 0.63ns

Example 3, FNOM = 133MHz tU = 0.47ns

PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS

nF1:0 Skew (Pair #1, #2) Skew (Pair #3) Skew (Pair #4)

LL (1) –4tUDivide by 2 Divide by 2

LM –3tU–6tU–6tU

LH –2tU–4tU–4tU

ML –1tU–2tU–2tU

MM Zero Skew Zero Skew Zero Skew

MH 1tU2tU2tU

HL 2tU4tU4tU

HM 3tU6tU6tU

HH 4tUDivide by 4 Inverted (2)

NOTES:

1 . LL disables outputs if TEST = MID and sOE = HIGH.

2. When pair #4 is set to HH (inverted), sOE disables pair #4 HIGH when PE = HIGH, sOE disables pair #4 LOW when PE = LOW.

RECOMMENDED OPERATING RANGE

Symbol Description Min. Typ. Max. Unit

VDD/VDDQ Power Supply Voltage 3 3.3 3.6 V

TAAmbient Operating Temperature -40 +25 +85 °C

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol Parameter Conditions Min. Max. Unit

VIH Input HIGH Voltage Guaranteed Logic HIGH (REF, FB Inputs Only) 2 — V

VIL Input LOW Voltage Guaranteed Logic LOW (REF, FB Inputs Only) — 0.8 V

VIHH Input HIGH Voltage(1) 3-Level Inputs Only VDD−0.6 — V

VIMM Input MID Voltage(1) 3-Level Inputs Only VDD/2−0.3 VDD/2+0.3 V

VILL Input LOW Voltage(1) 3-Level Inputs Only — 0.6 V

IIN Input Leakage Current VIN = VDD or GND −5+5µA

(REF, FB Inputs Only) VDD = Max.

VIN = VDD HIGH Level — +200

I33-Level Input DC Current VIN = VDD/2 MID Level −50 +50 µA

(TEST, FS, nF[1:0], DS[1:0])VIN = GND LOW Level −200 —

IPU Input Pull-Up Current (PE) VDD = Max., VIN = GND −100 — µA

IPD Input Pull-Down Current (sOE)VDD = Max., VIN = VDD — +100 µA

VOH Output HIGH Voltage VDDQ = Min., IOH = −12mA 2.4 — V

VOL Output LOW Voltage VDDQ = Min., IOL = 12mA — 0.4 V

NOTE:

1. These inputs are normally wired to VDD, GND, or unconnected. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched, the function and

timing of the outputs may be glitched, and the PLL may require an additional tLOCK time before all datasheet limits are achieved.

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

POWER SUPPLY CHARACTERISTICS

Symbol Parameter Test Conditions(1) Typ. Max. Unit

IDDQ Quiescent Power Supply Current VDD = Max., TEST = MID, REF = LOW, 8 25 mA

PE = LOW, sOE = LOW

All outputs unloaded

∆IDD Power Supply Current per Input HIGH VDD = Max., VIN = 3V, 1 30 µA

IDDD Dynamic Power Supply Current per Output VDD/VDDQ = Max., CL = 0pF 55 90 µA/MHz

VDD/VDDQ = 3.3V , FREF = 83MHz, CL = 160pF(1) 31 —

ITOT Total Power Supply Current VDD/VDDQ = 3.3V , FREF = 100MHz, CL = 160pF(1) 34 — mA

VDD/VDDQ = 3.3V , FREF = 133MHz, CL = 160pF(1) 39 —

NOTE:

1. For eight outputs, each loaded with 20pF.

NOTES:

1. Where pulse width implied by DH is less than tPWC limit, tPWC limit applies.

2. The minimum reference clock input frequency is 70MHz if Q/2 or Q/4 are not used as feedback

INPUT TIMING REQUIREMENTS

Symbol Description(1) Min. Max. Unit

tR, tFMaximum input rise and fall times, 0.8V to 2V — 1 0 ns/V

tPWC Input clock pulse, HIGH or LOW 2 — n s

DHInput duty cycle 1 0 9 0 %

FREF Reference clock input frequency(2) 17.5 133 MHz

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol Parameter Min. Typ. Max. Unit

FNOM VCO Frequency Range See Programmable Skew Range and Resolution Table

tRPWH REF Pulse Width HIGH(1) 2——ns

tRPWL REF Pulse Width LOW(1) 2——ns

tUProgrammable Skew Time Unit See Control Summary Table

tSKEWPR Zero Output Matched-Pair Skew (xQ0, xQ1)(2,3) — 0.05 0.2 ns

tSKEW0 Zero Output Skew (All Outputs)(4) — 0.1 0.25 ns

tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)(5) — 0.25 0.5 ns

tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)(5) — 0.3 1.2 ns

tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(5) — 0.25 0.5 ns

tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)(2) — 0.5 0.9 ns

tDEV Device-to-Device Skew(2,6) — — 0.75 ns

t(φ)REF Input to FB Static Phase Offset)(7) −0.25 0 0.25 ns

tODCV Output Duty Cycle Variation from 50% −1.2 0 1.2 ns

tPWH Output HIGH Time Deviation from 50%(8) ——2ns

tPWL Output LOW Time Deviation from 50%(9) — — 2.5 ns

tORISE Output Rise Time 0.15 1 1.8 ns

tOFALL Output Fall Time 0.15 1 1.8 ns

tLOCK PLL Lock Time(10) — — 0.5 ms

tJR Cycle-to-Cycle Output Jitter (peak-to-peak) — — 200 ps

NOTES:

1. Refer to Input Timing Requirements table for more detail.

2. Skew is the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with the specified

load.

3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.

4. tSK(0) is the skew between outputs when they are selected for 0tU.

5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-

by-4 mode).

6. tDEV is the output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)

7. tφ is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.

8. Measured at 2V.

9. Measured at 0.8V.

10. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter

is measured from the application of a new signal or frequency at REF or FB until tφ is within specified limits.

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

2.0V

tPWL

tPWH

tORISE tOFALL

0.8V

≤1ns ≤1ns

2.0V

0.8V

3.0V

VTH = 1.5 V

150Ω

VDDQ

Output

150Ω20pF

AC TEST LOADS AND WAVEFORMS

LVTTL Input Test Waveform

LVTTL Output Waveform

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

REF

OTHER Q

INV ER T ED Q

REF D IVIDED B Y 2

REF D IVIDED B Y 4

tREF

tSKEW2

tSK EW 3, 4

tSK EW 1, 3 , 4 tSKEW 2, 4

tSK EW 3, 4

tSKEW 3, 4

tSKEW2

tSKEWPR

tSK EW 0, 1

tJR

tODCV tODCV

tRPWH

tRPWL

tSKEWPR

tSKEW 0, 1

t(φ)

AC TIMING DIAGRAM

NOTES:

PE: The AC Timing Diagram applies to PE=VDD. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge

of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.

Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 20pF and terminated

with 75Ω to VDDQ/2.

tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.

tSKEW0: The skew between outputs when they are selected for 0tU.

tDEV: The output-to-output skew between any two devices operating under the same conditions (VDDQ, VDD, ambient temperature, air flow, etc.)

tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.

tPWH is measured at 2V.

tPWL is measured at 0.8V.

tORISE and tOFALL are measured between 0.8V and 2V.

tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VDD/VDDQ is stable and within normal operating limits. This parameter

is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.

INDUSTRIAL TEMPERATURE RANGE

IDT5V994

3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK PLUS

ORDERING INFORMATION

IDT XXXXX XX

Package

D evice Type

5V994 3.3V Progra mm ab le S kew PLL C loc k

Driv e r Tu rb oClo c k P lu s

32-pin P LC C

32-pin TQFP

PFI

Package

-4 0°C to +85°C (Industrial)

DATA SHEET DOCUMENT HISTORY

1/21/02 pages 1, 2, 4

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459