Datasheet 1 Rev. 1.1
www.infineon.com 2018-02-08
TLD5541-1
1 Overview
Features
• Single Inductor high power Buck-Boost controller
• Wide LED forward voltage Range (2 V up to 55 V)
• Wide VIN Range (IC 4.5 V to 40 V, Power 4.5 V to 55 V)
• Switching Frequency Range from 200 kHz to 700 kHz
• SPI for diagnostics and control
• Maximum Efficiency in every condition (up to 96%)
• Constant Current (LED) and Constant Voltage Regulation
• Drives Multiple Load with a single IC thanks to the Fast Output Discharge operation
• Limp Home Function (Fail Safe Mode)
• EMC optimized device: Features an auto Spread Spectrum
• LED and Input current sense with dedicated monitor Outputs
• Advanced protection features for device and load
• Enhanced Dimming features: Analog and PWM dimming
• LED current accuracy +/- 3%
• Available in a small thermally enhanced PG-VQFN-48-31 or PG-TQFP-48-9 package
• Automotive AEC Qualified
Figure 1 Application Drawing - TLD5541-1 as current regulator
H-Bridge DC/DC Controller with SPI Interface
Infineon® LITIX™ Power Flex
Package PG-VQFN-48-31 PG-TQFP-48-9
Marking TLD55411QV TLD55411QU
Sales Name TLD5541-1QV TLD5541-1QU
VDD
CSN
SI
SO
SCLK
COMP
IIN2
IIN1
SYNC
VIN
AGND
PWMI
L
OUT
C
OUT1
IVCC
BST1
BST2
HSGD1
LSGD1
SWN1
LSGD2
HSGD2
SWN2
FBH
FBL
SWCS
SGND
PGND1
C
IVCC
C
BST1
C
BST2
D
1
D
2
M
1
M
2
M
3
M
4
C
IN2
C
COMP
SPI
C
IN1
EN/INUVLO
INOVLO
SOFT_START
C
SOFT_START
PGND2
VSS
VFB
FREQ
C
filter
IVCC_ext
IINMON
IOUTMON
LIMPHOME
PWMI_LH
R
SENSE
A/D
GND
Micro
controller
V
DD
FAIL SAFE Circuit
FAIL SA FE Circu it
R
IIN
R
COMP
R
filter
R
FRE Q
R
1
R
2
R
3
R
PD
R
FB
R
VFBH
R
VFBL
R
SWCS
A/D
R
SENSE
I/O
R
PWMI
I/O
R
SYNC
V
DD
SPI
R
SI
R
SO
R
CSN
R
SCLK
I/O
R
EN
SET
R
5
R
4
IVCC
C
OUT2
C
OUT3
LHI
V
IN
Datasheet 2 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Overview
Description
The TLD5541-1 is a synchronous MOSFET H-Bridge DC/DC controller with built in protection features and SPI
interface. This concept is beneficial for driving high power LEDs with maximum system efficiency and
minimum number of external components. The TLD5541-1 offers both analog and digital (PWM) dimming.The
switching frequency is adjustable in the range of 200 kHz to 700 kHz. It can be synchronized to an external
clock source. A built in programable Spread Spectrum switching frequency modulation and the forced
continuous current regulation mode improve the overall EMC behavior. Furthermore the current mode
regulation scheme provides a stable regulation loop maintained by small external compensation
components. The adjustable soft start feature limits the current peak as well as voltage overshoot at start-up.
The TLD5541-1 is suitable for use in the harsh automotive environment.
Protective Functions
• Over load protection of external MOSFETs
• Shorted load, open load, output overvoltage protection
• Input overvoltage and undervoltage protection
• Thermal shutdown of device with autorestart behavior
• Electrostatic discharge protection (ESD)
Diagnostic Functions
• Latched diagnostic information via SPI
• Open load detection in ON-state
• Device Overtemperature shutdown and Temperature Prewarning
• Smart monitoring and advanced functions provide ILED and IIN information
Limp Home Function
• Limp Home activation via LHI pin
Applications
• Especially designed for driving high power LEDs in automotive applications
• Automotive Exterior Lighting: full LED headlamp assemblies (Low Beam, High Beam, Matrix Beam, Pixel
Light)
• General purpose current/voltage controlled DC/DC LED driver
Table 1 Product Summary
Power Stage input voltage range VPOW 4.5 V … 55 V
Device Input supply voltage range VVIN 4.5 V … 40 V
Maximum output voltage (depending by the
application conditions)
VOUT(max) 55 V as LED Driver Boost Mode
50 V as LED Driver Buck Mode
50 V as Voltage regulator
Switching Frequency range fSW 200 kHz... 700 kHz
Typical NMOS driver on-state resistance at
Tj= 25°C (Gate Pull Up)
RDS(ON_PU) 2.3 Ω
Typical NMOS driver on-state resistance at
Tj= 25°C (Gate Pull Down)
RDS(ON_PD) 1.2 Ω
SPI clock frequency fSCLK(MAX) 5MHz
Datasheet 3 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Block Diagram
2 Block Diagram
Figure 2 Block Diagram - TLD5541-1
GATE
DRIVER
COMP
VIN
FBL
FBH
AGND
SWCS
LDO
SGND
Internal Supply
PWM
Generator
Feedback Error Amplifier
Switch Current
Error Amplifier
BUCK
LO GIC
HSGD1
BOOST
LO GIC
BST1
SWN1
LSGD1
LSGD2
IVCC_EXT
HSGD2
SWN2
BST2
CSN
SI
SCLK
SO
Input/diagnosis
register
VDD
SPI
LED
Current
Monitor
Input
Current
Monitor
IIN1 IIN2
VSS
VFB
Voltage Loop
Feedback
IINMON
IOUTMON
IVCC
IVCC_EXT
PGND1
PGND2
IVCC_EXT
Power
On Reset
SYNC Oscillator
Soft Start
Slope Comp.
Thermal Protection
+ Prewarning
Auto-Spread
Spectrum
Generator
FREQ
Diagnosis Open Load + Short
to GND
SOFT_START
Digital Dimming
PWMI
Analog Dimming Pin
SET
Fast Output
Discharge
Operation
Mode
Output
current
accuracy
calibration
Limp Home Mode
LHI
EN/INUVLO
VI N
Voltage
Prot ectio n
+ Enable
INOVLO
8 Bit DAC
Analog
Dimming
Datasheet 4 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 3 Pin Configuration - TLD5541-1
Datasheet 5 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Pin Configuration
3.2 Pin Definitions and Functions
Pin Symbol I/O 1) Function
Power Supply
1, 12,
15, 21,
32, 33,
45, 48
n.c. - Not connected, tie to AGND on the Layout;
44 VIN - Power Supply Voltage;
Supply for internal biasing.
31 VDD - Digital GPIO Supply Voltage;
Connect to reverse voltage protected 5 V or 3.3 V supply.
47 IVCC_EXT I PD External LDO input;
Input to alternatively supply internal Gate Drivers via an external LDO.
Connect to IVCC pin to use internal LDO to supply gate drivers. Must not
be left open.
5, 8 PGND1, 2 - Power Ground;
Ground for power potential. Connect externally close to the chip.
26 VSS - Digital GPIO Ground;
Ground for GPIO pins.
40 AGND - Analog Ground;
Ground Reference
-EP -Exposed Pad;
Connect to external heatspreading Cu area (e.g. inner GND layer of
multilayer PCB with thermal vias).
Gate Driver Stages
2HSGD1 OHighside Gate Driver Output 1;
Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT
superimposed on the switch node voltage SWN1. Connect to gate of
external switching MOSFET.
11 HSGD2 O Highside Gate Driver Output 2;
Drives the top n-channel MOSFET with a voltage equal to VIVCC_EXT
superimposed on the switch node voltage SWN2. Connect to gate of
external switching MOSFET.
6LSGD1 OLowside Gate Driver Output 1;
Drives the lowside n-channel MOSFET between GND and VIVCC_EXT.
Connect to gate of external switching MOSFET.
7LSGD2 OLowside Gate Driver Output 2;
Drives the lowside n-channel MOSFET between GND and VIVCC_EXT.
Connect to gate of external switching MOSFET.
4SWN1 IOSwitch Node 1;
SWN1 pin swings from a diode voltage drop below ground up to VIN.
9SWN2 IOSwitch Node 2;
SWN2 pin swings from ground up to a diode voltage drop above VOUT.
Datasheet 6 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Pin Configuration
46 IVCC O Internal LDO output;
Used for internal biasing and gate driver supply. Bypass with external
capacitor close to the pin. Pin must not be left open.
Inputs and Outputs
37 LHI I PD Limp Home Input Pin;
Used to enter in Limp Home state during Fail Safe condition.
23 TEST1 - Test Pin;
Used for Infineon end of line test, connect to GND in application.
25 TEST2 - Test Pin;
Used for Infineon end of line test, connect to GND in application.
41 EN/INUVLO I PD Enable/Input Under Voltage Lock Out;
Used to put the device in a low current consumption mode, with
additional capability to fix an undervoltage threshold via external
components. Pin must not be left open.
35 FREQ I Frequency Select Input;
Connect external resistor to GND to set frequency.
34 SYNC I PD Synchronization Input;
Apply external clock signal for synchronization.
24 PWMI I PD Control Input; Digital input 5 V or 3.3 V.
13 FBH I Output current Feedback Positive;
Non inverting Input (+).
14 FBL I Output current Feedback Negative;
Inverting Input (-).
3BST1 IOBootstrap capacitor;
Used for internal biasing and to drive the Highside Switch HSGD1.
Bypass to SWN1 with external capacitor close to the pin. Pin must not be
left open.
10 BST2 IO Bootstrap capacitor;
Used for internal biasing and to drive the Highside Switch HSGD2.
Bypass to SWN2 with external capacitor close to the pin. Pin must not be
left open.
17 SWCS I Current Sense Input;
Inductor current measurement - Non Inverting Input (+).
18 SGND I Current Sense Ground;
Inductor current sense - Inverting Input (-).
Route as Differential net with SWCS on the Layout.
42 IIN1 I Input Current Monitor Positive;
Non Inverting Input (+), connect to VIN if input current monitor is not
needed.
43 IIN2 I Input Current Monitor Negative;
Inverting Input (-), connect to VIN if input current monitor is not needed.
19 COMP O Compensation Network Pin;
Connect R and C network to pin for stability phase margin adjustment.
Pin Symbol I/O 1) Function
Datasheet 7 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Pin Configuration
38 SOFT_START O Softstart configuration Pin;
Connect a capacitor CSOFT_START to GND to fix a soft start ramp default
time.
36 INOVLO I Input Overvoltage Protection Pin;
Define an upper voltage threshold and switches OFF the device in case
of overvoltages on the VIN supply. Must not be left open.
20 VFB I Voltage Loop Feedback Pin;
VFB is intended to set output protection functions.
22 SET I Analog current sense adjustment Pin;
39 IINMON O Input current monitor output;
Monitor pin that produces a voltage that is 20 times the voltage VIN1-IN2.
IINMON will be equal 1 V when VIIN1-VIIN2 = 50 mV.
16 IOUTMON O Output current monitor output;
Monitor pin that produces a voltage that is 200 mV + 8 times the voltage
VFBH-FBL. IOUTMON will be equal 1.4 V when VFBH-FBL = 150 mV.
SPI
30 SI I PD Serial data in; Digital input 5 V or 3.3 V.
29 SCLK I PD Serial clock; Digital input 5 V or 3.3 V.
28 CSN I PU SPI chip select; Digital input 5 V or 3.3 V. Active LOW.
27 SO O Serial data out; Digital output, referenced to VDD.
1) O: Output, I: Input,
PD: pull-down circuit integrated,
PU: pull-up circuit integrated
Pin Symbol I/O 1) Function
Datasheet 8 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Table 2 Absolute Maximum Ratings1)
TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Supply Voltages
VIN
Supply Input
VVIN -0.3 – 60 V – P_4.1.1
VDD
Digital supply voltage
VVDD -0.3 – 6 V – P_4.1.2
IVCC
Internal Linear Voltage Regulator
Output voltage
VIVCC -0.3 – 6 V – P_4.1.3
IVCC_EXT
External Linear Voltage Regulator Input
voltage
VIVCC_EXT -0.3 – 6 V – P_4.1.4
Gate Driver Stages
LSGD1,2 - PGND1,2
Lowside Gatedriver voltage
VLSGD1,2-
PGND1,2
-0.3 – 5.5 V – P_4.1.54
HSGD1,2 - SWN1,2
Highside Gatedriver voltage
VHSGD1,2-
SWN1,2
-0.3 – 5.5 V – P_4.1.55
SWN1, SWN2
switching node voltage
VSWN1, 2 -1 – 60 V – P_4.1.6
(BST1-SWN1), (BST2-SWN2)
Boostrap voltage
VBST1,2-
SWN1,2
-0.3 – 6 V – P_4.1.7
BST1, BST2
Boostrap voltage related to GND
VBST1, 2 -0.3 – 65 V – P_4.1.8
SWCS
Switch Current Sense Input voltage
VSWCS -0.3 – 0.3 V – P_4.1.9
SGND
Switch Current Sense GND voltage
VSGND -0.3 – 0.3 V – P_4.1.10
SWCS-SGND
Switch Current Sense differential
voltage
VSWCS-
SGND
-0.5 – 0.5 V – P_4.1.11
PGND1,2
Power GND voltage
VPGND1,2 -0.3 – 0.3 V – P_4.1.28
High voltage Pins
IIN1, IIN2
Input Current monitor voltage
VIIN1, 2 -0.3 – 60 V – P_4.1.12
Datasheet 9 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
General Product Characteristics
IIN1-IIN2
Input Current monitor differential
voltage
VIIN1-IIN2 -0.5 – 0.5 V – P_4.1.13
FBH, FBL
Feedback Error Amplifier voltage
VFBH, FBL -0.3 – 60 V – P_4.1.14
FBH-FBL
Feedback Error Amplifier differential
voltage
VFBH-FBL -0.5 – 0.5 V – P_4.1.15
EN/INUVLO
Device enable/input undervoltage
lockout
VEN/INUVLO -0.3 – 60 V – P_4.1.16
Digital (I/O) Pins
PWMI
Digital Input voltage
VPWMI -0.3 – 5.5 V – P_4.1.17
CSN
Voltage at Chip Select pin
VCSN -0.3 – 5.5 V – P_4.1.18
SCLK
Voltage at Serial Clock pin
VSCLK -0.3 – 5.5 V – P_4.1.19
SI
Voltage at Serial Input pin
VSI -0.3 – 5.5 V – P_4.1.20
SO
Voltage at Serial Output pin
VSO -0.3 – 5.5 V – P_4.1.21
SYNC
Synchronization Input voltage
VSYNC -0.3 – 5.5 V – P_4.1.22
LHI
Limp Home Input Voltage
VLHI -0.3 – 5.5 V – P_4.1.58
Analog Pins
VFB
Loop Input voltage
VVFB -0.3 – 5.5 V – P_4.1.25
INOVLO
Input overvoltage lockout
VINOVLO -0.3 – 5.5 V – P_4.1.26
SET
Analog dimming Input voltage
VSET -0.3 – 5.5 V – P_4.1.29
COMP
Compensation Input voltage
VCOMP -0.3 – 3.6 V – P_4.1.30
SOFT_START
Softstart Voltage
VSOFT_STAR
T
-0.3 – 3.6 V – P_4.1.31
FREQ
Voltage at frequency selection pin
VFREQ -0.3 – 3.6 V – P_4.1.32
Table 2 Absolute Maximum Ratings1) (cont’d)
TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 10 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
General Product Characteristics
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the datasheet. Fault conditions are considered as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation.
4.2 Functional Range
IINMON
Voltage at input monitor pin
VIINMON -0.3 – 3.6 V – P_4.1.33
IOUTMON
Voltage at output monitor pin
VIOUTMON -0.3 – 5.5 V – P_4.1.34
Temperatures
Junction Temperature Tj-40 – 150 °C – P_4.1.35
Storage Temperature Tstg -55 – 150 °C – P_4.1.36
ESD Susceptibility
ESD Resistivity of all Pins VESD,HBM -2 – 2 kV HBM2) P_4.1.37
ESD Resistivity to GND VESD,CDM -500 – 500 V CDM3) P_4.1.38
ESD Resistivity of corner Pins to GND VESD,CDM_c
orner
-750 – 750 V CDM3) P_4.1.39
1) Not subject to production test, specified by design.
2) ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5 kΩ, 100 pF)
3) ESD susceptibility, Charged Device Model “CDM” ESDA STM5.3.1 or ANSI/ESD S.5.3.1
Table 3 Functional Range
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Device Extended Supply Voltage
Range
VVIN 4.5 – 40 V 1)
1) Not subject to production test, specified by design.
P_4.2.1
Device Nominal Supply Voltage
Range
VVIN 8–36V– P_4.2.2
Power Stage Voltage Range VPOW 4.5 – 55 V 1) P_4.2.5
Digital Supply Voltage VDD 3–5.5V– P_4.2.3
Junction Temperature Tj-40 – 150 °C – P_4.2.4
Table 2 Absolute Maximum Ratings1) (cont’d)
TJ = -40°C to +150°C; all voltages with respect to AGND, (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 11 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
General Product Characteristics
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics
table.
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more
information, go to www.jedec.org.
Table 4
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Junction to Case RthJC –0.9–K/W
1) 2)
1) Not subject to production test, specified by design.
2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and the exposed pad are fixed
to ambient temperature). Ta = 25°C; The IC is dissipating 1 W.
P_4.3.1
Junction to Ambient RthJA –25–K/W
3) 2s2p
3) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area
at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5 mm board. The 2s2p board has
2 outer copper layers (2 x 70 µm Cu) and 2 inner copper layers (2 x 35 µm Cu). A thermal via (diameter = 0.3 mm and
25 µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner
layer and second outer layer (bottom) of the JEDEC PCB. Ta = 25°C; The IC is dissipating 1 W.
P_4.3.2
Datasheet 12 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
5 Power Supply
The TLD5541-1 is supplied by the following pins:
• VIN (main supply voltage)
• VDD (digital supply voltage)
• IVCC_EXT (supply for internal gate driver stages)
The VIN supply, in combination with the VDD supply, provides internal supply voltages for the analog and
digital blocks. In situations where VIN voltage drops below VDD voltage, an increased current consumption
may be observed at the VDD pin.
The SPI and IO interfaces are supplied by the VDD pin.
IVCC_EXT is the supply for the low side driver stages. This supply is used also to charge, through external
Schottky diodes, the bootstrap capacitors which provide supply voltages to the high side driver stages. If no
external voltage is available this pin must be shorted to IVCC, which is the output of an internal 5 V LDO.
The supply pins VIN, VDD and IVCC_EXT have undervoltage detections.
Undervoltage on VDD supply voltage prevents the activation of the gate driver stages and any SPI
communication (the SPI registers are reset). Undervoltage on IVCC_EXT or IVCC voltages forces a deactivation
of the driver stages, thus stopping the switching activity, but has no effect on the SPI register settings.
Moreover the double function pin EN/INUVLO can be used as an input undervoltage protection by placing a
resistor divider from VIN to GND (refer to Chapter 10.3).
If EN/INUVLO undervoltage is detected, it will turn-off the IVCC voltage regulator, stop switching, stop
communications and reset all the registers.
Figure 4 shows a basic concept drawing of the supply domains and interactions among pins VIN, VDD and
IVCC/IVCC_EXT.
Figure 4 Power Supply Concept Drawing
VIN
VREG (5V)
EN/INUVLO
Internal pre-regulated
voltage Supply
VREG
analog
VREG
digital
Bandgap
Reference
LOGIC
Register
Banks
SPI & I/O
VDD
IVCC
LS - Drivers
HS - Drivers
BSTx
SWNx
R
1
R
2
IVCC_EXT
PGND
Undervoltage
detection
Undervoltage
detection
Datasheet 13 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
Usage of EN/INUVLO pin in different applications
The pin EN/INUVLO is a double function pin and can be used to put the device into a low current consumption
mode. An undervoltage threshold should be fixed by placing an external resistor divider (A) in order to avoid
low voltage operating conditions. This pin can be driven by a µC-port as shown in (B) .
Figure 5 Usage of EN/INUVLO pin in different applications
A
EN/INUVLO
GND
VIN
R
1
V
in
R
2
B
EN/INUVLO
GND
VIN
R
1
V
in
R
2
µC Port
Datasheet 14 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
5.1 Different Power States
TLD5541-1 has the following power states:
•SLEEP state
•IDLE state
•LIMP HOME state
•ACTIVE state
The transition between the power states is determined according to these variables after a filter time of max.
3 clock cycles:
•VIN level
•EN/INUVLO level
• IVCC level
• IVCC_EXT level
• VDD level
•LHI level
•DVCCTRL.IDLE bit state
The state diagram including the possible transitions is shown in Figure 6.
The Power-up condition is entered when the supply voltage VVIN exceed its minimum supply voltage threshold
VVIN(ON).
SLEEP
When the device is powered it enters the SLEEP state, all outputs are OFF and the SPI registers are reset,
independently from the supply voltages at the pins VIN , VDD, IVCC, and IVCC_EXT. The current consumption
is low. Refer to parameters: IVDD(SLEEP), and IVIN(SLEEP).
The transition from SLEEP to ACTIVE state requires a specified time: tACTIVE.
IDLE
In IDLE state, the current consumption of the device can reach the limits given by parameter IVDD (P_5.3.4). The
internal voltage regulator is working. Not all diagnosis functions are available (refer to Chapter 10 for
additional informations). In this state there is no switching activity, independently from the supply voltages
VIN, VDD, IVCC and IVCC_EXT. When VDD is available, the SPI registers are working and SPI communication is
possible.
Limp Home
The Limp Home state is beneficial to fulfill system safety requirements and provides the possibility to
maintain a defined current/voltage level on the output via a backup control circuitry. The backup control
circuitry turns on required loads during a malfunction of the µC. For detailed info, refer to Chapter 8.
When Limp Home state is entered, SPI registers are reset to their default values and SPI communication is
possible but only in read mode (SPI registers can be read but cannot be written). In order to regulate the
output current/voltage, it is necessary that VIN and IVCC_EXT are present and above their undervoltage
threshold.
ACTIVE
In active state the device will start switching activity to provide power at the output only when PWMI = HIGH.
To start the Highside gate drivers HSGD1,2 the voltage level VBST1,2 - VSWN1,2 needs to be above the threshold
Datasheet 15 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
VBST1,2 -VSWN1,2_UVth. In ACTIVE state the device current consumption via VIN and VDD is dependent on the
external MOSFET used and the switching frequency fSW.
Figure 6 Simplified State Diagram
5.2 Different Possibilities to RESET the device
There are several reset triggers implemented in the device.
After any kind of reset, the Transmission Error Flag (TER) is set to HIGH.
Under Voltage Reset:
EN/INUVLO: When EN/INUVLO is below VEN/INUVLOth (P_5.3.7), the SPI interface is not working and all the
registers are reset to their default values. In addition, the device enters SLEEP mode and the current
consumption is minimized.
VDD: When VVDD is below VVDD(UV) (P_5.3.6), the SPI interface is not working and all the registers are reset to their
default values.
Reset via SPI command:
There is a command (DVCCTRL.SWRST = HIGH) available to RESET all writeable registers to their default
values. Note that the result coming from the Calibration routine, which is readable by the SPI when
DVCCTRL.ENCAL = HIGH, is not reset by the SWRST.
Reset via Limp Home:
When Limp Home state is detected the registers are reset to the default values.
SLEEP
LIMP HOME
Power-up
EN/INUVLO = LOW
EN/INUVLO = LOW
EN/INUVLO = LOW
VIN = HIGH
& IVCC = HIGH
& IVCC_EXT = HIGH
& VDD = HIGH
& DVCCTRL.IDLE = LOW
VIN = LOW
or IVCC = LOW
or IVCC_EXT = LOW
or VDD = LOW
or DVCCTRL.IDLE = HIGH
ACTIVE
LHI = LOW
IDLE
LHI = HIGH
& EN/INUVLO = HIGH
LHI = HIGH
LHI = LOW
& EN/INUVLO = HIGH
EN/INUVLO = LOW
LHI = HIGH
Datasheet 16 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
5.3 Electrical Characteristics
Table 5 EC Power Supply
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Power Supply VIN
Input Voltage Startup VVIN(ON) ––4.7VVIN increasing;
VEN/INUVLO = HIGH;
VDD = 5 V;
IVCC = IVCC_EXT =
10 mA;
P_5.3.1
Input Undervoltage switch OFF VVIN(OFF) ––4.5VVIN decreasing;
VEN/INUVLO = HIGH;
VDD = 5 V;
IVCC = IVCC_EXT =
10 mA;
P_5.3.14
Device operating current IVIN(ACTIVE) –4.46mA
1)ACTIVE mode;
VPWMI = 0 V;
P_5.3.2
VIN Sleep mode supply current IVIN(SLEEP) ––1.5µAVEN/INUVLO = 0 V;
VCSN = VDD = 5 V;
VIN = 13.5 V;
VIVCC = VIVCC_EXT= 0 V;
P_5.3.3
Digital Power Supply VDD
Digital supply current IVDD ––0.5mAVIN = 13.5 V;
fSCLK = 0 Hz;
VPWMI = 0 V;
VEN =VCSN = VDD = 5 V;
P_5.3.4
Digital Supply Sleep mode
current
IVDD(SLEEP) ––1.5µAVEN/INUVLO = 0 V;
VCSN = VDD = 5 V;
VIN = 13.5 V;
VIVCC = VIVCC_EXT = 0 V;
P_5.3.5
Undervoltage shutdown
threshold voltage
VVDD(UV) 1–3VVCSN = VDD;
VSI = VSCLK = 0 V;
SO from LOW to HIGH
impedance;
P_5.3.6
EN/INUVLO Pin characteristics
Input Undervoltage falling
Threshold
VEN/INUVLOth 1.6 1.75 1.9 V – P_5.3.7
EN/INUVLO Rising Hysteresis VEN/INUVLO(hy
st)
–90–mV
1) P_5.3.8
EN/INUVLO input Current LOW IEN/INUVLO(LO
W)
0.45 0.89 1.34 µA VEN/INUVLO = 0.8 V; P_5.3.9
Datasheet 17 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Power Supply
EN/INUVLO input Current HIGH IEN/INUVLO(HI
GH)
1.1 2.2 3.3 µA VEN/INUVLO = 2 V; P_5.3.10
LHI Pin characteristics
LOW level VLHI(L) 0- 0.8V– P_5.3.16
HIGH level VLHI(H) 2.0 - 5.5 V – P_5.3.17
L-Input pull-down current ILHI(L) 61218μAVLHI = 0.8 V; P_5.3.18
H-Input pull-down current ILHI(H) 15 30 45 μAVLHI = 2.0 V; P_5.3.19
Timings
SLEEP mode to ACTIVE time tACTIVE ––0.7ms
1)
VIVCC = VIVCC_EXT;
CIVCC = 10 µF;
VIN = 13.5 V;
VDD = 5 V;
P_5.3.11
1) Not subject to production test, specified by design.
Table 5 EC Power Supply (cont’d)
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 18 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6 Regulator Description
The TLD5541-1 includes all of the functions necessary to provide constant current to the output as usually
required to drive LEDs. A voltage mode regulation can also be implemented (Refer to Chapter 6.7).
It is designed to control 4 gate driver outputs in a H-Bridge topology by using only one inductor and 4 external
MOSFETs. This topology is able to operate in high power BOOST, BUCK-BOOST and BUCK mode applications
with maximum efficiency.
The transition between the different regulation modes is done automatically by the device itself, with respect
to the application boundary conditions.
The transition phase between modes is seamless.
A SPI flag provides mode feedback to the µC (refer to SPI bits REGUSETMON.REGUMODFB).
6.1 Regulator Diagram Description
The TLD5541-1 includes two analog current control inputs (IIN1, IIN2) to limit the maximum Input current
(Block A1 and A7 in Figure 7).
A second analog current control loop (A5, A6 with complessive gain = IFBxgm) connected to the sensing pins
FBL, FBH regulates the output current.
The regulator function is implemented by a pulse width modulated (PWM) current mode controller. The error
in the output current loop is used to determine the appropriate duty cycle to get a constant output current.
An external compensation network (RCOMP, CCOMP) is used to adjust the control loop to various application
boundary conditions.
The inductor current for the current mode loop is sensed by the RSWCS resistor.
RSWCS is used also to limit the maximum external switches / inductor current.
If the Voltage across RSWCS exceeds its overcurrent threshold (VSWCS_buck or V
SWCS_boost for buck or boost
operation respectively) the device reduces the duty cycle in order to bring the switches current below the
imposed limit.
The current mode controller has a built-in slope compensation as well to prevent sub-harmonic oscillations.
The control loop logic block (LOGIC) provides a PWM signal to four internal gate drivers. The gate drivers
(HSGD1,2 and LSGD1,2) are used to drive external MOSFETs in an H-Bridge setup . Once the soft start expires
a forced CCM regulation mode is performed.
The control loop block diagram displayed in Figure 7 shows a typical constant current application. The voltage
across RFB sets the output current. RIN is used to fix the maximum input current.
The output current is fixed via the SPI parameter (LEDCURRADIM.ADIMVAL = 11110000B = default at 100%)
plus an offset trimming (LEDCURRCAL.CALIBVAL = 0000B = default in the middle of the range). Refer to
Chapter 8.1 for more details.
Datasheet 19 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
Figure 7 Regulator Block Diagram - TLD5541-1
V
IN
+-
+
-
+
-
+-
+
-
+
-
-
+
+
-
LOGIC
CLK
HSGD1
HSGD2
M1
M2 M3
M4
R
SWCS
C
OUT
V
i_REF
SET
R
FB
I
IN
L
OUT
R
COMP
C
COMP
I
OUT
V
OUT
A
1
A
2
A
3
A
5
A
6
A
7
A
8
A
9
SLOPE SELECTION
& Compensation
BOOST
BUCK
IIN2IIN1
R
IN
SWCS
SGND
FBH FBL
COMP
V
COMP
HSGD2
LSGD1
LSGD2
LSGD2
HSGD1
LSGD1
R
filter
C
filter
I
SWCSx
Datasheet 20 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6.2 Adjustable Soft Start Ramp
The soft start routine limits the current through the inductor and the external MOSFET switches during
initialization to minimize potential overshoots at the output.
The soft start routine is applied:
• At first turn on (first PWM rise after EN = High)
• After Output Short to GND or Open Load detection
• After Input Overvoltage detection
The soft start rising edge gradually increases the current of the inductor (LOUT) over tSOFT_START by clamping the
COMP voltage . The soft start ramp is defined by a capacitor placed at the SOFT_START pin.
Selection of the SOFT_START capacitor (CSOFT_START) can be done according to the approximate formula
described in Equation (6.1):
(6.1)
Note: Vss_th_eff is the soft start effectiveness threshold, that depends on load condition. Its value is about
0.7 V for the buck mode and 1.4 V for the boost mode
The SOFT START pin is also used to implement a fault mask and wait-before-retry time, on rising and falling
edge respectively, see and chapter Chapter 10.2 for details.
If an open load or a short on the output is detected, a pull-down current source ISOFT_START_PD (P_6.4.20) is
activated. This current brings down the VSOFT_START until VSOFT_START_RESET (P_6.4.22) is reached, then the pull-up
current source ISOFT_START_PU (P_6.4.19) turns on again. If the fault condition hasn’t been removed until
VSOFT_START_LOFF (P_6.4.21) is reached, the pull-down current source turns back on again, initiating a new cycle.
This will continue until the fault is removed.
If an input overvoltage is detected the soft start is kept low as long as the overvoltage remains.
At first PWMI rise after EN = High, the internal PWM is extended till one of the 2 following condition is reached:
•Until VSOFT_START exceeds VSoft_Start1,2_LOFF
•Until VFBH-FBL exceeds VFBH_FBL_OL
STARTSOFT
PUSTARTSOFT
effthss
STARTSOFT C
I
V
t_
)(_
__
_⋅=
Datasheet 21 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
Figure 8 Soft Start timing diagram on a short to ground detected by the VFB pin
6.3 Switching Frequency setup
The switching frequency can be set from 200 kHz to 700 kHz by an external resistor connected from the FREQ
pin to GND or by supplying a sync signal as specified in chapter Chapter 11.2. Select the switching frequency
with an external resistor according to the graph in Figure 9 or the following approximate formulas.
(6.2)
(6.3)
Figure 9 Switching Frequency fSW versus Frequency Select Resistor to GND RFREQ
V
VFB_S2G
VFB1
SWN
SHORT
DETECTION
Normal
Operation Vout shorted to GND Normal
Operation
Application
Status
V
soft_Start_RESET
V
soft_Start_LOFF
Event
Vout short to GND
applied
Event
Vout short to GND
removed
I
SOFT_START
8 clock cycles
V
SOFT_START
V
soft_Start_reg
I
SOFT_START_PU
I
SOFT_START_PD
8.0
)][(*5375][ −
Ω= kRkHzf FREQSW
25.1
])[(*46023][ −
=Ω kHzfkR SWFREQ
Datasheet 22 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6.4 Operation of 4 switches H-Bridge architecture
Inductor LOUT connects in an H-Bridge configuration with 4 external N channel MOSFETs (M1, M2, M3 & M4)
• Transistor M1 and M3 provides a path between VIN and ground through LOUT in one direction (Driven by top
and bottom gate drivers HSGD1 and LSGD2)
• Transistor M2 and M4 provides a path between VOUT and ground through LOUT in the other direction
(Driven by top and bottom gate drivers HSGD2 and LSGD1)
• Nodes SWN1, SWN2, voltage across RSWCS, input and load currents are also monitored by the TLD5541-1
Figure 10 4 switches H-Bridge architecture Transistor Status summary
Figure 11 4 switches H-Bridge architecture overview
6.4.1 Boost mode (VIN < VOUT)
• M1 is always ON, M2 is always OFF
• Every cycle M3 turns ON first and inductor current is sensed (peak current control)
• M3 stays ON until the upper reference threshold is reached across RSWCS (Energizing)
BOOST
MODE
BUCK-BOOST
MODE
BUCK
MODE
M1 ON PWM PWM
M2 OFF PWM PWM
M3 PWM PWM OFF
M4 PWM PWM ON
L
OUT
SWN1 SWN2
R
SWCS
LSGD1
HSGD1
LSGD2
HSGD2
M3
M4
M2
M1
V
IN
V
OUT
Datasheet 23 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
• M3 turns OFF, M4 turns ON until the end of the cycle (Recirculation)
• Switches M3 and M4 alternate, behaving like a typical synchronous boost Regulator (see Figure 12)
Figure 12 4 switches H-Bridge architecture in BOOST mode
Simplified comparison of 4 switches H-Bridge architecture to traditional asynchronous Boost approach.
• M2 is always OFF in this mode (open)
• M1 is always ON in this mode (closed connection of inductor to VIN)
• M4 acts as a synchronous diode, with significantly lower conduction power losses (I2 x RDSON vs. 0.7 V x I)
Note: Diode is source of losses and lower system efficiency!
Figure 13 4 switches H-Bridge architecture in BOOST mode compared to standard async Booster
6.4.2 Buck mode (VIN > VOUT)
• M4 is always ON, M3 is always OFF
• Every cycle M2 turns ON and inductor current is sensed (valley current control)
• M2 stays ON until the lower reference threshold is reached across RSWCS (Recirculation)
(2) Recirculation
(1) Energizing
L
OUT
SWN1 SWN2
R
SWCS
LSGD1
HSGD1
LSGD2
HSGD2
M3
M4
M2
M1
V
IN
V
OUT
M1+M3
M1
+
M4
I
LOUT
t
M1+M3
M1
+
M4
M1+M3
M1
+
M4
OFF
ON
LSGD2
HSGD2
M3
M4
LSGD1
M2
(OFF)
HSGD1
M1 (ON)
R
SWCS
V
IN
V
OUT
L
OUT
M3
D1
V
IN
V
OUT
L
OUT
R
SWCS
a) 4 switch architecture BOOSTER b) standard asynchronous BOOSTER
Datasheet 24 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
• M2 turns OFF, M1 turns ON until the end of the cycle (Energizing)
• Switches M1 and M2 alternate, behaving like a typical synchronous BUCK Regulator (see Figure 14)
Figure 14 4 switches H-Bridge architecture in BUCK mode
Simplified comparison of 4 switches architecture to traditional asynchronous Buck approach.
• M3 is always OFF in this mode (open).
• M4 is always ON in this mode (closed connection inductor to VOUT).
• M2 acts as a synchronous diode, with significantly lower conduction losses (I2 x RDSON vs. 0.7 V x I)
Figure 15 4 switches H-Bridge architecture in BUCK mode compared to standard async BUCK
6.4.3 Buck-Boost mode (VIN ~ VOUT)
•When V
IN is close to VOUT the controller is in Buck-Boost operation
• All switches are switching in buck-boost operation. The direct energy transfer from the Input to the output
(M1+M4 = ON) is beneficial to reduce ripple current and improves the energy efficiency of the Buck-Boost
control scheme
• The two buck boost waveforms and switching behaviors are displayed in Figure 16 below
L
OUT
SWN1 SWN2
R
SWCS
LSGD1
HSGD1
LSGD2
HSGD2
M3
M4
M2
M1
V
IN
V
OUT
(4) Recirculation
(3) Energizing
M2+M4
M1
+
M4
M2+M4
I
LOUT
t
M1
+
M4
M2+M4
M1
+
M4
OFF
ON
LSGD1
HSGD1
M2
M1
LSGD2
M3
(OFF)
HSGD2
M4
(ON)
HSGD1
M1
D1
R
SWCS
V
IN
V
OUT
L
OUT
V
IN
V
OUT
L
OUT
a) 4 switch architecture BUCK b) standard asynchronous BUCK
Datasheet 25 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
Figure 16 4 switches H-Bridge architecture in BUCK-BOOST mode
6.5 Fast Output Discharge Operation Mode - Multi Floating Switches Topology
Multiple light functions can be driven by a single DC/DC converter adopting a Multi Floating Switch (MFS)
topology. In a MFS topology, each LED Function is connected in series and can be independently turned off via
a bypass switch. Because of the series connections, all the functions are driven with the same current .
Different brightness can be achieved with individual PWM duty cycles.
In order to drive different LED functions in this topology, a Buck Boost converter is probably needed. A single
stage buck boost topology has high efficiency buts requires several µF of output capacitance (COUT). The extra
voltage present on this capacitor, when shorting one function to turn it off, may create a current spike in the
LEDs that have to remain on.
The TLD5541-1 has a dedicated state machine which controls a fast discharge of the output cap to a desired
fraction of the initial output voltage. This Fast Output Discharge feature (F.D.), if carefully configured, limits
the current spike during load jump events preventing LED damage.
An Example of the Multi Floating Switch topology architecture and operation are shown in Figure 17
Figure 17 Multi Floating Switch topology: operation sequence on 2 Functions: (F1+F2) to (F2)
L
OUT
SWN1 SWN2
R
SWCS
LSGD1
HSGD1
LSGD2
HSGD2
M3
M4
M2
M1
V
IN
V
OUT
(3) Recirculation
(4) Direct Transfer
(2) Direct Transfer
(1) Energizing
M1
+
M3
M1
+
M4
I
LOUT
t
VIN ≤ VOUT
M2+ M4
M1
+
M4
M1
+
M3
M1
+
M4
M2+ M4
M1
+
M4
M1
+
M3
M1
+
M4
M2+ M4
M1
+
M4
VIN ≥ VOUT
M2
+
M4
M1
+
M4
I
LOUT
t
M1+ M3
M1
+
M4
M2
+
M4
M1
+
M4
M1+ M3
M1
+
M4
M2
+
M4
M1
+
M4
M1+ M3
M1
+
M4
External MOSFET
Control via µC
External MOSFET
Control via µC
DC/DC
LITIX FLEX
C
OUT
3x4.7µF
ON
ON
External MOSFET
Control via µC
External MOSFET
Control via µC
DC/DC
LITIX FLEX
Vout
Initial
Vout
Final
External MOSFET
Control via µC
External MOSFET
Control via µC
DC/DC
LITIX FLEX
Vout
Disharging
C
IN
V
BAT
R
VFBH
R
VFBL
To VFB
C
OUT
3x4.7µF
R
VFBH
R
VFBL
To VFB
C
OUT
3x4.7µF
R
VFBH
R
VFBL
To VFB
ON
OFF
OFF
OFF
INITIAL CONDITION FINAL CONDITIONFAST DISCHARG E
F1
F2
F1
F2
F1
F2
I F1
I F2
I F2
I Disch
(A) (B) (C)
Datasheet 26 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
The F.D. operation consists of discharging the capacitor COUT to the final load voltage (Figure 17-B) before the
bypass switch closure. The external Microcontroller Software has to take care of the synchronization between
the TLD5541-1 F.D. operation and the bypass Switches activation.
The discharged energy from COUT is recovered back to the Input capacitor CIN which could cause a small
overshoot on the CIN itself. This feature allows high efficiency designs also when PWM operation with repetitive
Load Jumps is needed.
The F.D. feature is needed when a negative VOUT step is performed, so when one or more LED functions are
switched off. If additional LED functions are turned on, increasing the output voltage, the F.D. does not have
to be used. In MFS topologies, a short interruption of the current is observed during the Load Transitions
(either positive or negative) in all the functions, until VOUT is stable and the device control loop is able to
provide the target output current.
We will refer to any Voltage-Current or Load configuration just before the Load Jump as "Initial" (Figure 17-A),
while we will refer to any value after the system is in the new Load configuration as "Final" (Figure 17-C).
Set the Target COUT discharge voltage
The Target output voltage (VOUTFinal) of an F.D. operation is communicated to the TLD5541-1 as a fraction of the
VOUT at the beginning of the Jump (VOUTInitial), and not as an absolute Value.
In order to quickly discharge the output Capacitor to a desired Ratio of the initial voltage, two SPI commands
have to be sent to the TLD5541-1 register MFSSETUP1.
• The first is to write in the MFSSETUP1.LEDCHAIN the Ratio Denominator
• The second is to write in the MFSSETUP1 register the Ratio Numerator and the Start Of Multi Floating
Switch, respectively in the LEDCHAIN and SOMFS bitfields
After the second command, as soon as the Chip select is raised the F.D. begins. The final output voltage of the
F.D. operation, after a MFS routine is correctly performed, will be approximately:
(6.4)
The MFSSETUP1.LEDCHAIN registers sets both the LED Ratio during F.D and the short circuit threshold. For
this reason both the correct VOUT Ratio and correct short circuit protection voltage have to be set according to
the LED Load. See Table 10 for reference.
To have the correct short circuit protection on a F.D. operation, the first LEDCHAIN value sent via SPI (Ratio
Denominator), should also guarantee an adequate short circuit detection for the Initial Load. The second
LEDCHAIN value (Ratio Numerator + SOMFS) should guarantee correct Short circuit detection for the Final
Load. For more information about short circuit protection, see Chapter 10.2.1.
Example:
If the VFB voltage divider for the Short circuit detection is set like in Table 10.
In order to jump from 6LED (18 V) to 2LEDs (6 V), the Ratio is 1/3 of initial voltage.
So the 2 SPI commands that have to be sent are:
Spi command 1: set MFSSETUP1 to 0x06 (Ratio Denominator = 6, VShort_LED = 16.8 V)
Spi command 2: set MFSSETUP1 to 0x22 (Ratio Numerator+SOMFS = 0x02+0x20, VShort_LED= 4.6 V )
Preparation time tprep:
The TLD5541-1 enables the user to set a delay between the beginning of the Load Jump and the moment in
which the switching activity will restart to provide output current. This delay is needed to safely close the
OUTInitialOUTFinal V
inatorRatioDenom
atorRatioNumer
V⋅=
Datasheet 27 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
bypass switches (to short the LEDs) for the new Light configuration, after the Final VOUT is reached and before
the normal switching activity would again raise the output voltage. See Figure 18.
The Preparation time has to be sufficient for the capacitors COUT and CCOMP to be discharged to the desired
value. The COUT discharge time depends heavily on: IDISCH, COUT size, VOUT Initial, VOUTFinal and VIN, so all those
values have to be considered when setting the preparation time. In order to set a preparation time on the
TLD5541-1, a SPI command has to be sent to the register MFSSETUP2.MFSDLY).
The Equation (6.5) below describes the relationship between the switching frequency fSW and the
MFSSETUP2.MFSDLY register value.
(6.5)
For SPI command details refer to Chapter 12.6.
Fast Discharge Phase
After programming the desired output voltage Ratio via SPI , the right Preparation Time and activating the
state machine (MFSSETUP1.SOMFS = HIGH) the TLD5541-1 inverts the inductor current IL and keeps it at the
switch current limit ISwLim until the VOUT reaches the desired target.
(6.6)
Figure 18 displays the relation of inductor current IL and the output voltage VOUT during a fast output discharge
operation mode.
Figure 18 Fast Output Discharge timing diagram
[]
dec
SW
prep MFSDLY
f
t)(2
1+⋅=
SWCS
boostSWCS
SwLim R
V
I_
=
I
L
T
DISCHARGE
T
PREP
I
SwLim
V
OUT
V
INITIAL
V
FINAL
SPI CSN
EOMFS
Break
Low
Fast Output Discharge Current
Recovery
External
Mosfet
Closure
Normal Switching
activity F1 on
Normal Switching
activity F1+F2 on
I F1
I F2 No current at the Load
during F.O.D.
SPI COMMANDS
LED N. INITIA L LE D N. FINAL
+ SOMF
TPREP
Datasheet 28 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
If the discharge current limit ISwLim needs to be reduced, the MFSSETUP1.ILIM_HALF_MFS bit can be used
to cut it in half (only during the F.D. phase and not in normal operation), see SPI Chapter for further details
Chapter 12.6.
Setting the EA_IOUT_MFS bit will reduce (only during the F.D. phase) the saturation current of the error
amplifier A6 that discharges the Comp capacitor.
Once VOUT reaches the desired target, the current recovery phase brings IL from a negative value back to 0 A.
When the current recovery phase has ended, an internal SPI flag (MFSSETUP1.EOMFS) is set to HIGH and the
device stays in “Brake-Low condition” (both Lowside gatedrivers = ON) until the programmed preparation
time (MFSSETUP2.MFSDLY) expires and the TLD5541-1 starts automatically switching again. Figure 18
displays one Fast Output Discharge cycle.
The effective COUT discharge current is smaller than the Inductor current and it depends on the application
condition, see Equation (6.7).
(6.7)
Sequence of operations to perform a Fast Output Discharge
In order to perform a F.D operation, the user has to :
• Set via SPI an adequate Preparation Time
•Send via SPI to MFSSETUP1.LEDCHAIN the Ratio Denominator.
•Send via SPI to MFSSETUP1.LEDCHAIN the Ration Numerator + SOMFS
• Wait until the preparation time is expired (so the Vout has reached the target value)
• Adjust the Floating switches to the new configuration
6.6 Flexible current sense
The flexible current sense implementation enables highside and lowside current sensing.
The Figure 19 displays the application examples for the highside and lowside current sense concept.
Figure 19 Highside and lowside current sensing - TLD5541-1
2
2⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
⋅−⋅
+
=
oi
i
SW
o
swLim
io
i
DISCH VV
V
Lf
V
I
VV
V
I
V
IN
Highside
Sensing
V
IN
Lowside
Sensing
FBH
FBL FBH
FBL
Datasheet 29 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6.7 Programming Output Voltage (Constant Voltage Regulation)
For a voltage regulator, the output voltage can be set by selecting the values RFB1, RFB2 and RFB3 according to
the following Equation (6.8):
(6.8)
After the output voltage is fixed via the resistor divider, the value can be changed via the Analog Dimming bits
ADIMVAL.
If Analog dimming is performed, due to the variations on the IFBL (IFBL_HSS (P_6.4.9) and IFBL_LSS (P_6.4.40))
current on the entire voltage spanning, a non linearity on the output voltage may be observed. To minimize
this effect RFBx resistors should be properly dimensioned.
Figure 20 Programming Output Voltage (Constant Voltage Regulation)
FBLFBHFBFBL
FB
FBLFBH
FB
FB
FBLFBH
FBHOUT VRI
R
V
R
R
V
IV −
−− +⋅
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛−+⋅
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+= 3
2
1
2
FBH
VOUT
R
FB1
R
FB2
FBL
R
FB3
I
FBH
I
FBL
Datasheet 30 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
6.8 Electrical Characteristics
Table 6 EC Regulator
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Regulator:
V(FBH-FBL) threshold V(FBH-FBL) 145.5 150 154.5 mV ADIM.ADIMVAL =
11110000B;
P_6.4.1
V(FBH-FBL) threshold @ analog
dimming 10%
V(FBH-
FBL)_10
12 15 18 mV ADIM.ADIMVAL =
00011000B;
Calibration
Procedure not
performed
P_6.4.5
FBH Bias current @ highside
sensing setup
IFBH_HSS 65 110 155 µA 1)VFBL = 7 V;
VFBH - FBL = 150 mV;
P_6.4.8
FBL Bias current @ highside
sensing setup
IFBL_HSS 17 30 43 µA 1)VFBL = 7 V;
VFBH - FBL = 150 mV;
P_6.4.9
FBH Bias current @ lowside
sensing setup
IFBH_LSS -7.5 -4 -2.5 µA 1)VFBL = 0 V;
VFBH - FBL = 150 mV;
P_6.4.39
FBL Bias current @ lowside
sensing setup
IFBL_LSS -45 -30 -20 µA 1)VFBL = 0 V;
VFBH - FBL = 150 mV;
P_6.4.40
FBH-FBL High Side sensing
entry threshold
VFBH_HSS_in
c
-2-V
1)VFBH1 increasing; P_6.9.1
FBH-FBL High Side sensing exit
threshold
VFBH_HSS_d
ec
-1.75-V
1)VFBH decreasing; P_6.9.2
OUT Current sense Amplifier gmIFBxgm – 890 – µS 1) P_6.4.10
Output Monitor Voltage VIOUTMON 1.33 1.4 1.47 V VFBH - FBL = 150 mV; P_6.4.11
Maximum BOOST Duty Cycle DBOOST_MA
X
89 91 93 % 1)fsw = 300 kHZ; P_6.4.12
Input Current Sense threshold
VIIN1-IIN2
VIIN1-IIN2 46 50 54 mV – P_6.4.13
Input Current sense Amplifier
gm
IIN_gm –2.12–mS
1) P_6.4.14
Input current Monitor Voltage VIINMON 0.95 1 1.05 V 1)VIIN1 - IIN2 = 50 mV;
VIIN1 = VVIN(ON) to 55 V;
P_6.4.15
Switch Peak Over Current
Threshold - BOOST
VSWCS_boost 40 50 60 mV 1) P_10.8.1
5
Switch Peak Over Current
Threshold - BUCK
VSWCS_buck -60 -50 -40 mV 1) P_10.8.1
6
Soft Start
Soft Start pull up current ISoft_Start_P
U
22 26 32 µA VSoft_Start = 1 V; P_6.4.19
Datasheet 31 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
Soft Start pull down current ISoft_Start_P
D
2.2 2.6 3.2 µA VSoft_Start = 1 V; P_6.4.20
Soft Start Latch-OFF Threshold VSoft_Start_L
OFF
1.65 1.75 1.85 V – P_6.4.21
Soft Start Reset Threshold VSoft_Start_R
ESET
0.1 0.2 0.3 V – P_6.4.22
Soft Start Voltage during
regulation
VSoft_Start_r
eg
1.9 2 2.1 V 1)No Faults P_6.9.3
Oscillator
Switching Frequency fSW 285 300 315 kHz Tj = 25°C;
RFREQ= 37.4 kΩ;
P_6.4.23
SYNC Frequency fSYNC 200 – 700 kHz – P_6.4.24
SYNC
Turn On Threshold
VSYNC,ON 2––V– P_6.4.25
SYNC
Turn Off Threshold
VSYNC,OFF ––0.8V– P_6.4.26
SYNC
High Input Current
ISYNC,H 15 30 45 µA VSYNC = 2.0 V; P_6.4.62
SYNC
Low Input Current
ISYNC,L 6 1218µAVSYNC = 0.8 V; P_6.4.63
Gate Driver for external Switch
Gate Driver undervoltage
threshold VBST1,2-
VSWN1,2_UVth
VBST1,2-
VSWN1,2_UVt
h
3.4 – 4 V VBST1,2 - VSWN1,2
decreasing;
P_6.4.64
HSGD1,2 NMOS driver on-state
resistance (Gate Pull Up)
RDS(ON_PU)
HS
1.4 2.3 3.7 ΩVBST1,2 - VSWN1,2 = 5 V;
Isource = 100 mA;
P_6.4.28
HSGD1,2 NMOS driver on-state
resistance (Gate Pull Down)
RDS(ON_PD)
HS
0.6 1.2 2.2 ΩVBST1,2 - VSWN1,2 = 5 V;
Isink = 100 mA;
P_6.4.29
LSGD1,2 NMOS driver on-state
resistance (Gate Pull Up)
RDS(ON_PU)
LS
1.4 2.3 3.7 ΩVIVCC_EXT = 5 V;
Isource = 100 mA;
P_6.4.30
LSGD1,2 NMOS driver on-state
resistance (Gate Pull Down)
RDS(ON_PD)L
S
0.4 1.2 1.8 ΩVIVCC_EXT = 5 V;
Isink = 100 mA;
P_6.4.31
HSGD1,2 Gate Driver peak
sourcing current
IHSGD1,2_SR
C
380 – – mA 1)
VHSGD1,2 - VSWN1,2 = 1 V
to 4 V;
VBST1,2 - VSWN1,2 = 5 V
P_6.4.32
Table 6 EC Regulator (cont’d)
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 32 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Regulator Description
HSGD1,2 Gate Driver peak
sinking current
IHSGD1,2_SN
K
410 – – mA 1)
VHSGD1,2 - VSWN1,2 = 4 V
to 1 V;
VBST1,2 - VSWN1,2 = 5 V
P_6.4.33
LSGD1,2 Gate Driver peak
sourcing current
ILSGD1,2_SRC 370 – – mA 1)
VLSGD1,2 = 1 V to 4 V;
VIVCC_EXT = 5 V;
P_6.4.34
LSGD1,2 Gate Driver peak
sinking current
ILSGD1,2_SN
K
550 – – mA 1)
VLSGD1,2 = 4V to 1V;
VIVCC_EXT = 5 V;
P_6.4.35
LSGD1,2 OFF to HSGD1,2 ON
delay
tLSOFF-
HSON_delay
15 30 40 ns 1) P_6.4.36
HSGD1,2 OFF to LSGD1,2 ON
delay
tHSOFF-
LSON_delay
35 60 75 ns 1) P_6.4.37
1) Not subject to production test, specified by design
Table 6 EC Regulator (cont’d)
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 33 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Digital Dimming Function
7 Digital Dimming Function
PWM dimming is adopted to vary LEDs brightness with greatly reduced chromaticity shift. PWM dimming
achieves brightness reduction by varying the duty cycle of a constant current in the LED string.
7.1 Description
A PWM signal can be transmitted to the TLD5541-1 as described below.
PWM via direct interface
The PWMI pin can be fed with a pulse width modulated (PWM) signals, thisenables when HIGH and disables
when LOWthe gate drivers of the main switches.
Figure 21 Digital Dimming Overview
Note: In Register REGUSETMON.REGUMODFB the regulation mode can be read. During PWMI = LOW the
SPI will always deliver the Regulation mode which was present at PWMI = HIGH as actual regulation
mode, instead of “no Regulation”.
To avoid unwanted output overshoots due to not soft start assisted startups, PWM dimming in LOW state
should not be used to suspend the output current for long time intervals. To stop in a safe manner
DVCCTRL.IDLE=HIGH or EN/INUVLO=LOW can be used.
VDD
CSN
SI
SO
SCLK AGND
SPI
+3.3V or +5V
VSS
µC
PWMIDigital dimming
PWM
Datasheet 34 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Digital Dimming Function
Figure 22 Timing Diagram LED Dimming and Start up behavior example ( VVDD and VVIN stable in the
functional range and not during startup)
V
EN/INUVLO
V
IVCC _EXT_RTH ,d
+V
IVCC X_HYST
V
IOUTMON
I
LED
V
EN/ INUVLOth
t
t
t
t
Normal
Gate ON
Diagnosis ON
Dim
Gate OFF
Diag OFF
Power ON
Normal
Gate ON
Diag ON
t
ACTIVE
V
PWMI
V
PWMI,ON
V
PWMI,OFF
t
T
PWMI
t
PWMI,H
Dim
Gate OFF
Diag OFF
Dim
Gate OFF
Diag OFF
Normal
Gate ON
Diag ON
Softstart
t
200mV
Switching
activity
Datasheet 35 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Digital Dimming Function
7.2 Electrical Characteristics
Table 7 EC Digital Dimming
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
PWMI Input:
PWMI
Turn On Threshold
VPWMI,ON 2–– V– P_7.2.1
PWMI
Turn Off Threshold
VPWMI,OFF ––0.8V– P_7.2.2
PWMI
High Input Current
IPWMI,H 15 30 45 µA VPWMI = 2.0 V; P_7.2.4
PWMI
Low Input Current
IPWMI,L 61218µAVPWMI = 0.8 V; P_7.2.5
Datasheet 36 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Analog Dimming
8 Analog Dimming
The analog dimming feature allows further control of the output current. This approach is used to:
• Reduce the default current in a narrow range to adjust to different binning classes of the used LEDs.
• Adjust the load current to enable the usage of one hardware for several LED types where different current
levels are required.
• Reduce the current at high temperatures (protect LEDs from overtemperature).
• Reduce the current at low input voltages (for example, cranking-pulse breakdown of the supply or power
derating).
8.1 Description
The analog dimming feature is adjusting the average load current level via the control of the feedback error
Amplifier voltage (VFBH-FBL).
The current adjustment is done via a 8BIT SPI parameter (LEDCURRADIM.ADIMVAL). Refer to Figure 23.
Figure 23 Analog Dimming Overview
Analog dimming adjustment during Limp Home state:
To enter in Limp Home state the LHI pin must be HIGH.
Note: If the PWMI and the EN/INUVLO are not set to HIGH, it is not possible to enable switching, even during
Limp Home state.
In Limp Home state the analog dimming control is done via the SET pin. A Resistor divider between
IVCC/IVCC_EXT, SET and GND is used to fix a default load current/voltage value (refer to Figure 24 below).
V
FBH-FBL
150mV
8 BIT SPI adjustment
Bitcode
b´11110000
0
Datasheet 37 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Analog Dimming
Figure 24 Limp Home state schematic overview
Using the SET pin to adjust the output current:
The SET pin is ignored if the device is not in Limp Home state.
For the calculation of the output current IOUT the following Equation (8.1) is used:
(8.1)
A decrease of the average output current can be achieved by controlling the voltage at the SET pin (VSET)
between 0.2 V and 1.4 V. The mathematical relation is given in the Equation (8.2) below:
(8.2)
If VSET is 200 mV (typ.) the LED current is only determined by the internal offset voltages of the comparators.
To assure the switching activity is stopped and IOUT = 0, VSET has to be < 100 mV, see Figure 25.
CSN
SI
SO
SCLK
VIN
AGND
L
OUT
C
OUT
IVCC
BST1
BST2
HSGD1
LSGD1
SWN1
LSGD2
HSGD2
SWN2
FBH
FBL
SWCS
SGND
PGND1
C
IVCC
C
BST1
C
BST2
D
1
D
2
M
1
M
2
M
3
M
4
C
IN
LHI
PGND2
VSS
VFB
IVCC_ext
LIMPHOME
PWMI_LH
FAIL SAFE Circuit
FAIL SAFE Circuit
R
FB
R
VFBH
R
VFBL
R
SWCS
SET
R
5
R
4
IVCC
Load
R
FB2
R
FB1
R
FB3
Current
Regulation
Voltage
Regulation
PWMI
default output
current/voltage
adjustment
HIGH
Set HIGH to
activate output
SPI Writing
disabled during
Limp Home state
> V
IN(PO)
> V
IVCC_EXT_RTH,d
EN/INUVLO
FB
FBLFBH
OUT R
VV
I
−
=
8
200
⋅
−
=
FB
SET
OUT R
mVV
I
Datasheet 38 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Analog Dimming
Figure 25 Analog Dimming Overview
8.2 LED current calibration procedure
The LED current calibration procedure improves the accuracy during analog dimming. In order to be most
effective, this routine has to be performed in the application, when the TLD5541-1 temperature and the output
voltage are the ones in which the driver has to be accurate. The output current must be 0 during the procedure
run. The optimum should be to re-calibrate the output periodically every time the application has PWMI=LOW
for a sufficent long time .
Current calibration procedure:
• Power the Load with a low analog dimming value (for example 10%)
• Set PWMI = LOW and disconnect the Load at the same time (to avoid Vout drifts from operating conditions
and bring the output current to 0)
• Quickly (to avoid Vout drifts) µC enables the calibration routine: DVCCTRL.ENCAL = HIGH
• Quickly (to avoid Vout drifts) µC starts the calibration: LEDCURRCAL.SOCAL = HIGH
• Waiting time (needed to internally perform the calibration routine) → aprox. 200 µs
• TLD5541-1 will set the FLAG: LEDCURRCAL.EOCAL = HIGH, when calibration routine has finished
• Reconnect the load
• The Output current is automatically adjusted to a low offset and more accurate analog dimming value
Once the Calibration routine is correctly performed, the output current accuracy with analog dimming = 10%
(LEDCURRADIM.ADIMVAL = 24) is 10%.
The Calibration routine is not affecting the accuracy at 100% analog dimming.
The ENCAL Bits affect both device operation and CALIBVAL reading result:
• ENCAL = HIGH: the calibration result coming from the routine is used by internal circuitry and can be read
back from CALIBVAL
• ENCAL = LOW: SPI value written in CALIBVAL is used by internal circuitry and can be read back; calibration
routine start is inhibited
As a result, μC can use a stored result from a previously performed calibration to directly impose the desired
value without waiting for a new routine to finish.
150mV
Analog Dimming Enabled
0mV
Analog Dimming
Disabled
200mV 1.4V 1.5V
100mV
V
FBH-FBL
V
SET
Datasheet 39 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Analog Dimming
Figure 26 LED current Accuracy Calibration Overview
8.3 Electrical Characteristics
Table 8 EC Analog Dimming
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Source current on SET Pin ISET_source ––1µA
1)VSET = 0.2 V to 1.4 V;
1) Specified by design: not subject to production test.
P_8.3.4
R
FB
FBH
FBL
+
-
I
OUT_sense
I
DC_offset
I
IN_feedback
V
ref_int
+
-
Latch
ADC Latch
ADC CLK
ADC out
DAC
8 bit resolution
4 bit calibration
V
int_supply
+
-
EA
COMP
V_sense_out
V_sense_in
Logic
2Bit Monitoring
ADC CLK
V
FBH-FBL
OUT H-Bridge
to LED
Load
Datasheet 40 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Linear Regulator
9 Linear Regulator
The TLD5541-1 features an integrated voltage regulator for the supply of the internal gate driver stages.
Furthermore an external voltage regulator can be connected to the IVCC_EXT pin to achieve an alternative
gate driver supply if required.
9.1 IVCC Description
When the IVCC pin is connected to the IVCC_EXT pin, the internal linear voltage regulator supplies the internal
gate drivers with a typical voltage of 5 V and current up to ILIM (P_9.2.2). An external output capacitor with low
ESR is required on pin IVCC for stability and buffering transient load currents. During normal operation the
external MOSFET switches will draw transient currents from the linear regulator and its output capacitor
(Figure 27, drawing A). Proper sizing of the output capacitor must be considered to supply sufficient peak
current to the gate of the external MOSFET switches. A minimum capacitance value is given in parameter CIVCC
(P_9.2.4).
Alternative IVCC_EXT Supply Concept:
The IVCC_EXT pin can be used for an external voltage supply to alternatively supply the MOSFET Gate drivers.
This concept is beneficial in the high input voltage range to avoid power losses in the IC (Figure 27, drawing B).
Integrated undervoltage protection for the external switching MOSFET:
An integrated undervoltage reset threshold circuit monitors the linear regulator output voltage. This
undervoltage reset threshold circuit will turn OFF the gate drivers in case the IVCC or IVCC_EXT voltage falls
below their undervoltage Reset switch OFF Thresholds VIVCC_RTH,d (P_9.2.9) and VIVCC_EXT_RTH,d (P_9.2.5).
In Limp Home state the Undervoltage Reset switch OFF threshold for the IVCC has no impact on the switching
activity.
The Undervoltage Reset threshold for the IVCC and the IVCC_EXT pins help to protect the external switches
from excessive power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of the
external logic level N-channel MOSFETs.
Figure 27 Voltage Regulator Configurations
Internal
VREG
Gate Drivers
V
IN
IVCC
IVCC_EXT
A B
External
VREG
Power
On Reset
Internal
VREG
Gate Drivers
V
IN
IVCC
IVCC_EXT
Power
On Reset
Datasheet 41 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Linear Regulator
9.2 Electrical Characteristics
Table 9 EC Line Regulator
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
IVCC
Output Voltage VIVCC 4.8 5 5.2 V VIN= 13.5 V;
0.1 mA ≤ IIVCC ≤ 50 mA;
P_9.2.1
Output Current
Limitation
ILIM 70 90 110 mA 1)
VIVCC = 4 V;
1) Not subject to production test, specified by design
P_9.2.2
Drop out Voltage (VIN -
VIVCC)
VDR – 200 350 mV VIN = 5 V;
IIVCC = 10 mA;
P_9.2.3
IVCC Buffer Capacitor CIVCC 10 – – µF 1) 2)
2) Minimum value given is needed for regulator stability; application might need higher capacitance than the minimum.
Use capacitors with LOW ESR.
P_9.2.4
IVCC_EXT Undervoltage
Reset switch OFF
Threshold
VIVCC_EXT_R
TH,d
3.7 3.9 4.1 V 3)
VIVCC_EXT decreasing;
3) Selection of external switching MOSFET is crucial. VIVCC_EXT_RTH,d and VIVCC_RTH,d min. as worst case VGS must be
considered.
P_9.2.5
IVCC Undervoltage Reset
switch OFF Threshold
VIVCC_RTH,d 3.7 3.9 4.1 V 3)
VIVCC decreasing;
P_9.2.9
IVCC and IVCC_EXT
Undervoltage Hysterisis
VIVCCX_HYST 0.3 0.33 0.36 V VIVCC increasing;
VIVCC_EXT increasing;
P_9.2.6
Datasheet 42 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10 Protection and Diagnostic Functions
10.1 Description
The TLD5541-1 has integrated circuits to diagnose and protect against overvoltage, open load, short circuits
of the load and overtemperature faults. Furthermore, the device provides a 2 Bit information of ILED, IIN by the
SPI to the µC.
In IDLE state, only the Over temperature Shut Down, Over Temperature Warning, IVCC or IVCC_EXT
Undervoltage Monitor, VDD or VEN/INUVLO Undervoltage Monitor are reported according to specifications.
In Figure 28 a summary of the protection, diagnostic and monitor functions is displayed.
Figure 28 Protection, Diagnostic and Monitoring Overview - TLD5541-1
Note: A device Overtemperature event overrules all other fault events!
Monitoring
Overvoltages
Open Load
Device
Overtemperature
Protection and Diagnostic
OR
No output current
Linear Regulators
OFF
(only IVCC disabled
in case of
overtemperature)
Input
Undervoltage
Short at the Load
OR
IOUT
IIN
Read-back via
SPI
2BIT data
Mode Indication
IOUT
IIN
IOUTMON
IINMON
KILIS Factor 20
KILIS Factor 8
SPI STD
Diagnosis
SPI
SPI
SPI
2BIT data
2BIT data
SPI
Datasheet 43 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10.2 Output Overvoltage, Open Load, Short circuit protection
The VFB pin measures the voltage on the application output and in accordance with the populated resistor
divider, short to ground, open load and output overvoltage thresholds are set. Refer to Figure 30 and Figure 29
for more details.
Figure 29 Definition of Protection Ranges
Figure 30 VFB Protection Pin - Overview
10.2.1 Short Circuit protection
The device detects a short circuit at the output if this condition is verified:
• The pin VFB falls below the threshold voltage VVFB_S2G for at least 8 clock cycles
V
FB
V
FB_OV TH
= fixed
V
FB_OL,rise
= fixed
V
OUT
V
FB_S2G
= adjustable
Short
Circuit
Overvoltage
Threshold can be
adjusted via SPI
e.g. 50V
Open LOAD
Normal Operation
L
OUT
C
OUT
V
IN
IVCC
BST1
BST2
HSGD1
LSGD1
SWN1
LSGD2
HSGD2
SWN2
FBH
FBL
SWCS
SGND
PGND
C
IVC C
R
SWCS
C
BST1
C
BST2
D
1
D
2
M
1
M
2
M
3
M
4
R
FB
VFB
V
VFB_OVTH
V
VFB_OL,rise
V
VFB_S2G
VOUT
R
VFBH
R
VFBL
Datasheet 44 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
During the rising edge of the Soft Start the short circuit detection via VFB is ignored until VSOFT_START_LOFF (see
Figure 8).
After a short circuit detection, the SPI flag (SHRTLED) in the STD diagnosis register is set to HIGH and the gate
drivers stop delivering output current (Break-Low condition, both LS MOSFETs ON). The Device will auto
restart with the soft start routine described in Chapter 6.2. The dedicated diagnosis flag (SHRTLED) will be
cleared after the next reading cycle of the STD diagnosis.
A voltage divider between VOUT, VFB pin and AGND is used to adjust the application short circuit thresholds
following Equation (10.1).
(10.1)
The short circuit threshold voltage VVFB_S2G (P_10.8.1) is set by 4-Bits in the SPI register
MFSSETUP1.LEDCHAIN as shown in Table 10.
The configurable short circuit threshold is especially useful in 2 types of applications:
1) Multifloat switch applications:
Multifloat switch applications are applications with a series connection of LEDs and parallel transistors to
switch ON and OFF single (or multiple) LEDs in a string. The built in feature “fast output discharge operation
mode” enables such applications but the short circuit threshold has to be adjusted in accordance to the LED
changes. This synchronization is needed to avoid wrong short circuit detection during load step variations.
For this reason the register MFSSETUP1.LEDCHAIN selects the short circuit threshold register but is also
related to the “fast dynamic behavior feature”. For more Info on the “fast output discharge operation mode”
please refer to Chapter 6.5.
2) Standard applications which require a large output voltage range:
The adjustable short circuit threshold VVFB_S2G enables applications with a large VOUT operation range.
The MFSSETUP1.LEDCHAIN register allows configuration of the short circuit threshold in 16 Steps.
The step size depends on the sizing of the RVFBH and RVFBL resistors.
In order to have proper short circuit detection MFSSETUP1.LEDCHAIN should be calculated as shown in
Equation (10.2).
(10.2)
Where KVFB=RVFBL/(RVFBH + RVFBL) and Vshort_led is the desired short circuit threshold value at VOUT.
The Table 10 below displays the relationship between the bitcode and the short circuit threshold voltage
VVFB_S2G based on an example (resistor divider RVFBH = 59 kΩ, RVFBL = 1.5 kΩ).
The application overvoltage protection is instead not dependent by LEDCHAIN and, based on the
Equation (10.3) for this particular resistor divider is fixed to 59.3 V.
Table 10 Adjustable Short Circuit threshold overview
LEDCHAIN VOUT_OVLO k = RVFBL / (RVFBH
+ RVFBL)
Vopen_load Vshort_led (V)
(VFB_S2G / k)
VVFB_S2G(V) Default
Condition
1 59.3 0.025 54.4 1.5 0.038
2 59.3 0.025 54.4 4.6 0.113
3 59.3 0.025 54.4 7.6 0.188
4 59.3 0.025 54.4 10.7 0.263
5 59.3 0.025 54.4 13.7 0.338
VFBL
VFBLVFBH
GSVFBledshort R
RR
VV
+
⋅= 2__
=
ℎ
_
∙
−
38
75
+
1
Datasheet 45 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
During Limp Home state the short circuit threshold VVFB_S2G is fixed at the default value (VVFB_S2G / VVFB_OVTH),
approx. 1/3 of the fixed overvoltage protection circuit in the application. There is no relationship between the
analog dimming feature at VSET pin and the VVFB_S2G threshold. The customer must take care by adjusting the
default voltage at SET pin to program the VOUT be higher than the default short circuit threshold.
During start-up the TLD5541-1 ignores the detection of a short circuit or an open load until the soft-start
capacitor reaches 1.75 V. To prevent false tripping after startup, a large enough soft-start capacitor must be
used to allow the output to get up to approximately 50% of the final value.
Note: If the short circuit condition disappears, the device will re-start with the soft start routine as
described in Chapter 6.2.
10.2.2 Overvoltage Protection
A voltage divider between VOUT, VFB pin and AGND is used to adjust the overvoltage protection threshold (refer
to Figure 30).
To fix the overvoltage protection threshold the following Equation (10.3) is used:
(10.3)
If VVFB gets higher than its overvoltage threshold VVFB_OVTH , the SPI flag (OUTOV) in the STD diagnosis set to
HIGH and the gate drivers stop switching for output regulation (Break-Low condition both LS MOSFETs ON).
When VVFB_OVTH- VVFB_OVTH,HYS threshold is reached the device will auto restart. The dedicated diagnosis flag
(OUTOV) will be cleared after the next reading cycle of the STD diagnosis.
If the SWTMOD.OUTOVLAT bit is set to HIGH the overvoltage protection is changed into latched behavior and
the µC has to set the DVCCTRL.CLRLAT bit to reset the OUTOV flag and restart the switching activities.
10.2.3 Open Load Protection
To reliably detect an open load event, two conditions need to be observed:
1) Voltage threshold: VVFB > VVFB_OL,rise
2) Output current information: V(FBH-FBL) < VFBH_FBL_OL
During the rising edge of the Soft Start the open load detection is ignored until VSOFT_START_LOFF.
6 59.3 0.025 54.4 16.8 0.413
7 59.3 0.025 54.4 19.8 0.488
8 59.3 0.025 54.4 22.8 0.563 default
9 59.3 0.025 54.4 25.9 0.638
10 59.3 0.025 54.4 28.9 0.713
11 59.3 0.025 54.4 32.0 0.788
12 59.3 0.025 54.4 35.0 0.863
13 59.3 0.025 54.4 38.1 0.938
14 59.3 0.025 54.4 41.1 1.013
15 59.3 0.025 54.4 44.2 1.088
0 59.3 0.025 54.4 47.2 1.163
Table 10 Adjustable Short Circuit threshold overview
LEDCHAIN VOUT_OVLO k = RVFBL / (RVFBH
+ RVFBL)
Vopen_load Vshort_led (V)
(VFB_S2G / k)
VVFB_S2G(V) Default
Condition
VFBL
VFBLVFBH
OVTHVFBprotectedOVOUT R
RR
VV
+
⋅= ___
Datasheet 46 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
After an open load detection, the SPI flag (OL) in the STD diagnosis register is set to HIGH and the gate drivers
stop switching (Break-Low condition). The Device will auto restart with a soft start routine. The dedicated
diagnosis flag (OL) will be cleared after the next reading cycle of the STD diagnosis.
After an Open Load error the TLD5541-1 is autorestarting the output control accordingly to the implemented
Softstart routine. An Open Load error causes an increase of the output voltage as well. An Overvoltage
condition could be reported in combination with an Open Load error (in general, multiple error detection may
happen if more error detection thresholds are reached during the autorestart funcion, as possible
consequence of reactive behavior at the output node during open load).
The COMP capacitor is discharged during an Open Load condition to prevent spikes if load reconnects. This
measure could artificially generate Short Circuit detections after open loads events.
10.3 Input voltage monitoring, protection and power derating
Input overvoltage and undervoltage shutdown levels can both be defined through an external resistor divider,
as shown in Figure 31.
Both INOVLO and EN/INUVLO pin voltages are internally compared to their respective thresholds by means of
hysteretic comparators.
Neglecting the hysteresis, the following equations hold:
(10.4)
(10.5)
(10.6)
(10.7)
(10.8)
(10.9)
thth INUVLOEN
RR
R
UV /1
32
1⋅
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
+
+=
thth INOVLO
R
RR
OV ⋅
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛+
+=
3
21
1
η
OUTOUT
IN
IV
P
⋅
=
η
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛⋅
=IN
OUTOUT
boundaryIN
I
IV
V_
IN
ININ
IN R
V
I21−
=
FB
FBLFBH
OUT R
V
I−
=
Datasheet 47 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
Figure 31 Input Voltage Protection
In case of overvoltage event at the input, the STD bit VINOVLO is set. The softstart capacitor will be discharged
by an internal pull down switch.
After the overvoltage event disappeared the device will auto restart with the softstart function.
10.4 Input current Monitoring and Limiter
The two inputs (IIN1, IIN2) can be used to limit and monitor the Input current (Block A1 and A7 in Figure 7).
The control loop reduces the Comp voltage when the voltage accross the pins reaches Input Current Sense
threshold VIIN1-IIN2 to keep the input current below IINMax Equation (10.10)
(10.10)
The input current, measured via IIN1 and IIN2 pins, can be monitored through an analog output pin and an SPI
routine.
The IINMON pin provides a linear indication of the current flowing through the input. The following
Equation (10.11) is applicable:
(10.11)
Note: If the RIN value is choosen in a way that the current limitiation is much bigger than the nominal input
current during the application the current measurement becomes inaccurate. Best results for an
accurate current measurement via the VIINMON pin is to set the current limit only slightly above the
specific application related nominal input current.
Purpose of the input current monitoring routine is to verify if the system is in current limitation.
• The output of the Input Current Sense is compared to the internal precise reference voltage
• The comparator works like a 2 bit window ADC referred to the internal precise reference voltage
To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready
when CURRMON.EOMON is read HIGH.
IINMax VIIN1 IIN2–
RIIN
---------------------------=
20
⋅⋅=
ININIINMON RIV
Datasheet 48 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
The result of the input monitor routine is reported on the CURRMON.INCURR bit.
Figure 32 Input Current Monitoring General Overview
10.5 Output current Monitoring
The output current can be monitored through an analog output pin and an SPI routine.
The IOUTMON pin provides a linear indication of the current flowing through the LEDs. The following
Equation (10.12) is applicable:
(10.12)
Purpose of the SPI current monitor routine is to verify if the system is in loop.
• The output of the Led Current Sense is compared to the output of the Analog Dimming DAC
• The comparator works like a 2 bit window ADC around 8 bit DAC output
To execute the current monitor routine the CURRMON.SOMON bit has to be set HIGH and the result is ready
when CURRMON.EOMON is read HIGH.
When CURRMON.SOMON bit is set to HIGH both input and output current monitor routines are executed in
parallel.
The result of the monitor routine is reported on the CURRMON.LEDCURR bit.
Figure 33 Output Current Monitoring General Overview
8200
⋅⋅+=
FBOUTIOUTMON RImVV
R
FB
FBH
FBL
+
-
I
OUT_sense
I
DC_offset
I
IN_feedback
V
ref_int
+
-Latch
ADC Latch
ADC CLK
Logic
ADC CLK
feedback
2Bit Monitoring
ADC out
ADC out
ADC in
VIOUT_target
VIOUT_target +25%
VIOUT_target -25%
DAC
8 bit resolution
4 bit calibration
V
int_supply
+
-EA
COMP
V_sense_out
IOUTMON
VIOUT_target
V
FBH-FBL
V_sense_in
11b 10b 00b 01b
OUT H-Bridge
to LED
Load
Datasheet 49 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10.6 Device Temperature Monitoring
A temperature sensor is integrated on the chip. The temperature monitoring circuit compares the measured
temperature to the warning and shutdown thresholds. If the internal temperature sensor reaches the warning
temperature, the temperature warning bit TW is set to HIGH. This bit is not latched (i.e. if the temperature falls
below the warning threshold (with hysteresis), the TW bit is reset to LOW again).
If the internal temperature sensor reaches the shut-down temperature, the Gate Drivers plus the IVCC
regulator are shut down as described in Figure 34 and the temperature shut-down bit: TSD is set to HIGH. The
TSD bit is latched while the Gate Drivers plus the IVCC regulator have an auto restart behavior.
Note: The Device will start up with a soft start routine after a TSD condition disappear.
Figure 34 Device Overtemperature Protection Behavior
t
t
t
T
j
IVCC
T
jSD
T
jW
T
jSD,hyst
T
jW,Hyst
T
jSD_exit
T
jW_exit
TW bit
TW bit is reset automatically
IVCC
autorestart
NO ERROR
0
1
5V
OFF
t
TSD error bit
TSD error bit latched until next reset or CLRLAT
NO ERROR
0
1
Warning
xSGDx
t
Gate Drivers
autorestart
Operating
OFF
Datasheet 50 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Protection and Diagnostic Functions
10.7 Electrical Characteristics
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions
described in the datasheet. Fault conditions are considered as “outside” normal operating range.
Protection functions are not designed for continuous repetitive operation.
Table 11 EC Protection and Diagnosis
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter Symbol Values Unit Note or Test Condition Number
Min. Typ. Max.
Short Circuit Protection
Short to GND threshold VVFB_S2G 0.53 0.563 0.59 V VVFB decreasing;
MFSSETUP1.LEDCHA
IN = 1000B
P_10.8.1
Temperature Protection:
Thermal Warning
junction temperature
Tj,W 125 140 155 °C 1) P_10.8.2
Temperature warning
Hysteresis
Tj,W,hyst –10–°C
1) P_10.8.3
Over Temperature
Shutdown
Tj,SD 160 175 190 °C 1)
1) Specified by design; not subject to production test.
P_10.8.4
Over Temperature
Shutdown Hysteresis
Tj,SD,hyst –10–°C
1) P_10.8.5
Overvoltage Protection:
VFB Over Voltage
Feedback Threshold
VVFB_OVTH 1.42 1.46 1.50 V P_10.8.6
Output Over Voltage
Feedback Hysteresis
VVFB_OVTH,
HYS
25 40 58 mV Output Voltage
decreasing;
P_10.8.7
Open Load and Open Feedback Diagnostics
Open Load rising
Threshold
VVFB_OL,rise 1.29 1.34 1.39 V VFBH-FBL = 0 V; P_10.8.9
Open Load reference
Voltage VFBH-FBL
VFBH_FBL_O
L
– 15 22.5 mV VFB = 1.4 V; P_10.8.10
Open Load falling
Threshold
VVFB_OL,fall 1.23 1.28 1.33 V VFBH-FBL = 0 V; P_10.8.11
Input Overvoltage protection
Input Overvoltage rising
Threshold
VINOVLOth 1.9 2 2.1 V – P_10.8.12
Input Overvoltage
Threshold Hysteresis
VINOVLO(hys
t)
18 40 62 mV – P_10.8.13
Datasheet 51 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Infineon FLAT SPECTRUM Feature set
11 Infineon FLAT SPECTRUM Feature set
11.1 Description
The Infineon FLAT SPECTRUM feature set has the target to minimize external additional filter circuits. The goal
is to provide several beneficial concepts to provide easy adjustments for EMC improvements after the layout
is already done and the HW designed.
11.2 Synchronization Function
The TLD5541-1 features a SYNC input pin which can be used by a µC pin to define an oscillator switching
frequency. The µC is responsible to synchronize with various devices by applying appropriate SYNC signals to
the dedicated DC/DC devices in the system. Refer to Figure 35
Note: The Synchronization function can not be used when the Spread Spectrum is active.
Figure 35 Synchronization Overview
H-Bridge DCDC
MASTER
INPUT
µC
SYNC
LOGIC
BUCK-
BOOST
GATE
CONTROL
SYNC1
e.g. 400kHz
Phaseshift A
defined phase shift between
Outputs of different devices
H-Bridge DCDC
Slave
SYNC LOGIC
BUCK-
BOOST
GATE
CONTROL
SYNC2
e.g. 400kHz
Phaseshift B
Datasheet 52 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Infineon FLAT SPECTRUM Feature set
11.3 Spread Spectrum
The Spread Spectrum modulation technique significantly improves the lower frequency range of the
spectrum (f < 30 MHz).
By using the spread spectrum technique, it is possible to optimize the input filter only for the peak limits, and
also pass the average limits (average emission limits are -20dB lower than the peak emission limits). By using
spread spectrum, the need for low ESR input capacitors is relaxed because the input capacitor series resistor
is important for the low frequency filter characteristic. This can be an economic benefit if there is a strong
requirement for average limits.
The TLD5541-1 features a built in Spread Spectrum function which can be enabled (SWTMOD.ENSPREAD)
and adjusted via the SPI interface. Dedicated SPI-Bits are used to adjust the modulation frequency fFM,
(P_11.6.3) and (P_11.6.4) (SWTMOD.FMSPREAD) and the deviation frequency fdev, (P_11.6.1) and (P_11.6.2)
(SWTMOD.FDEVSPREAD) accordingly to specific application needs. Refer to Figure 36 for more details.
The following adjustments can be programmed when SWTMOD.ENSPREAD = HIGH:
SWTMOD.FMSPREAD = LOW: 12 kHz
SWTMOD.FMSPREAD = HIGH: 18 kHz
SWTMOD.FDEVSPREAD = HIGH: ±8% of fSW
SWTMOD.FDEVSPREAD = LOW: ±16% of fSW
Note: The Spread Spectrum function can not be used when the synchronization pin is used.
Figure 36 Spread Spectrum Overview
f
SW
t
f
dev
FM
f
1
Datasheet 53 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Infineon FLAT SPECTRUM Feature set
11.4 EMC optimized schematic
Figure 37 below displays the Application circuit with additional external components for improved EMC
behavior.
Figure 37 Application Drawing Including Additional Components for an Improved EMC Behavior
Note: The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
V
IN
VDD
CSN
SI
SO
SCLK
COMP
IIN2
IIN1
SYNC
VIN
AGND
PWMI
L
OUT
C
OUT
IVCC
BST1
BST2
HSGD1
LSGD 1
SWN1
LSGD2
HSGD2
SWN2
FBH
FBL
SWCS
SGND
PGND1
C
IVCC
R
SWCS
C
BST1
C
BST2
D
1
D
2
M
1
M
2
M
3
M
4
R
FB
C
IN2
R
COMP
C
COMP
R
IIN
Spread Spectrum ON /OFF via SPI
+3.3V or +5V
Digital dimminig
µC SYNC signal
C
IN1
EN/INUVLO
Alternative
external
VREG supply
INOVLO
SOFT_START
C
SOFT_START
PGND 2
VSS
R
1
R
2
R
3
R
VFBH
R
VFBL
VFB
FREQ
R
FREQ
R
filter
C
filter
IVCC_EXT
IINMON
IOUTMON
Advanced monitoring via µC
L
PI
C
PI1
C
PI2
C
PI4
C
PI3
D
HSG1
D
LSG1
D
LSG2
D
HSG2
R
HSG1
R
LSG1
R
LSG2
R
HSG2
D
VS
R
SPI
R
M1
C
M1
R
M4
C
M4
R
M2
C
M2
R
M3
C
M3
C
FBL
C
FBH
C
FBH-FBL
4LED in
series /
1A
L
PO
C
PO2
C
PO4
C
PO3
C
PO1
Datasheet 54 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Infineon FLAT SPECTRUM Feature set
11.5 Electrical Characteristics
Table 12 EC Spread Spectrum
VIN = 8 V to 36 V, TJ = -40°C to +150°C, all voltages with respect to AGND; (unless otherwise specified)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Spread Spectrum Parameters
Frequency Deviation fdev –±8–%
1)
SWTMOD.FDEV
SPREAD = HIGH;
P_11.6.1
Frequency Deviation fdev – ±16 – % 1)
SWTMOD.FDEV
SPREAD = LOW;
1) Specified by design; not subject to production test.
P_11.6.2
Frequency Modulation fFM –12–kHz
1)
SWTMOD.FMSP
READ = LOW;
P_11.6.3
Frequency Modulation fFM –18–kHz
1)
SWTMOD.FMSP
READ = HIGH;
P_11.6.4
Datasheet 55 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12 Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) is a full duplex synchronous serial slave interface, which uses four lines:
SO, SI, SCLK and CSN. Data is transferred by the lines SI and SO at the rate given by SCLK. The falling edge of
CSN indicates the beginning of an access. Data is sampled in on line SI at the falling edge of SCLK and shifted
out on line SO at the rising edge of SCLK. Each access must be terminated by a rising edge of CSN. A modulo
8/16 counter ensures that data is taken only when a multiple of 8 bit has been transferred after the first 16 bits.
Otherwise, a TER (i.e. Transmission Error) bit is asserted. In this way the interface provides daisy chain
capability with 16 bit as well as with 8 bit SPI devices.
Figure 38 Serial Peripheral Interface
12.1 SPI Signal Description
CSN - Chip Select
The system microcontroller selects the TLD5541-1 by means of the CSN pin. Whenever the pin is in LOW state,
data transfer can take place. When CSN is in HIGH state, any signals at the SCLK and SI pins are ignored and
SO is forced into a high impedance state.
CSN HIGH to LOW Transition
• The requested information is transferred into the shift register.
• SO changes from high impedance state to HIGH or LOW state depending on the signal level at pin SI.
• If the device is in SLEEP mode, the SO pin remains in high impedance state and no SPI transmission will
occur.
•TER Flag will set the Bit number 10 in the STD diagnosis Frame. This Bit is set to HIGH after an undervoltage
contition, reset via SPI command, on Limp Home state entering or after an incorrect SPI transmission. TER
Flag can be read also direcly on the SO line between the falling edge of the CSN and the first rising edge of
the SCLK according to the Figure 39.
14 13 12 11
14 13 12 11MSB
MSB
SPI _16bit.emf
LSB6 5 4 3 2 1
LSB6 5 4 3 2 1
10 9 8
10 9 8
7
7
SO
SI
CSN
SCLK
time
Datasheet 56 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Figure 39 Combinatorial Logic for TER bit
CSN LOW to HIGH Transition
• Command decoding is only done, when after the falling edge of CSN exactly a multiple (0,1, 2, 3, …) of eight
SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the
transmission error bit (TER) is set and the command is ignored.
• Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the
falling edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the
serial clock. It is essential that the SCLK pin is in LOW state whenever chip select CSN makes any transition,
otherwise the command may be not accepted.
SI - Serial Input
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling
edge of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to
Chapter 12.5 for further information.
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN
pin goes to LOW state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Chapter 12.5 for further information.
12.2 Daisy Chain Capability
The SPI of the TLD5541-1 provides daisy chain capability. In this configuration several devices are activated by
the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see
Figure 40), in order to build a chain. The end of the chain is connected to the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
SPI_ 16bitTER .e m f
SI
SPI
OR
STDDIAG.TER
0
1
SO
SO
S
SI
CSN
SCLK
S
Datasheet 57 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Figure 40 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from the SI line is shifted in with each
SCLK. The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is
finished. In single chip configuration, the CSN line must turn HIGH to make the device acknowledge the
transferred data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2.
When using three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices
(depending on how many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must
turn HIGH (see Figure 41).
Figure 41 Data Transfer in Daisy Chain Configuration
SI
device 1
SPI
SCLK
SO
CSN
SI
device 2
SPI
SCLK
SO
CSN
SI
device 3
SPI
SCLK
SO
CSN
MO
MI
MCSN
MCLK
SPI_DaisyChain_1.emf
MI
MO
MCSN
MCLK
SI device 3 SI device 2 SI device 1
SO device 3 SO device 2 SO device 1
SP I_Da isy Ch ain _2.emf
Datasheet 58 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.3 Timing Diagrams
Figure 42 Timing Diagram SPI Access
CSN
SCLK
SI
t
CS(lead)
t
CS(td)
t
CS(lag)
t
SCLK (H)
t
SCLK (L)
t
SC L K(P )
t
SI ( s u)
t
SI (h)
SO
t
SO( v )
t
SO(en)
t
SO (dis )
0.7V
DD
0.2V
DD
0.7V
cc
0.2V
cc
SPI _Timings.emf
0.7V
DD
0.2V
DD
0.7V
DD
0.2V
DD
Datasheet 59 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.4 Electrical Characteristics
VIN = 8 V to 36 V, TJ = -40°C to +150°C, VDD= 3 V to 5.5 V, all voltages with respect to ground; (unless otherwise
specified)
Table 13 EC Serial Peripheral Interface (SPI)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Input Characteristics (CSN, SCLK, SI) - LOW level of pin
CSN VCSN(L) 0–0.8V– P_12.4.1
SCLK VSCLK(L) 0–0.8V– P_12.4.2
SI VSI(L) 0–0.8V– P_12.4.3
Input Characteristics (CSN, SCLK, SI) - HIGH level of pin
CSN VCSN(H) 2–VDD V–P_12.4.4
SCLK VSCLK(H) 2–VDD V–P_12.4.5
SI VSI(H) 2–VDD V–P_12.4.6
L-input pull-up current at CSN pin -ICSN(L) 31 63 94 μAVDD = 5 V;
VCSN = 0.8 V;
P_12.4.7
H-input pull-up current at CSN pin -ICSN(H) 22 45 67 μAVDD = 5 V;
VCSN = 2 V;
P_12.4.8
L-Input Pull-Down Current at Pin
SCLK ISCLK(L) 61218μAVSCLK = 0.8 V; P_12.4.9
SI ISI(L) 61218μAVSI = 0.8 V; P_12.4.10
H-Input Pull-Down Current at Pin
SCLK ISCLK(H) 15 30 45 μAVSCLK = 2 V; P_12.4.11
SI ISI(H) 15 30 45 μAVSI = 2 V; P_12.4.12
Output Characteristics (SO)
L level output voltage VSO(L) 0–0.4VISO = -2 mA; P_12.4.13
H level output voltage VSO(H) VDD -
0.4 V
–VDD VISO = 2 mA;
VDD = 5 V;
P_12.4.14
Output tristate leakage current ISO(OFF) -1 – 1 μAVCSN = VDD;
VSO = 0 V or
VSO = VDD;
P_12.4.15
Timings
Enable lead time (falling CSN to
rising SCLK)
tCSN(lead) 200 – – ns 1) P_12.4.17
Enable lag time (falling SCLK to
rising CSN)
tCSN(lag) 200 – – ns 1) P_12.4.18
Transfer delay time (rising CSN to
falling CSN)
tCSN(td) 250 – – ns 1) P_12.4.19
Output enable time (falling CSN to
SO valid)
tSO(en) – – 200 ns 1)
CL = 20 pF at SO
pin;
P_12.4.20
Datasheet 60 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Output disable time (rising CSN to
SO tristate)
tSO(dis) – – 200 ns 1)
CL = 20 pF at SO
pin;
P_12.4.21
Serial clock frequency fSCLK ––5 MHz
1) P_12.4.22
Serial clock period tSCLK(P) 200 – – ns 1) P_12.4.24
Serial clock HIGH time tSCLK(H) 75 – – ns 1) P_12.4.25
Serial clock LOW time tSCLK(L) 75 – – ns 1) P_12.4.26
Data setup time (required time SI
to falling SCLK)
tSI(su) 20 – – ns 1) P_12.4.27
Data hold time (falling SCLK to SI) tSI(h) 20 – – ns 1) P_12.4.28
Output data valid time with
capacitive load
tSO(v) – – 100 ns 1)
CL = 20 pF;
P_12.4.29
1) Not subject to production test, specified by design
Table 13 EC Serial Peripheral Interface (SPI) (cont’d)
Parameter Symbol Values Unit Note or
Test Condition
Number
Min. Typ. Max.
Datasheet 61 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.5 SPI Protocol
The relationship between SI and SO content during SPI communication is shown in Figure 43. The SI line
represents the frame sent from the µC and the SO line is the answer provided by the TLD5541-1. The first SO
response is the response from the previous command.
Figure 43 Relationship between SI and SO during SPI communication
The SPI protocol will provide the answer to a command frame only with the next transmission triggered by the
µC. Although the biggest majority of commands and frames implemented in TLD5541-1 can be decoded
without the knowledge of what happened before, it is advisable to consider what the µC sent in the previous
transmission to decode TLD5541-1 response frame completely.
More in detail, the sequence of commands to “read” and “write” the content of a register will look as follows:
Figure 44 Register content sent back to µC
There are 3 special situations where the frame sent back to the µC doesn't depend on the previously received
frame:
• in case an error in transmission happened during the previous frame (for instance, the clock pulses were
not multiple of 8 with a minimum of 16 bits), shown in Figure 45
• when TLD5541-1 logic supply comes out of an Undervoltage reset condition (VDD < VDD(UV) as shown in
Figure 46 or EN/INUVLO < VEN/INUVLOth )
• in case of a read or write command for a “not used” or “reserved” register (in this case TLD5541-1 answers
with Standard Diagnosis at the next SPI transmission)
SI
SO
frame A frame B
(previous
response)
response to
frame A
frame C
response to
frame B
SPI_ SI2SO.emf
SI
SO
write register A read register A
Standard
diagnostic
register A
content
(new command )
SPI_RWseq.emf
(previous
response)
Datasheet 62 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Figure 45 TLD5541-1 response after an error in transmission
Figure 46 TLD5541-1 response after coming out of Power-On reset at VDD
SI
SO
frame A
(error in trans .)
(new
command)
Standard diag +
TER
(previous
response)
SPI_SO_TER.emf
SI
SO
frame A frame B
(SO = „Z“)
frame C
response to frame B
Standard diag + TER
V
DD
≥ V
DD(UV)
Datasheet 63 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.6 SPI Registers Overview
Reading a register needs two SPI frames. In the first frame the read command is sent. In the second frame the
output at SPI signal SO will contain the requested information. The MSB will be HIGH (while in case of standard
diagnosis is LOW). A new command can be executed in the second frame.
12.6.1 Standard Diagnosis
The Standard Diagnosis reports several diagnostic informations and the status of the device and the utility
routines.
The bits UVLORST, TER, VINOVLO, OUTOV, IVCCUVLO, OL and SHRTLED are latched and automatically cleared
after a STD diagnosis reading (default condition if OUTOVLT is not set).
A CLRLAT command resets the diagnostic Latched Flags and Latched protections for the OUTOV, TSD bits,
restarting the switching activity if this was halted due the previously mentioned faults.
The TSD bit is always latched and clearable only via explicit CLRLAT command. Note that the OUTOV has
latched behavior only when SWTMOD.OUTOVLAT=1, see Chapter 10.2.2 for further details.
The STD bits which are real time status monitors or mirror of internal registers are not cleared after a STD
diagnosis reading or via explicit CLRLAT command:
• The STATE bits and TW are real time status flags
• The bits EOMON, EOMFS and EOCAL are mirror of internal register
• The SWRST_BSTUV bit is the logic OR of:
• latched SWRST flag after a DVCSTRL.SWRST command (clearable via STD Diagnosis reading )
• real time monitor of gate driver undervolage (VBSTx-VSWNx_UVth)
In standard operating condition (active state, no Limp Home), if no special routines have been executed and
no faults have been detected, the readout of the STD should be 1000H.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Frame W/R RB ADDR Data
Write Register in bank 0
SI 1 0 ADDR Data
Read Register in bank 0
SI 0 0 ADDR x x x x x x x 0
Read Standard Diagnosis
SI 0 x x x x x x x x x x x x x x 1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0SWRST_
BSTUV
UVLO
RST
STATE TER EO
MON
EOM
FS
EOC
AL
VINOV
LO
OUTOV IVCCU
VLO
OL SHRTL
ED
TSD TW
Datasheet 64 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
Field Bits Type Description
SWRST_BSTUV 14 r SWRST OR VBSTx-VSWNx_UVth Monitor
0B, no SWRST or undervoltage on the Gate Drivers occured
1B, there was at least one SWRST since last readout OR an
undervoltage condition at the gate drivers is occurring
UVLORST 13 r VDD OR VEN/INUVLO Undervoltage Monitor
0B, there was no VDD OR VEN/INUVLO undervoltage since last readout
1B, there was at least one VDD undervoltage OR VEN/INUVLO
undervoltage condition since last readout
STATE 12:11 r Operative State Monitor
00B, (reserved)
01B, Limp Home Mode
10B, Active Mode
11B, Idle Mode
TER 10 r Transmission Error
0B, Previous transmission was successful
(modulo 16 + n*8 clocks received, where n = 0, 1, 2...)
1B, Previous transmission failed or first transmission after reset
EOMON 9 r End of LED/Input Current Monitor Routine Bit
0B, Current monitoring routine not completed, not successfully
performed or never run.
1B, Current Monitor routine successfully performed (is reset to 0B
when SOMON is set to 1B)
EOMFS 8 r End of MFS Routine Bit
0B, MFS routine not completed, not successfully performed or
never run.
1B, MFS routine successfully performed (is reset to 0B when
SOMOFS is set to 1B)
EOCAL 7 r End of Calibration Routine
0B, Calibration routine not completed, not successfully
performed or never run.
1B, Calibration routine successfully performed (is reset to 0B
when SOCAL is set to 1B)
VINOVLO 6 r VINOVLO Voltage Monitor
0B, VINOVLO below VINOVLOth threshold since last readout
1B, There was at least one VINOVLO overvoltage condition since last
readout
OUTOV 5 r Output overvoltage Monitor
0B, Output overvoltage not detected since last readout
1B, Output overvoltage was detected since last readout
IVCCUVLO 4 r IVCC or IVCC_EXT Undervoltage Lockout Monitor
0B, IVCC and IVCC_EXT above VIVCC_RTH,d or VIVCC_EXT_RTH,d threshold
since last readout
1B, Undervoltage on IVCC or IVCC_EXT occurred since last
readout
Datasheet 65 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
OL 3 r Open Load in ON state Diagnosis
0B, Open Load condition not detected since last readout
1B, Open Load condition detected since last readout
SHRTLED 2 r Shorted LED Diagnosis
0B, Short circuit condition not detected since last readout
1B, Short circuit condition detected since last readout
TSD 1 r Over Temperature Shutdown
0B, Tj below temperature shutdown threshold
1B, Overtemperature condition detected since last readout
TW 0 r Over Temperature Warning
0B, Tj below temperature warning threshold
1B, Tj exceeds temperature warning threshold
Field Bits Type Description
Datasheet 66 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
12.6.2 Register structure
Table 15 describes in detail the available registers with their bit-fields function, size and position
Table 14 shows register addresses and summarize bit-field position inside each register
A write to a non existing address is ignored, a read to a non existing register is ignored and the STD Diagnosis
Frame is send out.
Table 14 Register Bank 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name W/
R
R
B
ADDR Data
LEDCURR
ADIM
W/
R
0000000ADIMVAL
LEDCURR
CAL
W/
R
0000011x x SOCALEOCALCALIBVAL
SWTMOD W/
R
0000101x x x OUTOV
LAT
xENSP
READ
FMSP
READ
FDEVSP
READ
DVCCTRL W/
R
0 0 0 0 1 1 0 x x x ENCAL CLRLA
T
SWRS
T
IDLE
MFSSETU
P1
W/
R
0001001EA_IO
UT_MF
S
ILIM_
HALF
_MFS
SOMFS EOMFS LEDCHAIN
MFSSETU
P2
W/
R
0001010MFSDLY
CURRMON W/
R
0001100x x SOMO
N
EOMON INCURR LEDCURR
REGUSET
MON
W/
R
0001111x x x REGUMODFB x
Table 15 Register description
Register name Field Bits Type Purpose
LEDCURRADIM ADIMVAL 7:0 r/w LED Current Configuration Register
00000000B, analog dimming @ 0% of LED current fixed via
RFB
11110000B, (default) analog dimming @ 100% of LED
current fixed via RFB
Datasheet 67 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
LEDCURRCAL CALIBVAL 3:0 r/w LED Current Accuracy Trimming Configuration Register
LED current calibration value definition, the first bit is the
calibration sign:
0000B, (default) Initial state in the middle of the range
0111B, maximum calibration value positive
1111B, maximum calibration value negative
EOCAL 4 r End of calibration routine signalling bit:
0B, (default) calibration routine not completed, not
successfully performed or never run.
1B, calibration successfully performed (is reset to 0B
when SOCAL is set to 1B)
SOCAL 5 r/w Start of calibration routine signalling bit:
0B, (default) no calibration routine started
1B, calibration routine start (autoclear)
SWTMOD FDEVSPREAD 0r/wSwitching Mode Configuration Register
Deviation Frequency fDEV definition:
0B, (default) ±16% of fSW
1B, ±8% of fSW
FMSPREAD 1 r/w Frequency Modulation Frequency fFM definition:
0B, (default) 12 kHz
1B, 18 kHz
ENSPREAD 2 r/w Enable Spread Spectrum feature:
0B, (default) Spread Spectrum modulation disabled
1B, Spread Spectrum modulation enabled
OUTOVLAT 4 r/w Output latch after overvoltage error enable Bit
0B, (default) gate driver outputs are autorestarting
after an overvoltage event
1B, gate drivers are latched in brake low condition and
bit is latched after an overvoltage event
DVCCTRL IDLE 0r/wDevice Control Register
IDLE mode configuration bit:
0B, ACTIVE mode (default)
1B, IDLE mode
SWRST 1 r/w Software reset bit:
0B, (default) normal operation
1B, execute reset command
CLRLAT 2 r/w Clear Latch bit:
0B, (default) normal operation
1B, execute CLRLAT command
ENCAL 3 r/w Enable automatic output current calibration bit:
0B, (default) DAC takes CALIBVAL from SPI registers
1B, DAC takes CALIBVAL from last completed automatic
calibration procedure; SOCAL Bit can be set.
Table 15 Register description (cont’d)
Register name Field Bits Type Purpose
Datasheet 68 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
MFSSETUP1 LEDCHAIN 3:0 r/w Multifloat Switch and Short Circuit configuration Register
Short circuit threshold and MFS ratio bits: change the
VVFB_S2G threshold and set the MFS jump ratio
0001B, smallest Value 1 Step
0010B, 2 Steps
1000B, (default) 8 Steps
1111B, 15 Steps
0000B, largest Value 16 Steps
EOMFS 4r End of MFS routine bit:
0B, (default) MFS routine not completed, not
successfully performed or never run.
1B, MFS routine successfully performed (is reset to 0B
when SOMFS is set to 1B).
SOMFS 5 r/w Start of MFS routine bit:
0B, (default) MFS routine not activated
1B, MFS routine activated
ILIM_HALF 6 r/w Adjust Current Limit (Switch Peak Over Current Threshold)
during MFS operation:
0B, (default) Switch Peak Over Current Threshold 100%
1B, Switch Peak Over Current Threshold 50%
EA_IOUT_MFS 7 r/w Bit to decrease the saturation current of the error
amplifier (A6) in current mode control loop only during
MFS routine:
0B, (default) inactive
1B, active: error amplifier current reduced to 20%
MFSSETUP2 MFSDLY 7:0 r/w Multifloatswitch configuration register 2 (delay time
programming)
00000000B, smallest delay time in respect to fSW
11111111B, largest delay time in respect to fSW
00100000B, (default) delay time in respect to fSW
Table 15 Register description (cont’d)
Register name Field Bits Type Purpose
Datasheet 69 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Serial Peripheral Interface (SPI)
CURRMON LEDCURR 1:0 r Current Monitor Register
Status of the LED Current bits:
00B, (default) LED current between Target and +25%
01B, LED current above +25% of Target
10B, LED current between Target and -25%
11B, LED current below -25% of Target
INCURR 3:2 r Status of the Input Current bits:
00B, (default) Input current between 75% and 90% of
Limit
01B, Input current between 90% and the Limit
10B, Input current between 60% and 75% of Limit
11B, Input current below 60% of Limit
EOMON 4 r End of LED/Input Current Monitoring bit:
0B, (default) Current monitoring routine not
completed, not successfully performed or never run.
1B, Current Monitor routine successfully performed (is
reset to 0B when SOMON is set to 1B)
SOMON 5 r/w Start of LED/Input Current Monitoring bit:
0B, (default) Current monitor routine not started
1B, Start of the current monitor routine
REGUSETMON REGUMODFB 3:2 r Regulation Setup And Monitor Register
Feedback of Regulation Mode bits:
01B, (default) Buck
10B, Boost
11B, Buck-Boost
Table 15 Register description (cont’d)
Register name Field Bits Type Purpose
Datasheet 70 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
13 Application Information
Note: The following information is given as a hint for the implementation of the device only and shall not
be regarded as a description or warranty of a certain functionality, condition or quality of the device.
Figure 47 Application Drawing - TLD5541-1 as current regulator
Table 16 BOM - TLD5541-1 as current regulator (IOUT = 1 A, fSW = 300 kHz)
Reference Designator Value Manufacturer Part Number Type
D1 , D2BAT46WJ -- BAT46WJ Diode
CIN1 1 µF, 100 V TDK X7R Capacitor
CIN2 4.7 µF, 100 V TDK X7R Capacitor
Cfilter 470 nF, 100 V TDK X7R Capacitor
CCOMP 22 nF, 16 V TDK X7R Capacitor
CSOFT_START 22 nF, 16 V TDK X7R Capacitor
COUT1 4.7 µF, 100 V TDK X7R Capacitor
COUT2 , COUT3 100 nF, 100 V TDK X7R Capacitor
CIVCC 10 µF, 16 V TDK X7R Capacitor
CBST1 , CBST2 100 nF, 16 V TDK X7R Capacitor
IC1-- Infineon TLD5541-1 IC
LOUT 10 µH Coilcraft XAL1010-103MEC Inductor
Rfilter 50 Ω, 1% Panasonic -- Resistor
RFB 0.150 Ω, 1% Panasonic -- Resistor
Datasheet 71 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
Figure 48 Application Drawing - TLD5541-1 as adjustable voltage regulator
Note: Max Vout set to 20V by RFB1 and RFB2, input current limiter resistor RIN can be moved at the output
to control the output current.
RIN 0.003 Ω, 1% Panasonic -- Resistor
R1 , R2 , R3 , RPD , REN , RPWMI
, RSense1 , RSense2 , RSYNC ,
RSCLK , RSI , RSO , RCSN
xx kΩ, 1% Panasonic -- Resistor
RVFBL , RVFBH 1.5 kΩ, 56 kΩ, 1% Panasonic -- Resistor
RCOMP 0 Ω, 1% Panasonic -- Resistor
RFREQ 37.4 kΩ, 1% Panasonic -- Resistor
RSWCS 0.005 Ω, 1% Panasonic ERJB1CFR05U Resistor
M1 , M2 , M3 , M4 Dual MOSFET:
100 V / 35 mΩ N-ch
Infineon IPG20N10S4L-35 Transistor
Table 17 BOM - TLD5541-1 as voltage regulator
Reference Designator Value Manufacturer Part Number Type
D1 , D2BAT46WJ -- BAT46WJ Diode
CIN1 1 µF, 100 V TDK X7R Capacitor
CIN2 4.7 µF, 100 V TDK X7R Capacitor
Cfilter 470 nF, 100 V TDK X7R Capacitor
Table 16 BOM - TLD5541-1 as current regulator (IOUT = 1 A, fSW = 300 kHz)
Reference Designator Value Manufacturer Part Number Type
V
BAT
VDD
CSN
SI
SO
SCLK
COMP
IIN2
IIN1
SYNC
VIN
AGND
PWMI
L
OUT
C
OUT1
IVCC
BST1
BST2
HSGD1
LSGD1
SWN1
LSGD2
HSGD2
SWN2
FBH
FBL
SWCS
SGND
PGND1
C
IVCC
C
BST1
C
BST2
D
1
D
2
M
1
M
2
M
3
M
4
C
IN2
C
COMP
SPI
C
IN1
EN/INUVLO
Alternative external
VREG supply
INOVLO
SOFT_START
C
SOFT_START
PGND2
VSS
VFB
FREQ
C
filter
IVCC_ext
IINMON
IOUTMON
PWMI_LH
R
SENSE
A/D
GND
Micro
controller
V
DD
OUT VS
GND
Voltage Regulator
FAIL SAFE Circuit
R
IIN
R
COMP
R
filter
R
FREQ
R
1
R
2
R
3
R
PD
R
FB1
R
VFBH
R
VFBL
R
SWCS
A/D
R
SENSE
I/O
R
PWMI
I/O
R
SYNC
C
VREG_OUT
V
DD
SPI
R
SI
R
SO
R
CSN
R
SCLK
I/O
R
EN
D
TVS
R
gate
M
RP
SET
R
5
R
4
IVCC
R
FB2
V
OUT
C
OUT2
C
OUT3
LIMPHOME
FAIL SAFE Circuit
LHI
R
FF
C
FF
Datasheet 72 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
CCOMP 22 nF, 16 V TDK X7R Capacitor
CFF 10 nF, 50 V TDK X7R Capacitor
CSOFT_START 22 nF, 16 V TDK X7R Capacitor
COUT1 4.7 µF, 100 V TDK X7R Capacitor
COUT2 , COUT3 100 nF, 100 V TDK X7R Capacitor
CIVCC 10 µF, 16 V TDK X7R Capacitor
CBST1 , CBST2 100 nF, 16 V TDK X7R Capacitor
IC1-- Infineon TLD5541-1 IC
LOUT 10 µH Coilcraft XAL1010-103MEC Inductor
RFF 1.5 kΩ, 1% Panasonic -- Resistor
Rfilter 50 Ω, 1% Panasonic -- Resistor
RFB1 , RFB2 150Ω, 20.5kΩ, 1% Panasonic -- Resistor
RIN 0.005 Ω, 1% Panasonic -- Resistor
R1 , R2 , R3 , RPD , REN ,
RPWMI , RSense1 , RSense2 ,
RSYNC , RSCLK , RSI , RSO ,
RCSN
xx kΩ, 1% Panasonic -- Resistor
RVFBL , RVFBH 1.5 kΩ, 24 kΩ, 1% Panasonic -- Resistor
RCOMP 0 Ω, 1% Panasonic -- Resistor
RFREQ 37.4 kΩ, 1% Panasonic -- Resistor
RSWCS 0.005 Ω, 1% Panasonic ERJB1CFR05U Resistor
M1 , M2 , M3 , M4Dual MOSFET:
100 V / 35 mΩ N-ch
Infineon IPG20N10S4L-35 Transistor
Table 17 BOM - TLD5541-1 as voltage regulator
Reference Designator Value Manufacturer Part Number Type
Datasheet 73 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
13.1 Further Application Information
Typical Performance Characteristics of Device
Figure 49 Characterization Diagrams 1
0
0,5
1
1,5
2
2,5
0 1020304050
VINVIVCC [V]
LDOcurrent[mA]
IVCCDropoutvsCurrent
Tj=40°C
Tj=150°C
Tj=25°C
4,80
4,85
4,90
4,95
5,00
5,05
5,10
5,15
5,20
40 10 60 110
VIVCC [V]
Temperature[°C]
IVCCVoltagevsTemperature
4,8
4,85
4,9
4,95
5
5,05
5,1
5,15
5,2
0 1020304050
VIVCC [V]
IIVCC[mA]
IVCCLoadregulation
IIVCC=10mA
146
147
148
149
150
151
152
153
154
0 102030405060
V(FBHFBL)[mV]
VFBH[V]
V(FBHFBL)ThresholdvsVFBH
AnalogDim.=100%
1,36
1,37
1,38
1,39
1,4
1,41
1,42
1,43
1,44
40 10 60 110
VIOUTMON [V]
Temperature[°C]
IOUTMONVoltagevsTemp
V(FBHFBL) =150mV
146
147
148
149
150
151
152
153
154
40 10 60 110
V(FBHFBL)[mV]
Temperature[°C]
V(FBHFBL)ThresholdvsTemp
AnalogDim.=100%,FBH=0,15V
AnalogDim.=100%,FBH=12V
AnalogDim.=100%,FBH=60V
TJ=25°C,VIN=12Vunlessotherwisespecified
Datasheet 74 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
Figure 50 Characterization Diagrams 2
0
0,2
0,4
0,6
0,8
1
1,2
1,4
0 20406080100120140
VIOUTMON [V]
V(FBHFBL) [mV]
IOUTMONVoltagevsV(FBHFBL)
VIN =12V
IVCC=10mA
VIN =12V
V(FBHFBL) =150mV
100
200
300
400
500
600
700
800
40 10 60 110
fSW [kHz]
Temperature[°C]
OscillatorFrequencyvsTemp
R_FREQ=61.9kOhm
R_FREQ=37.4kOhm
R_FREQ=12.7kOhm
47
48
49
50
51
52
53
40 10 60 110
V(IIN1IIN12 [mV]
Temperature[°C]
V(IIN1IIN2)ThresholdvsTemp
VIIN1=8V
VIIN1=13.5V
VIIN1=55V
0,96
0,97
0,98
0,99
1
1,01
1,02
1,03
1,04
40 10 60 110
VIINMON [V]
Temperature[°C]
IINMONVoltagevsTemp
V(IIN1IIN2) =50mV
3,1
3,2
3,3
3,4
3,5
3,6
3,7
3,8
3,9
4
40 10 60 110
V(SBTxSWNx) [V]
Temperature[°C]
V(BSTxSWNx)vsTemp
VBSTxVSWNx_dec[V]
VBSTxVSWNx_inc[V]
TJ=25
°
C,VIN=12Vun
l
essot
h
erwisespeci
f
ie
d
40
20
0
20
40
60
80
100
120
0 5 10 15 20 25 30 35 40 45 50 55 60
IFBH [uA],IFBL [uA]
VFBH[V]
IFBH ,IFBL vsVFBH
I_FBL[uA]
I_FBH[uA]
V(FBHFBL) =150mV
Datasheet 75 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Application Information
Figure 51 Characterization Diagrams 3
• For further information you may contact http://www.infineon.com/
V
IN = 12V
I
VCC=10mA
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
-40 10 60 110
LSGDx [Ohm]
Temperature [
°C]
LSGDx on-state resistance vs Temp
LSGDx_Pull-Up
LSGDx_Pull-down
0
0,5
1
1,5
2
2,5
3
3,5
4
4,5
-40 10 60 110
HSGDx [Ohm]
Temperature [°C]
HSGDx on resistance vs Temp
HSGDx_Pull-up
HSGDx_Pull-down
0
20
40
60
80
100
120
0,6 0,8 1 1,2 1,4 1,6
Duty Cycle [%]
V
COMP
[V]
VCOMP Voltage vs LSGD Duty Cycle
LSGD1_Buck [%]
LSGD2_Boost [%]
VIN = 12V
-60
-40
-20
0
20
40
60
-40 10 60 110
V
(SWCS-SGND)
[mV]
Temperature [°C]
V(SWCS-SGND) Treshold vs Temp
Boost
Buck
V
(SWCS
-
SGND)
=0
fsw=300kHz
TJ = 25
°C, VIN=12V unless otherwise specified
Datasheet 76 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Package Outlines
14 Package Outlines
Figure 52 PG-VQFN-48-31 (with LTI)
PG-VQFN-48-29, -31-PO V05
7±0.1 A
6.8
7
±0.1
B
11 x 0.5 = 5.5
0.5
0.5
±0.07
0.1
±0.05
0.13
±0.05
0.26
0.15
±0.05
(6)
(5.2)
0.9 MAX.
(0.65)
+0.03 1) 2)
48x
0.08
(0.2)
0.05 MAX.
C
(5.2)
(6)
0.1±0.03
±0.05
0.23
M
48x
0.1 A B C
1) Vertical burr 0.03 max., all sides
2) These four metal areas have exposed diepad potential
Index Marking
SEATING PLANE
Index Marking
6.8
12 1
13
24
25 36
(0.35)
37
48
0.4 x 45°
Datasheet 77 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Package Outlines
Figure 53 PG-TQFP-48-9
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant
with government regulations the device is available as a green product. Green products are RoHS-Compliant
(i.e Pb free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
2)EXPOSEDPADFORSOLDERINGPURPOSE
1)DOESNOTINCLUDEPLASTICORMETALPROTRUSIONOF0.25MAX.PERSIDE
1
±0.05
1.2 MAX.
C
SEATING
0.08 C48x
COPLANARITY
PLANE
0.5 0.08 A-B D C 48x
H
0.6
±0.15
0.125
+0.075
-0.035
0.25
GAUGE
PLANE
D
B
A
7
9
7
9
5
48x
0.2 A-B D
0.2 A-B D H 4x
INDEXMARKING
5
BOTTOMVIEW
2)
1)
1)
2)
EXPOSEDDIEPAD
48
1
48
1
0°..7°
0.1
±0.05
STAND OFF
0.22
±0.05
For further information on alternative packages, please visit our website:
http://www.infineon.com/packages.Dimensions in mm
Datasheet 78 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Revision History
15 Revision History
Revision Date Changes
Rev. 1.0 2016-05-20 Released Datasheet
Rev. 1.1 2018-02-08 LED number set to 0x22 on the MFS example register Chapter 6.5
Rev. 1.1 2018-02-08 Added: CCM on regulator description Chapter 6.1
Rev. 1.1 2018-02-08 Added item to Chapter 6.5
Rev. 1.1 2018-02-08 Added TQFP package
Rev. 1.1 2018-02-08 Changed RVFBH to 59 kΩ and RVFBL to 1.5 kΩ
Rev. 1.1 2018-02-08 Corrected graph VCOMP vs DUTY
Rev. 1.1 2018-02-08 Corrected soft start behavior Chapter 6.2 “if an open load”
Rev. 1.1 2018-02-08 MFSSETUP2 default value Chapter 12.6
Rev. 1.1 2018-02-08 Divided In and out overvoltage protection def. Chapter 10.2 Chapter 10.3
Rev. 1.1 2018-02-08 Modified Voltage regulator application Drawing and note, see Figure 48
Rev. 1.1 2018-02-08 Specified Complessive gain of error amp Chapter 6.1
Rev. 1.1 2018-02-08 Improved description of soft start Chapter 6.2
Rev. 1.1 2018-02-08 Improved description of calibration Routine Chapter 8.2
Rev. 1.1 2018-02-08 Added Soft Start mask in the Short circuit description Chapter 10.2
Rev. 1.1 2018-02-08 Added input current limiter description Chapter 10.4
Rev. 1.1 2018-02-08 Removed Parameter 6.4.2 covered now by updated 6.4.1 Chapter 6.7
Datasheet 79 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
Table of Content
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Different Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Different Possibilities to RESET the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Regulator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 Regulator Diagram Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.2 Adjustable Soft Start Ramp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.3 Switching Frequency setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.4 Operation of 4 switches H-Bridge architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1 Boost mode (VIN < VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.2 Buck mode (VIN > VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4.3 Buck-Boost mode (VIN ~ VOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5 Fast Output Discharge Operation Mode - Multi Floating Switches Topology . . . . . . . . . . . . . . . . . . . . 25
6.6 Flexible current sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.7 Programming Output Voltage (Constant Voltage Regulation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7 Digital Dimming Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8 Analog Dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.2 LED current calibration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9 Linear Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.1 IVCC Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
9.2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10 Protection and Diagnostic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.2 Output Overvoltage, Open Load, Short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.2.1 Short Circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.2.2 Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.2.3 Open Load Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.3 Input voltage monitoring, protection and power derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.4 Input current Monitoring and Limiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.5 Output current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.6 Device Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Datasheet 80 Rev. 1.1
2018-02-08
TLD5541-1
H-Bridge DC/DC Controller with SPI Interface
10.7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11 Infineon FLAT SPECTRUM Feature set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.2 Synchronization Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
11.3 Spread Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.4 EMC optimized schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11.5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
12 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.1 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
12.2 Daisy Chain Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
12.3 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
12.4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
12.5 SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
12.6 SPI Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.6.1 Standard Diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
12.6.2 Register structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
13.1 Further Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
14 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
15 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table of Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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µHVIC™, µIPM™, µPFC™, AU-ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™,
DAVE™, DI-POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™,
HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OPTIGA™,
OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™,
SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™.
Trademarks updated November 2015
Other Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2018-02-08
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2018 Infineon Technologies AG.
All Rights Reserved.
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aspect of this document?
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