October 1987
Revised January 1999
CD4007C Dual Complementary Pair Plus Inverter
© 1999 Fairchild Semicond uctor Corpor ation DS005943.prf www.fairchildsemi.com
CD4007C
Dual Complementary Pair Plus Inverter
General Descript ion
The CD400 7C con s ists of th ree comp l em ent ary pai rs of N-
and P-channel enhancement mode MOS transistors suit-
able for series/shunt applications. All inputs are protected
from static discharge by diode clamps to VDD and VSS.
For proper operation the voltages at all pins must be con-
strained to be between VSS − 0.3V and VDD + 0.3V at all
times.
Features
■Wide supply voltage range: 3.0V to 15V
■High noise immunity: 0.45 VCC (typ.)
Ordering Code:
Devices also available in Tape and Reel. Spec if y by appendin g t he suffix let t er “X” to the ordering c ode.
Connection Diagram
Pin Assignments for DIP and SOIC
Note: All P-c hannel s ubs t rat es are con nected to VDD and all N-c hannel substrate s are connec t ed t o V SS.
Top View
Order Number Package Number Package Description
CD4007CM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
CD4007CN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS–001, 0.300” Wide
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CD4007C
Absolute Maximum Ratings(Note 1)
Note 1: This device should not be connected to circuits with the power on
becau se high transient voltages m ay caus e per m anent d am age.
DC Electrical Characteristics
AC Electrical Character ist ics (Note 2)
TA = 25°C and CL = 15 pF and rise and fall times = 20 ns. Typical temperature coefficient for all values of VDD = 0.3%/°C
Note 2: AC Parameters are guaranteed by DC cor related test ing.
Voltage at Any Pin VSS −0.3V to VDD +0.3V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Power Dissi pation (PD)
Dual-In- Li ne 700 mW
Small Outline 500 mW
Operating VDD Range VSS +3.0V to VSS +15V
Lead Tempe ratu re
(Soldering, 10 seconds) 260°C
Limits
Symbol Parameter Conditions −40°C+25°C+85°CUnits
Min Typ Max Min Typ Max Min Typ Max
ILQuiescent Device VDD = 5.0V 0.5 0.005 0.05 15 µA
Current VDD = 10V 1.0 0.005 1.0 30 µA
PDQuiescent Device VDD = 5.0V 2.5 0.025 2.5 75 µW
Dissipation Package VDD = 10V 10 0.05 10 300 µW
VOL Output Voltage VDD = 5.0V 0.05 0 0.01 0.05 V
LOW Level VDD = 10V 0.05 0 0.01 0.05 V
VOH Output Voltage VDD = 5.0V 4.95 4.95 5.0 4.95 V
HIGH Leve l VDD = 10V 9.95 9.95 10 9.95 V
VNL Noise Immunity VDD = 5.0V, VO = 3.6V 1.5 2.25 1.5 1.4 V
(All inputs) VDD = 10V, VO = 7.2V 3.0 4.5 3.0 2.9 V
VNH Noise Immunity VDD = 5.0V, VO = 0.95V 3.6 3.5 2.25 3.5 V
(All Inputs) VDD = 10V, VO = 2.9V 7.1 7.0 4.5 7.0 V
IDN Output Drive Current VDD = 5.0V, VO = 0.4V, VI = VDD 0.35 0.3 1.0 0.24 mA
N-Channel VDD = 10V, VO = 0.5V, VI = VDD 1.2 1.0 2.5 0.8 mA
IDP Output Drive Current VDD = 5.0V, VO = 2.5V, VI = VSS −1.3 −1.1 −4.0 −0.9 mA
P-Channel VDD = 10V, VO = 9.5V, VI = VSS −0.65 −0.55 −2.5 −0.45 mA
IIInput Current 10 pA
Symbol Parameter Conditions Min Typ Max Units
tPLH = tPHL Propagation Delay Time VDD = 5.0V 35 75 ns
VDD = 10V 20 50 ns
tTLH = tTHL Transition Time VDD = 5.0V 50 100 ns
VDD = 10V 30 50 ns
CIInput Capacitance Any Input 5 pF
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CD4007C
AC Test Circuits
Switching Ti me Waveforms
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CD4007C
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
F airchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are im plied and Fairchild reserves the right at any time w ithout notice to change said circuitry and specifications.
CD4007C Dual Complementary Pair Plus Inverter
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support d evices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A cr itical c ompon ent in any com ponent of a li fe support
device or system whose failure to perform can be rea-
sonably expected to cause th e failure of the li fe suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
