I2C-Compatible, Wide Bandwidth,
Triple 3:1 Multiplexer
ADG793A/ADG793G
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Bandwidth: 195 MHz
Low insertion loss and on resistance: 2.6 Ω typical
On-resistance flatness 0.3 Ω typical
3.3 V analog signal range (5 V supply, 75 Ω load)
Single 3 V/5 V supply operation
Low quiescent supply current: 1 nA typical
Fast switching times: tON = 185 ns, tOFF = 181 ns
I2C®-compatible interface
Compact, 24-lead LFCSP
Two I2C-controllable logic outputs
ESD protection
4 kV human body model (HBM)
200 V machine model (MM)
1 kV field-induced charged device model (FICDM)
APPLICATIONS
RGB/YPbPr video switches
HDTV
Projection TV
DVD-R/RW
AV receivers
FUNCTIONAL BLOCK DIAGRAMS
ADG793A
I
2
CSERIAL
INTERFACE
SCLSDAA2A1A0
V
DD
GND
S1A
S1B D1
S1C
S2A
S2B D2
S2C
S3A
S3B D3
S3C
06030-001
GPO2
ADG793G
I
2
CSERIAL
INTERFACE
SCLSDAA2A1A0
GPO1
V
DD
GND
S1A
S1B D1
S1C
S2A
S2B D2
S2C
S3A
S3B D3
S3C
Figure 1.
GENERAL DESCRIPTION
The ADG793A/ADG793G are monolithic CMOS devices
comprising three 3:1 multiplexers/demultiplexers controllable
via a standard I2C serial interface. The CMOS process provides
ultralow power dissipation, yet gives high switching speed and
low on resistance.
The on-resistance profile is very flat over the full analog input
range, and the wide bandwidth ensures excellent linearity and
low distortion. These features, combined with a wide input
signal range, make the ADG793A/ADG793G the ideal
switching solution for a wide range of TV applications,
including RGB and YPbPr video switches.
The switches conduct equally well in both directions when on.
In the off condition, signal levels up to the supplies are blocked.
The ADG793A/ADG793G switches exhibit break-before-make
switching action. The ADG793G has two general-purpose logic
output pins controllable through the I2C interface, which can be
used to control other non-I2C-compatible devices such as video
filters. The integrated I2C interface provides a large degree of
flexibility in the system design. It has three configurable I2C
address pins that allow the user to connect up to eight devices
to the same bus to build larger switching arrays.
The ADG793A/ADG793G operate from a single 3 V or 5 V
supply voltage and are available in a compact, 4 mm × 4 mm
body, 24-lead, lead-free chip scale package (LFCSP).
PRODUCT HIGHLIGHTS
1. Wide bandwidth: 195 MHz.
2. Ultralow power dissipation.
3. Extended input signal range.
4. Integrated I2C serial interface.
5. Compact, 4 mm × 4 mm body, 24-lead, lead-free chip scale
package (LFCSP).
6. ESD protection tested as per ESD Association standards:
4 kV HBM (ANSI/ESD STM5.1-2001)
200 V MM (ANSI/ESD STM5.2-1999)
1 kV FICDM (ANSI/ESDSTM5.3.1-1999)
ADG793A/ADG793G
Rev. 0 | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
I2C Timing Specifications................................................................ 7
Timing Diagram ........................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 11
Test Circuits..................................................................................... 14
Terminology .................................................................................... 16
Theory of Operation ...................................................................... 17
I2C Serial Interface ..................................................................... 17
I2C Address.................................................................................. 17
Write Operation.......................................................................... 17
LDSW Bit..................................................................................... 19
Power On/Software Reset.......................................................... 19
Read Operation........................................................................... 19
Evaluation Board ............................................................................ 20
Using the ADG793G Evaluation Board .................................. 20
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
REVISION HISTORY
7/06—Revision 0: Initial Version
ADG793A/ADG793G
Rev. 0 | Page 3 of 24
SPECIFICATIONS
VDD = 5 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Conditions Min Typ1 Max Unit
ANALOG SWITCH
Analog Signal Range2VS = VDD, RL = 1 MΩ 0 4 V
V
S = VDD, RL = 75 Ω 0 3.3 V
On Resistance, RON V
D = 0 V, IS = −10 mA, see Figure 22 2.6 3.5 Ω
V
D = 0 V to 1 V, IS = −10 mA, see Figure 22 4 Ω
On-Resistance Matching Between
Channels, ∆RON
VD = 0 V, IS = −10 mA 0.15 0.5 Ω
V
D = 1 V, IS = −10 mA 0.6 Ω
On-Resistance Flatness, RFLAT(ON) VD = 0 V to 1 V, IS = −10 mA 0.3 0.55 Ω
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF) V
D = 4 V/1 V, VS = 1 V/4 V, see Figure 23 ±0.25 nA
Drain Off Leakage, ID(OFF) V
D = 4 V/1 V, VS = 1 V/4 V, see Figure 23 ±0.25 nA
Channel On Leakage, ID(ON), IS(ON) V
D = VS = 4 V/1 V, see Figure 24 ±0.25 nA
DYNAMIC CHARACTERISTICS3
tON, tENABLE CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 185 240 ns
tOFF, tDISABLE CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 181 235 ns
Break-Before-Make Time Delay, tD C
L = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V,
see Figure 29
1 3 ns
I2C-to-GPO Propagation Delay, tH, tL ADG793G only 130 ns
Off Isolation f = 10 MHz, RL = 50 Ω, see Figure 26 −60 dB
Channel-to-Channel Crosstalk f = 10 MHz, RL = 50 Ω, see Figure 27
Same Multiplexer −55 dB
Different Multiplexer −75 dB
−3 dB Bandwidth RL = 50 Ω, see Figure 25 195 MHz
THD + N RL = 100 Ω 0.14 %
Charge Injection CL = 1 nF, VS = 0 V, see Figure 30 5 pC
CS(OFF) 10 pF
CD(OFF) 26 pF
CD(ON), CS(ON) 37 pF
Power Supply Rejection Ratio, PSSR f = 20 kHz 70 dB
Differential Gain Error CCIR330 test signal 0.59 %
Differential Phase Error CCIR330 test signal 0.83 Degrees
LOGIC INPUTS3
A0, A1, A2
Input High Voltage, VINH 2.0 V
Input Low Voltage, VINL 0.8 V
Input Current, IINL or IINH VIN = 0 V to VDD 0.005 ±1 μA
Input Capacitance, CIN 3 pF
SCL, SDA
Input High Voltage, VINH 0.7 × VDD V
DD + 0.3 V
Input Low Voltage, VINL −0.3 +0.3 × VDD V
Input Leakage Current, IIN VIN = 0 V to VDD 0.005 ±1 μA
Input Hysteresis 0.05 × VDD V
Input Capacitance, CIN 3 pF
ADG793A/ADG793G
Rev. 0 | Page 4 of 24
Parameter Conditions Min Typ1 Max Unit
LOGIC OUTPUTS3
SDA Pin
Output Low Voltage, VOL I
SINK = 3 mA 0.4 V
I
SINK = 6 mA 0.6 V
Floating-State Leakage Current ±1 μA
Floating-State Output Capacitance 10 pF
GPO1 Pin and GPO2 Pin
Output Low Voltage, VOL I
LOAD = +2 mA 0.4 V
Output High Voltage, VOH I
LOAD = −2 mA 2.0 V
POWER REQUIREMENTS
IDD Digital inputs = 0 V or VDD, I2C interface
inactive
0.001 1 μA
I
2C interface active, fSCL = 400 kHz 0.2 mA
I
2C interface active, fSCL = 3.4 MHz 0.7 mA
1All typical values are at TA = 25°C, unless otherwise stated.
2Guaranteed by initial characterization, not subject to production test.
3Guaranteed by design, not subject to production test.
ADG793A/ADG793G
Rev. 0 | Page 5 of 24
VDD = 3 V ± 10%, GND = 0 V, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter Conditions Min Typ1 Max Unit
ANALOG SWITCH
Analog Signal Range2VS = VDD, RL = 1 MΩ 0 2.2 V
V
S = VDD, RL = 75 Ω 0 1.7 V
On Resistance, RON V
D = 0 V, IS = −10 mA, see Figure 22 3 4 Ω
V
D = 0 V to 1 V, IS = −10 mA, see Figure 22 6 Ω
On-Resistance Matching Between
Channels, ∆RON
VD = 0 V, IS = −10 mA 0.15 0.6 Ω
V
D = 1 V, IS = −10 mA 1.1 Ω
On-Resistance Flatness, RFLAT(ON) VD = 0 V to 1 V, IS = −10 mA 0.3 2.8 Ω
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF) V
D = 3 V/1 V, VS = 1 V/3 V, see Figure 23 ±0.25 nA
Drain Off Leakage, ID(OFF) V
D = 3 V/1 V, VS = 1 V/3 V, see Figure 23 ±0.25 nA
Channel On Leakage, ID(ON), IS(ON) V
D = VS = 3 V/1 V, see Figure 24 ±0.25 nA
DYNAMIC CHARACTERISTICS3
tON, tENABLE CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 200 260 ns
tOFF, tDISABLE CL = 35 pF, RL = 50 Ω, VS = 2 V, see Figure 28 197 255 ns
Break-Before-Make Time Delay, tD C
L = 35 pF, RL = 50 Ω, VS1 = VS2 = 2 V,
see Figure 29
1 3 ns
I2C-to-GPO Propagation Delay, tH, tL ADG793G only 121 ns
Off Isolation f = 10 MHz, RL = 50 Ω, see Figure 26 −60 dB
Channel-to-Channel Crosstalk f = 10 MHz, RL = 50 Ω, see Figure 27
Same Multiplexer −55 dB
Different Multiplexer −75 dB
−3 dB Bandwidth RL = 50 Ω, see Figure 25 190 MHz
THD + N RL = 100 Ω 0.14 %
Charge Injection CL = 1 nF, VS = 0 V, see Figure 30 3.5 pC
CS(OFF) 10 pF
CD(OFF) 26 pF
CD(ON), CS(ON) 37 pF
Power Supply Rejection Ratio, PSRR f = 20 kHz 70 dB
Differential Gain Error CCIR330 test signal 0.51 %
Differential Phase Error CCIR330 test signal 0.62 Degrees
LOGIC INPUTS3
A0, A1, A2
Input High Voltage, VINH 2.0 V
Input Low Voltage, VINL 0.8 V
Input Current, IINL or IINH VIN = 0 V to VDD 0.005 ±1 μA
Input Capacitance, CIN 3 pF
SCL, SDA
Input High Voltage, VINH 0.7 × VDD V
DD + 0.3 V
Input Low Voltage, VINL −0.3 +0.3 × VDD V
Input Leakage Current, IIN VIN = 0 V to VDD 0.005 ±1 μA
Input Hysteresis 0.05 × VDD V
Input Capacitance, CIN 3 pF
ADG793A/ADG793G
Rev. 0 | Page 6 of 24
Parameter Conditions Min Typ1 Max Unit
LOGIC OUTPUTS3
SDA Pin
Output Low Voltage, VOL I
SINK = 3 mA 0.4 V
I
SINK = 6 mA 0.6 V
Floating-State Leakage Current ±1 μA
Floating-State Output Capacitance 3 pF
GPO1 Pin and GPO2 Pin
Output Low Voltage, VOL I
LOAD = +2 mA 0.4 V
Output High Voltage, VOH I
LOAD = −2 mA 2.0 V
POWER REQUIREMENTS
IDD Digital inputs = 0 V or VDD, I2C interface
inactive
0.001 1 μA
I
2C interface active, fSCL = 400 kHz 0.1 mA
I
2C interface active, fSCL = 3.4 MHz 0.2 mA
1All typical values are at TA = 25°C, unless otherwise stated.
2 Guaranteed by initial characterization, not subject to production test.
3 Guaranteed by design, not subject to production test.
ADG793A/ADG793G
Rev. 0 | Page 7 of 24
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; GND = 0 V; TA = −40°C to +85°C, unless otherwise noted. See Figure 2 for timing diagram.
Table 3.
Parameter1Conditions Min Max Unit Description
fSCL Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
High speed mode
C
B = 100 pF max 3.4 MHz
C
B = 400 pF max 1.7 MHz
t1 Standard mode 4 μs tHIGH, SCL high time
Fast mode 0.6 μs
High speed mode
C
B = 100 pF max 60 ns
C
B = 400 pF max 120 ns
t2 Standard mode 4.7 μs tLOW, SCL low time
Fast mode 1.3 μs
High speed mode
C
B = 100 pF max 160 ns
C
B = 400 pF max 320 ns
t3 Standard mode 250 ns tSU;DAT, data setup time
Fast mode 100 ns
High speed mode 10 ns
t42Standard mode 0 3.45 μs tHD;DAT, data hold time
Fast mode 0 0.9 μs
High speed mode
C
B = 100 pF max 0 703 ns
C
B = 400 pF max 0 150 ns
t5 Standard mode 4.7 μs tSU;STA, setup time for a repeated start condition
Fast mode 0.6 μs
High speed mode 160 ns
t6 Standard mode 4 μs tHD;STA, hold time (repeated) start condition
Fast mode 0.6 μs
High speed mode 160 ns
t7 Standard mode 4.7 μs tBUF, bus free-time between a stop and a start condition
Fast mode 1.3 μs
t8 Standard mode 4 μs tSU;STO, setup time for stop condition
Fast mode 0.6 μs
High speed mode 160 ns
t9 Standard mode 1000 ns tRDA, rise time of SDA signal
Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
B = 100 pF max 10 80 ns
C
B = 400 pF max 20 160 ns
t10 Standard mode 300 ns tFDA, fall time of SDA signal
Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
B = 100 pF max 10 80 ns
C
B = 400 pF max 20 160 ns
ADG793A/ADG793G
Rev. 0 | Page 8 of 24
Parameter1Conditions Min Max Unit Description
t11 Standard mode 1000 ns tRCL, rise time of SCL signal
Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
B = 100 pF max 10 40 ns
C
B = 400 pF max 20 80 ns
t11A Standard mode 1000 ns tRCL1, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
B = 100 pF max 10 80 ns
C
B = 400 pF max 20 160 ns
t12 Standard mode 300 ns tFCL, fall time of SCL signal
Fast mode 20 + 0.1 CB 300 ns
High speed mode
C
B = 100 pF max 10 40 ns
C
B = 400 pF max 20 80 ns
tSP Fast mode 0 50 ns Pulse width of suppressed spike
High speed mode 0 10 ns
1Guaranteed by initial characterization. CB refers to capacitive load on the bus line, tr and tf measured between 0.3 VDD and 0.7 VDD.
2A device must provide a data hold time for SDA in order to bridge the undefined region of the SCL falling edge.
TIMING DIAGRAM
SCL
S
DA
PS S P
t8
t6
t5
t3t10 t9
t4
t6t1
t7
t2
t11 t12
0
6030-002
Figure 2. Timing Diagram for 2-Wire Serial Interface
ADG793A/ADG793G
Rev. 0 | Page 9 of 24
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +6 V
Analog, Digital Inputs −0.3 V to VDD + 0.3 V or 30 mA,
whichever occurs first
Continuous Current, S or D Pins 100 mA
Peak Current, S or D Pins 300 mA (pulsed at 1 ms,
10% duty cycle max)
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
24-Lead LFCSP 30°C/W
Lead Temperature, Soldering
(10 sec)
300°C
IR Reflow, Peak Temperature
(<20 sec)
260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any one
time.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ADG793A/ADG793G
Rev. 0 | Page 10 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2
. THE EXPOSED PAD MUST BE TIED TO GND.
1S1A
2S1B
3D1
4NC
5S1C
6NC
15 D3
16 NC
17 S3C
18 A2
14 S3B
13 S3A
7
S2A
8
S2B
9
D2
11
S2C
12
NC
10
NC 21 SCL
22 SDA
23 V
DD
24 GND
20 A0
19 A1
ADG793A
TOP VIEW
(Not to Scale)
06030-029
PIN 1
INDICATOR
NOTES
1. NC = NO CONNECT.
2
. THE EXPOSED PAD MUST BE TIED TO GND.
1S1A
2S1B
3D1
4NC
5S1C
6GPO2
15 D3
16 NC
17 S3C
18 A2
14 S3B
13 S3A
7
S2A
8
S2B
9
D2
11
S2C
12
GPO1
10
NC 21 SCL
22 SDA
23 V
DD
24 GN
D
20 A0
19 A1
ADG793G
TOP VIEW
(Not to Scale)
06030-030
Figure 3. ADG793A Pin Configuration Figure 4. ADG793G Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 S1A A-Side Source Terminal for Mux 1. Can be an input or output.
2 S1B B-Side Source Terminal for Mux 1. Can be an input or output.
3 D1 Drain Terminal for Mux 1. Can be an input or output.
4 NC Not internally connected.
5 S1C C-Side Source Terminal for Mux 1. Can be an input or output.
6 NC/GPO2 Not internally connected for ADG793A. General-Purpose Logic Output 2 for ADG793G.
7 S2A A-Side Source Terminal for Mux 2. Can be an input or output.
8 S2B B-Side Source Terminal for Mux 2. Can be an input or output.
9 D2 Drain Terminal for Mux 2. Can be an input or output.
10 NC Not internally connected.
11 S2C C-Side Source Terminal for Mux 2. Can be an input or output.
12 NC/GPO1 Not internally connected for ADG793A. General-Purpose Logic Output 1 for ADG793G.
13 S3A A-Side Source Terminal for Mux 3. Can be an input or output
14 S3B B-Side Source Terminal for Mux 3. Can be an input or output.
15 D3 Drain Terminal for Mux 3. Can be an input or output.
16 NC Not internally connected.
17 S3C C-Side Source Terminal for Mux 3. Can be an input or output.
18 A2 Logic Input. Sets Bit A2 from the third least significant bit of the 7-bit slave address.
19 A1 Logic Input. Sets Bit A1 from the second least significant bit of the 7-bit slave address.
20 A0 Logic Input. Sets Bit A0 from the first least significant bit of the 7-bit slave address.
21 SCL Digital Input, Serial Clock Line. Open-drain input that is used in conjunction with SDA to clock data into
the device. External pull-up resistor required.
22 SDA Digital I/O. Bidirectional open-drain data line. External pull-up resistor required.
23 VDD Positive Power Supply Input.
24 GND Ground (0 V) Reference.
ADG793A/ADG793G
Rev. 0 | Page 11 of 24
INPUT SIGNAL (V)
OUTPUT SIGNAL (V)
TYPICAL PERFORMANCE CHARACTERISTICS
3.0
0
03
.5
2.5
2.0
1.5
1.0
0.5
0.5 1.0 1.5 2.0 2.5 3.0
TA=25°C
1 CHANNEL
VDD =2.7V,R
L=75Ω
VDD =3V,R
L=75Ω
VDD =3.3V,R
L=75Ω
VDD =2.7V,R
L=1MΩ
VDD =3V,R
L=1MΩ
VDD =3.3V,R
L=1MΩ
06030-003
Figure 5. Analog Signal Range (3 V Supply)
06030-004
5.0
0
06
INPUT SIGNAL (V)
OUTPUT SIGNAL (V)
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
12345
T
A
=25°C
1CHANNEL
V
DD
=5.5V,R
L
=1MΩ
V
DD
=4.5V,R
L
=1MΩ
V
DD
=4.5V,R
L
=75Ω
V
DD
=5V,R
L
=75Ω
V
DD
=5.5V,R
L
=75Ω
V
DD
=5V,R
L
=1MΩ
Figure 6. Analog Signal Range (5 V Supply)
6
0
01
.8
06030-005
4.0
0
03.0
V
D
(V
S
)(V)
R
ON
T
A
= 25°C
1 CHANNEL V
DD
=5.0V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
DD
=4.5V
V
DD
=5.5V
(
Ω)
0.5 1.0 1.5 2.0 2.5
06030-006
.6
V
D
(V
S
)(V)
R
ON
(
Ω)
5
4
3
2
1
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
T
A
= 25°C
1 CHANNEL
V
DD
=2.7V
V
DD
=3.3V
V
DD
=3.0V
Figure 7. On Resistance vs. VD (VS) with 3 V Supply
Figure 8. On Resistance vs. VD (VS) with 5 V Supply
7
0
01
V
D
(V
S
)(V)
R
ON
(
Ω)
6
5
4
3
2
1
0.20.40.60.81.01.21.4
T
A
= 25°C
1 CHANNEL
V
DD
=3V
T
A
= +25°C
T
A
=+85°C
T
A
=–40°C
0
6030-007
Figure 9. On Resistance vs. VD (VS) for Various Temperatures
with 3 V Supply
4.5
0
03.0
V
D
(V
S
)(V)
R
ON
T
A
=+25°C
1 CHANNEL
V
DD
=5V
T
A
= +85°C
(
Ω)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
T
A
= +25°C
T
A
= –40°C
0.51.01.52.02.5
06030-008
Figure 10. On Resistance vs. VD (VS) for Various Temperatures
with 5 V Supply
ADG793A/ADG793G
Rev. 0 | Page 12 of 24
SOURCE VOLTAGE (V)
CHARGE INJECTION (pC)
0
–6
03
.5
0
–120
0.01 1000
FREQUENCY (MHz)
CROSSTALK (dB)
T
A
=25°C
V
DD
=3V/5V
–1
–2
–3
–4
–5
0.5 1.0 1.5 2.0 2.5 3.0
T
A
= 25°C
V
DD
=3V V
DD
=5V
06030-009
Figure 11. Charge Injection vs. Source Voltage
220
160
–40 –20 0 20 40 60 80
TEMPERATURE (°C)
t
ON
/
t
OFF
(ns)
210
200
190
180
170
t
ON
(3V)
t
OFF
(3V)
t
OFF
(5V)
t
ON
(5V)
06030-010
Figure 12. tON/tOFF vs. Temperature
0
–120
0.01 1000
FREQUENCY (MHz)
OFF ISOLATION (dB)
0.1 1 10 100
–20
–40
–60
–80
–100
T
A
=25°C
V
DD
=3V/5V
06030-011
Figure 13. Off Isolation vs. Frequency
0.1 1 10 100
–20
–40
–60
–80
–100
SAME
MULTIPLEXER
DIFFERENT
MULTIPLEXER
06030-012
Figure 14. Crosstalk vs. Frequency
–20
0
0.01 1000
FREQUENCY (MHz)
ATTENUATION (dB)
0.1 1 10 100
–2
–4
–6
–8
–10
–12
–14
–16
–18
T
A
=25°C
V
DD
=5V
06030-013
Figure 15. Bandwidth
0
–100
0.0001 1000
FREQUENCY (MHz)
PSRR (dB)
–10
–20
–30
–40
–50
–60
–70
–80
–90
0.001 0.01 0.1 1 10 100
06030-014
T
A
=25°C
1 CHANNEL
V
DD
=3V/5V
NO DECOUPLING CAPACITORS USED
Figure 16. PSRR vs. Frequency
ADG793A/ADG793G
Rev. 0 | Page 13 of 24
0.40
0
0.1 3.1
f
CLK FREQUENCY (MHz)
IDD (mA)
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.6 1.1 1.6 2.1 2.6
TA= 25°C
VDD =3V
VDD =5V
06030-015
Figure 17. IDD vs. fCLK Frequency
1.4
–0.2
06
I
2
C LOGIC INPUT VOLTAGE (V)
I
DD
(mA)
1.2
1.0
0.8
0.6
0.4
0.2
0
12345
T
A
= 25°C
V
DD
=3V
V
DD
=5V
06030-016
Figure 18. IDD vs. I2C Logic Input Voltage (SDA, SCL)
120
95
–40–200 20406080
TEMPERATURE (°C)
PROPAGATION DELAY (ns)
115
110
105
100
t
PLH
(5V)
t
PHL
(3V)
t
PLH
(3V)
t
PHL
(5V)
06030-017
Figure 19. I2C-to-GPO Propagation Delay vs. Temperature
6
0
–20 0
LOAD CURRENT (mA)
GPO VOLTAGE (V)
5
4
3
2
1
–18 –16 –14 –12 –10 –8 –6 –4 –2
T
A
= 25°C
V
DD
=3V
V
DD
=5V
06030-018
Figure 20. GPO VOH vs. Load Current
2.5
0
03
LOAD CURRENT (mA)
GPO VOLTAGE (V)
5
2.0
1.5
1.0
0.5
5 1015202530
T
A
= 25°C
V
DD
=3V V
DD
=5V
06030-019
Figure 21. GPO VOL vs. Load Current
ADG793A/ADG793G
Rev. 0 | Page 14 of 24
TEST CIRCUITS
SD
R
ON
=V1/I
DS
V1
I
DS
V
S
06030-020
Figure 22. On Resistance
SD
A A
IS(OFF)
V
SVD
ID(OFF)
0
6030-021
Figure 23. Off Leakage
SD
A
V
D
I
D
(ON)
NC
NC = NO CONNECT
06030-022
Figure 24. On Leakage
D
V
DD
0.1µF
V
S
V
OUT
50Ω
50Ω
50Ω
50Ω
NETWORK
ANALYZER
GND
SA
SB
06030-025
Figure 25. Bandwidth
S
D
V
DD
0.1µF
V
S
V
OUT
50Ω
50Ω
50Ω
50Ω
50Ω
NETWORK
ANALYZER
GND
06030-026
Figure 26. Off Isolation
SY
DY
DX
SX
V
DD
0.1µF
V
S
V
OUT
50Ω
50Ω
50Ω
R
L
50Ω
NETWORK
ANALYZER
GND 50Ω50Ω
06030-027
Figure 27. Channel-to-Channel Crosstalk
ADG793A/ADG793G
Rev. 0 | Page 15 of 24
I
2
C
INTERFACE
SCL
GND
SDA
C
L
35pF
R
L
50Ω
V
S
V
OUT
V
DD
5V
0.1µF
SD
SCL
V
OUT
50%
90%
10%
50%
tOFF
tON
CLOC
K
PULSES
CORRESPONDING TO THE
LDSW BITS
SCL
V
GPO
50%
90%
10%
50%
tL
tH
CLOCK PULSES
CORRESPONDING TO THE
LDSW BITS
0
6030-023
Figure 28. Switching Times
I
2
C
INTERFACE
SCL
GND
SDA
C
L
35pF
R
L
50Ω
V
S
V
OUT
V
DD
5
V
0.1µF
SA D
SB
SCL
V
S
t
D
V
OUT
80%
CLOCK PULSE
CORRESPONDING
TO THE LDSW BIT
06030-024
Figure 29. Break-Before-Make Time Delay
ΔV
OUT
Q
INJ
=C
L
×ΔV
OUT
SWITCH ON
SWITCH OFF
V
S
V
OUT
GND
V
DD
R
S
5
V
C
L
1nF
SD
06030-028
Figure 30. Charge Injection
ADG793A/ADG793G
Rev. 0 | Page 16 of 24
TERMINOLOGY
On Resistance (RON)
The series on-channel resistance measured between the S pin
and D pin.
On Resistance Match (ΔRON)
The channel-to-channel matching of on resistance when
channels are operated under identical conditions.
On Resistance Flatness (RFLAT(ON))
The variation of on resistance over the specified range produced
by the specified analog input voltage change with a constant
load current.
Channel Off Leakage (IOFF)
The sum of leakage currents into or out of an off channel input.
Channel On Leakage (ION)
The current loss/gain through an on-channel resistance,
creating a voltage offset across the device.
Input Leakage Current (IIN, IINL, IINH)
The current flowing into a digital input when a specified low
level voltage or high level voltage is applied to that input.
Input/Output Off Capacitance (COFF)
The capacitance between an analog input and ground when the
switch channel is off.
Input/Output On Capacitance (CON)
The capacitance between the inputs or outputs and ground
when the switch channel is on.
Digital Input Capacitance (CIN)
The capacitance between a digital input and ground.
Output On Switching Time (tON)
The time required for the switch channel to close. The time is
measured from 50% of the falling edge of the LDSW bit to the
time the output reaches 90% of the final value.
Output Off Switching Time (tOFF)
The time required for the switch to open. The time is measured
from 50% of the falling edge of the load switch (LDSW) bit to
the time the output reaches 10% of the final value.
I2C-to-GPO Propagation Delay (tH, tl)
The time required for the logic value at the GPO pin to settle
after loading a GPO command. The time is measured from 50%
of the falling edge of the LDSW bit to the time the output
reaches 90% of the final value for high and 10% for low.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitudes plus noise of a signal to
the fundamental.
−3 dB Bandwidth
The frequency at which the output is attenuated by 3 dB.
Off Isolation
The measure of unwanted signal coupling through an off switch.
Crosstalk
The measure of unwanted signal that is coupled through from
one channel to another as a result of parasitic capacitance.
Charge Injection
The measure of the glitch impulse transferred from the digital
input to the analog output during on/off switching.
Differential Gain Error
The measure of how much color saturation shift occurs when
the luminance level changes. Both attenuation and amplification
can occur; therefore, the largest amplitude change between any
two levels is specified and expressed in percent (%).
Differential Phase Error
The measure of how much hue shift occurs when the luminance
level changes. It can be a negative or positive value and is
expressed in degrees of subcarrier phase.
Input High Voltage (VINH)
The minimum input voltage for Logic 1.
Input Low Voltage (VINL)
The maximum input voltage for Logic 0.
Output High Voltage (VOH)
The minimum input voltage for Logic 1.
Output Low Voltage (VOL)
The maximum output voltage for Logic 0.
IDD
Positive supply current.
ADG793A/ADG793G
Rev. 0 | Page 17 of 24
THEORY OF OPERATION
The ADG793A/ADG793G are monolithic CMOS devices
comprising three 3:1 multiplexers/demultiplexers controllable
via a standard I2C serial interface. The CMOS process provides
ultralow power dissipation, yet gives high switching speed and
low on resistance.
The on-resistance profile is very flat over the full analog input
range, and the wide bandwidth ensures excellent linearity and
low distortion. These features, combined with a wide input
signal range make the ADG793A/ADG793G the ideal switching
solution for a wide range of TV applications.
The switches conduct equally well in both directions when on.
In the off condition, signal levels up to the supplies are blocked.
The integrated serial I2C interface controls the operation of the
multiplexers and general-purpose logic pins (ADG793G only).
The ADG793A/ADG793G has many attractive features, such as
the ability to individually control each multiplexer, the option of
reading back the status of any switch, and two general purpose
logic output pins controllable through the I2C interface. The
following sections describe these features in more detail.
I2C SERIAL INTERFACE
The ADG793A/ADG793G are controlled via an I2C-compatible
serial bus interface (refer to the I2C-Bus Specification available
from Philips Semiconductor) that allows the part to operate
as a slave device (no clock is generated by the ADG793A/
ADG793G). The communication protocol between the I2C
master and the device operates as follows.
1. The master initiates data transfer by establishing a start
condition defined as a high-to-low transition on the SDA
line while SCL is high. This indicates that an address/data
stream follows. All slave devices connected to the bus
respond to the start condition and shift in the next eight
bits, consisting of a 7-bit address (MSB first) plus an R/W
bit. This bit determines the direction of the data flow
during the communication between the master and the
addressed slave device.
2. The slave device whose address corresponds to the trans-
mitted address responds by pulling the SDA line low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its serial register. If the R/W bit is set high, the
master reads from the slave device. However, if the R/W bit
is set low, the master writes to the slave device.
3. Data transmits over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of the clock signal, SCL, and remain stable
during the high period of SCL, because a low-to-high
transition when the clock signal is high can be interpreted
as a stop event which ends the communication between the
master and the addressed slave device.
4. After transferring all data bytes, the master establishes a
stop condition, defined as a low-to-high transition on the
SDA line while SCL is high. In write mode, the master pulls
the SDA line high during the tenth clock pulse to establish
a stop condition. In read mode, the master issues a no
acknowledge for the ninth clock pulse (the SDA line
remains high). The master brings the SDA line low before
the tenth clock pulse and then high during the tenth clock
pulse to establish a stop condition.
I2C ADDRESS
The ADG793A/ADG793G have a 7-bit I2C address. The four
most significant bits are internally hardwired and the last three
bits A0, A1, and A2 are user-adjustable. This allows the user to
connect up to eight ADG793As/ADG793Gs to the same bus.
The I2C bit map shows the configuration of the 7-bit address.
7-Bit I2C Address Bit Configuration
MSB LSB
1 0 1 0 A2 A1 A0
WRITE OPERATION
When writing to the ADG793A/ADG793G, the user must
begin with an address byte and R/W bit, after which time the
switch acknowledges that it is prepared to receive data by
pulling SDA low. Data is loaded into the device as a 16-bit word
under the control of a serial clock input, SCL. Figure 31
illustrates the entire write sequence for the ADG793A/
ADG793G. The first data byte (AX7 to AX0) controls the status
of the switches and the LDSW and RESETB bits from the
second byte control the operation mode of the device. Table 6
shows a list of all commands supported by the ADG793A/
ADG793G with the corresponding byte that needs to be loaded
during a write operation.
To achieve the desired configuration, one or more commands
can be loaded into the device. Any combination of the
commands in Table 6 can be used with these restrictions:
• Only one switch from a given multiplexer can be on at any
given time.
• When a sequence of successive commands affect the same
element (that is, the switch or GPO pin), only the last
command is executed.
ADG793A/ADG793G
Rev. 0 | Page 18 of 24
SCL
SDA A2 A1 A0 AX6AX7R/W AX5 AX4 AX3 AX2 AX1 AX0 X X X X X X
RESETB
LDSW
START
CONDITION
BY MASTER
STOP
CONDITION
BY MASTER
ADDRESS BYTE
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH ACKNOWLEDGE
BY SWITCH
06030-031
Figure 31. Write Operation
Table 6. ADG793A/ADG793G Command List
AX7 AX6 AX5 AX4 AX3 AX2 AX1 AX0 Addressed Switch/GPO Pin
0 1 0 0 0 0 0 0 S1A/D1, S2A/D2, S3A/D3 off
1 1 0 0 0 0 0 0 S1A/D1, S2A/D2, S3A/D3 on
0 1 0 0 0 0 0 1 S1B/D1, S2B/D2, S3B/D3 off
1 1 0 0 0 0 0 1 S1B/D1, S2B/D2, S3B/D3 on
0 1 0 0 0 0 1 0 S1C/D1, S2C/D2, S3C/D3 off
1 1 0 0 0 0 1 0 S1C/D1, S2C/D2, S3C/D3 on
X11 0 0 0 0 1 1 Reserved
0 1 0 0 0 1 0 0 S1A/D1 off
1 1 0 0 0 1 0 0 S1A/D1 on
0 1 0 0 0 1 0 1 S1B/D1 off
1 1 0 0 0 1 0 1 S1B/D1 on
0 1 0 0 0 1 1 0 S1C/D1 off
1 1 0 0 0 1 1 0 S1C/D1 on
X11 0 0 0 1 1 1 Reserved
0 1 0 0 1 0 0 0 S2A/D2 off
1 1 0 0 1 0 0 0 S2A/D2 on
0 1 0 0 1 0 0 1 S2B/D2 off
1 1 0 0 1 0 0 1 S2B/D2 on
0 1 0 0 1 0 1 0 S2C/D2 off
1 1 0 0 1 0 1 0 S2C/D2 on
X11 0 0 1 0 1 1 Reserved
0 1 0 0 1 1 0 0 S3A/D3 off
1 1 0 0 1 1 0 0 S3A/D3 on
0 1 0 0 1 1 0 1 S3B/D3 off
1 1 0 0 1 1 0 1 S3B/D3 on
0 1 0 0 1 1 1 0 S3/C/D3 off
1 1 0 0 1 1 1 0 S3/C/D3 on
X11 0 0 1 1 1 1 Reserved
X11 0 1 0 0 0 0 Mux 1 disabled (all switches connected to D1 are off)
X11 0 1 0 0 0 1 Mux 2 disabled (all switches connected to D2 are off)
X11 0 1 0 0 1 0 Mux 3 disabled (all switches connected to D3 are off)
0 1 0 1 0 0 1 1 Reserved for ADG793A/GPO1 low for ADG793G
1 1 0 1 0 0 1 1 Reserved for ADG793A/GPO1 high for ADG793G
0 1 0 1 0 1 0 0 Reserved for ADG793A/GPO2 low for ADG793G
1 1 0 1 0 1 0 0 Reserved for ADG793A/GPO2 high for ADG793G
0 1 0 1 0 1 0 1 Reserved for ADG793A/GPO1, GPO2 low for ADG793G
1 1 0 1 0 1 0 1 Reserved for ADG793A/GPO1, GPO2 high for ADG793G
0 1 0 1 1 1 1 1 All muxes disabled (all switches are off)
1 1 0 1 1 1 1 1 Reserved
1X = Logic state does not matter.
ADG793A/ADG793G
Rev. 0 | Page 19 of 24
LDSW BIT
The LDSW bit allows the user to control the way the device
executes the commands loaded during the write operations.
The ADG793A/ADG793G execute all the commands loaded
between two successive write operations that have set the
LDSW bit high.
Setting the LDSW high for every write cycle ensures that the
device executes the command right after the LDSW bit was
loaded into the device. This setting can be used when the
desired configuration can be achieved by sending a single
command or when the switches and/or GPO pin are not
required to be updated at the same time. When the desired
configuration requires multiple commands with simultaneous
updates, the LDSW bit should be set low while loading the
commands, except the last one when the LDSW bit should be
set high. Once the last command with LDSW = high is loaded,
the device executes all commands received since the last update
simultaneously.
POWER ON/SOFTWARE RESET
The ADG793A/ADG793G have a software reset function
implemented by the RESETB bit from the second data byte
loaded into the device during a write operation. For normal
operation of the multiplexers and GPO pins, this bit should be
set high. When RESETB = low or after power-up, the switches
from all multiplexers are turned off (open) and the GPO pins
are set low.
READ OPERATION
When reading data back from the ADG793A/ADG793G, the
user must begin with an address byte and R/W bit. The switch
then acknowledges that it is prepared to transmit data by
pulling SDA low. Following this acknowledgement, the
ADG793A/ADG793G transmit two bytes on the next clock
edges. These bytes contain the status of the switches, and each
byte is followed by an acknowledge bit. A logic high bit
represents a switch in the on (close) state while a low represents
a switch in the off (open) state. For the GPO pin (ADG793G
only), the bit represents the logic value of the pin. Figure 32
illustrates the entire read sequence.
The bit maps accompanying Figure 32 show the relationship
between the elements of the ADG793A and ADG793G (that it,
the switches and GPO pins) and the bits that represent their
status after a completed read operation.
Bit Map for the ADG793A
RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
S1A-D1 S1B-D1 S1C-D1 - S2A-D2 S2B-D2 S2C-D2 - S3A-D3 S3B-D3 S3C-D3 - - - - -
Bit Map for the ADG793G
RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
S1A-D1 S1B-D1 S1C-D1 - S2A-D2 S2B-D2 S2C-D2 - S3A-D3 S3B-D3 S3C-D3 - GPO1 GPO2 - -
Read Operation
SCL
SDA A2 A1 A0 RB14RB15R/W RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
START
CONDITION
BY MASTER
STOP
CONDITION
BY MASTER
ADDRESS BYTE
ACKNOWLEDGE
BY SWITCH
ACKNOWLEDGE
BY SWITCH ACKNOWLEDGE
BY SWITCH
06030-032
Figure 32. ADG793A/ADG793G Read Operation
ADG793A/ADG793G
Rev. 0 | Page 20 of 24
EVALUATION BOARD
The ADG793G evaluation kit allows designers to evaluate the
high performance of the device with a minimum of effort.
The evaluation kit includes a printed circuit board populated
with the ADG793G. The evaluation board can be used to
evaluate the performance of both the ADG793A and
ADG793G. It interfaces to the USB port of a PC, or it can be
used as a standalone evaluation board.
Software is available with the evaluation board that allows the
user to program the ADG793G easily through the USB port. The
software runs on any PC that has Microsoft® Windows® 2000 or
Windows XP installed with a minimum screen resolution of
1200 × 768. See Figure 33 and Figure 34 for schematics of the
evaluation board.
USING THE ADG793G EVALUATION BOARD
The ADG793G evaluation kit is a test system designed to
simplify the evaluation of the device. Each input/output
of the part comes with a socket specifically chosen for easy
audio/video evaluation. An evaluation board data sheet is also
available and provides full instructions for operating the
evaluation board.
ADG793A/ADG793G
Rev. 0 | Page 21 of 24
J2-1 J2-2 T1
T4
R5
75Ω
R6
75Ω
R1
2.2kΩ
R2
2.2kΩ
R7
0Ω
C4
10µF
C9
0.1µF
C18
0.1µF
C23
2.2µF
3.3V 3.3V
3.3V
SHIELD
1
2
3
4
5
J1
USB-MINI-B
VBUS
D–
D+
IO
GND
42
44
54
9
8
33
34
35
36
37
38
39
40
1
2
13
14
PA0/INT0
*WAKEUP
CLKOUT
D–
D+
PA1/INT1
PA2/ *SLOE
PA3/ *W U2
PA4/ FIFOADR0
PA5/ FIFOADR1
PA6/ *PKTEND
PA7/*FLD/SLCS
RESET
RDY0/*SLRD
RDY1/*SLWR
IFCLK
RSVD
18
PB0/FD0 19
PB1/FD1 20
PB2/FD2 21
PB3/FD3 22
PB4/FD4 23
PB5/FD5 24
PB6/FD6 25
PB7/FD7 45
PD0/FD8 46
PD1/FD9 47
PD2/FD10 48
PD3/FD11 49
PD4/FD12 50
PD5/FD13 51
PD6/FD14 52
29
30
31
16
15
4
5
PD7/FD15
3.3V
3.3V
3.3V
3.3V
3.3V
7
3
43
55
32
27
17
11
AVCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
R31
10kΩ
R32
10kΩ
R12
2.2kΩ
R9
2.2kΩ
R10
10kΩ
SCL_EN
CTL0/*FLAGA
CTL1/*FLAGB
CTL2/*FLAGC
SDA
SCL
XTALOUT
XTALIN XTAL1
24MHz
AGND
GND
GND
GND
GND
GND
GND
GND
6
10
12
26
28
41
53
56
3.3V
T27 T28
C21
0.1µF
C20
0.1µF
C19
0.1µF
C8
0.1µF
C7
0.1µF
C5
0.1µF
C6
0.1µF
J5
AB
VDD
C3
0.1µF
C13
10µF
8
7
5
1
2
6
3
4
IN1
IN2
SD
OUT1
OUT2
ERROR
NR
U5
GND
ADP3303-3.3
C16
0.1µF
C14
10µF
C15
0.1µF
T26
3.3V
R11
1kΩ
C10
22pF
C17
22pF
3.3V
D4
24LC64
A0
A1
A2
VSS
VCC
WP
SCL
SDA
U2
C22
0.1µF
C2
0.1µF
U3
CY7C68013-CS P
Q1
Q2
G
G
SD
SD
SCL_EN
VDD
SDA
SCL
U4
ADG821
8
7
6
5
1
2
3
4
S1
D1
IN2
GND
VDD
IN1
D2
S2
1
2
3
4
8
7
6
5
06030-033
*DENOTES
PROGRAMMABLE
POLARITY.
Figure 33. EVAL-ADG793GEB Schematic, USB Controller Section
ADG793A/ADG793G
Rev. 0 | Page 22 of 24
1
5
4
2
3
K4
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
1
5
4
2
3
K5
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
1
5
4
2
3
K6
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
R19
R20
R21
R22
R23
R24
T10
T11
T12
T13
T14
T15
A
T2 T3
T22 T23
T24
T25
T7 T8 T9 T5 T6
12
7
8
9
10
11
23
24
22
21
20
19
U1
ADG793G
25
PADDLE
13
14
15
16
17
18
1
2
3
4
5
6
R36
0Ω
GPO1 VDD
A
1
5
4
2
3
K7
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
1
5
4
2
3
K8
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
1
5
4
2
3
K9
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
GPO2
R25
R26
R28
R29
R30
R27
T16 T17 T18 T19 T20 T21
1
5
4
2
3
K3
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
1
5
4
2
3
K2
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
1
5
4
2
3
K1
PHONO_DUAL
BOTTOM
TOP
GND
CASE
CASE
R13
R14
R15
R16
R17
R3
10kΩ
R4
10kΩ
R8
10kΩ
R34
0Ω
R35
0Ω
R18
J3
J7
J8
J6-1
J6-2
J6-3
J4-1
J4-3
J4-2
GPO1
GPO2
C1
0.1µF
SCL
SCL
SDA
SCL
SDA
SDA
06030-034
Figure 34. EVAL-ADG793GEB Schematic, Chip Section
ADG793A/ADG793G
Rev. 0 | Page 23 of 24
OUTLINE DIMENSIONS
*COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
EXCEPT FOR EXPOSED PAD DIMENSION
1
24
6
7
13
19
18
12
*2.45
2.30 SQ
2.15
0.60 MAX
0.50
0.40
0.30
0.30
0.23
0.18
2.50 REF
0.50
BSC
12° MAX
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
PIN 1
INDICATOR TOP
VIEW 3.75
BSC SQ
4.00
BSC SQ PIN 1
INDICATOR
0.60 MAX
COPLANARITY
0.08
0.20 REF
0.23 MIN
EXPOSED
PA D
(BOTTOMVIEW)
Figure 35. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-24-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range I2C Speed Package Description Package Option
ADG793ABCPZ-REEL1−40°C to +85°C 100 kHz, 400 kHz 24-Lead LFCSP_VQ CP-24-2
ADG793ABCPZ-500RL71−40°C to +85°C 100 kHz, 400 kHz 24-Lead LFCSP_VQ CP-24-2
ADG793ACCPZ-REEL1−40°C to +85°C 100 kHz, 400 kHz, 3.4 MHz 24-Lead LFCSP_VQ CP-24-2
ADG793ACCPZ-500RL71−40°C to +85°C 100 kHz, 400 kHz, 3.4 MHz 24-Lead LFCSP_VQ CP-24-2
ADG793GBCPZ-REEL1−40°C to +85°C 100 kHz, 400 kHz 24-Lead LFCSP_VQ CP-24-2
ADG793GBCPZ-500RL71−40°C to +85°C 100 kHz, 400 kHz 24-Lead LFCSP_VQ CP-24-2
ADG793GCCPZ-REEL1−40°C to +85°C 100 kHz, 400 kHz, 3.4 MHz 24-Lead LFCSP_VQ CP-24-2
ADG793GCCPZ-500RL71−40°C to +85°C 100 kHz, 400 kHz, 3.4 MHz 24-Lead LFCSP_VQ CP-24-2
EVAL-ADG793GEB2 Evaluation Board
1 Z = Pb-free part.
2 Evaluation board is RoHS compliant.
ADG793A/ADG793G
Rev. 0 | Page 24 of 24
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06030–0–7/06(0)
