Cover 88PG839 Ultra Low Power, 2MHz, 2A Output Current Field Programmable Hysteretic Step-Down Switching Regulator Datasheet Microsoft Use Only Doc. No. MV-S106081-02, Rev. D July 8, 2010 Marvell. Moving Forward Faster Document Classification: Proprietary 88PG839 Datasheet Document Conventions Note: Provides related information or information of special importance. Caution: Indicates potential damage to hardware or software, or loss of data. Warning: Indicates a risk of personal injury. Document Status Doc Status: 2.00 Technical Publication: 0.xx For more information, visit our website at: www.marvell.com Disclaimer No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose, without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. 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At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any such information. Copyright (c) 1999-2009. Marvell International Ltd. All rights reserved. Marvell, Moving Forward Faster, the Marvell logo, Alaska, AnyVoltage, DSP Switcher, Fastwriter, Feroceon, Libertas, Link Street, PHYAdvantage, Prestera, TopDog, Virtual Cable Tester, Yukon, and ZJ are registered trademarks of Marvell or its affiliates. CarrierSpan, LinkCrypt, Powered by Marvell Green PFC, Qdeo, QuietVideo, Sheeva, TwinD, and VCT are trademarks of Marvell or its affiliates. Patent(s) Pending--Products identified in this document may be covered by one or more Marvell patents and/or patent applications. Doc. No. MV-S106081-02 Rev. D Page 2 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 88PG839 Ultra Low Power, 2MHz, 2A Output Current Field Programmable Hysteretic Step-Down Switching Regulator PRODUCT OVERVIEW The Marvell(R) 88PG839 is a high performance, hysteretic step-down switching regulator that utilizes a proprietary, internally compensated Pulse Width Modulation (PWM) control to regulate the output voltage. The regulator offers fast transient response time and requires no external compensation. The device operates from an input voltage range of 2.7V to 5.5V and delivers up to 2A DC output current. The switching frequency is typically 2MHz, allowing the use of low profile surface mounted inductors and low value ceramic capacitors. Features The step-down regulator includes programmable ability to easily set the output voltage with external resistors. The output voltage range is 0.64V to 3.63V. The output voltage can be changed On-the-Fly (OTF) from a nominal value by a percentage through connecting the OTF pin to a high level, making it ideal for portable applications. The adjustment percentage is user programmable from -20% to +10% by a resistor connected between PSET pin and ground. Input voltage range 2.7V to 5.5V Output voltage range 0.64V to 3.63V Hysteretic step-down regulator 32A (typical) quiescent current 3mm x 4mm DFN-12 package 2MHz switching frequency Small and low-profile inductors Stable with low-ESR ceramic output capacitor -20% to +10% On-the-Fly output voltage adjustment Internal compensation Up to 95% efficiency 2A DC output current 72 output voltage selections using AnyVoltageTM Technology Built-in under/over voltage lockout Thermal shutdown protection Soft start to minimize the in-rush current Applications The 88PG839 can be externally set to Pulse Frequency Modulation (PFM) or Pulse Width Modulation (PWM) mode via the PFM pin. The quiescent current in PFM mode is less than 32A. The regulator can achieve 95% efficiency under loaded conditions. Portable computing Personal Digital Assistant (PDA) Cell phones Ultra-Mobile PC (UMPC) Figure 1: Typical Application Circuit R2 U1 88PG839 Example placement for input capacitors R3 1 PFM 2 EN 3 4 5 6 PSET PFM VSET EN SHDN/SDI SGND SVIN SFB SW PG PVIN 12 PSET 11 VSET 10 SHDN /SDI 9 SVIN 8 PG L1* 1.0uH R1 10 VIN C3 0.1uF/10V 7 IC PVIN PGND Cin PVIN Trace PGND Trace Yes C1 C2* VIN 10uF/6.3V 22uF/6.3V Hi di/dt trace Cin PVIN Trace VOUT Caution! IC PVIN PGND R4 1M 13 SW OTF PGND OTF * See Section 6, Applications Information for the inductor and output capacitance recommendations . PGND Trace No All input capacitors (Cin) must place close to the IC!!!! This is a very high frequency device, and proper PCB layout is required. Refer to Section 6, Applications Information, on page 47 for further information. Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 3 88PG839 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S106081-02 Rev. D Page 4 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Table of Contents Table of Contents Product Overview ....................................................................................................................................... 3 Table of Contents ....................................................................................................................................... 5 List of Figures............................................................................................................................................. 7 List of Tables .............................................................................................................................................. 9 1 Signal Description ....................................................................................................................... 11 1.1 Pin Configuration.............................................................................................................................................11 1.2 Pin Description ................................................................................................................................................12 2 Electrical Specifications ............................................................................................................. 15 2.1 Absolute Maximum Ratings ............................................................................................................................15 2.2 Recommended Operating Conditions .............................................................................................................16 2.3 Electrical Characteristics .................................................................................................................................17 2.4 Switching Step-down Regulator ......................................................................................................................18 3 Functional Description................................................................................................................ 21 3.1 Overview .........................................................................................................................................................21 3.2 Soft Start .........................................................................................................................................................22 3.3 Output Voltage Setting ....................................................................................................................................22 3.3.1 Serial Programmability of Switching Regulator (SDI) .......................................................................22 3.3.2 Logic Programmability ......................................................................................................................24 3.3.3 Programmability--AnyVoltage(R) Technology....................................................................................24 3.4 Enable and Shutdown .....................................................................................................................................25 3.5 PFM and PWM Mode Selection ......................................................................................................................25 3.6 Under Voltage Lockout (UVLO) ......................................................................................................................25 3.7 Over Voltage Protection (OVP) .......................................................................................................................26 3.8 Thermal Shutdown ..........................................................................................................................................26 3.9 Power Good (PG)............................................................................................................................................27 4 Functional Characteristics ......................................................................................................... 29 4.1 Startup Waveforms .........................................................................................................................................29 4.2 Short-Circuit Waveform ..................................................................................................................................31 4.3 Switching Waveforms......................................................................................................................................32 4.4 Load Transient Waveforms .............................................................................................................................34 5 Typical Characteristics ............................................................................................................... 37 5.1 Efficiency .........................................................................................................................................................37 Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 5 88PG839 Datasheet 5.2 Load Regulation ..............................................................................................................................................39 5.3 Dropout Voltage ..............................................................................................................................................39 5.4 RDS (ON) Resistance .....................................................................................................................................40 5.5 IC Case and Inductor Temperature.................................................................................................................41 5.6 Input Voltage ...................................................................................................................................................42 5.7 Temperature 6 Applications Information ............................................................................................................ 47 6.1 Inductor and Output capacitance recommendations.......................................................................................47 6.2 PC Board Layout Conciderations and Guidelines ...........................................................................................47 6.2.1 PC Board Layout Examples..............................................................................................................50 6.3 Bill of Materials ...............................................................................................................................................52 7 Mechanical Drawings .................................................................................................................. 53 7.1 Mechanical Drawings ......................................................................................................................................53 7.2 Typical Pad Layout Dimensions ......................................................................................................................54 7.2.1 Recommended Solder Pad Layout ...................................................................................................54 8 Part Order Numbering/Package Marking .................................................................................. 55 8.1 Part Order Numbering Scheme.......................................................................................................................55 8.2 Part Ordering Options .....................................................................................................................................55 8.3 Package Marking ............................................................................................................................................56 A Revision History .......................................................................................................................... 57 ...............................................................................................................................................44 Doc. No. MV-S106081-02 Rev. D Page 6 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 List of Figures List of Figures Product Overview ....................................................................................................................................... 3 Figure 1: 1 Typical Application Circuit...................................................................................................................3 Signal Description ........................................................................................................................... 11 Figure 2: DFN-12 Pin Configuration (Top View) ..............................................................................................11 2 Electrical Specifications ................................................................................................................. 15 3 Functional Description.................................................................................................................... 21 4 Figure 3: Block Diagram ..................................................................................................................................21 Figure 4: Serial Programmability......................................................................................................................22 Figure 5: UVLO and OVP Waveforms .............................................................................................................26 Figure 6: Power Good Operating Waveform....................................................................................................27 Functional Characteristics.............................................................................................................. 29 Figure 7: 5 Startup Using Enable Pin..................................................................................................................29 Figure 8: Turn Off Using Enable Pin ................................................................................................................29 Figure 9: Startup Using Shutdown Pin .............................................................................................................29 Figure 10: Turn Off Using Shutdown Pin ...........................................................................................................29 Figure 11: Soft Start ..........................................................................................................................................30 Figure 12: Hot Plug ............................................................................................................................................30 Figure 13: UVLO and OVP Thresholds .............................................................................................................30 Figure 14: Step-Down Short Circuit ...................................................................................................................31 Figure 15: DCM Mode........................................................................................................................................32 Figure 16: PWM Mode .......................................................................................................................................32 Figure 17: PWM Output Ripple Voltage .............................................................................................................33 Figure 18: Slow Load Rise Time ........................................................................................................................34 Figure 19: Slow Load Fall Time .........................................................................................................................34 Figure 20: Fast Load Rise Time.........................................................................................................................34 Figure 21: Fast Load Fall Time ..........................................................................................................................34 Figure 22: Load Transient Response.................................................................................................................35 Typical Characteristics ................................................................................................................... 37 Figure 23: Efficiency vs. Output Current (PFM = High)......................................................................................37 Figure 24: Efficiency vs. Output Current in Log Scale (PFM = High).................................................................37 Figure 25: Efficiency vs. Output Current (PFM = Low) ......................................................................................38 Figure 26: Efficiency vs. Output Current in Log Scale (PFM = Low)..................................................................38 Figure 27: Output Voltage vs. Output Current ...................................................................................................39 Figure 28: Step-down Regulator Dropout ..........................................................................................................39 Figure 29: Resistance vs. Input Voltage ............................................................................................................40 Figure 30: Resistance vs. Temperature .............................................................................................................40 Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 7 88PG839 Datasheet Figure 31: 6 7 8 A Input Current vs. Output Current ......................................................................................................41 Figure 32: IC Case Temperature vs. Output Current .........................................................................................41 Figure 33: Inductor Temperature vs. Output Current .........................................................................................41 Figure 34: Supply Current vs. Input Voltage ......................................................................................................42 Figure 35: Shutdown Supply Current vs. Input Voltage .....................................................................................42 Figure 36: Shutdown Enable Threshold vs. Input Voltage .................................................................................42 Figure 37: Output Voltage vs. Input Voltage ......................................................................................................43 Figure 38: Efficiency vs. Input Voltage...............................................................................................................43 Figure 39: Load Regulation vs. Input Voltage ....................................................................................................43 Figure 40: Average Output Current Limit vs. Input Voltage ...............................................................................43 Figure 41: Frequency vs. Input Voltage .............................................................................................................43 Figure 42: Supply Current vs. Temperature.......................................................................................................44 Figure 43: UVLO Threshold vs. Temperature ....................................................................................................44 Figure 44: OVP Threshold vs. Temperature ......................................................................................................44 Figure 45: Shutdown Enable Threshold vs. Temperature .................................................................................44 Figure 46: Shutdown Supply Current vs. Temperature......................................................................................45 Figure 47: Output Voltage vs. Temperature.......................................................................................................45 Figure 48: Efficiency vs. Temperature ...............................................................................................................45 Figure 49: Load Regulation vs. Temperature ....................................................................................................45 Figure 50: Line Regulation vs. Temperature......................................................................................................45 Figure 51: Average Output Current Limit vs. Temperature ................................................................................46 Figure 52: Frequency vs. Temperature..............................................................................................................46 Applications Information ................................................................................................................ 47 Figure 53: PCB Board Schematic ......................................................................................................................49 Figure 54: Top Silk Screen, Top Traces, Vias, and Copper (Not to scale) ........................................................50 Figure 55: Bottom Silk Screen, Top Traces, Vias, and Copper (Not to scale) ...................................................51 Mechanical Drawings ...................................................................................................................... 53 Figure 56: 3mm x 4mm 12-Lead DFN Mechanical Drawing ..............................................................................53 Figure 57: 3mm x 4mm DFN-12 Land Pattern (mm)..........................................................................................54 Part Order Numbering/Package Marking....................................................................................... 55 Figure 58: Sample Part Number ........................................................................................................................55 Figure 59: Package Marking and Pin 1 Location ...............................................................................................56 Revision History ............................................................................................................................... 57 Doc. No. MV-S106081-02 Rev. D Page 8 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 List of Tables List of Tables 1 2 3 Signal Description ............................................................................................................................ 11 Table 1: Pin Types ..........................................................................................................................................12 Table 2: Pin Description..................................................................................................................................12 Electrical Specifications .................................................................................................................. 15 Table 3: Absolute Maximum Ratings ..............................................................................................................15 Table 4: Recommended Operating Conditions...............................................................................................16 Table 5: Electrical Characteristics ..................................................................................................................17 Table 6: Switching Step-down Regulator........................................................................................................18 Functional Description..................................................................................................................... 21 Table 7: Default Value of Data Field ...............................................................................................................23 Table 8: Voltage and Percentage Set .............................................................................................................23 Table 9: VSET and PSET Logic Programming ...............................................................................................24 Table 10: VSET and PSET Programming Table for 5% Resistors ...................................................................25 4 Functional Characteristics............................................................................................................... 29 5 Typical Characteristics .................................................................................................................... 37 6 Applications Information ................................................................................................................. 47 Table 11: Capacitance Recommendations .......................................................................................................47 Table 12: BOM..................................................................................................................................................52 Table 13: BOM for Microsoft Application ..........................................................................................................52 7 Mechanical Drawings ....................................................................................................................... 53 8 Part Order Numbering/Package Marking........................................................................................ 55 Table 14: A Part Order Options............................................................................................................................55 Revision History ............................................................................................................................... 57 Table 15: Revision History ................................................................................................................................57 Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 9 88PG839 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S106081-02 Rev. D Page 10 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Signal Description Pin Configuration 1 Signal Description 1.1 Pin Configuration Figure 2: DFN-12 Pin Configuration (Top View) OTF 1 12 PSET PFM 2 11 VSET EN 3 10 SHDN/SDI SGND 4 9 SVIN SFB 5 8 PG SW 6 7 PVIN 13 PGND Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 11 88PG839 Datasheet 1.2 Pin Description Table 1: Pin Types Pi n Typ e D e s c r i p t io n I Input O Output S Supply NC Not Connected GND Ground Table 2: Pin Description Pi n # Pin Name P in Ty p e P in Fu n c ti on 1 OTF I On-the-Fly Logic input for dynamic output voltage change: * Logic high sets the output voltage that is determined from the VSET and PSET resistors. * Logic low sets the output voltage that is determined from the VSET resistor only. * Do not float this pin. 2 PFM I Pulse Frequency Modulation * Logic input to set the operation mode. Connect PFM to SVIN to select PFM mode under light load conditions and connect PFM to SGND to select forced PWM mode in light load condition. See Section 6, Applications Information for the inductor and output capacitance recommendations when operating and PFM and PWM mode. * Do not float this pin. 3 EN I Enable * Logic high enables the switching step-down regulator. * In shutdown, the switch node for the step-down regulator is high impedance. Logic low disables the step-down switching regulator. The low signal has to be at least 20s to disable the switching regulator. (See Table 5, Electrical Characteristics, on page 17 for detailed logic high and logic low specifications) * SHDN/SDI must be kept low to enable EN function * Do not float this pin. 4 SGND GND 5 SFB I Signal Ground * This pin must be connected to PGND and make a star connection to system ground. Switching Regulator Output Voltage Sense Feedback * Senses the output voltage of the switching regulator. * Connect to the output capacitor of the switching regulator. Doc. No. MV-S106081-02 Rev. D Page 12 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Signal Description Pin Description Table 2: Pin Description (Continued) Pi n # Pin Name P in Ty p e P in Fu n c ti on 6 SW O Switch Node * Internally connected to the drains of the high side and low side MOSFETs. * Connect to the external inductor. 7 PVIN S Switching Regulator Power Input * Power input voltage. Internally connected to the source of the high side MOSFET. Connect a ceramic input capacitor between PVIN and PGND and place it as close as possible to PVIN and PGND pins. See Section 6, Applications Information for example. * The voltage between SVIN and PVIN should equal to 50mV or less. 8 PG O Switching Regulator Power Good Output * It is an open-drain output. * Connect a 100k pull-up resistor from this pin to VOUT or a logic rail that is equal to or less than SVIN. * The PG is held low when the output voltage is outside its regulation band and goes high after the output voltage is within regulation. * In shutdown, the PG will be actively on. 9 SVIN S Signal Input Voltage * Input voltage to the internal circuitry. See Table 5, Electrical Characteristics, on page 17 for input voltage range. * Connect a decoupling capacitor between SVIN an SGND and position it as close as possible to the IC. See Section 6, Applications Information for example. * The voltage between SVIN and PVIN should equal to 50mV or less. 10 SHDN/SDI I Shutdown / Serial Data Input * Logic high disables the switching step-down regulator. In shutdown, the switch node for the step-down regulator is high impedance. Logic high enables the step-down switching regulator. * EN must be kept high to enable the shutdown function. * Input data into this pin is used to program the output voltage (see Section 3.3.1, Serial Programmability of Switching Regulator (SDI), on page 22). * To program the output voltage using serial interface, the part must be in PWM mode (see Section 3.5). * Do not share this pin with other serial interface pins. * Do not float this pin. 11 VSET I Switching Regulator Voltage Set To set the nominal output voltage values: * Connect VSET to SVIN or GND in conjunction with PSET connected to SVIN or GND to set four nominal output voltages. * Connect a resistor from VSET to GND to set eight nominal output voltages. See Table 9, VSET and PSET Logic Programming, on page 24 for resistor values and Output Voltage Settings. * The total capacitance across this pin and SGND must be 25pF or less. Use resistor values with a 5% tolerance or better. OTF pin must be kept low to maintain nominal output voltages. * Do not float this pin. Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 13 88PG839 Datasheet Table 2: Pin Description (Continued) Pi n # Pin Name P in Ty p e 12 PSET I 13 PGND GND P in Fu n c ti on Switching Regulator Percent Set To set the margining percentage set to output voltage: * Set the nominal output voltage in conjunction with VSET as described above. * Connect an external resistor to ground to set the percentage change of the output voltage. See Table 9, VSET and PSET Logic Programming, on page 24 for resistor values and Output Voltage Settings. * The total capacitance across this pin and SGND must be 25pF or less. Use resistor values with a 5% tolerance or better. * Do not float this pin. Power Ground * It must be connected to the negative terminals of the input and output capacitors. Doc. No. MV-S106081-02 Rev. D Page 14 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Electrical Specifications Absolute Maximum Ratings 2 Electrical Specifications 2.1 Absolute Maximum Ratings Table 3: Absolute Maximum Ratings1 Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Parameter R a ng e U n i ts VPVIN to PGND -0.3 to 6.0 V VPVIN to VSVIN -0.3 to 0.3 V PGND to SGND -0.3 to 0.3 V VSW to PGND2 -0.3 to (VPVIN + 0.3) V VSFB to SGND -0.3 to (VSVIN + 0.3) V VVSET, VPSET to SGND -0.3 to (VSVIN + 0.3) V VPFM, VOTF ,VEN , VSHDN/SDI, VPG to SGND -0.3 to (VSVIN + 0.3) V -40 to 85 C 150 C -65 to +150 C Operating Ambient Temperature Range3 Maximum Junction Temperature Storage Temperature Range 1. Exceeding the absolute maximum rating may damage the device. 2. Capable of -1.0V for less than 50ns and 7V for less than 200ns. 3. Specifications over the -40C to 85C operating temperature ranges are assured by design, characterization, and correlation with statistical process controls. Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 15 88PG839 Datasheet 2.2 Table 4: Recommended Operating Conditions Recommended Operating Conditions1 Sy m b o l Parameter Min VSVIN Signal Input Voltage VPVIN Power Input Voltage JA Package Thermal Resistance2 Max U n i ts 2.7 5.5 V 2.7 5.5 V JC TJMAX Maximum Operational Junction Temperature Typ 66.2 C/W 43.8 C/W 125 C 1. This device is not guaranteed to function outside the specified operating range. 2. Simulated on a 3"x4.5" 4-Layer JEDEC PCB with 2 thermal vias. Doc. No. MV-S106081-02 Rev. D Page 16 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Electrical Specifications Electrical Characteristics 2.3 Table 5: Electrical Characteristics Electrical Characteristics The following applies unless otherwise noted (refer to schematic shown in Figure 1): VSVIN = VPVIN = VEN = 3.3V, VPSET = VSHDN/SDI = SGND = PGND, VBUCK = 1.5V, TA = 25 C. Bold Values indicate 0C TA 85C. Specifications over temperature are assured by design, characterization, and correlation with statistical process controls. Sy m b o l P a r a m e te r C o n di ti o ns M in VSVIN Signal Input Voltage VSVIN = VPVIN VPVIN Power Input Voltage VSVIN = VPVIN IQ_PFM Total Quiescent Current (PFM Mode) No load VPFM = VSVIN = VPVIN IQ_PWM Total Quiescent Current (PWM Mode) No load VPFM = VSGND ISHDN Shutdown Supply Current VSHDN/SDI = VSVIN = VPVIN, VEN = 0V VUVLO Under Voltage Lockout High Threshold, VSVIN increasing Low Threshold, VSVIN decreasing VOVP Over Voltage Protection TOTS Over-Temperature Thermal Shutdown 2.7 5.5 V 32 50 A 6 9 mA 10 A 2.700 V 2.600 2.400 2.500 5.780 5.500 V 5.975 V 5.670 110 C EN, SHDN/SDI, OTF, and PFM Input Voltage Threshold Logic Low IEN Enable Input Current VEN = VSVIN = VPVIN VEN = 0V 2 0.4 -10 VPFM = 0V -10 Copyright (c) 2010 Marvell A A 10 -10 A A 10 VPFM = VSVIN = VPVIN V V 10 VOTF = VSVIN = VPVIN VOTF = 0V July 8, 2010, 2.00 V Low Threshold, TJ decreasing (Enable regulator) VIL PFM Input Current 5.5 C Logic High IPFM 2.7 150 EN, SHDN/SDI, OTF, and PFM Input Voltage Threshold OTF Input Current Units High Threshold, TJ increasing (Disable regulator) VIH IOTF Max High Threshold, VSVIN increasing Low Threshold, VSVIN decreasing Ty p A A Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 17 88PG839 Datasheet 2.4 Table 6: Switching Step-down Regulator Switching Step-down Regulator The following applies unless otherwise noted (refer to schematic shown in Figure 1): VSVIN = VPVIN = VEN = 3.3V, VPSET = VSHDN/SDI = SGND = PGND, VBUCK = 1.5V, TA = 25 C. Bold Values indicate 0C TA 85C. Specifications over temperature are assured by design, characterization, and correlation with statistical process controls. Sy m b o l P a r a m e te r C o n di ti o ns M in VOUT Output Voltage (PWM Mode) VOTF = VSVIN, RVSET = 18k, RPSET = 100k, PWM mode, ILOAD = 0 - 1.2A Ty p Max 1.025 V Over Temperature1 -2 +2.5 % Over Temperature2 -4 +4 % VOTF = SGND, RVSET = 100k, PWM mode, ILOAD = 0 - 1.2A 1.8 V VOTF = SGND, VVSET = VSVIN, VPSET = SGND, PWM mode, ILOAD = 0 - 1.2A Over Temperature VOUT Output Voltage (PFM Mode) V -4 +4 1.025 VOTF = VSVIN, RVSET = 18k, RPSET = 100k, PFM mode, ILOAD = 10mA Over Temperature -7 VOTF = SGND, RVSET = 100k, PFM mode, ILOAD = 10mA Over Temperature Percentage Set +7 1.8 % V V -7 +7 % VOTF = VSVIN RPSET = 0 -20 % VOTF = VSVIN RPSET = 11k -10 % VOTF = VSVIN RPSET = 18k -7.5 % VOTF = VSVIN RPSET = 30k -5.0 % VOTF = VSVIN RPSET = 51k -2.5 % VOTF = VSVIN RPSET = 100k 2.5 % VOTF = VSVIN RPSET = 160k 5.0 % VOTF = VSVIN RPSET = 270k 7.5 % VOTF = VSVIN RPSET = 470k 10 % Doc. No. MV-S106081-02 Rev. D Page 18 % V VOTF = SGND, VVSET = VSVIN, VPSET = SGND, PFM mode, ILOAD = 10mA PSET Units Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Electrical Specifications Switching Step-down Regulator Table 6: Switching Step-down Regulator (Continued) The following applies unless otherwise noted (refer to schematic shown in Figure 1): VSVIN = VPVIN = VEN = 3.3V, VPSET = VSHDN/SDI = SGND = PGND, VBUCK = 1.5V, TA = 25 C. Bold Values indicate 0C TA 85C. Specifications over temperature are assured by design, characterization, and correlation with statistical process controls. Sy m b o l P a r a m e te r C o n di ti o ns VLNREG Output Voltage Line Regulation VSVIN = VPVIN = 3.0V to 5.0V, ILOAD = 1A -0.8 % VLDREG Output Voltage Load Regulation VSVIN = VPVIN = 5.0V, ILOAD = 500mA to 2A 0.9 % RDSON_HS High Side Switch On Resistance VSVIN = VPVIN = 5V RDSON_LS Low Side Switch On Resistance VSVIN = VPVIN = 5V M in Ty p Max Units 84 140 196 m 102 170 238 m 60 100 140 m 69 115 161 m 2.2 3 3.9 A ILIM Peak Switch Current Limit ILSW_HS High Side Switch Leakage Current VSHDN/SDI = VSVIN = VPVIN, VSW = VSVIN = VPVIN 10 A ILSW_LS Low Side Switch Leakage Current VSHDN/SDI = VSVIN = VPVIN, VSW = PGND 10 A fsw Switching Frequency PWM mode 2.6 MHz DMAX Maximum Duty Cycle THICCUP 1.4 2 100 % Hiccup Mode Time Interval 2 ms tDEGLITCH Deglitch 25 s IFB FB Leakage Current VEN = 0V, VPVIN = VFB = VSHDN/SDI = VSVIN = VPVIN 1 IFB FB Leakage Current VEN = VFB = VSVIN = VPVIN, VVSET = < 1.8V, VOTF = VSHDN/SDI = SGND 1 A IFB FB Leakage Current VEN = VFB = VSVIN = VPVIN, VVSET = > 1.5V, VOTF = VSHDN/SDI = SGND 6 A VPGTH Power Good (PG) Threshold Voltage VOUT x 90% V VPGL Maximum PG Output Low Voltage 0.4 V tDELAY PG Delay Time 1.2 ms IPG PG Leakage Current ISINK = 2mA, VEN = VSVIN VEN = 0V 10 1 A A 1. This rating is for the 88PG839-A1-NAE2C000-T181 / 88PG839-A1-NAE2C000TT181 (Tape and Reel) part number only. Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 19 88PG839 Datasheet 2. The rating is for the 88PG839-A1-NAE2C000 / 88PG839-A1-NAE2C000-T (Tape and Reel) part number only. THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S106081-02 Rev. D Page 20 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Functional Description Overview 3 Functional Description 3.1 Overview The 88PG839 step-down switching regulator uses a proprietary Pulse Width Modulation (PWM) control scheme to regulate the output voltage. If Pulse Frequency Modulation (PFM) pin is set high, the regulator changes automatically from PWM to PFM mode under light load conditions. If PFM pin is set low, the regulator is in forced PWM mode. This control scheme offers a number of advantages, which include fast transient response time, small output ripple, and no external compensation required. When PVIN drops down close or below the target output voltage, the regulator is capable of operating in drop out mode by turning on the upper switch continuously (100% ON mode). Figure 3: Block Diagram R1 VIN C3* SVIN ON OFF EN INTERNAL CIRCUITRY POWER SUPPLY SHDN/SDI OSCILLATOR & SWITCHING FREQUENCY CALIBRATION CURRENT SENSE + OFF PVIN - ON PFM + - PFM PWM PWM CONTROL C1* SW L1 VOUT ERROR AMPLIFIER C2 PGND OTF THERMAL SHUTDOWN VOUT SFB BAND-GAP VOLTAGE REFERENCE SGND UNDER/ OVERVOLTAGE LOCKOUT FAULT RESISTOR NETWORK PG R4 VPG POWER GOOD RESISTOR SENSING CIRCUITRY VSET PSET R2 R3 Note(*): All input capacitors must be placed close to the IC. Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 21 88PG839 Datasheet 3.2 Soft Start Soft start is used in "Hot-Plug" applications to reduce the inrush current during startup of the switching regulator. The 88PG839 controls the rise time of the output voltage. The output ramp rate is between 0.5V/ms to 3V/ms depending on the output voltage setting and the internal clock frequency. However, the output ramp is independent of output capacitance and load current. 3.3 Output Voltage Setting 3.3.1 Serial Programmability of Switching Regulator (SDI) The output voltage of the step-down switching regulator can be programmed by using serial data (shown in Figure 4) into the Serial Data Input (SDI) pin in PWM mode by connecting PFM pin in low state or high state with heavy load. The serial interface is disabled when the PFM pin connects to low state at a light load. Caution: Do not share the SHDN/SDI pin with other serial interface pins. Figure 4: Serial Programmability WRITE MODE Stop Start Chip Select "1" Pulse Register Address "1" "0" "0" pulse Pulse pulse "1" Pulse The period of a pulse is 1 s 20ns VHIGH > VIH VLow < VIL DATA FIELD "0" "1" "0" "0" pulse pulse Pulse pulse "1" Pulse D7 D6 D5 D4 D3 D2 D1 D0 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 "1" pulse The write operation: VHIGH VLOW 1) Each write sequence needs 18 pulses to complete. 2) During a non-write operation, the input needs to be at VLOW (<VIL). 3) In between two successive write operations, the PWM input needs to be at VLOW (<VIL) for a minimum of 10s. For "1" pulse, the high is 0.8s 15ns and the low period is 0.2s 15ns "0" pulse 1st Write sequence VLOW Low for at least 10 s 2nd Write sequence VHIGH For "0" pulse, the high is 0.2s 15ns and the low period is 0.8s 15ns Doc. No. MV-S106081-02 Rev. D Page 22 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Functional Description Output Voltage Setting The first 4 bits (MSB-bits) of the data field are used to select the output voltage where the second 4 bits (LSB-bits) of the data field are used to trim the output voltage (percent of output voltage). The default value for the data field is as follows: Table 7: Default Value of Data Field D a ta F i e l d Description Voltage Set Percent Set Bits 7 6 5 4 3 2 1 0 Default Value 0 0 0 0 0 0 0 0 On power up, the output voltage is set according to VPSET and VVSET. The output voltage can then be field programmed by setting bit 3 and bit 7 to "1". The output voltage and percent set are selected according to Table 8. For PSET voltage options, OTF pin has to connect to logic high. Table 8: Voltage and Percentage Set D a ta F i e ld V OUT ( V) Bits 7 6 5 4 Value 0 0 0 0 1 0 0 1 0 1 D a ta F i e ld P e r c e nt S e t 3 2 1 0 Default power up value 0 0 0 0 Default power up value 0 0.8 1 0 0 0 -10% 0 1 1.0 1 0 0 1 -7.5% 0 1 0 1.2 1 0 1 0 -5.0% 1 0 1 1 1.5 1 0 1 1 -2.5% 1 1 0 0 1.8 1 1 0 0 +2.5% 1 1 0 1 2.5 1 1 0 1 +5.0% 1 1 1 0 3.0 1 1 1 0 +7.5% 1 1 1 1 3.3 1 1 1 1 +10% All combinations of the VSET (Table 10) can be used with all combinations of the PSET (Table 10) to provide maximum flexibility in output voltage selection (Table 10). Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 23 88PG839 Datasheet 3.3.2 Logic Programmability The output voltage of the step-down switching regulator can be programmed for the standard output voltages by connecting the VSET and PSET pins to "0" (SGND) and/or "1" (SVIN). This is useful for standard output voltages, and eliminates the use of an external resistor to set the output voltage. The OTF pin provides an additional feature to reduce the output voltage by -20%. Table 9: VSET and PSET Logic Programming VVSET V PS E T V O U T (V ) OTF = 0 (SGND) OTF = 1 (SVIN) SGND SGND 1.0 0.8 SGND SVIN 1.5 1.2 SVIN SGND 1.8 1.44 SVIN SVIN 2.5 2.0 11k RVSET 470k SGND VOUT1 VOUT (1-20%) SGND or SVIN 11k RPSET 470k High Impedance 1. See Table 10. 3.3.3 Programmability--AnyVoltage(R) Technology The output voltage is programmable using VSET and PSET resistors between 11k and 470k (Table 10). The VSET and PSET resistors are read once during startup after the output voltage is powered on. To configure the output to a different voltage, power has to recycle or the device has to turn OFF and back ON using the EN or SHDN/SDI pin. Using a VSET resistor value greater than 619k or less than 7.68k disables the step-down switching regulator and sets the SW pin to high impedance. When the PSET pin is not used, it must be connected to ground. The VSET and PSET pins are sensitive to excessive leakage currents and stray capacitance. The output voltage can be programmed to the lower output voltage if there is contamination, especially for a RVSET and RPSET of 470k or higher values. The parasitic resistance on these nodes must be greater than 3M, and the stray capacitance must be less than 25pF. After the output voltage is on, it can be changed on-the-fly (OTF) from 0% to a percentage between -20% and +10% when the OTF pin connection is high (Table 10). The percentage value is determined by the PSET resistor. Doc. No. MV-S106081-02 Rev. D Page 24 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Functional Description Enable and Shutdown Table 10: VSET and PSET Programming Table for 5% Resistors Perc en t S et (%) Vo l ta g e S e t ( V ) O T F =0 (S GN D) O T F = 1 ( S V I N) 0 11 k 1 8k 3 0k 51 k 1 00 k 16 0k 2 70 k 47 0k 0% -2 0% -10 % -7. 50% - 5. 0 0% -2 .50 % 2 . 5 0% 5 . 00 % 7. 50% 10 % 11k 0.8 0.64 0.72 0.74 0.76 0.78 0.82 0.84 0.86 0.88 18k 1.0 0.8 0.9 0.925 0.95 0.975 1.025 1.05 1.075 1.1 30k 1.2 0.96 1.08 1.11 1.14 1.17 1.23 1.26 1.29 1.32 51k 1.5 1.2 1.35 1.388 1.425 1.463 1.538 1.575 1.613 1.65 1 00 k 1.8 1.44 1.62 1.665 1.71 1.755 1.845 1.89 1.935 1.98 1 60 k 2.5 2.0 2.25 2.313 2.375 2.438 2.563 2.625 2.688 2.75 2 70 k 3.0 2.4 2.7 2.775 2.85 2.925 3.075 3.15 3.225 3.3 4 70 k 3.3 2.64 2.97 3.053 3.135 3.218 3.383 3.465 3.548 3.63 3.4 Enable and Shutdown To simplify the interface to different control logic, both Enable (EN) and Shutdown (SHDN/SDI) pins are available for controlling the 88PG839. If a positive logic is selected, the EN pin is used and the SHDN/SDI pin is pulled below VIL. Voltage above VIH at the EN pin enables the regulator, while voltage below VIL disables the regulator. If a negative logic is desired, the SHDN/SDI pin is used and the EN pin is pulled above VIH. Voltage above VIH at the SHDN/SDI pin shuts down the regulator, while voltage below VIL powers on the regulator. 3.5 PFM and PWM Mode Selection When PFM pin is connected to low state, the regulator is in the forced PWM mode, where the regulator runs at a constant frequency. The quiescent current of the forced PWM mode increases to IQ_PWM. When PFM pin is connected to a high state, the regulator runs in PFM mode, where the switching frequency decreases when the load current reduces, thus improving the light load efficiency. 3.6 Under Voltage Lockout (UVLO) This feature ensures that both internal MOSFETs have adequate voltage levels to operate properly. When the input voltage is below UVLO low threshold both MOSFETs are off until the input rises above the UVLO high threshold. The switching node (SW) is in high Z state when the input voltage is less than UVLO high threshold. Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 25 88PG839 Datasheet 3.7 Over Voltage Protection (OVP) An over voltage comparator guards against line transient overshoots, as well as other serious conditions that may damage the IC. When the input voltage is above OVP high threshold the output turns off and the switching node (SW) is high Z. The device will remain at this state until the input voltage comes back below OVP low threshold. Figure 5: UVLO and OVP Waveforms VOVP_HTH VOVP-LTH VUVLO-HTH VUVLO-LTH VIN Output Enable Output Disable 3.8 Thermal Shutdown When the junction temperature exceeds OTS high threshold, the thermal shutdown circuitry disables the 88PG839. The device is enabled when the junction temperature is decreased to OTS low threshold. Doc. No. MV-S106081-02 Rev. D Page 26 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Functional Description Power Good (PG) 3.9 Power Good (PG) The PG is an active-high, open-drain output. The output is held low when the output voltage of the step-down regulator is below the threshold. When the output voltage is above the threshold, the power good pin goes high after 1.2ms delay time (tDELAY). The threshold voltage is 0.9% x VOUT (typical). In shutdown, PG will be actively on. Figure 6: Power Good Operating Waveform VPG_TH < t DEGLITCH 0V VPG RPG_PULLUP x IPG V PGL tDELAY Copyright (c) 2010 Marvell July 8, 2010, 2.00 tDEGLITCH Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 27 88PG839 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S106081-02 Rev. D Page 28 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Functional Characteristics Startup Waveforms 4 Functional Characteristics 4.1 Startup Waveforms . Figure 7: Startup Using Enable Pin Figure 8: Turn Off Using Enable Pin 5V/DIV VEN VEN 5V/DIV 1V/DIV VBUCK 1V/DIV VBUCK 1ms/DIV VIN = 5V 1ms/DIV ILOAD(BUCK) = 50 VIN = 5V VOUT(BUCK) = 1.5V ILOAD(BUCK) = 50 VOUT(BUCK) = 1.5V . Figure 9: Startup Using Shutdown Pin Figure 10: Turn Off Using Shutdown Pin 5V/DIV VSHDN 5V/DIV VSHDN 1V/DIV VBUCK VBUCK 1V/DIV 1ms/DIV VIN = 5V VOUT(BUCK) = 1.5V 1ms/DIV ILOAD(BUCK) = 50 VIN = 5V VOUT(BUCK) = 1.5V Copyright (c) 2010 Marvell July 8, 2010, 2.00 ILOAD(BUCK) = 50 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 29 88PG839 Datasheet . Figure 11: Soft Start Figure 12: Hot Plug VIN 5V/DIV VIN 5V/DIV VBUCK 1V/DIV VBUCK 1V/DIV VPG 5V/DIV VPG 5V/DIV 10ms/DIV VIN = 5V 10ms/DIV ILOAD(BUCK) = 50 VIN = 5V VOUT(BUCK) = 1.5V ILOAD(BUCK) = 50 VOUT(BUCK) = 1.5V . Figure 13: UVLO and OVP Thresholds VIN 2V/DIV VBUCK 2V/DIV 500ms/DIV VIN = 0V to 6V VUVLO(HTH) = 2.61V VOVP(HTH) = 5.67V VOUT(BUCK) = 1.5V VUVLO(LTH) = 2.52V VOVP(LTH) = 5.56V ILOAD(BUCK) = 50 Doc. No. MV-S106081-02 Rev. D Page 30 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Functional Characteristics Short-Circuit Waveform 4.2 Short-Circuit Waveform Figure 14: Step-Down Short Circuit VSW 2V/DIV IIND 5A/DIV 2ms/DIV VIN = 5V VOUT(BUCK) = GND Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 31 88PG839 Datasheet 4.3 Switching Waveforms NOTE: For repeatability of measuring output ripple (VOUT(P-P)) for the BUCK regulator, the standard test procedure limits the scope bandwidth to 20MHz and uses a coax cable with very short leads terminated into 50. The coax leads must be routed away from the switching node as much as possible. Figure 15: DCM Mode VSW 5V/DIV IIND 1A/DIV VBUCK 10mV/DIV 1s/DIV VIN = 5V ILOAD(BUCK) = 20mA + 50 VOUT(BUCK) = 1.5V IIND(PK) = 518mA VOUT(P-P) = 8.2mV Frequency = 288kHz . Figure 16: PWM Mode VSW 5V/DIV IIND 1A/DIV 10mV/DIV VBUCK 100mV/DIV VIN 500ns/DIV CIN = 10F VIN(P-P) = 72.9mV VIN = 5V ILOAD(BUCK) = 2A + 50 IIND(PK) = 2.45A VOUT(BUCK) = 1.5V VOUT(P-P) = 12.0mV Frequency = 2.13MHz Doc. No. MV-S106081-02 Rev. D Page 32 IIND(P-P) = 690.6mA Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Functional Characteristics Switching Waveforms . Figure 17: PWM Output Ripple Voltage 10mV/DIV VBUCK 100ms/DIV VIN = 5V ILOAD(BUCK) = 1A + 50 VOUT(BUCK) = 1.5V VOUT(P-P) = 7.6mV Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 33 88PG839 Datasheet 4.4 Load Transient Waveforms . Figure 18: Slow Load Rise Time Figure 19: Slow Load Fall Time VSW 5V/DIV VBUCK 100mV/DIV VSW 5V/DIV 100mV/DIV VBUCK ILOAD IIND ILOAD IIND 1A/DIV 1A/DIV 5s/DIV 5s/DIV VIN = 5V COUT = 10F VIN = 5V COUT = 10F VOUT(BUCK) = 1.5V tRISE = 0.2A/s VOUT(BUCK) = 1.5V tFALL = 0.2A/s ILOAD(BUCK) = 500mA to 2A ILOAD(BUCK) = 2A to 500mA . Figure 20: Fast Load Rise Time Figure 21: Fast Load Fall Time VSW 5V/DIV VBUCK 100mV/DIV 5V/DIV VSW VBUCK 100mV/DIV ILOAD IIND ILOAD 1A/DIV IIND 1A/DIV 2s/DIV 2s/DIV VIN = 5V COUT = 10F VIN = 5V COUT = 10F VOUT(BUCK) = 1.5V tRISE = 10A/s VOUT(BUCK) = 1.5V tFALL = 48A/s ILOAD(BUCK) = 500mA to 2A ILOAD(BUCK) = 2A to 500mA Doc. No. MV-S106081-02 Rev. D Page 34 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Functional Characteristics Load Transient Waveforms . Figure 22: Load Transient Response VBUCK 100mV/DIV 1A/DIV ILOAD 20s/DIV VIN = 5V COUT = 10F VOUT(BUCK) = 1.5V tRISE = 10A/s, tFALL = 48A/s IOUT(BUCK) = 500mA to 2A Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 35 88PG839 Datasheet THIS PAGE INTENTIONALLY LEFT BLANK Doc. No. MV-S106081-02 Rev. D Page 36 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Typical Characteristics Efficiency 5 Typical Characteristics 5.1 Efficiency Figure 23: Efficiency vs. Output Current (PFM = High) Efficiency vs. Output Current Vin = 3.3V 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 0 0.5 1 1.5 Efficiency (%) Efficiency (%) Efficiency vs. Output Current Vin = 5.0V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 2 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 0 Output Current (A) 0.5 1 1.5 2 Output Current (A) Efficiency vs. Output Current Vin = 5.0V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 1E-06 1E-05 0.0001 0.001 0.01 0.1 1 Efficiency vs. Output Current Vin = 3.3V 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 10 Effic ienc y (% ) Efficiency (% ) Figure 24: Efficiency vs. Output Current in Log Scale (PFM = High) 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 1E-06 1E-05 0.0001 0.001 0.01 Output Current (A) 1.8V 1.5V 1.2V 1.0V 0.8V 0.1 1 10 Output Current (A) Copyright (c) 2010 Marvell July 8, 2010, 2.00 2.5V Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 37 88PG839 Datasheet Figure 25: Efficiency vs. Output Current (PFM = Low) Efficiency vs. Output Current Vin = 3.3V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V Efficiency (%) Efficiency (%) Efficiency vs. Output Current Vin = 5.0V 1.0V 0.8V 0 0.5 1 1.5 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 0 2 0.5 1 1.5 2 Output Current (A) Output Current (A) Figure 26: Efficiency vs. Output Current in Log Scale (PFM = Low) 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 1E-06 1E-05 0.0001 0.001 Efficiency vs. Output Current Vin = 3.3V 3.3V 3.0V 2.5V 1.8V 1.5V 1.2V 1.0V 0.8V 0.01 0.1 1 10 Effic ienc y (% ) Efficiency (%) Efficiency vs. Output Current Vin = 5.0V 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% 1E-06 1E-05 0.0001 0.001 1.8V 1.5V 1.2V 1.0V 0.8V 0.01 0.1 1 10 Output Current (A) Output Current (A) Doc. No. MV-S106081-02 Rev. D Page 38 2.5V Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Typical Characteristics Load Regulation 5.2 Load Regulation Figure 27: Output Voltage vs. Output Current Output Voltage vs. Output Current Vout = 1.5V 1.53 Output Voltage (V) 3.3V 1.52 5V 1.50 1.49 1.47 0 0.5 1 1.5 2 Output Current (A) 5.3 Dropout Voltage Figure 28: Step-down Regulator Dropout Buck Dropout vs. Load Current 0.7 125C 105C 0.6 85C 65C Buck Dropout (V) 0.5 45C 25C 0.4 0C -20C 0.3 -40C 0.2 0.1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 Load Current(A) Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 39 88PG839 Datasheet 5.4 RDS (ON) Resistance Figure 29: Resistance vs. Input Voltage TOP FET Resistance vs. Input Voltage BOTTOM FET Re sis tance vs. Input Voltage 0.25 0.16 Resistance () Resistance () 0.14 TA = 25C 0.20 0.15 0.10 0.05 TA = 25 C 0.12 0.10 0.08 0.06 0.04 0.02 0.00 0.00 2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 2.7 5.4 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 Input Voltage(V) Input Voltage (V) Figure 30: Resistance vs. Temperature TOP FET Resistance vs. Temperature Bottom FET Resistance vs. Tem perature 0.30 0.20 Resistance () Resistance () 0.25 0.20 0.15 Vin = 2.7V 0.10 Vin = 3.6V 0.05 0 20 40 60 Vin = 2.7V 0.05 0.00 -40 0.00 -20 0.10 80 Temperature (C) Doc. No. MV-S106081-02 Rev. D Page 40 Vin = 3.6V Vin = 5.1V Vin = 5.1V -40 0.15 -20 0 20 40 60 80 Temperature ( C) Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Typical Characteristics IC Case and Inductor Temperature 5.5 IC Case and Inductor Temperature The following data was taken using a 0.88 square inch PCB 1 oz. copper and L = 1H. Actual results depend upon the size of the PCB proximity to other heat emitting components. Figure 31: Input Current vs. Output Current Input Current vs. Output Current Vin = 3.3V, TA = 25C Input Current vs. Output Current Vin = 5V, TA = 25C 2.5 3.3V 3.3V 1.6 3.0V 1.4 2.5V 3.0V 2.5V 2.0 1.8V 1.8V 1.2 Input Current (A) Input Current (A) 1.8 1.5V 1.0 1.2V 0.8 1.0V 0.8V 0.6 0.4 1.5V 1.5 1.2V 1.0V 1.0 0.8V 0.5 0.2 0.0 0 0.5 1 1.5 0.0 2 0 0.5 Output Current (A) 1 1.5 2 Output Current (A) Figure 32: IC Case Temperature vs. Output Current IC Case Temprature vs. Output Current Vin = 5V, TA = 25C IC Case Temprature vs. Output Current Vin = 3.3V, TA = 25C 90 80 3.3V 110 3.0V 100 3.0V 90 2.5V 2.5V 1.8V 1.5V 60 1.2V 1.0V 50 0.8V 1.8V 80 Temprature (C) 70 Temprature (C) 3.3V 1.5V 70 40 1.2V 60 1.0V 50 0.8V 40 30 30 20 20 0 0 0.5 1 1.5 0.5 2 1 1.5 2 Output Current (A) Output Current (A) Figure 33: Inductor Temperature vs. Output Current Inductor Temprature vs. Output Current Vin = 5V, TA = 25C Inductor Temprature vs. Output Current Vin = 3.3V, TA = 25C 70 3.3V 65 3.3V 3.0V 3.0V 70 2.5V 60 2.5V 1.5V 50 1.2V 45 1.0V 40 0.8V 35 30 Temprature (C) 1.8V 55 Temprature (C) 80 1.8V 60 1.5V 1.2V 50 1.0V 0.8V 40 30 25 20 20 0 0.5 1 1.5 2 0 Copyright (c) 2010 Marvell July 8, 2010, 2.00 0.5 1 1.5 2 Output Current (A) Output Current (A) Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 41 88PG839 Datasheet 5.6 Input Voltage . Figure 34: Supply Current vs. Input Voltage Figure 35: Shutdown Supply Current vs. Input Voltage Supply Current vs. Input Voltage PFM Mode Shutdown Supply Current vs. Input Voltage 40 1.0 0.8 Current (A) Current (A) 35 30 25 0.6 0.4 0.2 20 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.0 Input Voltage (V) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) ILOAD(BUCK) = No Load; VOUT(BUCK) = 1.5V ILOAD(BUCK) = No Load; VEN= 0V; VSHDN = VIN . Figure 36: Shutdown Enable Threshold vs. Input Voltage Shutdown Threshold vs. Input Voltage 2.0 UTH-Disable Threshold (V) LTH-Enable 1.5 1.0 0.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) ILOAD(BUCK) = 10mA; VOUT(BUCK) = 1.5V Doc. No. MV-S106081-02 Rev. D Page 42 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Typical Characteristics Input Voltage . . Figure 37: Output Voltage vs. Input Voltage Figure 38: Efficiency vs. Input Voltage Efficiency vs. Input Voltage 100% 1.545 95% Efficiency Voltage (V) Output Voltage vs. Input Voltage 1.560 1.530 1.515 90% 85% 1.500 80% 1.485 2.5 3.0 3.5 4.0 4.5 5.0 2.5 5.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) Input Voltage (V) ILOAD(BUCK) = 500mA ILOAD(BUCK) = 1A; VOUT(BUCK) = 1.5V Figure 39: Load Regulation vs. Input Voltage Figure 40: Average Output Current Limit vs. Input Voltage Load Regulation vs. Input Voltage 1.40% Average Output Current Limit vs. Input Voltage 1.20% 3 1.00% Current (A) Load Regulation 4 0.80% 2 1 0.60% 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) ILOAD(BUCK) = 500mA-2A; VOUT (BUCK) = 1.5V VOUT (BUCK) = 1.5V Figure 41: Frequency vs. Input Voltage Frequency vs. Input Voltage Frequency (MHz) 4 3 2 1 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Input Voltage (V) ILOAD(BUCK) = 1A; VOUT(BUCK) = 1.5V Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 43 88PG839 Datasheet 5.7 Temperature Figure 42: Supply Current vs. Temperature Figure 43: UVLO Threshold vs. Temperature Supply Current vs. Temperature PFM Mode UVLO Threshold vs. Temperature 2.8 40 UTH 2.7 Threshold (V) Current (A) 35 30 2.6 2.5 25 20 -40 LTH -20 0 20 40 60 2.4 -40 80 -20 0 20 40 60 80 Temperature (C) Temperature (C) VIN = 3.6V; ILOAD(BUCK) = No Load ILOAD(BUCK) = 10mA Figure 44: OVP Threshold vs. Temperature Figure 45: Shutdown Enable Threshold vs. Temperature OVP Threshold vs. Temperature 5.8 Shutdown Enable Threshold vs. Temperature 2.0 OVP HIGH LTH - Enable 5.6 Voltage (V) Threshold (V) UTH - Disable OVP LOW 5.7 5.5 5.4 -40 -20 0 20 40 Temperature (C) 60 80 1.5 1.0 0.5 -40 -20 0 20 40 60 80 Temperature (C) ILOAD(BUCK) = 10mA VIN = 3.6V; ILOAD(BUCK) = 10mA;VOUT (BUCK) = 1.5V; VEN = VIN Doc. No. MV-S106081-02 Rev. D Page 44 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Typical Characteristics Temperature Figure 46: Shutdown Supply Current vs. Temperature Shutdown Supply Current vs.Temperature 4 Current (A) 3 2 1 0 -40 -20 0 20 40 60 80 Temperature (C) VIN = 3.6V; ILOAD(BUCK) = No Load; VEN= 0V; VSHDN = VIN . . Figure 47: Output Voltage vs. Temperature Figure 48: Efficiency vs. Temperature Efficiency vs. Temperature 100% 1.515 95% Efficiency Voltage (V) Output Voltage vs. Temperature 1.530 1.500 1.485 1.470 -40 90% 85% -20 0 20 40 60 80% 80 -40 Temperature (C) -20 0 20 40 60 80 Temperature (C) VIN = 3.6V; ILOAD(BUCK) = 500mA VIN = 3.6V; VOUT(BUCK) = 1.5V; ILOAD(BUCK) = 1A Figure 49: Load Regulation vs. Temperature Figure 50: Line Regulation vs. Temperature Line Regulation vs. Temperature -0.4% 1.2% -0.6% Line Regulation Load Regulation Load Regulation vs. Temperature 1.6% 0.8% 0.4% -0.8% -1.0% 0.0% -40 -20 0 20 40 60 80 -1.2% -40 -20 Temperature (C) 0 20 40 VIN = 5V; ILOAD(BUCK) = 500mA-2A; VIN = 3V-5V; ILOAD(BUCK) = 1A; VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V Copyright (c) 2010 Marvell July 8, 2010, 2.00 60 80 Temperature (C) Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 45 88PG839 Datasheet . Figure 51: Average Output Current Limit vs. Temperature Figure 52: Frequency vs. Temperature Frequency vs. Tem perature 4 Average Output Current Limit vs. Temperature Frequency (MHz) 4 Current (A) 3 2 3 2 1 1 0 -40 0 -40 -20 0 20 40 60 -20 80 0 20 40 60 80 Temperature (C) Temperature (C) VIN = 3.6V; VOUT(BUCK) = 1.5V VIN = 3.6V; VOUT(BUCK) = 1.5V; ILOAD(BUCK) = 1A Doc. No. MV-S106081-02 Rev. D Page 46 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Applications Information Inductor and Output capacitance recommendations 6 Applications Information 6.1 Inductor and Output capacitance recommendations When operating in PFM mode (PFM pin = SVIN), it is recommended to use inductor values operating at the specified output voltage range in Table 11. The recommended output capacitance is 22F. Additional output capacitance can be used but the LC product do not exceed 5 x (1.3H) x (28.6F). Table 11: Capacitance Recommendations V OUT R a n g e L Va l ue s 0.64V =< Vout =< 1.32V L = 1.0H +/-30% 1.20V =< Vout =< 1.96V L = 1.8H +/-30% 2.00V =< Vout =< 3.33V L = 2.2H +/-30% When operating in PWM mode (PFM pin = SGND), it is recommended to use inductor values L > 1.0H -30% for output voltage range and LC product do not exceed 5 x (1.3H) x (28.6F). 6.2 PC Board Layout Conciderations and Guidelines Caution: To avoid noise and abnormal operating behavior, follow these layout recommendations The PC board layout is very critical in any switching converter. An improper layout can contribute to system instability, excessive Electromagnetic Interference (EMI), and high switching loss. Follow these basic guidelines for good PC layout: 1. 2. 3. 4. 5. Do not lay out the inductor first. The input capacitor placement is the most critical for proper operation. The AC current circulating through the input capacitor and loop 1 (LP1) are square wave with rise and fall times of 8ns and slew rates as high as 300A/s (see Figure 53). At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per inch of PCB trace, VIND = L x di/dt. Therefore, the Ceramic input capacitor must be place as close as possible to the PVIN and PGND pins with as short and wide trace as possible. Also, the PVIN and PGND traces must be placed on the top layer. This will isolate the fast AC currents from interfering with the analog ground plane. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as shown in Figure 53, is recommended for best results. This is a 2-layer board with 1 ground plane and 1 routing layer. Copy the routing layer in Figure 54 on page 50 as much as possible and place it on the top layer. The ground plane in Figure 55 on page 51 can be placed on any other layer. Use the recommend BOM in Section 6.3, Bill of Materials, on page 52. Contact the factory if substitutions are made. Review the recommended solder pad layout and notes in Figure 57 on page 54. Make sure that you place a dot on the top silk screen to indicate the location of pin 1, see Figure 54. Ensure Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 47 88PG839 Datasheet that the dot is outside the package outline. This way you can visually inspect the package orientation after assembly. 6. Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of capacitor can be placed in parallel with the input capacitor as long as the Ceramic input capacitor is placed next to the IC. 7. Use either X7R or X5R type ceramic capacitors. 8. Any type of capacitor can be placed in parallel with the output capacitor. 9. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide the lowest noise and smallest foot print solution. 10. Use planes for the ground, input and outputs power to maintain good voltage filtering and to keep power losses low. 11. If there is not enough space for a power plane for the input supply, then the input supply trace must be at least 3/8 inch wide. 12. If there is not enough space for a power plane for the output supplies, then place the output as close to the load as possible with a trace of at least 3/8 inch wide. Doc. No. MV-S106081-02 Rev. D Page 48 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Applications Information PC Board Layout Conciderations and Guidelines 13. The device has two internal grounds, analog (SGND) and power (PGND). The analog ground ties to all the noise sensitive signals (VSET, and SVIN) while the power ground ties to the higher current power paths. Noise on an analog ground can cause problems with the IC's internal control and bias signals. For this reason, separate analog and power ground traces are recommended. The signal ground is connected to the power ground at one point, which is the (-) terminal of the output capacitor. 14. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle. 15. Try not to route analog or digital lines in close proximity to the power supply, especially the SW node. If this can't be avoided, shield these lines with a power plane placed between the SW node and the signal lines. 16. The type of solder paste recommended for QFN packages is "No clean", due to the difficulty of cleaning flux residues from beneath the QFN package. Figure 53: PCB Board Schematic R2 U1 88PG839 R3 OTF 1 PFM 2 EN 3 4 5 L1 1.0uH PSET PFM VSET EN SHDN/SDI SGND SVIN SFB PG SW PGND 6 PVIN PSET 11 VSET 10 SHDN /TDI 9 SVIN 8 PG LP2 R1 10 VIN C3 0.1uF/10V 7 R4 1M 13 SW OTF 12 LP1 C1 VIN C2 VOUT 10uF/6.3V 22uF/6.3V I Cout Hi di/dt trace I Cin LP2 LP1 Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 49 88PG839 Datasheet 6.2.1 PC Board Layout Examples Actual board size = 580 mil x 540 mil Total copper layers = 2 (Top and Bottom) All the components are on the top layer Figure 54: Top Silk Screen, Top Traces, Vias, and Copper (Not to scale) Example placement for input capacitors IC IC PVIN PGND PVIN PGND Cin PVIN Trace PGND Trace Cin PVIN Trace Yes PGND Trace No All input capacitors (Cin) must place close to the IC !!!! Doc. No. MV-S106081-02 Rev. D Page 50 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Applications Information PC Board Layout Conciderations and Guidelines . Figure 55: Bottom Silk Screen, Top Traces, Vias, and Copper (Not to scale) Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 51 88PG839 Datasheet 6.3 Bill of Materials Table 12: BOM It e m Qty Ref M a n u fa c tu r e r P a r t N um be r Manufacture r D e s c r ip t i o n 1 1 U1 88PG839 Marvell Ultra Low Power, 2MHz, 2A Output Current Field Programmable Hysteretic Step-Down Switching Regulator 2 1 C1 GRM219R60J106KE19D Murata CAP CER 10F 6.3V X5R 10% 0805 3 1 C2 GRM21BR60J226ME39L Murata CAP CER 22F 6.3V X5R 20% 0805 4 1 C3 C1005X5R1A104K TDK Corporation CAP CER .10F 10V X5R 10% 0402 5 1 L1 1071AS-1R0N TOKO DE2815C Series, 1.0H, 2.10A, 40m, H=1.5mm, L=3.0mm, W=3.2mm 6 1 R1 ERJ-2RKF10R0X Panasonic ECG RES 10.0 1/16W 1% 0402 SMD 7 1 R2 See Table 10, VSET and PSET Programming Table for 5% Resistors, on page 25, 1/16W 1% 0402 SMD 8 1 R3 See Table 10, VSET and PSET Programming Table for 5% Resistors, on page 25, 1/16W 1% 0402 SMD 9 1 R4 CRCW04021M00FKTD Vishay/Dale RES 1.00M 1/16W 1% 0402 SMD Table 13: BOM for Microsoft Application It e m Qty Ref M a n u fa c tu r e r P a r t N um be r Manufacture r D e s c r ip t i o n 1 1 U1 88PG839 Marvell Ultra Low Power, 2MHz, 2A Output Current Field Programmable Hysteretic Step-Down Switching Regulator 2 1 C1 GRM219R60J106KE19D Murata CAP CER 10F 6.3V X5R 10% 0805 3 3 C2 GRM21BR60J226ME39L Murata CAP CER 22F 6.3V X5R 20% 0805 4 1 C3 C1005X5R1A104K TDK Corporation CAP CER .10F 10V X5R 10% 0402 5 1 L1 VLCF4028T-3R3N1R6-2 TDK Corporation VLCF Series, 3.3H, 2.31A, 48m, H=2.8mm, L=4.0mm, W=4.0mm 6 1 R1 ERJ-2RKF10R0X Panasonic ECG RES 10.0 1/16W 1% 0402 SMD 7 1 R2 See Table 10 on page 25, 1/16W 1% 0402 SMD 8 1 R3 See Table 10 on page 25, 1/16W 1% 0402 SMD 9 1 R4 CRCW04021M00FKTD Vishay/Dale RES 1.00M 1/16W 1% 0402 SMD Doc. No. MV-S106081-02 Rev. D Page 52 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Mechanical Drawings 7 Figure 56: 3mm x 4mm 12-Lead DFN Mechanical Drawing Document Classification: Proprietary Mechanical Drawings Copyright (c) 2010 Marvell July 8, 2010, 2.00 7.1 All dimensions in mm. See Section 8, Part Order Numbering/Package Marking, on page 55 for package marking and pin 1 location. Mechanical Drawings Mechanical Drawings Page 53 Doc. No. MV-S106081-02 Rev. D Notes: 88PG839 Datasheet 7.2 Typical Pad Layout Dimensions 7.2.1 Recommended Solder Pad Layout Figure 57: 3mm x 4mm DFN-12 Land Pattern (mm) Package Outline 0.55 0.23 1 0.50 0.67 0.075 4.00 0.83 3.50 0.56 1.75 1.60 2.20 3.30 3x4 DFN-12 Land Pattern (mm) 0.50 mm 0.23 mm 0.27 mm Pad SM Pad SM 0.051 mm Pad 0.168 mm DFN Lead with Non-Solder Mask Defined Terminal Note * * * * * * Top view The "1" indicates pin 1 Drawing not to scale Oversize solder mask (SM) by 4 mils over pad size (2 mil annular ring) 0.168mm solder mask between pads Tolerance 0.05mm Doc. No. MV-S106081-02 Rev. D Page 54 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 Part Order Numbering/Package Marking Part Order Numbering Scheme 8 Part Order Numbering/Package Marking 8.1 Part Order Numbering Scheme Figure 58 shows the part order numbering scheme. Refer to a Marvell Field Application Engineer (FAE) or sales representative for further information when ordering parts. Figure 58: Sample Part Number 88PG839 -xx-NAE2C000-xxxx Custom code (optional) Part number Custom code Custom code Temperature code C = Commercial I = Industrial Custom code Environmental code 1 = RoHS 6/6 2 = Green Package code 8.2 Part Ordering Options The standard ordering part numbers for the respective solutions are the following: Table 14: Part Order Options1 P a c k a g e Ty p e P a r t O r d er N um be r 12-pin DFN, 3mm x 4mm 88PG839-A1-NAE2C000-T181 12-pin DFN, 3mm x 4mm 88PG839-A1-NAE2C000TT181 (Tape and Reel) 12-pin DFN, 3mm x 4mm 88PG839-A1-NAE2C000 12-pin DFN, 3mm x 4mm 88PG839-A1-NAE2C000-T (Tape and Reel) 1. Please review Table 6, Switching Step-down Regulator, on page 18 PWM Mode output voltage over temperature ratings for part order number differences. Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 55 88PG839 Datasheet 8.3 Package Marking Figure 59 shows a sample package marking and pin 1 location. Figure 59: Package Marking and Pin 1 Location Marvell "M" and partial part number 0xXXP YWW$$ Pin 1 Power code, custom code, assembly house code 0x = power code (either "00" or "01")* XX = custom code P = assembly house code Date code and lot traceability code Y = last digit of year WW = work week $$ = lot traceability code The above example is not drawn to scale. Location of markings are approximate. *Note: The power code (either "00" or "01") is determined by the part order number used. Power code "00" = Part Order Number 88PG839-A1-NAE2000-T181 Power code "01" = Part Order Number 88PG839-A1-NAE2000 Doc. No. MV-S106081-02 Rev. D Page 56 Copyright (c) 2010 Marvell Document Classification: Proprietary July 8, 2010, 2.00 A Revision History Table 15: Revision History D o c u m e n t Ty p e D o c u m e n t R e v i s io n Release Rev. D * * Electrical Characteristics: Table 6: Changed PG Leakage Current values. Applications: Bill of Materials edits. Copyright (c) 2010 Marvell July 8, 2010, 2.00 Doc. No. MV-S106081-02 Rev. D Document Classification: Proprietary Page 57 Back Cover Marvell Semiconductor, Inc. 5488 Marvell Lane Santa Clara, CA 95054, USA Tel: 1.408.222.2500 Fax: 1.408.752.9028 www.marvell.com Marvell. Moving Forward Faster