88PG839-A1-NAE2C000-T181 - Marvell Semiconductor, Inc.

Marvell. Moving Forward Faster

Doc. No. MV-S106081-02, Rev. D

July 8, 2010

Document Classification: Proprietary

Microsoft Use Only

Cover

88PG839

Ultra Low Power, 2MHz, 2A Output

Current Field Programmable

Hysteretic Step-Down Switching

Regulator

Datasheet

Document Conventions

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88PG839

Datasheet

Page 2 Document Classification: Proprietary July 8, 2010, 2.00

88PG839

Ultra Low Power, 2MHz, 2A Output Current Field

Programmable Hysteretic Step-Down Switching

Regulator

July 8, 2010, 2.00 Document Classification: Proprietary Page 3

PRODUCT OVERVIEW

The Marvell® 88PG839 is a high performance, hysteretic

step-down switching regulator that utilizes a proprietary,

internally compensated Pulse Width Modulation (PWM)

control to regulate the output voltage. The regulator

offers fast transient response time and requires no

external compensation. The device operates from an

input voltage range of 2.7V to 5.5V and delivers up to 2A

DC output current. The switching frequency is typicall y

2MHz, allowing the use of low profile surface mounted

inductors and low value ceramic capacitors.

The step-down regulator includes programmable ability

to easily set the ou tput voltage with external resistors.

The output voltage range is 0.64V to 3.63V. The output

voltage can be changed On-the-Fly (OTF) from a

nominal value by a percentage through connecting the

OTF pin to a high level, making it id eal for portable

applications. The adjustment percentage is user

programmable from -20% to +10% by a resistor

connected between PSET pin and ground.

The 88PG839 can be externally set to Pulse Frequency

Modulation (PFM) or Pulse Width Modulation (PWM)

mode via the PFM pin. The quiescent current in PFM

mode is less than 32µA. The regulator can achieve 95%

efficiency under loaded conditions.

Features

Input voltage range 2.7V to 5.5V

Output voltage range 0.64V to 3.63V

Hysteretic step-down regulator

32µA (typical) quiescent current

3mm x 4mm DFN-12 package

2MHz switching frequency

Small and low-profile inductor s

Stable with low-ESR ceramic output capacitor

-20% to +10% On-the-Fly output voltage adjustment

Internal compensation

Up to 95% efficiency

2A DC output current

72 output voltage selections using AnyVoltageTM

Technology

Built-in under/over voltage lockout

Thermal shutdown protection

Soft start to minimize the in-rush current

Applications

Portable computing

Personal Digital Assistant (PDA)

Cell phones

Ultra-Mobile PC (UMPC)

Figure 1: Typical Application Circuit

Caution! This is a very high frequency device, and proper PCB layout is required. Refer to

Section 6, Applications Information, on page 47 for further information.

PFM

SHDN /SDI

1MΩ

SVIN VIN

C2*

22uF/6.3V

VSET

10uF/6.3V

0.1uF/10V

10Ω

L1*

1.0uH

OTF

SGND

4SHDN/SDI 10

PG 8

SVIN 9

PGND

SFB

PFM

2OTF

6PVIN 7

VSET 11

PSET 12

U1 88PG839

PSET

VIN

VOUT

PVIN PGND

Yes No

Example placement

for input c apacit or s

All i nput c apac i tors

(Cin) must place

close to the IC!!!!

PVIN PGND

Cin Cin

PVIN

Trace PGND

Trace

PVIN

Trace PGND

Trace

Hi di/dt trace *

See S ec ti on 6 , Applic at i ons

Information for the inductor

and output capac i t anc e

recommendations .

88PG839

Datasheet

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Table of Contents

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Table of Contents

Product Overview.......................................................................................................................................3

Table of Contents .......................................................................................................................................5

List of Figures.............................................................................................................................................7

List of Tables ..............................................................................................................................................9

1 Signal Description.......................................................................................................................11

1.1 Pin Configuration.............................................................................................................................................11

1.2 Pin Description................................................................................................................................................12

2 Electrical Specifications .............................................................................................................15

2.1 Absolute Maximum Ratings ............................................................................................................................15

2.2 Recommended Operating Conditions.............................................................................................................16

2.3 Electrical Characteristics.................................................................................................................................17

2.4 Switching Step-down Regulator........ ... ...................... ....................... ...................... ... .....................................18

3 Functional Description................................................................................................................21

3.1 Overview .........................................................................................................................................................21

3.2 Soft Start.........................................................................................................................................................22

3.3 Output Voltage Setting....................................................................................................................................22

3.3.1 Serial Programmability of Swit ching Regulator (SDI) .................... ...................................................22

3.3.2 Logic Programmability......................................................................................................................24

3.3.3 Programmability—AnyVoltage® Technology....................................................................................24

3.4 Enable and Shutdown.....................................................................................................................................25

3.5 PFM and PWM Mode Selection......................................................................................................................25

3.6 Under Voltage Lockout (UVLO) ........... ... ...................... ....................... ...................... .....................................25

3.7 Over Voltage Protection (OVP).......................................................................................................................26

3.8 Thermal Shutdown..........................................................................................................................................26

3.9 Power Good (PG)............................................................................................................................................27

4 Functional Characteristics .........................................................................................................29

4.1 Startup Waveforms .......... ... ............................................................................................................................29

4.2 Short-Circuit Waveform ..................................................................................................................................31

4.3 Switching Waveforms..................... ....................... .......................................... ................................................32

4.4 Load Transient Waveforms.............................................................................................................................34

5 Typical Characteristics ...............................................................................................................37

5.1 Efficiency.........................................................................................................................................................37

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5.2 Load Regulation..............................................................................................................................................39

5.3 Dropout Voltage......................................... .. ... .................... ... .........................................................................39

5.4 RDS (ON) Resistance.....................................................................................................................................40

5.5 IC Case and Inductor Temperature.................................................................................................................41

5.6 Input Voltage...................................................................................................................................................42

5.7 Temperature ...............................................................................................................................................44

6 Applications Information ........ ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ......................47

6.1 Inductor and Output capacitance recommendations.......................................................................................47

6.2 PC Board Layout Conciderati ons and Guidelines...........................................................................................47

6.2.1 PC Board Layout Examples..............................................................................................................50

6.3 Bill of Materials ........ ...................... .................................................................................................................52

7 Mechanical Drawings..................................................................................................................53

7.1 Mechanical Drawings......................................................................................................................................53

7.2 Typical Pad Layout Dimensions......................................................................................................................54

7.2.1 Recommended Solder Pad Layout...................................................................................................54

8 Part Order Numbering/Package Marking ..................................................................................55

8.1 Part Order Numbering Scheme.......................................................................................................................55

8.2 Part Ordering Options...... .......................................... .......................................... ...........................................55

8.3 Package Marking ............. ... ... .........................................................................................................................56

A Revision History ..........................................................................................................................57

List of Figures

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List of Figures

Product Overview.......................................................................................................................................3

Figure 1: Typical Application Circuit ...................................................................................................................3

1 Signal Description ........................................................................................................................... 11

Figure 2: DFN-12 Pin Configuration (Top View)..............................................................................................11

2 Electrical Specifications ................................................................................................................. 15

3 Functional Description.................................................................................................................... 21

Figure 3: Block Diagram ..................................................................................................................................21

Figure 4: Serial Programmability ......................................................................................................................22

Figure 5: UVLO and OVP Waveforms .............................................................................................................26

Figure 6: Power Good Operating Waveform....................................................................................................27

4 Functional Characteristics.............................................................................................................. 29

Figure 7: Startup Using Enable Pin..................................................................................................................29

Figure 8: Turn Off Using Enable Pin........... ...................... ...................... ... ....................... ............ ...................29

Figure 9: Startup Using Shutdown Pin.............................................................................................................29

Figure 10: Turn Off Using Shutdown Pin............................ ... ...................... ....................... ...............................29

Figure 11: Soft Start ..........................................................................................................................................30

Figure 12: Hot Plug............................................................................................................................................30

Figure 13: UVLO and OVP Thresholds .............................................................................................................30

Figure 14: Step-Down Short Circuit...................................................................................................................31

Figure 15: DCM Mode........................................................................................................................................32

Figure 16: PWM Mode.......................................................................................................................................32

Figure 17: PWM Output Ripple Voltage.............................................................................................................33

Figure 18: Slow Load Rise Time........................................................................................................................34

Figure 19: Slow Load Fall Time.........................................................................................................................34

Figure 20: Fast Load Rise Time.........................................................................................................................34

Figure 21: Fast Load Fall Time..........................................................................................................................34

Figure 22: Load Transient Response .................................................................................................................35

5 Typical Characteristics ................................................................................................................... 37

Figure 23: Efficiency vs. Output Current (PFM = High)......................................................................................37

Figure 24: Efficiency vs. Output Current in Log Scale (PFM = High).................................................................37

Figure 25: Efficiency vs. Output Current (PFM = Low) ......................................................................................38

Figure 26: Efficiency vs. Output Current in Log Scale (PFM = Low)..................................................................38

Figure 27: Output Voltage vs. Output Current ...................................................................................................39

Figure 28: Step-dow n Regulator Dropout ..........................................................................................................39

Figure 29: Resistance vs. Input Voltage ............................................................................................................40

Figure 30: Resistance vs. Temperature.............................................................................................................40

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Figure 31: Input Current vs. Output Current ......................................................................................................41

Figure 32: IC Case Temperature vs. Output Current.........................................................................................41

Figure 33: Inductor Temperature vs. Output Current.........................................................................................41

Figure 34: Supply Current vs. Input Voltage...... ....................... .. ....................... ... ...................... ... ....................42

Figure 35: Shutdown Supply Current vs. Input Voltage.....................................................................................42

Figure 36: Shutdown Enabl e Threshold vs. Input Voltage.................................................................................42

Figure 37: Output Voltage vs. Input Voltage......................................................................................................43

Figure 38: Efficiency vs. Input Voltage...............................................................................................................43

Figure 39: Load Regulation vs. Input Voltage....................................................................................................43

Figure 40: Average Output Current Limit vs. Input Voltage...............................................................................43

Figure 41: Frequency vs. Input Voltage.............................................................................................................43

Figure 42: Supply Current vs. Temperature......................................... ... ...................... ... ..................................44

Figure 43: UVLO Threshold vs. Temperature....................................................................................................44

Figure 44: OVP Threshold vs. Temperature......................................................................................................44

Figure 45: Shutdown Enable Threshold vs. Temperature .................................................................................44

Figure 46: Shutdown Supply Current vs. Temperature......................................................................................45

Figure 47: Output Voltage vs. Temperature.......................................................................................................45

Figure 48: Efficiency vs. Temperature ...............................................................................................................45

Figure 49: Load Regulation vs. Temperature ....................................................................................................45

Figure 50: Line Regulation vs. Temperature......................................................................................................45

Figure 51: Average Output Current Limit vs. Temperature................................................................................46

Figure 52: Frequency vs. Temperature..............................................................................................................46

6 Applications Information ............. ... .... ... ................ ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ......................... 47

Figure 53: PCB Board Schematic......................................................................................................................49

Figure 54: Top Silk Screen, Top Traces, Vias, and Copper (Not to scale)........................................................50

Figure 55: Bottom Silk Screen , Top Traces, Vias, and Copper (Not to scale)...................................................51

7 Mechanical Drawings ...................................................................................................................... 53

Figure 56: 3mm x 4mm 12-Lead DFN Mechanical Drawing..............................................................................53

Figure 57: 3mm x 4mm DFN-12 Land Pattern (mm)..........................................................................................54

8 Part Order Numbering/Package Marking....................................................................................... 55

Figure 58: Sample Part Number........................................................................................................................55

Figure 59: Package Marking and Pin 1 Location ...............................................................................................56

A Revision History ...............................................................................................................................57

List of Tables

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List of Tables

1 Signal Description ............................................................................................................................11

Table 1: Pin Types..........................................................................................................................................12

Table 2: Pin Description..................................................................................................................................12

2 Electrical Specifications ..................................................................................................................15

Table 3: Absolute Maximum Ratings..............................................................................................................15

Table 4: Recommended Operating Conditions...............................................................................................16

Table 5: Electrical Characteristics ..................................................................................................................17

Table 6: Switching Step-down Regulator ........................................................................................................18

3 Functional Description.....................................................................................................................21

Table 7: Default Value of Data Field...............................................................................................................23

Table 8: Voltage and Percentage Set.............................................................................................................23

Table 9: VSET and PSET Logic Programming...............................................................................................24

Table 10: VSET and PSET Programming Table for 5% Resistors...................................................................25

4 Functional Characteristics...............................................................................................................29

5 Typical Characteristics ....................................................................................................................37

6 Applications Information ............. ... .... ... ................ ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ..........................47

Table 11: Capacitance Recommendations.......................................................................................................47

Table 12: BOM ..................................................................................................................................................52

Table 13: BOM for Microsoft Application ..........................................................................................................52

7 Mechanical Drawings .......................................................................................................................53

8 Part Order Numbering/Package Marking........................................................................................55

Table 14: Part Order Options............................................................................................................................55

A Revision History ...............................................................................................................................57

Table 15: Revision History................................................................................................................................57

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Signal Description

Pin Configuration

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1Signal Description

1.1 Pin Configuration

Figure 2: DFN-12 Pin Configuration (Top View)

SVIN

7PVIN

10 SHDN/SDI

11 VSET

12 PSET

OTF

PFM

SGND

SFB

13 PGND

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1.2 Pin Description

Table 1: Pin Types

Pin Type Description

I Input

OOutput

S Supply

NC Not Connected

GND Ground

Table 2: Pin Description

Pin # Pin Name Pin Type Pin Function

1 OTF I On-the-Fly

Logic input for dynamic output voltage change:

• Logic high sets the output voltage that is determined from the VSET and

PSET resistors.

• Logic low sets the output volt age that is determin ed from the VSET resistor

only.

• Do not float this pin.

2 PFM I Pulse Frequency Modulation

• Logic input to set the operation mode. Connect PFM to SVIN to select PFM

mode under light load conditions and connect PFM to SGND to select

forced PWM mode in light load condition. See Section 6, Applications

Information for the inductor and output capacitance recommendati ons

when operating and PFM and PWM mode.

•Do not float this pin.

3 EN I Enable

• Logic high enables the switching step-down regulator.

• In shutdown, the switch node for the step-down regulator is high

impedance. Logic low disables the step-down swit ching regulator. The low

signal has to be at least 20µs to disable the switching regulator. (See

Table 5, Electrical Characteristics, on page 17 for detailed logic high and

logic low specifications)

• SHDN/SDI must be kept low to enable EN function

•Do not float this pin.

4 SGND GND Signal Ground

• This pin must be connected to PGND and make a star connection to

system ground.

5 SFB I Switching Regulator Output Voltage Sense Feedback

• Senses the output voltage of the switching regul ator.

• Connect to the outpu t capacitor of the switching regulator.

Signal Description

Pin Description

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6 SW O Switch Node

• Internally connected to the drains of the high side and low side MOSFETs.

• Connect to the externa l inductor.

7 PVIN S Switching Regulator Power Input

• Power input voltage. Internally connect ed to the source of the high side

MOSFET. Connect a ceramic input capacitor be tween PV IN and PGND

and place it as close as possible to PVIN and PGND pins. See

Section 6, Applications Information for example.

• The voltage between SVIN and PVIN should equal to 50mV or less.

8 PG O Switching Regulator Power Good Output

• It is an open-drain output.

• Connect a 100kΩ pull-up res istor from t his pin t o VOUT or a logic rai l t hat is

equal to or less than SVIN.

• The PG is held low when the output voltage is outside its regulation band

and goes high after the output voltage is within regulation.

• In shutdown, the PG will be actively on.

9 SVIN S Signal Input Voltage

• Input voltage to the internal circuitry. See Table 5, Electrical

Characteristics, on page 17 for input voltage range.

•Connect a decoupling capacitor between SVIN an SGND an d posit ion

it as close as possible to the IC. See Sect ion 6, Applications Information

for example.

• The voltage between SVIN and PVIN should equal to 50mV or less.

10 SHDN/SDI I Shutdown / Serial Data Input

• Logic high disables the switching step-down regulator. In shutdown, the

switch node for the step-down re gulator is high impedance. Logic high

enables the step-down switching regulator.

• EN must be kept high to enable the shutdown function.

• Input data into this pin is used to program the output voltage (see

Section 3.3.1, Serial Programmability of Switching Regulator (SDI),

on page 22).

• To program the output voltage using serial interface, the part must be in

PWM mode (see Section 3.5).

•Do not share this pin with other serial interface pins.

•Do not float this pin.

11 VSET I Switching Regulator Voltage Set

To set the nominal output voltage values:

• Connect VSET to SVIN or GND in conjunction with PSET connected to

SVIN or GND to set four nominal output voltages.

• Connect a resistor from VSET to GND to set eigh t nominal output volt ages.

See Tabl e 9, VSET and PSET Logic Programming, on page 24 for resistor

values and Output Vol tage Settings.

• The total cap acitance across t his pin and SGND must be 25pF or less. Use

resistor values with a 5% to lerance or better. OTF pin must be kept low to

maintain nominal output voltag es.

•Do not float this pin.

Table 2: Pin Description (Continued)

Pin # Pin Name Pin Type Pin Function

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12 PSET I Switching Regulator Percent Set

To set the margining percentage set to output voltage:

• Set the nominal outp ut voltage in conjunction with VSET as described

above.

• Connect an external resistor to ground to se t the percent age change of t he

output voltage. See Table 9, VSET and PSET Logic Programming, on

page 24 for resistor values and Output Voltage Settings.

• The total cap acitance across t his pin and SGND must be 25pF or less. Use

resistor values with a 5% tolerance or better.

•Do not float this pin.

13 PGND GND Power Ground

• It must be connected to the negative terminals of the input and output

capacitors.

Table 2: Pin Description (Continued)

Pin # Pin Name Pin Type Pin Function

Electri ca l Specific at io ns

Absolute Maximum Ratings

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2Electrical Specifications

2.1 Absolute Maximum Ratings

Table 3: Absolute Maximum Ratings1

Note: S tresses above those listed in Absolute Maximum Ratings may cause permanent device failure. Functionality at

or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device

reliability.

Parameter Range Units

VPVIN to PGND -0.3 to 6.0 V

VPVIN to VSVIN -0.3 to 0.3 V

PGND to SGND -0.3 to 0.3 V

VSW to PGND2-0.3 to (VPVIN + 0.3) V

VSFB to SGND -0.3 to (VSVIN + 0.3) V

VVSET, VPSET to SGND -0.3 to (VSVIN + 0.3) V

VPFM, VOTF

,VEN

, VSHDN/SDI, VPG

to SGND -0.3 to (VSVIN + 0.3) V

Operating Ambient Temperature Range3 -40 to 85 °C

Maximum Junction Temperature 150 °C

Storage Temperature Range -65 to +150 °C

1. Exceeding the absolute maximum rating may damage the device.

2. Capable of -1.0V for less than 50ns and 7V for less than 200ns.

3. Specifications over the -40°C to 85°C operating temperature ranges are assured by design, characterization, and

correlation with statistical process controls.

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2.2 Recommended Operating Conditions

Table 4: Recommended Operating Conditions1

1. This device is not guaranteed to function outside the specified operating range.

Symbol Parameter Min Typ Max Units

VSVIN Signal Input Voltage 2.7 5.5 V

VPVIN Power Input Voltage 2.7 5.5 V

θJA Package Thermal Resistance2

2. Simulated on a 3”x4.5” 4-Layer JEDEC PCB with 2 thermal vias.

66.2 °C/W

θJC 43.8 °C/W

TJMAX Maximum Operational Junction

Temperature 125 °C

Electri ca l Specific at io ns

Electrical Characteristics

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2.3 Electrical Characteristics

Table 5: Electrical Characteristics

The following applies unless otherwise noted (re fer to schematic shown in Figure 1): VSVIN = VPVIN = VEN = 3.3V,

VPSET = VSHDN/SDI = SGND = PGND, VBUCK = 1.5V, TA = 25C. Bold V a lues indicate 0°C ≤ TA ≤ 85°C. Specifications

over temperature are assured by design, characterization, and correlation with statistical process controls.

Symbol Parameter Conditions Min Typ Max Units

VSVIN Signal Inpu t Voltage VSVIN = VPVIN 2.7 5.5 V

VPVIN Power Input Voltage VSVIN = VPVIN 2.7 5.5 V

IQ_PFM Total Quiescent Current

(PFM Mode) No load

VPFM = VSVIN = VPVIN

32 50 µA

IQ_PWM Total Quiescent Current

(PWM Mode) No load

VPFM = VSGND

69mA

ISHDN Shutdown Supply Current VSHDN/SDI = VSVIN = VPVIN,

VEN = 0V 10 µA

VUVLO Under Voltage Lockout High Threshold, VSVIN increasing 2.600 2.700 V

Low Threshold, VSVIN decreasing 2.400 2.500 V

VOVP Over Voltage Protection High Threshold, VSVIN increasing 5.780 5.975 V

Low Threshold, VSVIN decreasing 5.500 5.670

TOTS Over-Temperature Thermal

Shutdown High Threshold, TJ increasing

(Disable regulator) 150 °C

Low Threshold, TJ decreasing

(Enable regulator) 110 °C

VIH EN, SHDN/SDI, OTF, and

PFM Input Voltage Threshold Logic High 2V

VIL EN, SHDN/SDI, OTF, and

PFM Input Voltage Threshold Logic Low 0.4 V

IEN Enable Inp ut Curr en t VEN = VSVIN = VPVIN 10 µA

VEN = 0V -10 µA

IOTF OTF Input Current VOTF = VSVIN = VPVIN 10 µA

VOTF = 0V -10 µA

IPFM PFM Input Current VPFM = VSVIN = VPVIN 10 µA

VPFM = 0V -10 µA

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2.4 Switching Step-down Regulator

Table 6: Switching Step-down Regulator

The following applies unless otherwise noted (re fer to schematic shown in Figure 1): VSVIN = VPVIN = VEN = 3.3V,

VPSET = VSHDN/SDI = SGND = PGND, VBUCK = 1.5V, TA = 25C. Bold V a lues indicate 0°C ≤ TA ≤ 85°C. Specifications

over temperature are assured by design, characterization, and correlation with statistical process controls.

Symbol Parameter Conditions Min Typ Max Units

VOUT Output Voltage

(PWM Mode) VOTF = VSVIN, RVSET = 1 8k ,

RPSET = 100k, PWM mode,

ILOAD = 0 – 1.2A

1.025 V

Over Temperature1-2 +2.5 %

Over Temperature2-4 +4 %

VOTF = SGND, RVSET = 100k,

PWM mode, ILOAD = 0 – 1.2A 1.8 V

VOTF = SGND,

VVSET = VSVIN,

VPSET = SGND,

PWM mode, ILOAD = 0 – 1.2A

Over Temperature -4 +4 %

VOUT Output Voltage

(PFM Mode) VOTF = VSVIN, RVSET = 1 8k ,

RPSET = 100k, PFM mode,

ILOAD = 10mA

1.025 V

Over Temperature -7 +7 %

VOTF = SGND, RVSET = 100k,

PFM mode, ILOAD = 10mA 1.8 V

VOTF = SGND,

VVSET = VSVIN,

VPSET = SGND,

PFM mode, ILOAD = 10mA

Over Temperature -7 +7 %

PSET Percentage Set VOTF = VSVIN RPSET = 0 -20 %

VOTF = VSVIN RPSET = 11k -10 %

VOTF = VSVIN RPSET = 18k -7.5 %

VOTF = VSVIN RPSET = 30k -5.0 %

VOTF = VSVIN RPSET = 51k -2.5 %

VOTF = VSVIN RPSET = 100k 2.5 %

VOTF = VSVIN RPSET = 160k 5.0 %

VOTF = VSVIN RPSET = 270k 7.5 %

VOTF = VSVIN RPSET = 470k 10 %

Electri ca l Specific at io ns

Switching Step-down Regulator

July 8, 2010, 2.00 Document Classification: Proprietary Page 19

VLNREG Output Voltage

Line Regulation VSVIN = VPVIN = 3.0V to 5.0V,

ILOAD = 1A -0.8 %

VLDREG Output Voltage

Load Regulation VSVIN = VPVIN = 5.0V,

ILOAD = 500mA to 2A 0.9 %

RDSON_HS High Side Switch On

Resistance VSVIN = VPVIN = 5V 84 140 196 mΩ

102 170 238 mΩ

RDSON_LS Low Side Switch On

Resistance VSVIN = VPVIN = 5V 60 100 140 mΩ

69 115 161 mΩ

ILIM Peak Switch

Current Limit 2.2 33.9 A

ILSW_HS High Side Swit ch Leakage

Current VSHDN/SDI = VSVIN = VPVIN,

VSW = VSVIN = VPVIN

10 µA

ILSW_LS Low Side Switch Leakage

Current VSHDN/SDI = VSVIN = VPVIN,

VSW = PGND 10 µA

fsw Switching Frequency PWM mode 1.4 2 2.6 MHz

DMAX Maximum Duty Cycle 100 %

THICCUP Hiccup Mode Time Interval 2 ms

tDEGLITCH Deglitch 25 µs

IFB FB Leakage Current VEN = 0V, VPVIN = VFB =

VSHDN/SDI = VSVIN = VPVIN

110 µA

IFB FB Leakage Current VEN = VFB = VSVIN = VPVIN,

VVSET = < 1.8V, VOTF =

VSHDN/SDI = SGND

1µA

IFB FB Leakage Current VEN = VFB = VSVIN = VPVIN,

VVSET = > 1.5V, VOTF =

VSHDN/SDI = SGND

6µA

VPGTH Power Good (PG) Threshold

Voltage VOUT ×

90% V

VPGL Maximum PG Output Low

Voltage ISINK = 2mA, VEN = VSVIN 0.4 V

tDELAY PG Delay Time 1.2 ms

IPG PG Leakage Current VEN = 0V 1µA

1. This rating is for the 88PG839-A1-NAE2C000-T181 / 88PG839-A1-NAE2C000TT181 (Tape and Reel) part number only.

Table 6: Switching Step-down Regulator (Continued)

The following applies unless otherwise noted (re fer to schematic shown in Figure 1): VSVIN = VPVIN = VEN = 3.3V,

VPSET = VSHDN/SDI = SGND = PGND, VBUCK = 1.5V, TA = 25C. Bold V a lues indicate 0°C ≤ TA ≤ 85°C. Specifications

over temperature are assured by design, characterization, and correlation with statistical process controls.

Symbol Parameter Conditions Min Typ Max Units

88PG839

Datasheet

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THIS PAGE INTENTIONALLY LEFT BLANK

2. The rating is for the 88PG839-A1-NAE2C000 / 88PG839-A1-NAE2C000-T (Tape and Reel) part number only.

Functional Description

Overview

July 8, 2010, 2.00 Document Classification: Proprietary Page 21

3Functional Description

3.1 Overview

The 88PG839 step-down switching regulator uses a proprietary Pulse Width Modulation (PWM)

control scheme to regulate the output voltage. If Pulse Frequency Modulation (PFM) pin is set high,

the regulator changes automatically from PWM to PFM mode under light load conditions. If PFM pin

is set low , the regulator is in forced PWM mode. This control scheme offers a number of advantages,

which include fast transient response time, small output ripple, and no external compensation

required. When PVIN drops down close or below the target output voltage, the regulator is capable

of operating in drop out mode by turning on the upper switch continuously (100% ON mode).

Figure 3: Block Diagram

Note(*): All input capacitors must be placed close to the IC.

RESISTOR

SENSING

CIRCUITRY

PWM CONTROL

SFB

PSETVSET

R3R2

PGND

RESISTOR

NETWORK

SHDN/SDI

OUT

FAULT

BAND-GAP

VOLTAGE

REFERENCE

SGND

THERMAL

SHUTDOWN

UNDER/

OVER-

VOLTAGE

LOCKOUT

INTERNAL

CIRCUITRY

POWER SU PP LY

C1 *

PVIN

SVIN

CURRENT

SENSE

OFF

OTF

OSCILLA T OR &

SWITCHING

FREQUENCY

CALIBRATION

ERROR

AMPLIFIER

PFM

C3*

PWM

OFF

POWER

GOOD

OUT

88PG839

Datasheet

Page 22 Document Classification: Proprietary July 8, 2010, 2.00

3.2 Soft Start

Soft start is used in "Hot-Plug" applications to reduce the inrush current during startup of the

switching regulator. The 88PG839 controls the rise time of the output voltage. The output ramp rate

is between 0.5V/ms to 3V/ms dependin g on the output voltage setting and the internal clock

frequency. However, the output ramp is independent of output capacitance and load current.

3.3 Output Voltage Setting

3.3.1 Serial Programmability of Switching Regulator (SDI)

The output voltage of the step-down switching regu lator can be programmed by using serial data

(shown in Figure 4) into the Serial Data Input (SDI) pin in PWM mode by connecting PFM pin in low

state or high state with heavy load. The serial interface is disabled when the PFM pin connects to

low state at a light load.

Figure 4: Serial Programmability

Caution: Do not share the SHDN/SDI pin with other serial interface pins.

BIT2

"1"

Pulse "0"

pulse "0"

pulse "1"

pulse

"0"

Pulse

"1"

Pulse

"1"

Pulse "1"

Pulse

DATA FIELD

D7 D6 D5 D4 D3 D2 D1 D0

The period of a pulse is 1 μs ±20ns

HIGH

> V

Low

< V

HIGH

LOW

For " 1" pulse, the hi gh is 0.8μs ±15ns and the low

period i s 0.2μs ±15ns

For "0" pulse, the high is 0.2μs ±15ns and the l ow

period i s 0.8μs ±15ns

LOW

HIGH

The write operation:

1) Each write sequence needs 18 pulses to complete.

2) During a non-write operation, the input needs to be at V

LOW

(<V

3) In between two successive write operations, the PWM input needs to be at

LOW

(<V

) for a minimum of 10μs.

Write

sequence 2

Write

sequence

Low for at least 10 μs

WRITE MODE

"1" pulse

"0" pulse

BIT7 BIT6 BIT5 BIT4 BIT3 BIT1 BIT0

Address

Chip

Select

Start Stop

Functional Description

Output Voltage Setting

July 8, 2010, 2.00 Document Classification: Proprietary Page 23

The first 4 bits (MSB-bits) of the data field are used to select th e output voltage where the second 4

bits (LSB-bits) of the data field are used to trim the output voltage (percent of output voltage). The

default value for the data field is as follows:

On power up, the output voltage is set according to VPSET and VVSET. The output voltage can then

be field programmed by setting bit 3 and bit 7 to “1”. The output voltage and percent set are selected

according to Table 8. For PSET voltage options, OTF pin has to connect to logic high.

All combinations of the VSET (Table 10) can be used with all combinations of the PSET (Table 10) to

provide maximum flexibility in output voltage selection (Table 10).

Table 7: Default Value of Data Field

Data Field

Description Voltage Set Percent Set

Bits 76543210

Default Value 00000000

Table 8: Voltage and Percentage Set

Data Field VOUT (V) Data Field Percent Set

Bits 7654 3210

Value 0 0 0 0 Default power up

value 0 0 0 0 Default power up value

1000 0.8 1000 -10%

1 0 0 1 1.0 1 0 0 1 -7.5%

1 0 1 0 1.2 1 0 1 0 -5.0%

1 0 1 1 1.5 1 0 1 1 -2.5%

1 1 0 0 1.8 1 1 0 0 +2.5%

1 1 0 1 2.5 1 1 0 1 +5.0%

1 1 1 0 3.0 1 1 1 0 +7.5%

1 1 1 1 3.3 1 1 1 1 +10%

88PG839

Datasheet

Page 24 Document Classification: Proprietary July 8, 2010, 2.00

3.3.2 Logic Programmability

The output voltage of the step-down switching regulator can be programmed for the standard output

voltages by connecting the VSET and PSET pins to “0” (SGND) and/or “1” (SVIN). This is useful for

standard output voltages, and eliminates the use of an external resistor to set the output voltage.

The OTF pin provides an additional feature to reduce the output voltage by -20%.

3.3.3 Programmability—AnyVoltage® Technology

The output voltage is programmable using VSET and PSET resistors between 11kΩ and 470kΩ

(Table 10). The VSET and PSET resistors are read once during startup after the output voltage is

powered on. To configure the output to a different volt age, power has to recycle or the device has to

turn OFF and back ON using the EN or SHDN/SDI pin.

Using a VSET resistor value greater than 619kΩ or less than 7.68kΩ disables the step-down

switching regulator and sets the SW pin to high impedance. When the PSET pin is not used, it must

be connected to ground. The VSET and PSET pins are sensitive to excessive leakage currents and

stray capacitance. The output voltage can be programmed to the lower output voltage if there is

contamination, especially for a RVSET and RPSET of 470kΩ or higher values. The parasitic resistance

on these nodes must be greater than 3MΩ, and the stray capacitance must be less than 25pF.

After the output voltage is on, it can be changed on-the-fly (OTF) from 0% to a percentage between

-20% and +10% when the OTF pin connection is high (Table 10). The percentage value is

determined by the PSET resistor.

Table 9: VSET and PSET Logic Programming

VVSET VPSET VOUT (V)

OTF = 0 (SGND) OT F = 1 (SVIN)

SGND SGND 1.0 0.8

SGND SVIN 1.5 1.2

SVIN SGND 1.8 1.44

SVIN SVIN 2.5 2.0

11kΩ ≤ RVSET ≤ 470kΩSGND VOUT1VOUT (1-20%)

SGND or SVIN 11kΩ ≤ RPSET ≤ 470kΩHigh Impedance

1. See Table 10.

Functional Description

Enable and Shutdown

July 8, 2010, 2.00 Document Classification: Proprietary Page 25

3.4 Enable and Shutdown

To simplify the interface to different control logic, both Enable (EN) and Shutdown (SHDN/SDI) pins

are available for controlling the 88PG839. If a positive logic is selected, the EN pin is used and the

SHDN/SDI pin is pulled below VIL. Voltage above VIH at the EN pin enables the regulator, while

voltage below VIL disables the regulator . If a negative logic is desired, the SHDN/SDI pin is used and

the EN pin is pulled above VIH. Voltage above VIH at the SHDN/SDI pin shuts down the regulator,

while voltage below VIL powers on the regulator.

3.5 PFM and PWM Mode Selection

When PFM pin is connected to low state, the regulator is in the forced PWM mode, where the

regulator runs at a constant frequency. The quiescent current of the f orced PWM mode increases to

IQ_PWM. When PFM pin is connected to a high state, the regulator runs in PFM mode, wher e the

switching frequency decreases when the load current reduces, thus improving the light load

efficiency.

3.6 Under Voltage Lockout (UVLO)

This feature ensures that both internal MOSFETs have adequate voltage levels to operate properly.

When the input voltage is below UVLO low thresho ld both MOSFETs are off until the input rises

above the UVLO high threshold. The switching node (SW) is in high Z state when the input voltage is

less than UVLO high threshold.

Table 10: VSET and PSET Programming Table for 5% Resistors

Percent Set (%)

OTF=0

(SGND) OTF = 1 (SVIN)

0Ω11k 18k 30k 51k 100k 160k 270k 470k

0% -20% -10% -7.50% -5.00% -2.50% 2.50% 5.00% 7.50% 10%

Vo lt ag e Se t (V )

11k 0.8 0.64 0.72 0.74 0.76 0.78 0.82 0.84 0.86 0.88

18k 1.0 0.8 0.9 0.925 0.95 0.975 1.025 1.05 1.075 1.1

30k 1.2 0.96 1.08 1.11 1.14 1.17 1.23 1.26 1.29 1.32

51k 1.5 1.2 1.35 1.388 1.425 1.463 1.538 1.575 1.613 1.65

100k 1.8 1.44 1.62 1.665 1.71 1.755 1.845 1.89 1.935 1.98

160k 2.5 2.0 2.25 2.313 2.375 2.438 2.563 2.625 2.688 2.75

270k 3.0 2.4 2.7 2.775 2.85 2.925 3.075 3.15 3.225 3.3

470k 3.3 2.64 2.97 3.053 3.135 3.218 3.383 3.465 3.548 3.63

88PG839

Datasheet

Page 26 Document Classification: Proprietary July 8, 2010, 2.00

3.7 Over Voltage Protection (OVP)

An over voltage comparator guards against line transient overshoots, as well as other serious

conditions that may damage the IC. When the input voltage is above OVP high threshold the output

turns off and the switching node (SW) is high Z. The device will remain at this state until the input

voltage comes back below OVP low threshold .

3.8 Thermal Shutdown

When the junction temperature exceeds OTS high threshold, the thermal shutdown circuitry disables

the 88PG839. The device is enable d when the junction temperature is decreased to OTS low

threshold.

Figure 5: UVLO and OVP Waveforms

OVP_HTH

UVLO-HTH

UVLO-LTH

OVP-LTH

Output

Disable

Output

Enable

VIN

Functional Description

Power Good (PG)

July 8, 2010, 2.00 Document Classification: Proprietary Page 27

3.9 Power Good (PG)

The PG is an active-high, open-drain output. The output is held low when the output voltage of the

step-down regulator is below the threshold. When the output voltage is above the threshold, the

power good pin goes high after 1.2ms delay time (tDELAY). The threshold voltage is 0.9% × VOUT

(typical). In shutdown, PG will be actively on.

Figure 6: Power Good Operating Waveform

DELAY

DEGLITCH

< t

DEGLITCH

RPG_PULLUP × IPG

VPGL

PG_TH

88PG839

Datasheet

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Functional Characteristics

S tar tup Waveform s

July 8, 2010, 2.00 Document Classification: Proprietary Page 29

4Functional Characteristics

4.1 Startup Waveforms

VEN

VBUCK

Figure 7: Startup Using Enable

5V/DIV

1V/DIV

VEN

VBUCK

Figure 8: Turn Off Using Enable

5V/DIV

1V/DIV

1ms/DIV 1ms/DIV

VIN = 5V ILOAD(BUCK) = 50ΩVIN = 5V ILOAD(BUCK) = 50Ω

VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V

VSHDN

VBUCK

Figure 9: Startup Using Shutdown

5V/DIV

1V/DIV

VSHDN

VBUCK

Figure 10: Turn Off Using Shutdown

5V/DIV

1V/DIV

1ms/DIV 1ms/DIV

VIN = 5V ILOAD(BUCK) = 50ΩVIN = 5V ILOAD(BUCK) = 50Ω

VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V

88PG839

Datasheet

Page 30 Document Classification: Proprietary July 8, 2010, 2.00

VIN

VBUCK

VPG

Figure 11: Soft Start

5V/DIV

1V/DIV

5V/DIV

VIN

VBUCK

VPG

Figure 12: Hot Plug

5V/DIV

1V/DIV

5V/DIV

10ms/DIV 10ms/DIV

VIN = 5V ILOAD(BUCK) = 50ΩVIN = 5V ILOAD(BUCK) = 50Ω

VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V

VIN

VBUCK

Figure 13: UVLO and OVP Thresholds

2V/DIV

500ms/DIV

VIN = 0V to 6V VUVLO(HTH) = 2.61V VOVP(HTH) = 5.67V

VOUT(BUCK) = 1.5V VUVLO(LTH) = 2.52V VOVP(LTH) = 5.56V

ILOAD(BUCK) = 50Ω

Functional Characteristics

Short-Circuit Waveform

July 8, 2010, 2.00 Document Classification: Proprietary Page 31

4.2 Short-Circuit Waveform

VSW

IIND

Figure 14: Step-Down Short Circuit

2V/DIV

5A/DIV

2ms/DIV

VIN = 5V VOUT(BUCK) = GND

88PG839

Datasheet

Page 32 Document Classification: Proprietary July 8, 2010, 2.00

4.3 Switching Waveforms

NOTE: For repeatabili ty of measuring output ripple (VOUT(P-P)) for the BUCK regulator, the standard test

procedure limit s the scope bandwidth to 20MHz and uses a coax cable with very short leads

terminated into 50Ω. The coax leads must be routed away from the switching node as much as

possible.

VSW

IIND

VBUCK

Figure 15: DCM Mode

5V/DIV

1A/DIV

10mV/DIV

1µs/DIV

VIN = 5V ILOAD(BUCK) = 20mA + 50Ω

VOUT(BUCK) = 1.5V IIND(PK) = 518mA

VOUT(P-P) = 8.2mV Frequency = 288kHz

VSW

IIND

VBUCK

VIN

Figure 16: PWM Mode

5V/DIV

1A/DIV

10mV/DIV

100mV/DIV

500ns/DIV

CIN = 10µF VIN(P-P) = 72.9mV IIND(P-P) = 690.6mA

VIN = 5V ILOAD(BUCK) = 2A + 50ΩIIND(PK) = 2.45A

VOUT(BUCK) = 1.5V VOUT(P-P) = 12.0mV Frequency = 2.13MHz

Functional Characteristics

Switching Waveforms

July 8, 2010, 2.00 Document Classification: Proprietary Page 33

VBUCK

Figure 17: PWM Output Ripple

Voltage

10mV/DIV

100ms/DIV

VIN = 5V ILOAD(BUCK) = 1A + 50Ω

VOUT(BUCK) = 1.5V VOUT(P-P) = 7.6mV

88PG839

Datasheet

Page 34 Document Classification: Proprietary July 8, 2010, 2.00

4.4 Load Transient Waveforms

VSW

VBUCK

ILOAD

IIND

Figure 18: Slow Load Rise Time

5V/DIV

100mV/DIV

1A/DIV

VSW

VBUCK

ILOAD

IIND

Figure 19: Slow Load Fall Time

5V/DIV

100mV/DIV

1A/DIV

5µs/DIV 5µs/DIV

VIN = 5V COUT = 10µF VIN = 5V COUT = 10µF

VOUT(BUCK) = 1.5V tRISE = 0.2A/µs VOUT(BUCK) = 1.5V tFALL = 0.2A/µs

ILOAD(BUCK) = 500mA to 2A ILOAD(BUCK) = 2A to 500mA

VSW

VBUCK

ILOAD

IIND

Figure 20: Fast Load Rise Time

5V/DIV

100mV/DIV

1A/DIV

VSW

VBUCK

ILOAD

IIND

Figure 21: Fast Load Fall Time

5V/DIV

100mV/DIV

1A/DIV

2µs/DIV 2µs/DIV

VIN = 5V COUT = 10µF VIN = 5V COUT = 10µF

VOUT(BUCK) = 1.5V tRISE = 10A/µs VOUT(BUCK) = 1.5V tFALL = 4 8A / µ s

ILOAD(BUCK) = 500mA to 2A ILOAD(BUCK) = 2A to 500mA

Functional Characteristics

Load Transient Waveforms

July 8, 2010, 2.00 Document Classification: Proprietary Page 35

VBUCK

ILOAD

Figure 22: Load Transient Response

100mV/DIV

1A/DIV

20µs/DIV

VIN = 5V COUT = 10µF

VOUT(BUCK) = 1.5V tRISE = 10A/µs, tFALL = 48A/µs

IOUT(BUCK) = 500mA to 2A

88PG839

Datasheet

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THIS PAGE INTENTIONALLY LEFT BLANK

Typi ca l Chara ct eris tics

Efficiency

July 8, 2010, 2.00 Document Classification: Proprietary Page 37

5Typical Characteristics

5.1 Efficiency

Figure 23: Efficiency vs. Output Current (PFM = High)

Figure 24: Efficiency vs. Output Current in Log Scale (PFM = High)

Efficiency vs. Output Current

Vin = 5.0V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

00.511.52

Output Current (A)

Efficiency (%)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Efficiency vs. Out put Curre nt

Vin = 3.3 V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

00.511.52

Output Current (A)

Efficiency (%)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Efficie ncy vs. Outpu t Curr ent

Vin = 5.0V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1E-06 1E-05 0.0001 0.001 0.01 0.1 1 10

Output Current (A)

Efficiency (% )

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Efficiency vs. Output Current

Vin = 3.3V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1E-06 1E-05 0.0001 0.001 0.01 0.1 1 10

O utput Current (A)

Efficienc y ( %)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

88PG839

Datasheet

Page 38 Document Classification: Proprietary July 8, 2010, 2.00

Figure 25: Efficiency vs. Output Current (PFM = Low)

Figure 26: Efficiency vs. Output Current in Log Scale (PFM = Low)

Efficie ncy vs. Out put Cu r r ent

Vin = 5.0V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

00.511.52

Ou tput C urrent (A)

Efficiency (%)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Efficiency vs. Output Current

Vin = 3.3V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

00.511.52

Ou tput Cu rrent (A)

Efficiency (%)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Eff ic ienc y vs. O utput Cur r ent

Vin = 5. 0 V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1E-06 1E-05 0.0001 0.001 0.01 0.1 1 10

Output Current (A)

Efficiency (%)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Efficien cy vs. Output Current

Vin = 3.3V

10%

20%

30%

40%

50%

60%

70%

80%

90%

100%

1E-06 1E-05 0.0001 0.001 0.01 0.1 1 10

Output Current (A)

Effic ienc y ( %)

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Typi ca l Chara ct eris tics

Load Regula tion

July 8, 2010, 2.00 Document Classification: Proprietary Page 39

5.2 Load Regulation

5.3 Dropout Voltage

Figure 27: Output Voltage vs. Output Current

O utpu t Voltage vs. Output Cur r ent

Vout = 1.5V

1.47

1.49

1.50

1.52

1.53

00.511.52

O utpu t Cu rrent (A)

Output Voltage (V)

3.3V

Figure 28: Step-down Regulator Dropout

Buck Dropout vs. Load Current

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Load Current(A)

Buck Dropout (V)

125C

105C

85C

65C

45C

25C

-20C

-40C

88PG839

Datasheet

Page 40 Document Classification: Proprietary July 8, 2010, 2.00

5.4 RDS (ON) Resistance

Figure 29: Resistance vs. Input Voltage

Figure 30: Resistance vs. Temperature

TOP FET

Resist a nce vs. Input Vol t age

0.00

0.05

0.10

0.15

0.20

0.25

2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

Input Volta ge (V)

Resi stan c e (Ω)

TA = 25° C

BOTTOM FET

Resistance vs. Input Voltage

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4

Input Voltage(V)

Resistance (Ω

)

TA = 25ºC

TOP FET

Resist anc e vs. Temper ature

0.00

0.05

0.10

0.15

0.20

0.25

0.30

-40-200 20406080

Temperature (°C)

Resi stan ce (Ω)

Vin = 2.7V

Vin = 3.6V

Vin = 5.1V

Bottom FET

Resistance vs. Temperature

0.00

0.05

0.10

0.15

0.20

-40-200 20406080

Temperature (ºC)

R e si sta nce ( Ω

)

Vin = 2.7V

Vin = 3.6V

Vin = 5.1V

Typi ca l Chara ct eris tics

IC Case and Inductor Temperature

July 8, 2010, 2.00 Document Classification: Proprietary Page 41

5.5 IC Case and Inductor Temperature

The following data was taken using a 0.88 square inch PCB 1 oz. copper and L = 1μH. Actual results

depend upon the size of the PCB proximity to other heat emitting components.

Figure 31: Input Current vs. Output Current

Figure 32: IC Case Temperature vs. Output Current

Figure 33: Inductor Temperature vs. Output Current

Input Current vs. Output Current

Vin = 5V, TA = 25°C

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

00.511.52

Output Current (A)

Input Current (A)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Input Current v s. Output Current

Vin = 3. 3V, TA = 25°C

0.0

0.5

1.0

1.5

2.0

2.5

00.511.52

Ou tput Current (A)

Input Current (A)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

IC Case Temprature vs. Output Current

V in = 5V, TA = 25 °C

00.511.52

O ut put Curr ent (A)

Temprature (°C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

IC Case Temprature v s. Output Current

Vin = 3.3V, T A = 25°C

100

110

0 0.5 1 1.5 2

Out put Curren t (A)

Temprature (°C

)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Inductor Temprature v s. Output Current

Vin = 5V, TA = 25° C

0 0.5 1 1.5 2

Output Current (A)

Temprature (°C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

Inductor Temprat ure vs . O ut put Current

Vi n = 3.3V, TA = 25°C

00.511.52

Output Current (A)

Temprature (°C)

3.3V

3.0V

2.5V

1.8V

1.5V

1.2V

1.0V

0.8V

88PG839

Datasheet

Page 42 Document Classification: Proprietary July 8, 2010, 2.00

5.6 Input Voltage

Figure 34: Supply Current vs. Input Voltage Figure 35: Shutdown Supply Current vs.

Input Voltage

ILOAD(BUCK) = No Load; VOUT(BUCK) = 1.5V ILOAD(BUCK) = No Load; VEN= 0V; VSHDN = VIN

Supply Current vs. Input Volt age

PFM Mode

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Current (μA)

Sh utdown S upp ly Cur r ent vs. Inp ut Voltage

0.0

0.2

0.4

0.6

0.8

1.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Current (μA)

Figure 36: Shutdown Enable Threshold vs.

Input Voltage

Shu t d own Thr eshold vs. Input Volt a ge

0.5

1.0

1.5

2.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Threshold (V)

UTH-Disable

LTH-Enable

ILOAD(BUCK) = 10mA; VOUT(BUCK) = 1.5V

Typi ca l Chara ct eris tics

Input Voltage

July 8, 2010, 2.00 Document Classification: Proprietary Page 43

. .

Figure 37: Output Voltage vs. Input Voltage Figure 38: Efficiency vs. Input Voltage

ILOAD(BUCK) = 500mA ILOAD(BUCK) = 1A; VOUT(BUCK) = 1.5V

Figure 39: Load Regulation vs. Input Voltage Figure 40: Average Output Current Limit vs.

Input Voltage

ILOAD(BUCK) = 500mA-2A; VOUT (BUCK) = 1.5V VOUT (BUCK) = 1.5V

Figure 41: Frequency vs. Input Voltage

ILOAD(BUCK) = 1A; VOUT(BUCK) = 1.5V

O ut put Voltage vs. I nput Voltage

1.485

1.500

1.515

1.530

1.545

1.560

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Voltage ( V)

Efficienc y vs. Input Voltage

80%

85%

90%

95%

100%

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Efficiency

Load Regulation vs. Input Voltage

0.60%

0.80%

1.00%

1.20%

1.40%

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Load Regulation

Av er a ge O u t put Cur r ent Limit vs. Input Voltage

2.5 3.0 3.5 4.0 4.5 5.0 5.5

Input Voltage (V)

Current ( A)

Frequency vs. Input Voltage

2.53.03.54.04.55.05.5

Input Voltage (V)

Frequency (MHz

)

88PG839

Datasheet

Page 44 Document Classification: Proprietary July 8, 2010, 2.00

5.7 Temperature

Figure 42: Supply Current vs. Temperature Figure 43: UVLO Threshold vs. Temperature

VIN = 3.6V; ILOAD(BUCK) = No Load ILOAD(BUCK) = 10mA

Figure 44: OVP Threshold vs. Temperature Figure 45: Shutdown Enable Threshold vs.

Temperature

ILOAD(BUCK) = 10mA VIN = 3.6V; ILOAD(BUCK) = 10mA;VOUT (BUCK) = 1.5V;

VEN = VIN

Supply Current vs. Temperature

PFM Mode

-40-200 20406080

Temperature (°C)

Current (μA)

UVLO T hreshold vs. Temperatur e

2.4

2.5

2.6

2.7

2.8

-40 -20 0 20 40 60 80

Temperature (°C)

Thre shol d (V)

UTH

LTH

O VP Thr eshold vs. Temperature

5.4

5.5

5.6

5.7

5.8

-40 -20 0 20 40 60 80

Temperature (°C)

Threshold (V)

OVP HIGH

OVP LO W

Shu tdown E n able Thr eshold vs. Temperat u r e

0.5

1.0

1.5

2.0

-40-200 20406080

Temperature (°C)

Voltage (V)

UTH - Disable

LTH - Enable

Typi ca l Chara ct eris tics

Temperature

July 8, 2010, 2.00 Document Classification: Proprietary Page 45

. .

Figure 46: Shutdown Supply Current vs. Temperature

VIN = 3.6V; ILOAD(BUCK) = No Load; VEN= 0V; VSHDN = VIN

Shutdo wn S upply Cur r ent vs.Temperatur e

-40-200 20406080

Temperature (°C)

Current (μA)

Figure 47: Output Voltage vs. Temperature Figure 48: Efficiency vs. Temperature

VIN = 3.6V; ILOAD(BUCK) = 500mA VIN = 3.6V; VOUT(BUCK) = 1.5V; ILOAD(BUCK) = 1A

Figure 49: Load Regulation vs. Temperature Figure 50: Line Regulation vs. Temperature

VIN = 5V; ILOAD(BUCK) = 500mA-2A; VIN = 3V-5V; ILOAD(BUCK) = 1A;

VOUT(BUCK) = 1.5V VOUT(BUCK) = 1.5V

O utput Voltage vs. T emperatur e

1.470

1.485

1.500

1.515

1.530

-40-200 20406080

Temperature (°C)

Voltage (V)

Ef ficienc y vs. T emperat ur e

80%

85%

90%

95%

100%

-40-200 20406080

Temperature (°C)

Efficiency

Load Regulation vs. Temperat ur e

0.0%

0.4%

0.8%

1.2%

1.6%

-40-20020406080

Temperature (°C)

Load Regulation

Line Regulation vs. Temperat ur e

-1.2%

-1.0%

-0.8%

-0.6%

-0.4%

-40-20020406080

Temperature (°C)

Line Regulation

88PG839

Datasheet

Page 46 Document Classification: Proprietary July 8, 2010, 2.00

Figure 51: Average Output Current Limit vs.

Temperature Figure 52: Frequency vs. Temperature

VIN = 3.6V; VOUT(BUCK) = 1.5V VIN = 3. 6V; VOUT(BUCK) = 1.5V; ILOAD(BUCK) = 1A

Average Output Cur r ent Limit vs. Temperat ur e

-40-200 20406080

T e mperature (°C)

Current (A)

Frequency vs. Temperature

-40 -20 0 20 40 60 80

Temperature (°C)

Frequency (MHz

)

Applications Information

Inductor and Output capacitance recommendations

July 8, 2010, 2.00 Document Classification: Proprietary Page 47

6Applications Information

6.1 Inductor and Output capacitance recommendations

When operating in PFM mode (PFM pi n = SVIN), i t is recommende d to use inductor values

operating at the specified output voltage range in Table 11. The recommended output capacitance

is 22μF. Additional output capacitance can be used but the LC product do not exceed

5 × (1.3μH) × (28.6μF).

When operating in PWM mode (PFM pin = SGND), it is recommended to use inductor values L >

1.0μH -30% for output voltage range and LC product do not exceed 5 × (1.3μH) × (28.6μF).

6.2 PC Board Layout Conciderations and Guidelines

The PC board layout is very critical in any switching converter. An improper layout can contribute to

system instability, excessive Electromagnetic Interference (EMI), and high switching loss. Follow

these basic guidelines for good PC layout:

1. Do not lay out the inductor first. The input capacitor placem ent is the most critical for

proper operation. The AC current circulating through the input capacitor and loop 1 (LP1) are

square wave with rise and fall times of 8ns and slew rates as high as 300A/μs (see Figure 53).

At these fast slew rates, stray PCB inductance can generate a voltage spike as high as 3V per

inch of PCB trace, VIND = L × di/dt. Therefore, the Ceramic input capacitor must be place

as close as possible to the PVIN and PGND pins with as short and wide trace as

possible. Also, the PVIN and PGND traces must be placed on the top layer . This will isolate the

fast AC currents from interfering with the analog grou nd plane.

2. Keep loop 2 (LP2) as small as possible and connect the (-) terminal of the output capacitor as

close to the (-) terminal of the input capacitor. A back-to-back placing of bypass capacitors, as

shown in Figure 53, is recommended for best results.

3. This is a 2-layer board with 1 ground plane and 1 routing laye r.

4. Copy the routing layer in Figure 54 on page 50 as much as possible and place it on the top

layer. The ground plane in Figure 55 on page 51 can be pla c ed on any other layer. Use the

recommend BOM in Section 6.3, Bill of Materials, on page 52. Contact the factory if

substitutions are made.

5. Review the recommended solder pad layout and notes in Figure 57 on page 54. Make sure that

you place a dot on the top silk screen to indicate the location of pin 1, see Figure 54. Ensure

Table 11: Capacitance Recommenda tions

VOUT Range L Values

0.64V =< Vout =< 1.32V L = 1.0μH +/-30%

1.20V =< Vout =< 1.96V L = 1.8μH +/-30%

2.00V =< Vout =< 3.33V L = 2.2μH +/-30%

Caution: To avoid noise and abnormal operating behavior, follow

these layout recommendations

88PG839

Datasheet

Page 48 Document Classification: Proprietary July 8, 2010, 2.00

that the dot is outside the package outline. This way you can visually inspect the package

orienta ti o n after assembly.

6. Do not replace the Ceramic input capacitor with any other type of capacitor. Any type of

capacitor can be placed in parallel with the input capacitor as long as the Ceramic input

capacitor is placed next to the IC.

7. Use either X7R or X5R type ceramic capacitors.

8. Any type of capacitor can be placed in parallel with the output capacitor.

9. Low-ESR capacitors like the POSCAP from Sanyo can replace the Ceramic output capacitors

as long as the capacitor value is the same or greater. Note that the Ceramic capacitors provide

the lowest noise and smallest foot print solution.

10. Use planes for the ground, input and outputs power to maintain good voltage filtering and to

keep power losses low.

11. If there is not enough space for a power plane for the input supply, then the input supply trace

must be at least 3/8 inch wide.

12. If there is not enough space for a power plane for the output supplies, then place the output as

close to the load as possible with a trace of at least 3/8 inch wide.

Applications Information

PC Board Layout Conciderations and Guid el ines

July 8, 2010, 2.00 Document Classification: Proprietary Page 49

13. The device has two internal grounds, analog (SGND) and power (PGND). The analog ground

ties to all the noise sensitive signals (VSET, and SVIN) while the power ground ties to the higher

current power paths. Noise on an analog ground can cause problems with the IC's internal

control and bias signa ls. For this reason, separate analog and power ground traces are

recommended. The signal ground is connected to the power ground at one point, which is th e

(-) terminal of the output capacitor.

14. Keep the switching node (SW) away from the SFB pin and all sensitive signal nodes, minimizing

capacitive coupling effects. If the SFB trace must cross the SW node, cross it at a right angle.

15. Try not to route analog or digital lines in close proximity to the power supply, especially the SW

node. If this can’t be avoided, shield these lines with a power plane placed between the SW

node and the signal lines.

16. The type of solder paste recommended for QFN packages is “No clean”, due to the difficulty of

cleaning flux residues from beneath the QFN package.

Figure 53: PCB Board Schematic

PFM

SHDN /TDI

1MΩ

SVIN VIN

22uF/6.3V

VSET

10uF/6.3V

0.1uF/10V

10Ω

1.0uH

OTF

SGND

4SHDN/SDI 10

PG 8

SVIN 9

PGND

SFB

PFM

2OTF

6PVIN 7

VSET 11

PSET 12

U1 88PG839

PSET

VIN

VOUT

I Cin

LP1

I Cout

LP2

LP1

LP2

Hi di/dt trace

88PG839

Datasheet

Page 50 Document Classification: Proprietary July 8, 2010, 2.00

6.2.1 PC Board Layout Examples

Actual board size = 580 mil x 540 mil

Total copper layers = 2 (Top and Bottom)

All the components are on the top layer

Figure 54: Top Silk Screen, Top Traces, Vias, and Copper (Not to scale)

PVIN PGND

Yes No

Example placement

for input capacitors

All i nput capacitors

( Cin) m ust pl ac e

cl ose to t he I C! ! ! !

PVIN PGND

Cin Cin

PVIN

Trace PG ND

Trace

PVIN

Trace PGND

Trace

Applications Information

PC Board Layout Conciderations and Guid el ines

July 8, 2010, 2.00 Document Classification: Proprietary Page 51

Figure 55: Bottom Silk Screen, Top Traces, Vias, and Copper (Not to scale)

88PG839

Datasheet

Page 52 Document Classification: Proprietary July 8, 2010, 2.00

6.3 Bill of Materials

Table 12: BOM

Item Qty Ref Manufacturer Part

Number Manufacturer Description

1 1 U1 88PG839 Marvell Ultra Low Power, 2MHz, 2A Output Current

Field Progr ammable Hysteretic Step-Down

Switching Regulator

2 1 C1 GRM219R60J106KE19D Murata CAP CER 10μF 6.3V X5R 10% 0805

3 1 C2 GRM21BR60J226ME39L Murata CAP CER 22μF 6.3V X5R 20% 0805

4 1 C3 C1005X5R1A104K TDK Corporation CAP CER .10μF 10V X5R 10% 0402

5 1 L1 1071AS-1R0N TOKO DE28 15C Series, 1.0μH, 2.10A, 40mΩ,

H=1.5mm, L=3.0mm, W=3.2mm

6 1 R1 ERJ-2RKF10R0X Panasonic ECG RES 10.0Ω 1/16W 1% 0402 SMD

71R2 See Table 10, VSET and PSET Programming

Table for 5% Resistors, on p age 25, 1/16W 1%

0402 SMD

81R3 See Table 10, VSET and PSET Programming

Table for 5% Resistors, on p age 25, 1/16W 1%

0402 SMD

9 1 R4 CRCW04021M00FKTD Vishay/Dale RES 1.00MΩ 1/16W 1% 0402 SMD

Table 13: BOM for Microsoft Application

Item Qty Ref Manufacturer Part

Number Manufacturer Description

1 1 U1 88PG839 Marvell Ultra Low Power, 2MHz, 2A Output Current

Field Progr ammable Hysteretic Step-Down

Switching Regulator

2 1 C1 GRM219R60J106KE19D Murata CAP CER 10μF 6.3V X5R 10% 0805

3 3 C2 GRM21BR60J226ME39L Murata CAP CER 22μF 6.3V X5R 20% 0805

4 1 C3 C1005X5R1A104K TDK Corporation CAP CER .10μF 10V X5R 10% 0402

5 1 L1 VLCF4028T-3R3N1R6-2 TDK Corporation VLCF Series, 3.3μH, 2.31A, 48mΩ,

H=2.8mm, L=4.0mm, W=4.0mm

6 1 R1 ERJ-2RKF10R0X Panasonic ECG RES 10.0Ω 1/16W 1% 0402 SMD

71R2 See Table 10 on page 25, 1/16W 1% 0402

SMD

81R3 See Table 10 on page 25, 1/16W 1% 0402

SMD

9 1 R4 CRCW04021M00FKTD Vishay/Dale RES 1.00MΩ 1/16W 1% 0402 SMD

Mechanical Drawings

July 8, 2010, 2.00 Document Classification: Proprietary Page 53

7Mechanical Drawings

7.1 Mechanical Drawings

Figure 56: 3mm x 4mm 12-Lead DFN Mechanical Drawing

Notes:

All dimensions in mm.

See Section 8, Part Order Numbering/Package Marking, on page 55 for package marking and pin 1

location.

88PG839

Datasheet

Page 54 Document Classification: Proprietary July 8, 2010, 2.00

7.2 Typical Pad Layout Dimensions

7.2.1 Recommended Solder Pad Layout

Figure 57: 3mm x 4mm DFN-12 Land Pattern (mm)

4.00

2.20

1.60

3.50

0.55

3.30

0.075

0.83

0.56

0.50 0.67

Package

Outline

3x 4 DFN-12

Land P at tern ( m m )

1.75

0.23

D F N Lead w i th

N on-S ol der M ask D efined T ermi nal

Pad SM

0.23 mm

0.50 mm

0.051 mm

0.27 mm

Pad Pad

0.168 mm

Note

•Top view

• The “1” indicates pin 1

• Drawing not to scale

• Oversize solder mask (SM) by 4 mils over pad size (2 mil annular ring)

• 0.168mm solder mask between pads

• Tolerance ±0.05mm

Part Order Numbering/Package Mark ing

Part Order Numbering Scheme

July 8, 2010, 2.00 Document Classification: Proprietary Page 55

8Part Order Numbering/Package Marking

8.1 Part Order Numbering Scheme

Figure 58 shows the part order numbering scheme. Refer to a Marvell Field App lication Engineer

(FAE) or sales representative for further information when ordering parts.

8.2 Part Ordering Options

The standard ordering part numbers for the respective solutions are the following:

Figure 58: Sample Part Number

–xx–NAE2C000–xxxx

Part number

Package code

Environmental code

1 = RoHS 6/6

2 = Green

Temperature code

C = Commercial

I = Industrial

Custom code (optional)

88PG839

Custom code

Table 14: Part Order Options1

Package Type Part Order Number

12-pin DFN, 3mm x 4mm 88PG839-A1-NAE2C000-T181

12-pin DFN, 3mm x 4mm 88PG839-A1-NAE2C000TT181 (Tape and Reel)

12-pin DFN, 3mm x 4mm 88PG839-A1-NAE2C000

12-pin DFN, 3mm x 4mm 88PG839-A1-NAE2C000-T (Tape and Reel)

1. Please review Table 6, Switching S tep-down Regulator , on page 18 PWM Mode output voltage over temperature ratings

for part order number differences.

88PG839

Datasheet

Page 56 Document Classification: Proprietary July 8, 2010, 2.00

8.3 Package Marking

Figure 59 shows a sample package marking and pin 1 location.

Figure 59: Package Marking and Pin 1 Location

*Note: The power code (either “00” or “01”) is determined by the part order number used.

Power code “00” = Part Order Number 88PG839-A1-NAE2000-T181

Power code “01” = Part Order Number 88PG839-A1-NAE2000

0xXXP

YWW$$

Marvell “M” and partial part number

Date code and lot traceability code

Y = last digit of year

WW = work week

$$ = lot traceability code

The above example is not drawn to scale. Location of markings are approximate.

Pin 1

Power code, custom code, assembly house code

0x = power code (either “00” or “01”)*

XX = custom code

P = assembly house code

July 8, 2010, 2.00 Document Classification: Proprietary Page 57

ARevision History

Table 15: Revision History

Document Type Document Revision

Release Re v. D

• Electrical Characteristics: Table 6: Changed PG Leakage Current values.

• Applications: Bill of Materials edits.

Marvell. Moving Forward Faster

Marvell Semiconductor, Inc.

5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500

Fax: 1.408.752.9028

www.marvell.com

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