RIS HI-506, HI-507, rewigenvueron HI-508, HI-509 Single 16 and 8/Differential 8-Channel and August 1997 4-Channel CMOS Analog Multiplexers Features Description * Low ON Resistance ...........0000 eee eeee 180Q The HI-506/HI-507 and HI-508/HI-509 monolithic CMOS Wide Analog Signal Range .................0-. HBV multiplexers each include an array of sixteen and eight ana- log switches respectively, a digital decoder circuit for channel * TTL/CMOS Compatible selection, voltage reference for logic thresholds, and an enable input for device selection when several multiplexers are present. The Dielectric Isolation (DI) process used in fab- + Maximum Power Supply ...........-.....+-55- 44v__irication of these devices eliminates the problem of latchup. DI also offers much lower substrate leakage and parasitic capacitance than conventional junction isolated CMOS (see * No Latch-Up Application Note AN521). * Access Time ..........-2200 cece cece eres 250ns * Break-Before-Make Switching Replaces DG506A/DG506AA and DG507A/DG507AA The switching threshold for each digital input is established by an internal +5V reference, providing a guaranteed minimum + Replaces DG508A/DG508AA and DG509A/DGS509AA 2.4V for logic 1 and maximum 0.8V for logic 0. This allows direct interface without pullup resistors to signals from most Applications logic families: CMOS, TTL, DTL and some PMOS. For protec- oo tion against transient overvoltage, the digital inputs include a * Data Acquisition Systems series 2002 resistor and diode clamp to each supply. * Precision Instrumentation The HI-506 is a single 16-Channel, the HI-507 is an * Demultiplexing 8-Channel differential, the HI-508 is a single 8-Channel and ; the HI-509 is a 4-Channel differential multiplexer. The * Selector Switch HI-506/HI-507 are available in a 28 lead ceramic or plastic DIP, 28 pad leadless chip carrier (CLCC), 28 pin plastic leaded chip carrier (PLCC) and 28 lead SOIC packages. The HI-508/HI-509 are available in a 16 pin plastic or ceramic DIP, a 20 pin plastic leaded chip carrier (PLCC), 20 pad ceramic leadless chip carrier (CLCC) and 16 lead SOIC packages. If input overvoltages are present, the HI-546/HI-547/HI-548/ HI-549 multiplexers are recommended. For further information see Application Notes AN520 and AN521._ The HI-506/HI-507/HI-508/HI-509 is offered in both commercial and military grades. For additional High Reliability Screening including 160 hour burn-in specify the -8 suffix. For MIL-STD-883 compliant parts, request the HI-506/883, HI-507/883, HI-508/883 or HI-509/883 data sheet. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. File Number 31 42 1 Copyright Harris Corporation 1997 11-54HI-506, HI-507, HI-508, HI-509 Ordering Information TEMP. PKG. TEMP. PKG. PART NUMBER | RANGE (C) PACKAGE NO. PART NUMBER | RANGE (C) PACKAGE NO. H11-0506/883 -55 to 125 |28Ld CERDIP F28.6 H11-0508-8 Hi-Rel 16 Ld CERDIP F16.3 Pressing with HI1-0506-8 Hi-Rel 28 Ld CERDIP F28.6 Burn-In Pressing with Burn-In H14-0508/883 -55 to 125 |20Ld CLCC J20.A H14-0506/883 -55to 125 |28Ld CLCC J28.A H11-0509/883 -55 to 125 |16Ld CERDIP F16.3 H11-0507/883 -55 to 125 |28Ld CERDIP F28.6 H11-0508-5 0 to 75 16 Ld CERDIP F16.3 HI9P0506-9 -40 to 85 =|28Ld SOIC M28.6 HI3-0508-5 0 to 75 16 Ld PDIP E16.3 HI3-0506-5 0 to 75 28 Ld PDIP E28.6 H11-0508-4 -25to 85 |16Ld CERDIP F16.3 H11-0506-7 0 to 75 +96 |28 Ld CERDIP F28.6 H11-0508-2 -55 to 125 |16Ld CERDIP F16.3 Hour Burn-In HI4P 0508-5 0 to 75 20 Ld PLCG N20.35 HI9P0506-5 0 to 75 28 Ld SOIC M28.3 HI9P0508-9 -40 to 85 |16Ld SOIC M16.15 H11-0506-5 0 to 75 28 Ld CERDIP F28.6 HI9P0508-5 0 to 75 16 Ld SOIC M16.15 H11-0506-4 -25to 85 |28Ld CERDIP F28.6 H11-0509-8 Hi-Rel 16 Ld CERDIP F16.3 HI1-0506-2 -55to125 |28Ld CERDIP F28.6 Pressing with Burn-In H|1-0507-8 Hi-Rel 28 Ld CERDIP F28.6 Pressing with H14-0509/883 -55to 125 |20Ld CLCC J20.A Burn-In HI9P0509-5 0 to 75 16 Ld SOIC M16.15 H14-0507/883 -55to 125 |28Ld CLCC J28.A HI9P0509-9 -40 to 85 |16Ld SOIC M16.15 H11-0507-4 -25to 85 |28Ld CERDIP F28.6 H11-0509-4 -25to 85 |16Ld CERDIP F16.3 HI4P0507-5 0 to 75 28 Ld PLCC N28.45 H11-0509-5 0 to 75 16 Ld CERDIP F16.3 HI9P0507-5 0 to 75 28 Ld SOIC M28.3 HI3-0509-5 0 to 75 16 Ld PDIP E16.3 H11-0507-5 0 to 75 28 Ld CERDIP F28.6 HI4P0509-5 0 to 75 20 Ld PLCG N20.35 HI3-0507-5 0 to 75 28 Ld PDIP E28.3 H11-0509-2 -55 to 125 |16Ld CERDIP F16.3 HI9P0507-9 -40 to 85 =|28Ld SOIC M28.3 H|1-0509-7 0 to 75 +96 | 16 Ld CERDIP F16.3 H11-0507-2 -55to125 |28Ld CERDIP F28.6 Hour Burn-In H11-0508/883 -55 to 125 |16Ld CERDIP F16.3 11-55HI-506, HI-507, HI-508, HI-509 Pinouts HI-506 (PDIP, CERDIP, SOIC) TOP VIEW +VsuppLy [1] 28] OUT NC 2] 27] -VSUPPLY ne [3] 26] IN 8 IN 16 [4] 25] IN 7 IN 15 [5] 24] IN 6 IN 14 [6] 23] IN 5 IN 13 [7] 23] IN 4 IN 12 [8] 21] IN 3 IN 11 [9] 20] IN 2 IN 10 fio] ig] IN 41 Ino [i] 8] ENABLE GND fi2 7] ADDRESS Ap ne [i3| 6] ADDRESS A, ADDRESS As [14] 15] ADDRESS Az HI-506 (CLCC, PLCC) TOP VIEW z 3 5, rr no a 5 wn z?ee?r%s5oeFe2z - tT tt tt tt tt tt tt tT (iad tgd i2d tt | test ta7t je) IN15 [51 125| IN7 fo oe oll oo R= ro IN14 [6! 124] ING = cod IN13 [71 123] INS Cy 4 INi2 | st 122] IN4 bes os oll Lae: ot Cr _4 IN11 Jot 121| IN3 | a IN1o [401 In0| o 10) 120} IN2 Cr _4 INQ [441 149] IN4 NO righ Fist Fal Fgh Fel Fd Tiel 7 XG LI LI LU Lt LI Hd o9 2 g@ ee Hy 9 < za WW IN 7B IN 6B IN 5B IN 4B IN 3B IN 2B IN 1B HI-507 (PDIP, CERDIP, SOIC) TOP VIEW +Vsuppty [1 [28] OUT A OUT B 2] 27] -VSUPPLY ne [3] 26] IN 8A IN 8B [4) 25] IN 7A IN 7B [5] 24] IN GA IN 6B [6] 23] IN 5A IN 5B [7] 22] IN 4A IN 48 [8] 21] IN 3A IN 3B [9 20] IN 2A IN 2B [io ig] IN 1A IN 1B fi] 8] ENABLE GND [i2 7] ADDRESS Ap ne [i3| 6] ADDRESS A, Ne [4] 15] ADDRESS Az HI-507 (CLCC, PLCC) TOP VIEW on be E a 3 FEF BE BE z?v?223grF2z = z o + o 7 = (TaTia Tal fled tad fad S 5 | 125] IN7A = r-a 6! 124] INGA eS rea 7! 123] IN5A ers 4 8! 122] IN 4A eos _4 9! 121] IN3A ers _4 iof 120] IN 2A eos _4 111 119] IN1A NT Fist Fist Fal Fig] Fed FG Tel 7 Qe ] LI LI LI Hd 2 928?egae? ENABLE 11-56HI-506, HI-507, HI-508, HI-509 Pinouts (Continued) HI-508 HI-509 (PDIP, CERDIP, SOIC) (PDIP, CERDIP, SOIC) TOP VIEW TOP VIEW Ww ed ENABLE [2| 15] Az ENABLE [2| 5] GND -Vsuppcy [3] 4] GND -Vsuppcy [3] 4] +VsuppLy In1 [4] 13] +VsupPLy IN 1A [4] 13] IN 1B IN 2 [5] 2] IN 5 IN 2A [5 12] IN 2B In 3 [6] Hi] IN 6 IN 3A [6 Hi] IN 3B In4 [7] HO] IN 7 IN 4A [7] 9] IN 4B out [8] Pa] Ins ouT a [BI [9] OUT B HI-508 HI-509 (CLCC, PLCC) (CLCC, PLCC) TOP VIEW TOP VIEW W a a <t Zz W VSUPPLY -VSUPPLY 118 +VSUPPLY IN4 INA 17 IN 1B NC NC 1161 NC IN2 IN 2A IN 2B IN3 IN3A 174] IN 3B 11-57HI-506, HI-507, HI-508, HI-509 Functional Diagrams HI-506 HI-507 IN1 Oo OUT IN1A O}0f 0o@__________1_9 oT A ! e I ST , I IN? Om I INBA o_ Lofo e L DECODER/ I : DRIVER IN14B oo 09 4 9 ours I IN16 Of of 1 beads t= e ! DECODER/ 4S I DRIVER IN8B O-ofo 5V LEVEL .---- REF SHIFT Zy + DIGITAL 5V LEVEL INPUT THIEL REF SHIFT PROTECTION DIGITAL good 3 TNPUT Ap Ay Ap Az EN PROTECTION 6 6 6 86 Ap Ay Az EN HI-508 HI-509 IN 1 on O OUT INTA 0|$-0 9g 0 ou A ' I . e I IN2 o_o I 1 IN4A o-t-ofo_ t DECODER/ or : DRIVER IN1B o-oo _____1-0 ous I INS Of _of e or e oo el ! DECODER/ 4 | DRIVER IN4B O-o7 o 5V LEVEL t---- REF SHIFT zy + DIGITAL 5V LEVEL INPUT EL REE REF SHIFT PROTECTION DIGITAL $6 8 6 TINBUT Ap A, Az EN PROTECTION 6 6 5 Ao Ay EN 11-58HI-506, HI-507, HI-508, HI-509 Schematic Diagrams ADDRESS DECODER 9 4 a, i TO P-CHANNEL N | DEVICE OF | THE SWITCH +_| A, OR A, > TO N-CHANNEL 4 DEVICE OF _ THE SWITCH Az ORAZ Az OR Ag ENABLE DELETE Az OR Ag INPUT FOR HI-507 : DELETE Ag OR Ag INPUT FOR HI-508 J DELETE A> OR A> INPUT FOR HI-509 V- ADDRESS INPUT BUFFER LEVER SHIFTER P3 gr it Pt a. LJ L, >A + N1 pa pef~ | P7 P8 P9 Pid D1 LY qo AH VL > > N7 be Ve NG Le No Nio _l2| Heo N4 _ 2002. >A " be Lad A N3 t IN ALL N-CHANEL BODIES TO V- ALL P-CHANNEL BODIES TO V+ VV UNLESS OTHERWISE INDICATED TTL REFERENCE CIRCUIT MULTIPLEX SWITCH y V+ ___4 PIs ap aapl aap FROM DECODE N18 L QiP ] | Q5N V * N17 Q6N QsN [is +4 NC | rk re Vv R2 P17 L N12 16.8K | =| QUP Q7P V- D3 el Vv QI0N A 7% SRB VR aor > 6.8K - Pis {i N13 N14 | N15 PiG Pa LR > x = FROM DECODE V- GND 11-59HI-506, HI-507, HI-508, HI-509 Absolute Maximum Ratings Thermal Information Vsu PPLY(+) to Vsy PPLY() oot eee ees +44V Thermal Resistance (Typical, Note 1) QUA (CM) 8Jc (CM) VSUPPLY(+) tO GND... 6. eee +22V 16 Ld CERDIP Package ............ 85 32 VsuPPLY(-) tO GND... 60. eee -25V 16 Ld SOIC Package.............. 115 N/A Digital Input Overvoltage 16 Ld PDIP Package.............. 100 N/A FVENL TVA cee +VsupPPLy +4V 20 Ld CLCC Package .............. 80 28 VEN. CVA Lc teens -VsupPPLy -4V 20 Ld PLCC Package ............. 80 N/A or 20mA, Whichever Occurs First 28 Ld CERDIP Package ........... 55 18 Analog Signal Overvoltage (Note 7) 28 Ld PDIP Package.............. 60 N/A PVG eee +VsuPPLY +2V 28 Ld SOIC Package.............. 70 N/A Ngo eee -VsupPLy -2V 28 Ld CLCC Package .............. 70 20 Continuous Current, SorD ....... 0.0.0... e eee 20mA 28 Ld PLCC Package ............. 70 N/A Peak Current, SorD ............ 0000 cee 40mA Maximum Junction Temperature (Pulsed at 1ms, 10% Duty Cycle Max) Ceramic Package ... 0.0.00... eee 175C Plastic Package... 0... cee ee 150C Operating Conditions Temperature Ranges HI-506/507/508/509-2, -8....... HI-506/507/508/509-4.......... HI-506/507/508/509-5.......... Maximum Storage Temperature Range Maximum Lead Temperature (Soldering 10s) (SOIC and PLCC - Lead Tips Only) eee ee ees -55C to 125C Doce e eee eee -25C to 85C eee e eee eens 0C to 75C .. . 300C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. 9ja is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Supplies = +15V, -15V; Vay (Logic Level High) = +2.4V; Va; (Logic Level Low) = +0.8V, Unless Otherwise Specified. For Test Conditions, Consult Performance Curves TEST TEMP HI-5XX-2, HI-5XX-8 HI-5XX-4, HI-5XX-5 PARAMETER CONDITIONS | (C) MIN | TYP | MAX [| MIN | TYP | MAX [ UNITS SWITCHING CHARACTERISTICS Access Time, la (Note 1) 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns Break-Before-Make Delay, topen | (Note 1) 25 25 80 - 25 80 - ns Enable Delay (ON), tON(EN) (Note 1) 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns Enable Delay (OFF), toFF(EN) (Note 1) 25 - 250 500 - 250 - ns Full - - 1000 - - 1000 ns Settling Time to 0.1%, tg 25 - 1.2 - - 1.2 - ps (HI-506 and HI-507) Settling Time to 0.01%, ts 25 - 2.4 - - 2.4 - ps (HI-506 and HI-507) Settling Time to 0.1%, tg 25 - 360 - - 360 - ns (HI-508 and HI-509) Settling Time to 0.01%, ts 25 - 600 - - 600 - ns (HI-508 and HI-509) Off Isolation (Note 5) 25 50 68 - 50 68 - dB Channel Input Capacitance, 25 - 10 - - 10 - pF Cs(OFF) Channel Output Capacitance, 25 - 52 - - 52 - pF CD(OFF) (HI-506) Channel Output Capacitance, 25 - 30 - - 30 - pF CD(OFF) (HI-507) Channel Output Capacitance, 25 - 17 - - 17 - pF CD(OFF) (HI-508) Channel Output Capacitance, 25 - 12 - - 12 - pF CD(OFF) (HI-509) 11-60HI-506, HI-507, HI-508, HI-509 Electrical Specifications Supplies = +15V, -15V; Vay (Logic Level High) = +2.4V; Va, (Logic Level Low) = +0.8V, Unless Otherwise Specified. For Test Conditions, Consult Performance Curves (Continued) TEST TEMP HI-5XX-2, HI-5XX-8 HI-5XX-4, HI-5XX-5 PARAMETER CONDITIONS (C) MIN TYP MAX MIN TYP MAX UNITS Digital Input Capacitance, Ca 25 - 6 - - 6 - pF Input to Output Capacitance, 25 - 0.08 - - 0.08 - pF CDS(OFF) DIGITAL INPUT CHARACTERISTICS Input Low Threshold, Va; (Note 1) Full - - +0.8 - - +0.8 Vv Input High Threshold, Vay (Note 1) Full +2.4 - - +2.4 - - Vv Input Leakage Current (Notes 1, 4) Full - - 1.0 - - 1.0 HA (High or Low), la ANALOG CHANNEL CHARACTERISTICS Analog Signal Range, Vs Full -15 - +15 -15 - +15 Vv On Resistance, ron (Notes 1, 2) 25 - 180 300 - 180 400 Q Aron: (Any Two Channels) 25 - 5 - - 5 - % Off Input Leakage Current, (Note 3) 25 - 0.03 - - 0.03 - nA IS(OFF) Full - - 50 - - 50 nA Off Output Leakage Current, (Note 3) 25 - 0.3 - - 0.3 - nA ID(OFF) HI-506 Full - - 300 - - 300 nA HI-507 Full - - 200 - - 200 nA HI-508 Full - - 200 - - 200 nA HI-509 Full - - 100 - - 100 nA On Channel Leakage Current, (Note 3) 25 - 0.3 - - 0.3 - nA ID(ON) HI-506 Full - - 300 - - 300 nA HI-507 Full - - 200 - - 200 nA HI-508 Full - - 200 - - 200 nA HI-509 Full - - 100 - - 100 nA Differential Off Output Leakage (Note 1) Full - - 50 - - 50 nA Current, IpiFF (HI-507, HI-509 Only) POWER REQUIREMENTS Current, l+, Pin 1 HI-506/HI-507 | (Note 6) Full - 1.5 3.0 - 1.5 3.0 mA Current, 1+, HI-508/HI-509 (Note 6) Full - 1.5 2.4 - 1.5 2.4 mA Current, I-, Pin 27 HI-506/HI-507 | (Note 6) Full - 0.4 1.0 - 0.4 1.0 mA Current, I-, HI-508/HI-509 (Note 6) Full - 0.4 1.0 - 0.4 1.0 mA Power Dissipation, Pp HI-506/HI-507 Full - - 60 - - 60 mw HI-508/HI-509 Full - - 51 - - 51 mw NOTES: 1. 100% tested for Dash 8. Leakage currents not tested at -55C. . Vout = 10V, lout = +1mA. . 10nA is the practical lower limit for high speed measurement in the production test environment. . Digital input leakage is primarily due to the clamp diodes (see Schematic). Typical leakage is less than 1nA at 25C. . Ven = 0.8V, RL = 1K, CL = 15pF, Vs = 7Vpms, f= 100kHz. . Ven: Va = OV or 2.4V. . Signal voltage at any analog input or output (S or D) will be clamped to the supply rail by internal diodes. Limit the resulting current as shown under absolute maximum ratings. If an overvoltage condition is anticipated (analog input exceeds either power supply voltage), the Harris HI-546/HI-547/HI-548/HI-549 multiplexers are recommended. NO oR WD 11-61HI-506, HI-507, HI-508, HI-509 Typical Performance Curves 1p = 25C, Vsuppiy = 15V, VaH = 2.4V, VaL = 0.8V, Unless Otherwise Specified V2 1mA FIGURE 1A. TEST CIRCUIT 400 2.2 S20 125C TO -55C wis . VIN =0V 300 oF g Zi 18 g Ta = 125C B35 1.6 z A= na = F200 az 14 n Ta = 25C we Fd IO 1.2 z ie 100 #5 10 Ta = 55C on Z2zu 08 0 0.6 15 -10 5 0 45 +10 +15 +748 +9 HO 411 +12 +3 414 +15 ANALOG INPUT (V) SUPPLY VOLTAGE (V) FIGURE 1B. ON RESISTANCE vs ANALOG INPUT VOLTAGE, FIGURE 1C. NORMALIZED ON RESISTANCE vs SUPPLY TEMPERATURE VOLTAGE FIGURE 1. ON RESISTANCE 100nA OFF OUTPUT jona |. LEAKAGE CURRENT Ip(oFF) 3S E +0.8V = Wu oe oe 3 w nA A) ID(orF) 6 < i 4 +10V OFF INPUT LEAKAGE CURRENT 100pA IS(OFF) 10pA 25 50 75 100 125 TEMPERATURE (C) FIGURE 2A. LEAKAGE CURRENT vs TEMPERATURE FIGURE 2B. Ip(orrF) TEST CIRCUIT 11-62HI-506, HI-507, HI-508, HI-509 Typical Performance Curves 1, = 25C. Vsuppy = +15V, Vay = 2.4V, Va = 0.8V, Unless Otherwise Specified (Continued) A) !s(orF) +2.4V FIGURE 2C. Is(OFF) TEST CIRCUIT FIGURE 2D. ID(ON) TEST CIRCUIT FIGURE 2. ON RESISTANCE NOTE: 1. Two measurements per channel: +10V/-10V and -10V/+10V. (Two measurements per device for Ip(oFF) +10V/-10V and -10V/+10V.) oy 100 80 oa 60 40 INPUT LOGIC THRESHOLD (V) = NO (Vg), (Vp) OFF ISOLATION (dB) CLoap = 28pF Vs =7VRus 0 0 +6 +8 +10 +H12+14 H6 +18 +20 104 10 10 10 POWER SUPPLY VOLTAGE (V) FREQUENCY (Hz) FIGURE 3. LOGIC THRESHOLD vs POWER SUPPLY VOLTAGE FIGURE 4. OFF ISOLATION vs FREQUENCY Nn + POWER SUPPLY CURRENT (mA) POWER SUPPLY CURRENT (mA) 55-35 15 -5 2 45 65 85 105 125 55 35 -15 -5 25 45 65 85 105 125 TEMPERATURE (C) TEMPERATURE (C) FIGURE 5A. HI-506/HI-507 FIGURE 5B. HI-508/HI-509 FIGURE 5. POWER SUPPLY CURRENT vs TEMPERATURE 11-63HI-506, HI-507, HI-508, HI-509 Typical Performance Curves 1, = 25C. Vsuppy = +15V, Vay = 2.4V, Va = 0.8V, Unless Otherwise Specified (Continued) 70 60 Ta=-55C | 50 b A Ty = 25C iy 40 a 3 30 A mat a5 5 Yr ra r a o = 20 A a Y 10 0 o +2 +4 +60 +8 10 sH12es HA HIG VOLTAGE ACROSS SWITCH (V) FIGURE 6A. ON CHANNEL CURRENT vs VOLTAGE FIGURE 6B. TEST CIRCUIT FIGURE 6. ON CHANNEL CURRENT vs VOLTAGE 8 +15V/+10V +ISUPPLY VsupPLy = +15V q@ 6 t +V E A3 IN 1 o +10V/+5V rm HI-506 + c 4 A2 IN 2 ro THRUY 1 y Va 500 Ay IN 7/151a_o PL > = a / = = LI] IN816>~9 +oVvit5v oH 2 WA +3.5V O4 EN OUT o J VsuppLy = +10V HIGH = 3.5V GND we 14 | Va < LOW =0V L Ma pF 0 | 50% DUTY CYCLE 4 = -ISUPPLY 1K 10K 100K 1M 10M _ . _ TOGGLE FREQUENCY (Hz) t Similar connection for HI-507/HI-508/ 45V/-10V = FIGURE 7A. SUPPLY CURRENT vs TOGGLE FREQUENCY FIGURE 7B. TEST CIRCUIT FIGURE 7. SUPPLY CURRENT 600 | +15V +V z i As IN1o +10v y, 400 Ww . A IN 2 THRU = ww IN715 7 r V, 502 = 2 Sa A AY uLso6t _ uw +10V 9 = = Ly? IN 16 fo PROBE < 200 EE Bee ee +3.5V o4 EN OUT o ' GND 1 0g 50 | ' pka> PFT, . : | 1 0 i i 2 3 4 5 z 13 14 15 = -15V i = I LOGIC LEVEL (HIGH) (V) + Similar connection for HI-507/HI-508/ bees HI-509 FIGURE 8A. ACCESS TIME vs LOGIC LEVEL (HIGH) FIGURE 8B. TEST CIRCUIT 11-64HI-506, HI-507, HI-508, HI-509 Switching Waveforms 3.5V ADDRESS Va INPUT DRIVE (Va) OVIDIV. ; $1 ON I +10V I OUTPUT I 9 OUTPUT 90% 40V 5VIDIV. > ta la S15 ON 200ns/DIV. FIGURE 8C. WAVEFORMS FIGURE 8D. ACCESS TIME FIGURE 8. ACCESS TIME +15V j Az +V HI-506 7 +5V Ao IN 1 o IN 7/IN 15 _l Va 502. Ay IN 8/16 = = L Ja 7 7 Vout +3.5V O4 EN OUT T o 50pF GND 2002S i uJ - -15v lL + Similar connection for HI-507/HI-508/HI-509 FIGURE 9A. TEST CIRCUIT 3.5V ADDRESS S16 ON ov DRIVE (Va) OUTPUT OUTPUT A IV/DIV. 50% 50% l l ~~ Pea topEN 100ns/DIV. FIGURE 9B. WAVEFORMS FIGURE 9C. BREAK-BEFORE-MAKE DELAY (topen) FIGURE 9. BREAK-BEFORE-MAKE DELAY (topen) 11-65HI-506, HI-507, HI-508, HI-509 Switching Waveforms (continued) +15V a +V HI-506 A t IN 1 Jo +10V > IN 2 THRU IN 7/IN 15 Ay IN 8/16 _ = 4 Ao = VouT EN OUT Jo Vy L Va $500 cn T 2002S 50pF L -15V + Similar connection for HI-507/HI-508/HI-509 FIGURE 10A. TEST CIRCUIT ENABLE DRIVE 3.5V I ov OUTPUT A 10% I I >! ton(EN) <_ ; OUTPUT 1 =, LOFF(EN) i 2v/DIV. FIGURE 10B. WAVEFORMS FIGURE 10C. ENABLE DELAY toncen); torF(EN) FIGURE 10. ENABLE DELAY 11-66HI-506, HI-507, HI-508, HI-509 Truth Tables HI-508 HI-506 i z Zz < x o z ON CHANNEL HI-509 rm Zz Zz < = 5 z HI-507 i z Zz < x o z 11-67HI-506, HI-507, HI-508, HI-509 Die Characteristics WORST CASE CURRENT DENSITY: 1.4x 10 A/em2 DIE DIMENSIONS: 129 mils x 82 mils TRANSISTOR COUNT: 421 METALLIZATION: Type: CuAl Thickness: 16kA +2kA PROCESS: CMOS-DI SUBSTRATE POTENTIAL (NOTE): -VSUPPLY PASSIVATION: Type: Nitride/Silox Nitride Thickness: 3.5kA +1kA +2kA NOTE: The substrate appears resistive to the -Vsupp,y terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted 12kA on a conductor at -Vsypp_y potential. Silox Thickness: Metallization Mask Layout HI-507 Az Ag Ay EN Ao N 8B Hoa 3 es ee NOTE: Pad numbers correspond to DIP pin numbers only. 11-68HI-506, HI-507, HI-508, HI-509 Die Characteristics DIE DIMENSIONS: WORST CASE CURRENT DENSITY: 81.9 mils x 90.2 mils 1.4x 10 A/em2 METALLIZATION: TRANSISTOR COUNT: Type: CuAl . . 234 Thickness: 16kA +2kA PROCESS: SUBSTRATE POTENTIAL (NOTE): CMOS-DI -VSUPPLY PASSIVATION: Type: Nitride/Silox : : Nitride Thickness: 3.5kA +1kA Silox Thickness: 12kA+2kA NOTE: The substrate appears resistive to the -Vsupp,y terminal, therefore it may be left floating (Insulating Die Mount) or it may be mounted on a conductor at -Vsypp_y potential. Metallization Mask Layout HI-508 HI-509 ice te t | arRis | (TIGL HE-SOS Tellme IN 4 OUT IN8 IN4A OUTA OUTB IN4B NOTE: Pad numbers correspond to DIP pin numbers only. 11-69