ATS636LSETN-T - Allegro Microsystems

Description

The ATS636LSE programmable, true power-on state (TPOS),

device is optimized Hall-effect IC and rare-earth pellet

combinations that switch in response to magnetic signals

created by ferromagnetic targets in gear-tooth sensing and

proximity applications.

The device is externally programmable. A wide range of

programmability is available on the magnetic operate point

(BOP) while the hysteresis remains fixed. This advanced

feature allows for optimization of the circuit switchpoint and

can drastically reduce the effects of mechanical placement

tolerances found in production environments .

A proprietary dynamic offset cancellation technique, with

an internal high-frequency clock, reduces the residual offset

voltage, which is normally caused by device overmolding,

temperature dependencies, and thermal stress. Having the Hall

element and amplifier in a single chip minimizes many problems

normally associated with low-level analog signals.

This device is ideal for use in gathering speed or position

information using gear-tooth-based configurations, or for

proximity sensing with ferromagnetic targets.

635LSE-DS, Rev. 5

Features and Benefits

▪ Chopper Stabilization

▫ Extremely low switchpoint drift over temperature

▪ On-chip Protection

▫ Supply transient protection

▫ Output short-circuit protection

▫ Reverse-battery protection

▪ True Zero-Speed Operation

▪ True Power-On State

▪ Single-chip Sensing IC for High Reliability

▪ Optimized Magnetic Circuit

▪ Wide Operating Voltage Range

▪ Internal Regulator

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Continued on the next page…

Package: 4-pin SIP (suffix SE)

Not to scale

ATS636LSE

Functional Block Diagram

Reg

Clock/Logic

AMP S/H LPF Current

Limit

VCC

OUT

GND

Programmming

Logic

Program / Lock

Offset Adjust

To all

subcircuits

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

The ATS636LSE has the opposite polarity and switches low in the

presence of a ferromagnetic target or tooth and switches high in

the presence of a target valley, window, or when the ferromagnetic

target is removed.

These devices are lead (Pb) free, with 100% matte tin leadframe

plating.

Description (continued)

Pin-out Diagram

Absolute Maximum Ratings

Characteristic Symbol Notes Rating Unit

Supply Voltage VCC

Fault conditions that produce supply voltage

transients will be clamped by an internal Zener

diode. These conditions can be tolerated but

should be avoided.

28 V

Reverse Supply Voltage VRCC –18 V

Overvoltage Supply Current ICC 100 mA

Output Off Voltage VOUT 26.5 V

Output Sink Current IOUT

Internal current limiting is intended to protect

the device from output short circuits, but is not

intended for continuous operation.

20 mA

Magnetic Flux Density B Unlimited –

Package Power Dissipation PDSee Graph –

Operating Ambient Temperature TARange L –40 to 150 ºC

Junction Temperature TJ165 ºC

Storage Temperature Range Tstg –65 to 170 ºC

Terminal List

Number Name Function

1 VCC Device supply

2 VOUT Device output

3 NC No connect

4 GND Device ground

Selection Guide

Part Number Output

(Tooth) Packing*

ATS636LSETN-T Low 13-in. reel, 450 pieces/reel

*Contact Allegro® for additional packing options.

2431

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

ELECTRICAL CHARACTERISTICS over operating voltage and junction temperature range; unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ.1Max. Unit

Supply Voltage2VCC Operating 4.2 – 24 V

Power-Up State POS After programming VCC = 0 × VCC

(min), t > tON

: B < BOP High High High –

Low Output Voltage VOUT(SAT) Output on, IOUT = 20 mA – 175 400 mV

Output Current Limit3IOUTM Pulse test method, output on 30 50 90 mA

Output Leakage Current IOFF Output off, VOUT = 24 V – – 10 A

Supply Current ICC Output off (high) – 2.5 5.5 mA

Output on (low) – 2.5 5.5 mA

Reverse Supply Current IRCC VRCC = –18 V – – –5 mA

Power-On Delay4tON Output off, VCC > VCC(min) – 35 50 s

Output Rise Time tr R

L = 820 , CL = 10 pF – 1.2 5 s

Output Fall Time tf R

L = 820 , CL = 10 pF – 1.2 5 s

Sampling Frequency fsample – 250 – kHz

Supply Zener Voltage VZsupply I

CC = ICC(max) + 3 mA, TA = 25°C 28 – – V

Output Zener Voltage VZoutput I

OUT = 3 mA, TA = 25°C 30 – – V

Supply Zener Current5IZsupply V

S = 28 V – – 8.5 mA

Output Zener Current IZoutput V

O = 30 V – – 3 mA

1Typical data is at VCC = 12 V and TA = 25°C.

2Do not exceed the maximum thermal junction temperature: see power derating curve.

3Short circuit protection is not intended for continuous operation and is tested using pulses.

4The Power-On Delay is the time that is necessary before the output signal is valid.

5The maximum spec limit for this parameter is equivalent to ICC

(max) + 3 mA.

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

MAGNETIC CHARACTERISTICS over operating voltage and junction temperature range using reference target; unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Unit

Number of Programming Bits

Switchpoint – 7 – bit

Switchpoint Polarity – 1 – bit

Programming Lock – 1 – bit

Gear Tooth / Proximity Characteristics (Low switchpoint only)

Programming Air Gap Range1AGRange

Temperature = 25°C, Code = –127 2.5 – – mm

Temperature = 25°C, Code = +127 – – 1.5 mm

Programming Resolution AGRes Temperature = 25°C Program Air Gap = 2.5 mm – 0.05 – mm

Air Gap Drift Over Full Temperature

Range2AGDrift Device programmed to 2.5 mm – 0.2 – mm

Polarity P Over tooth (ATS636LSE) – Low – –

Over valley (ATS636LSE) – High – –

1The switchpoint will vary over temperature. A sufficient margin obtained through customer testing is required to guarantee functionality over

temperature. Programming at larger air gaps leaves no safety margin for switchpoint drift. See the applications note Proximity Sensing

Programming Technique on the Allegro website at http://www.allegromicro.com for additional information.

2The switchpoint will vary over temperature, proportionally to the programmed air gap. This parameter is based on characterization data and is not

a tested parameter in production. Switchpoint air gap generally drifts downward as temperature increases.

Tooth and Valley Field vs. Air Gap

Reference Target

200

400

600

800

1000

1200

1400

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

Air Gap [mm]

Flux Density [Gauss]

Reference Target Tooth

Reference Target Valley

Reference Target Tooth and Valley Field vs. Air Gap

Reference Target Flux Density vs. Position

200

400

600

800

1000

1200

1400

0 30 60 90 120 150 180 210 240 270 300 330 360

Position (º)

Flux Density (Gauss)

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

3.25

3.50

3.75

4.00

4.25

4.50

4.75

5.00

5.25

5.50

5.75

6.00

Reference Target Flux Density vs. Position: Typical

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

Characteristic Performance

ICC ON

-50 -25 0 2 5 50 75 100 125 150 175

TEMPERATURE (°C)

ICC (mA)

15V

24V

ICC OFF

-50 -25 0 2 5 5 0 75 1 00 125 150 175

TEMPERATURE (°C)

ICC (mA)

15V

24V

VSAT

100

200

300

400

500

-50 -25 0 25 50 75 100 125 150 175

TEMPERATURE (°C)

VSAT (mV)

20mA

Data taken from 3 lots, 30 pieces/lot

Reference Target 8x

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

BOP/BRP vs. Program Code

-50 0 50 100 150 200

TEMPERATURE (°C)

AIR GAP (mm)

Code -8 BOP

Code -8 BRP

Code 0 BOP

Code 0 BRP

Code +32 BOP

Code +32 BRP

Code +127 BOP

Code +127 BRP

Notes:

• Air gaps for Code 127 at 150°C are interpolated due to test limitations at minimum air gap.

• These graphs are intended to provide an understanding of how the program codes affect the switchpoints. In a production

environment, individual devices would be programmed to individual codes to ensure all devices switch at the same air gap.

Data taken from 3 lots, 30 pieces/lot

Reference Target 8x

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

Gear Parameters for Correct Operation

Characteristic Description Min. Typ. Max. Unit

Tooth Whole Depth (ht) Depth of Target Valley 5 – – mm

Circular Valley Length (Pc – T) Length of Target Valley 13 – – mm

Circular Tooth Length (T) Length of Target Tooth 5 – – mm

Face Width (F) Thickness or Width of Target Tooth 5 – – mm

REFERENCE TARGET DIMENSIONS

Target Outside Diameter

(Do) Face Width

(F) Circular Tooth Length

(T) Circular Valley Length

(PC – T) Tooth Whole Depth

(ht)

Reference Target 120 mm 6 mm 23.5 mm 23.5 mm 5 mm

Reference Target Reference Target

Material: CRS 1018

Electromagnetic Capability (EMC) Performance

Please Contact Allegro MicroSystems for EMC Performance

Test Name Reference Specification

ESD – Human Body Model AEC-Q100-002

ESD – Machine Model AEC-Q100-003

Conducted Transients ISO 7637-1

Direct RF Injection ISO 11452-7

Bulk Current Injection ISO 11452-4

TEM Cell ISO 11452-3

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

Functional Description

Chopper-Stabilized Technique

The basic Hall element is a small sheet of semiconductor material

in which a constant bias current will flow when a constant volt-

age source is applied. The output will take the form of a voltage

measured across the width of the sheet and will have negligible

value in the absence of a magnetic field. When a magnetic field

with flux lines at right angles to the Hall current is applied, a

small signal voltage directly proportional to the strength of the

magnetic field will occur at the output terminals.

This signal voltage is proportionally small relative to the offset

produced at the input of the chip. This makes it very difficult

to process the signal and maintain an accurate, reliable output

over the specified temperature and voltage range. Therefore, it is

important to reduce any offset on the signal that could be ampli-

fied when the signal is processed.

Chopper stabilization is a unique approach used to minimize

input offset on the chip. This technique removes a key source of

output drift with temperature and stress, and produces a 3× reduc-

tion in offset over other conventional methods.

This offset reduction chopping technique is based on a signal

modulation-demodulation process. The undesired offset signal is

separated from the magnetically induced signal in the frequency

domain. The offset (and any low frequency noise) component of

the signal can be seen as signal corruption added after the signal

modulation process has taken place. Therefore, the DC offset is

not modulated and remains a low frequency component. Con-

sequently, the signal demodulation process acts as a modulation

process for the offset causing the magnetically induced signal

to recover its original spectrum at baseband while the DC offset

becomes a high frequency signal. Then, using a low pass filter,

the signal passes while the modulated DC offset is suppressed.

The advantage of this approach is significant offset reduction,

which desensitizes the chip against the effects of temperature and

stress. The disadvantage is that this technique features a demodu-

lator that uses a sample and hold block to store and recover the

signal. This sampling process can slightly degrade the signal-to-

noise Ratio (SNR) by producing replicas of the noise spectrum at

the baseband. The degradation is a function of the ratio between

the white noise spectrum and the sampling frequency. The effect

of the degradation of the SNR is higher jitter, a.k.a. signal repeat-

ability. In comparison to a continuous time device, the jitter spec

can be increased by a factor of five.

Regulator

Amplifier Sample/

Hold

Clock

Hall Element

Figure 1. Concept of Chopper-Stabilization Algorithm

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

The ATS636LSE magnetic operate point, BOP , is programmed by

serially addressing the devices through the supply terminal (1).

After the correct operate point is determined, the device program-

ming bits are selected and blown, then a lock bit is selected and

blown to prevent any further (accidental) programming.

Addressing BOP is programmable in both the positive and

negative direction from its initial value. Addressing is used to

determine the desired code, while programming is used to lock

the code. A unique key is needed to blow fuses, while addressing

as described below does not allow for the device to be pro-

grammed accidentally.

Addressing with positive polarity The magnetic oper-

ate point, BOP

, is adjustable using 7 bits or 128 addresses. The

addresses are sequentially selected (figure 2) until the required

operate point is reached. The first address must be selected with

a high voltage pulse, VPP , while the remaining pulses should

be VPH pulses. Note that the difference between BOP and the

magnetic release point, BRP

, the hysteresis, BHYS , is fixed for all

addresses.

Addressing with negative polarity The magnetic operate

point, BOP

, is adjustable with negative polarity using 7 bits or

128 addresses. To invert the polarity it is necessary to first apply

a keying sequence (figure 3). The polarity key contains a VPP

pulse and at least 1 VPH pulse, but no more than 6 VPH pulses;

the key in figure 3 shows 2 VPH pulses. The addresses are then

sequentially selected until the required operate point is reached.

The first address must be selected with a high voltage pulse, VPP ,

while the remaining pulses should be VPH pulses.

d(1)

d(0)

Code 1

Code 2

Code 3

Code N-2

Code N-1

Code N

(Up to 127)

Figure 2. Addressing Pulses: Positive Polarity

d(1)

d(0)

Code -1

Code -2

Code -3

Code -(N-2)

Code -(N-1)

Code -N

(Up to -127)

Polarity

Key

Figure 3. Addressing Pulses: Negative Polarity

Addressing / Programming Protocol

PROGRAMMING PROTOCOL Valid over operating temperature range, unless otherwise noted

Characteristics Symbol Test Conditions Min. Typ. Max. Units

Programming Protocol (TA = 25°C)

Programming Voltage1,2

VPL Minimum voltage range during programming 4.5 5 5.5 V

VPH 8.5 – 15 V

VPP 25 – 27 V

Programming Current IPP Maximum supply current during programming – 500 – mA

Pulse Width

td(0) Off-time between bits 20 – – s

td(1) Enable, address, program, or lock bit on-time 20 – – s

tdP Program pulse on-time 100 300 – s

Pulse Rise Time tr V

PL to VPH or VPP – – 11 s

Pulse Fall Time tf V

PH or VPP to VPL – – 5 s

1Programming voltages are measured at pin 1 (VCC) of the SIP. A minimum capacitance of 0.1 F must be connected from VCC to GND of the SIP to

provide the current necessary to blow the fuse.

2Testing is the only method that guarantees successful programming.

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

Program Enable To program the device, a keying sequence

is used to activate / enable the programming mode as shown in

figure 4. This program key sequence consisting of a VPP pulse, at

least seven VPH pulses, and a VPP pulse with no supply interrup-

tions. The sequence is designed to prevent the device from being

programmed accidentally (e.g., as a result of noise on the supply

line).

Code Programming After the desired switchpoint code is

selected (0 through 127), each bit of the corresponding binary

address should be programmed individually, not at the same

time. For example, to program code 5 (binary 000101), bits 1 and

3 need to be programmed. A bit is programmed by addressing

the code and then applying a VPP pulse, the programming is not

reversible. An appropriate sequence for blowing code 5 is shown

in figure 5.

Polarity Bit Programming If the desired switchpoint has

negative polarity, the polarity bit must be programmed. To do this

it is necessary to first apply the polarity key sequence before the

program key sequence (figure 6). Finally a VPP pulse of duration

tdP must be applied to program this bit, the programming is not

reversible. The polarity bit is for adjusting programming range

only and will not affect the output polarity.

d(1)

d(0)

PROGRAM ENABLE

7 or More Pulses

(8 Pulses Shown)

Figure 4. Program Enable Pulse Sequence

Figure 5. Code Programming Example

Program Enable

d(1)

d(0)

Polarity

Key

Polarity Bit

Program

Figure 6. Polarity Bit Programming

Program Enable

Bit 1 Address

Bit 1 Program

Bit 3 Address

000100

Code 4

Bit 3 Program

Program Enable

d(1)

d(0)

000001

Code 1

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

Lock-Bit Programming After the desired code is programmed, the

lock bit (code 128), can be programmed (figure 7) to prevent further

programming of the device. Again, programming is not reversible.

See Allegro website at http://www.allegromicro.com for extensive

information on device programming as well as programming

products. Programming hardware is available for purchase and

programming software is available for free.

Figure 7. Lock -Bit Programming Pulse Sequence

VPH

VPP

Program Enable

VPL

td(1) td(1) td(0) tdP

Lock Bit

Address

128 Pulses

Lock Bit

Program

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

For applications it is strongly recommended that an external

ceramic bypass capacitor in the range of 0.01 μF to 0.1 μF be

connected between the supply and ground of the device to reduce

both external noise and noise generated by the chopper-stabi-

lization technique. (The diagram below shows a 0.1 μF bypass

capacitor.)

The series resistor RS in combination with the bypass capacitor

creates a filter for EMC pulses. The series resistor will have a

drop of approximately 800 mV, this must be considered for the

minimum VCC requirement of the ATS636LSE. The small capaci-

tor on the output of the device improves the EMC performance

of the device. The pull-up resistor should be chosen to limit the

current through the output transistor; do not exceed the maximum

continuous output current of the device.

Note: This circuit cannot be used to program the device, as the

series resistance is too large, and a minimum capacitance of

0.1 μF must be connected from VCC to GND of the SIP to pro-

vide the current necessary to blow the fuse.

Extensive applications information on magnets and Hall-

effect ICs including chopper stabilization is available in

the Allegro Electronic Data Book CD, or at the website:

http://www.allegromicro.com.

1.2k Ohm

Supply

VCC

100 Ohm

GND

0.1 F

VOUT

ATS636

120 pF

Typical Application:

Typical Application Circuit

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

Power Derating – SE Package

Due to internal power consumption, the junction temperature

of the IC (junction temperature, TJ) is higher than the ambient

environment temperature, TA. To ensure that the device does not

operate above the maximum rated junction temperature use the

following calculations:

ΔT = PD × RθJA

Where:

PD = VCC × ICC

∴ΔT = VCC × ICC × RθJA

Where ΔT denotes the temperature rise resulting from the IC’s

power dissipation.

J = TA + ΔT

θJA = 77°C/W

TJ(max) = 165°C

Typical TJ calculation:

A = 25°C

= 5 V

CC(on) = 5.5 mA

D = VCC × ICC = 5 V × 5.5 mA = 27.5 mW

ΔT = PD × RθJA = 27.5 mW × 77°C/W = 2.0°C

J = TA + ΔT = 25°C + 2.0°C = 27.0°C

Maximum Allowable Power Dissipation Calculation:

J = TA + ΔT

J(max) = 165°C, if TA = 150°C

then:

165 = 150 + ΔT

ΔT = 15°C

ΔT = PD × RθJA (RθJA = 77°C/W)

\ PD(max) = 15°C / 77°C/W = 195 mW at TA = 150°C

Maximum VCC for PD(max) = 111 mW at TA = 150°C

D = VCC × ICC , ICC = 10 mA (max) at 150°C

CC = PD / ICC = 195 mW / 5.5 mA = 35.4 V

500

1000

1500

2000

2500

3000

3500

4000

4500

20 40 60 80 100 120 140 160 180

Temperature (°C)

Power Dissipation, P

(mW)

Power Dissipation versus Ambient Temperature

(RQJA = 77 ºC/W)

2-layer PCB

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

Package SE 4-Pin SIP

1.0 REF

0.9±0.1

1.3±0.1

4.9±0.1

3.3±0.1

10.00±0.05

7.00±0.05

6.23±0.10

11.60±0.10

0.60±0.10

24.65±0.10

0.71±0.10 0.71±0.10

1.60±0.10

1.27±0.10

5.50±0.10

2.00±0.10

1.0 REF

For Reference Only, not for tooling use (reference DWG-9001)

Dimensions in millimeters

243

Dambar removal protrusion (16X)

Metallic protrusion, electrically connected to pin 4 and substrate (both sides)

Thermoplastic Molded Lead Bar for alignment during shipment

Standard Branding Reference View

LLLLLLL

YYWW

NNN

Branded

Face

= Supplier emblem

L = Lot identifier

N = Last three numbers of device part number

Y = Last two digits of year of manufacture

W = Week of manufacture

Branding scale and appearance at supplier discretion

0.38 +0.06

–0.04

Active Area Depth, 0.43 mm

Hall element (not to scale)

Programmable Back Biased Hall-Ef fect

Switch with TPOS Functionality

Allegro MicroSystems, Inc.

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

ATS636LSE

For the latest version of this document, visit our website:

www.allegromicro.com

Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-

mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the

information being relied upon is current.

Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the

failure of that life support device or system, or to affect the safety or effectiveness of that device or system.

The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;

nor for any in fringe ment of patents or other rights of third parties which may result from its use.

Revision History

Revision Revision Date Description of Revision

Rev. 5 January 30, 2012 Update product availability