32K x 8 Reprogrammable Registered PROM
CY7C277
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 9 5 1 3 4 • 408- 943-2600
August 1988 – Re vi sed December 1993
1CY7C277
Features
•Windowed for reprogrammability
•CMOS for optimum speed/power
•High speed
—30-ns address set-up
—15-ns clock to output
•Low power
—660 mW (commercial)
—715 mW (military)
•Program mable address latch enable input
•Programmable synchronous or asynchr onous output
enable
•On-c hip edge-triggered output regist ers
•EPROM technology, 100% programmable
•Slim 3 00-mil, 28-pin plastic or hermeti c DIP
•5V ±10% VCC, commercial and military
•TTL-compatible I/O
•Direct replacement for bipolar PROMs
•Capable of withstanding greater than 2001V static dis-
charge
PROGRAMMABLE
MULTIPLEXER
PROGRAMMABLE
CP/ALEOPTIONS
Logic Block Diagram Pin Configurations
C277-1
1
2
3
4
5
6
7
8
9
10
11
12 16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
VCC
A10
A11
A12
A13
A14
ALE
CP
E/ES
O7
O6
O4
O5
O3
C277-2
12
O0
31
4
5
6
7
8
9
10
32130
1314151617
26
25
24
23
22
21
11
A6
A5
A4
A3
A2
A1
A0
A13
A14
NC
CP
O7
O6
LCC/PLCC (Opaque Only)
A12
ALE
181920
27
28
29
32
15
C277-3
E/ES
A14
A13
A12
A11
A10
A9
A8
8-BIT
1OF128
MUX
A7
A6
A5
A4
A3
A2
A1
A0
E/ES
CP
15-BIT
ADDRESS
TRANSPARENT/
LATCH
256 x 1024
PROGRAMMABLE
ARRAY
8-BIT
EDGE-
TRIGGERED
REGISTER
ROW
DECODER
1OF256
ALE
COLUMN
DECODER
1OF32
ALE
CP
D
C
Q
NC
Top View
DIP/Flatpack
Top View
Y
ADDRESS
X
ADDRESS
O7
O6
O5
O4
O3
O2
O1
O0
Selectio n G uid e
7C277-30 7C277-40 7C277-50
M inimum Addre ss Set -Up Time (n s) 30 40 50
M aximum Clock to Output (ns) 15 20 25
Maximum Operating
Cur rent (mA) Com’l 120 120 120
Mil 130 130
CY7C277
2
Functional Description
The CY7C277 is a hig h-performance 32K word by 8-bit CMOS
PROMs. It is packaged in the slim 28-pin 300-mil package . The
ceramic package may be equipped with an erasure window;
when exposed to UV light, the PROM is erased and can then
be reprogrammed. The memory cells utilize proven EPROM
floating-gate technology and byte-wide algorithms.
The CY7C277 offers the advantages of low power, superior
performance, and high programming yield. The EPROM cell
requires only 12.5V for the supervoltage and low current re-
quirements allow for gang programming. The EPROM cells
allow for each memory location to be 100% tested, as each
loca tion is written into, erased, and repeatedly exercised prior
to encapsulation. Each PROM is also tested for AC perfor-
mance to guarantee that the product will meet DC and AC
specification limits after customer programming.
On the 7C277, the outputs are pipelined through a mas-
ter-slav e register. On the ris ing edge of CP, data is loaded into
the 8-bit edge triggered output register. The E/ES input pro-
vides a programmable bit to select between async hronous an d
synchronous operation. The default condition is asynchro-
nous. When the asynchronous mode is sele cted, the E/ES pin
operates as an asynchronous output enable. If the synchro-
nous mode is selected, the E/ES pin is sampled on t he rising
ed ge of C P to enab le and disa ble the outputs. The 7C27 7 a ls o
provides a programmable bit to enable the Addre ss Lat ch in-
put. If this bit is n ot programmed , the device will ignore the ALE
pin and the address will enter the de vice async hronously. If the
ALE function is selected, the address enters the PROM while
the ALE pin is active, and is captured when ALE is d easserted.
The user may define the polarity of the ALE signal, with the
default being active HIGH.
Maximum Ratings
(Abo ve which the useful life may be impaired. For user guide-
lines, not tested.)
Stora ge Temperature ....................................−65°C to +150°C
Ambient Temperature with
Power Applied.................................................−55°C t o +125°C
Supply Voltage to Ground Potential.................−0.5V to +7.0V
(Pin 24 to Pin 12)
DC Volt ag e A pplied to Outputs
in High Z State.....................................................−0.5V to +7.0V
DC Input Voltag e.................................................−3.0V to +7.0V
DC Program Volta ge (Pins 7, 18, 20)...........................13.0V
UV Erasure...... ..... ..... ..... ....... ..... ..... ....... ..... .7258 W sec/cm2
Static Discharge Voltage...........................................>2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.. .......... ....... .......... ............ ..... .......>200 mA
Operating Range
Range Ambient Temperatur e VCC
Commercial 0°C to +70°C 5V ±10%
Industrial[1] −40°C to +85°C 5V ±10%
Military[2] −55°C to +125°C 5V ±10%
Electrical Characteristics Over the Operating Range[3 , 4]
Parameter
7C277-30 7C277-40, 50
Description Test Condition s Min. Max. Min. Max. Unit
VOH Output HIGH Voltage VCC = Min. , IOH = − 2.0 mA 2.4 2.4 V
VOL Output LOW Voltage VCC = Min. , IOL = 8. 0 mA 0.4 0.4 V
VIH Input HIGH Level Guaranteed Input Logical HI GH
Voltage for All Inputs 2.0 VCC 2.0 VCC V
VIL Input LOW Level Guaranteed Input Logical LOW
Voltage for All Inputs 0.8 0.8 V
IIX Input Leakage Current GND < VIN < VCC −10 +10 −10 +10 µA
VCD Input Clamp Diode Volta ge Note 4
IOZ Output Leakage Current 0 < VOUT < VCC, Output Disabled[5] −40 +40 −40 +40 µA
IOS Output Short Circuit Current VCC = Max., VOUT = 0. 0V[6] −20 −90 −20 −90 mA
ICC Power Supply Cur rent VCC = Max., CS > VIH
IOUT = 0 mA Commercial 120 120 mA
Military 130
VPP Programming Supply Voltage 12 13 12 13 V
IPP Programming Supply Current 50 50 mA
VIHP I nput HIGH Programming Voltage 3.0 3.0 V
VILP I nput LOW Programming Volta ge 0.4 0.4 V
Notes:
1. Contact a Cypress representative for industrial temperature range specifications.
2. TA i s the “i nstant o n” case temper ature.
3. See the last page of this specification for Group A s u bgroup testing information.
4. See “Introduction to CMOS PROMs” in this Book for general information on testing.
5. For devices using the synchronous enable, the device must be clocked after applying thes e voltages to perform this meas urement.
6. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 30 seco nds.
CY7C277
3
Capacitance[4]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C , f = 1 MHz,
VCC = 5.0V 10 pF
COUT Out p ut Capacitance 10 pF
AC Test Loads and Waveforms[4]
3.0V
5V
OUTPUT
R1 500Ω
R2
333Ω
30 pF
INCLUDING
JIG AN D
SCOPE
GND
90%
10%
90%
10%
<5ns <5ns
5V
OUTPUT
R1 500Ω
R2
333Ω
5pF
INCLUDING
JIG AN D
SCOPE
(a) NormalLoad (b) HighZ Load
OUTPUT 2.0V
Equivalent to: THÉ VENIN EQUIVALENT
C277-4 C277-5
ALL INPUT PULSES
(658Ω MIL)
(403Ω MIL) (403Ω MIL)
OUTPUT 1.9V
Commercial Military
C277-6
(658Ω MIL)
C277-7
200Ω250Ω
CY7C277 Switching Characteristics Over the Operat ing Range[3, 4]
7C277-30 7C277-40 7C277-50
Parameter Description Min. Max. Min. Max. Min. Max. Unit
tAL Address Set-Up to ALE Inactive 5 10 10 ns
tLA Address Hold from ALE Inacti ve 10 10 15 ns
tLL ALE Pulse Width 10 10 15 ns
tSA Address Set-Up to Clock HIGH 30 40 50 ns
tHA Address Hold from Clock HIGH 0 0 0 ns
tSES ES Set-Up to Clo ck HIGH 12 15 15 ns
tHES ES Hold from Clock HIGH 5 10 10 ns
tCO Clock HIGH to Output Valid 15 20 25 ns
tPWC Clock Pulse Width 15 20 20 ns
tLZC[7] Output Valid from Clock HIGH 15 20 30 ns
tHZC Output High Z from Clock HIGH 15 20 30 ns
tLZE[8] Output Valid from E LOW 15 20 30 ns
tHZE[8] Output High Z from E HI GH 15 20 30 ns
Notes:
7. Applies only when the synchronous (ES) function is used.
8. Applies only when the asynchronous (E) fun ct ion is us ed.
CY7C277
4
Architecture Byte (8000)
D7 D0
C7C6C5C4 C3 C2 C 1 C0
Architecture Configuration Bits
Architecture Bit Archi tectur e Ver ify D7 - D0Function
ALE D10 = DEFAULT Input Transpar ent
1 = PGMED Input Latche d
ALEP D20 = DEFAULT ALE = Active HIGH
1 = PGMED ALE = Active LOW
E/ESD00 = DEFAULT Asynchronous Output Enable (E)
1 = PGMED Sy nchronous Output Enable (ES)
Bit Map
Programmer Address
(Hex.) RAM Data
0000
.
.
.
7FFF
8000
Data
.
.
.
Data
Cont rol Byte
Notes:
9. ALE is shown wi th positive polarity.
tHZE tLZE
tSES
tSES
tLZC
tHZC
tCO
tHES tHES
HIGHZ HIGHZ
tAL tLA
tLL
tSA tHA
A0-A
14
ALE
ES
(SYNCH)
CP
O0-O
7
E
S
(ASYNCH) C277-8
tPWC
tPWC
Timing Diagram (Input Latched)[9]
tLZE
tHZE
tSES
tHZC
Timing Diagram (Input Transparent)
tSES
tLZC
tCO
tHES tHES
HIGHZ HIGHZ
tSA tHA
A0-A
14
ES
(SYNCH)
CP
O0-O
7
E
S
(ASYNCH) C277-9
tPWC
tPWC
CY7C277
5
Prog ramming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
progra mming information, including a listing of software pack-
ages, please see the PROM Programming Information located
at the end of this section. Programming algorithms can be o b-
tained fr om any Cypress r epresentative.
Table 1. Mode Selection
Pin Function[10]
Read or Output Disable A14 - A0E, ESCP ALE O7 - O0
Mode Other A14 - A 0VFY PGM VPP D7 - D 0
Read A14 - A0VIL VIH VIL O7 - O0
Output Disable A14 - A0VIH X X Hig h Z
Program A14 - A0VIHP VILP VPP D7 - D0
Pro gram Veri fy A14 - A0VILP VIHP/VILP VPP O7 - O0
Program Inhibit A14 - A0VIHP VIHP VPP Hig h Z
Blank Check A14 - A0VILP VIHP/VILP VPP O7 - O0
Notes:
10. X = “don’t care” but not to exceed VCC ±5%.
Figure 1. Programm ing Pi n outs
1
2
3
4
5
6
7
8
9
10
11
12 16
17
18
19
20
24
23
22
21
13
14
25
28
27
26
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
VCC
A10
A11
A12
A13
A14
VPP
PGM
VFY
D7
D6
D4
D5
D3
C277-10
C277-11
12
D0
31
4
5
6
7
8
9
10
32130
1314151617
26
25
24
23
22
21
11
A6
A5
A4
A3
A2
A1
A0PGM
NC
D7
D6
VFY
181920
27
28
29
32
NC
15
VPP
DIP LCC/PLCC (Opaque Onl y)
Top View Top View
A12
A13
A14
CY7C277
6
Typical DC and AC Characteristics
1.4
1.6
1.0
0.8
4.0 4.5 5.0 5.5 6.0 −55 25 125
1.2
1.1
SUPPLYVOLTAGE (V)
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEM PERATURE
AMBIENTTEMPERATURE (°C)
0.6
1.2
150
175
125
75
50
25
0.0 1.0 2.0 3.0
0
100
OUTPUT VOLTAGE (V)
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
1.0
0.9
0.8
VCC =5.0V
TA=25°C
60
50
40
30
20
10
0 1.0 2.0 3.0
OUTPUT VOLTAGE (V)
30.0
25.0
20.0
15.0
10.0
5.0
0 200 400 600 800
CAPACITANCE (pF)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADIN G
4.0 0.0 1000
TA=25°C
VCC =4.5V
TA=25°C
f= f
MAX
0
OUTPUT SOURCE CURRENT
vs. V OLTAG E
4.0
1.6
1.4
1.2
1.0
0.8
−55 125
0.6 25
AMBIENT TEMPERATURE (°C)
NORMALIZED SET-UP TIME
vs. TEM PERATURE
1.2
4.0 4.5 5.0 5.5 6.0
0.4
SUPPLYVOLTAGE (V)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
TA=25°C
1.0
0.8
0.6
C277-12
CY7C277
7
MIL ITARY SPECIFICATION S
Group A Subgroup Testing
Document #: 38-00085-E
Orde rin g Inf orm a tio n[11]
Speed
(ns) O rdering Code Package
Name Package Type Operating
Range
30 CY7C277-30JC J65 32-Lead Pl ast ic Leaded Chip Carrier Commercial
CY7C277-30PC P21 28-L ead (300-Mil) Molded DIP
CY7C277-30WC W22 28-Lead (300-Mil) Windowed CerDIP
40 CY7C277-40JC J65 32-Lead Pl ast ic Leaded Chip Carrier Commercial
CY7C277-40PC P21 28-L ead (300-Mil) Molded DIP
CY7C277-40WC W22 28-Lead (300-Mil) Windowed CerDIP
CY7C277-40DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C277-40KMB K74 28-Lead Rectangular Cerpack
CY7C277-40LMB L55 32-Pin Rectangular Leadless Chip Carrier
CY7C277-40QMB Q55 32-Pin Win dowed Rec tan gular Leadless Chip Carrier
CY7C277-40TMB T74 28-Lead Windowed Cerpack
CY7C277-40WMB W22 28-Lead ( 300-Mil) Windowed CerDIP
50 CY7C277-50JC J65 32-Lead Pl ast ic Leaded Chip Carrier Commercial
CY7C277-50PC P21 28-L ead (300-Mil) Molded DIP
CY7C277-50WC W22 28-Lead (300-Mil) Windowed CerDIP
CY7C277-50DMB D22 28-Lead (300-Mil) CerDIP Military
CY7C277-50KMB K74 28-Lead Rectangular Cerpack
CY7C277-50LMB L55 32-Pin Rectangular Leadless Chip Carrier
CY7C277-50QMB Q55 32-Pin Win dowed Rec tan gular Leadless Chip Carrier
CY7C277-50TMB T74 28-Lead Windowed Cerpack
CY7C277-50WMB W22 28-Lead ( 300-Mil) Windowed CerDIP
Notes:
11. Most of the above products are available in industrial temperature range. Contact a Cypress representative for specifications and product
availability.
DC Characteristics
Parameter Subgroups
VOH 1, 2, 3
VOL 1, 2, 3
VIH 1, 2, 3
VIL 1, 2, 3
IIX 1, 2, 3
IOZ 1, 2, 3
ICC 1, 2, 3
Switching Characteristics
Parameter Subgroups
tSA 7, 8, 9, 10, 11
tHA 7, 8, 9, 10, 11
tCO 7, 8, 9, 10, 11
CY7C277
8
Package Diagrams
28-Lead (300-Mil) CerDIPD22
MIL-STD-1835 D-15 Config.A 32-Lead Plastic Leaded Chip Carrier J65
28-Lead Rectangular Cerpack K74
MIL-STD-1835 F-11 Con fig .A 32-Pin Rectangular Leadless ChipCarrier L55
MIL-STD-1835 C-12
CY7C277
9
Package Diagrams (Continued)
28-Lead (300-Mil) Molded DIP P21
32-Pin Windowed Rectangular Leadless Chip Carrier Q55
MIL-STD-1835 C-12
CY7C277
© Cypress Semiconductor Corporation, 1993. T h e information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry othe r than circui try embodi ed in a Cypress Semi conductor prod uct. Nor does it convey or im ply an y li cense under patent o r other rights . Cypress Semi conductor does not authori ze
its products for use a s criti cal components in life-support systems where a malfunction or failure may re a sonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufactur er assumes all risk of su ch use and in doing so indemnifies Cypr ess Semiconductor against all charges.
Package Diagrams (Continued)
28-Lead Windowed Cerpack T74
28-Lead (300-Mil) Windowed CerDIP W22
MIL-STD-1835 D-15 Config.A
