STP20NE06L STP20NE06LFP N - CHANNEL 60V - 0.06 - 20A TO-220/TO-220FP STripFET POWER MOSFET TYPE V DSS R DS( on ) ID STP20NE06L STP20NE06LF P 60 V 60 V < 0.07 < 0.07 20 A 13 A TYPICAL RDS(on) = 0.06 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW GATE CHARGE 100 oC APPLICATION ORIENTED CHARACTERIZATION 3 1 DESCRIPTION This Power Mosfet is the latest development of STMicroelectronics unique " Single Feature Size " strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalance characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. 3 2 1 TO-220 2 TO-220FP INTERNAL SCHEMATIC DIAGRAM APPLICATIONS DC MOTOR CONTROL DC-DC & DC-AC CONVERTERS SYNCHRONOUS RECTIFICATION ABSOLUTE MAXIMUM RATINGS Symb ol Parameter Value STP20NE06 V DS V DGR V GS Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) G ate-source Voltage o Unit ST P20NE06F P 60 V 60 V 20 V ID Drain Current (continuous) at Tc = 25 C 20 13 A ID o 14 9 A I DM (*) P tot Drain Current (continuous) at Tc = 100 C Drain Current (pulsed) 80 80 A T otal Dissipation at Tc = 25 oC 70 30 W 0.47 0.2 W /o C 2000 V Derating Factor V ISO Insulation W ithstand Voltage (DC) dv/dt Peak Diode Recovery voltage slope T s tg Storage T emperature Tj Max. O perating Junct ion T emperature (*) Pulse width limited by safe operating area April 1999 7 V/ns -65 to 175 o C 175 o C ( 1) ISD 20 A, di/dt 300 A/s, VDD V(BR)DSS, Tj TJMAX 1/9 STP20NE06L/FP THERMAL DATA R thj -case R thj -amb R thc-sink Tl Thermal Resistance Junction-case TO-220 TO-220FP 2.14 5 Max Thermal Resistance Junction-ambient Max Thermal Resistance Case-sink Typ Maximum Lead Temperature F or Soldering Purpose 62.5 0.5 300 o C/W o C/W C/W o C o AVALANCHE CHARACTERISTICS Symbo l Parameter Max Value Unit IAR Avalanche Current, Repetitive or Not-Repetitive (pulse width limited by Tj max) 20 A E AS Single Pulse Avalanche Energy (starting Tj = 25 o C, ID = IAR , V DD = 35 V) 100 mJ ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbo l V (BR)DSS Parameter Drain-source Breakdown Voltage Test Con ditions I D = 250 A V GS = 0 I DSS V DS = Max Rating Zero Gate Voltage Drain Current (V GS = 0) V DS = Max Rating IGSS Gate-body Leakage Current (VDS = 0) Min. Typ. Max. 60 Unit V 1 10 A A 100 nA Typ. Max. Unit 0.07 0.06 0.085 0.07 T c = 125 oC V GS = 20 V ON () Symbo l V GS(th) Parameter Test Con ditions ID = 250 A Gate Threshold Voltage V DS = V GS R DS(on) Static Drain-source On Resistance V GS = 5 V V GS = 10 V I D(o n) On State Drain Current V DS > ID(o n) x R DS(on )ma x V GS = 10 V Min. 1 I D = 10 A ID = 10 A V 20 A DYNAMIC Symbo l g f s () C iss C os s C rss 2/9 Parameter Test Con ditions Forward Transconductance V DS > ID(o n) x R DS(on )ma x Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS = 25 V f = 1 MHz I D =10 A V GS = 0 Min. Typ. Max. Unit 5 9 S 800 125 40 pF pF pF STP20NE06L/FP ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbo l Parameter Test Con ditions Min. Typ. Max. Unit t d(on) tr Turn-on Delay T ime Rise Time V DD = 30 V I D = 10 A R G =4.7 W VGS = 5 V (see test circuit, figure 3) 20 45 Qg Q gs Q gd Total G ate Charge Gate-Source Charge Gate-Drain Charge V DD = 48 V 14 8 4 20 nC nC nC Typ. Max. Unit I D = 20 A V GS = 5 V ns ns SWITCHING OFF Symbo l tr (Voff) tf tc Parameter Off-voltage Rise T ime Fall T ime Cross-over Time Test Con ditions Min. 10 25 42 V DD = 48 V I D = 20 A R G =4.7 V GS = 5 V (see test circuit, figure 5) ns ns ns SOURCE DRAIN DIODE Symbo l ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Test Con ditions Min. Typ. Max. Unit 20 80 A A Source-drain Current Source-drain Current (pulsed) Forward On Voltage I SD = 20 A Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 20 A di/dt = 100 A/s o Tj = 150 C V DD = 30 V (see test circuit, figure 5) V GS = 0 1.5 V 65 ns 130 nC 4 A () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area Safe Operating Area for TO-220 Safe Operating Area for TO-220FP 3/9 STP20NE06L/FP Thermal Impedance for TO-220 Thermal Impedance forTO-220FP Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance 4/9 STP20NE06L/FP Gate Charge vs Gate-source Voltage Capacitance Variations Normalized Gate Threshold Voltage vs Temperature Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics 5/9 STP20NE06L/FP Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/9 STP20NE06L/FP TO-220 MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.40 4.60 0.173 0.181 C 1.23 1.32 0.048 0.051 D 2.40 2.72 0.094 0.107 D1 1.27 0.050 E 0.49 0.70 0.019 0.027 F 0.61 0.88 0.024 0.034 F1 1.14 1.70 0.044 0.067 F2 1.14 1.70 0.044 0.067 G 4.95 5.15 0.194 0.203 G1 2.4 2.7 0.094 0.106 H2 10.0 10.40 0.393 0.409 14.0 0.511 L2 16.4 L4 0.645 13.0 0.551 2.65 2.95 0.104 0.116 L6 15.25 15.75 0.600 0.620 L7 6.2 6.6 0.244 0.260 L9 3.5 3.93 0.137 0.154 DIA. 3.75 3.85 0.147 0.151 D1 C D A E L5 H2 G G1 F1 L2 F2 F Dia. L5 L9 L7 L6 L4 P011C 7/9 STP20NE06L/FP TO-220FP MECHANICAL DATA mm DIM. MIN. inch TYP. MAX. MIN. TYP. MAX. A 4.4 4.6 0.173 0.181 B 2.5 2.7 0.098 0.106 D 2.5 2.75 0.098 0.108 E 0.45 0.7 0.017 0.027 F 0.75 1 0.030 0.039 F1 1.15 1.7 0.045 0.067 F2 1.15 1.7 0.045 0.067 G 4.95 5.2 0.195 0.204 G1 2.4 2.7 0.094 0.106 H 10 10.4 0.393 0.409 L2 16 L3 0.630 28.6 30.6 1.126 1.204 9.8 10.6 0.385 0.417 L6 15.9 16.4 0.626 0.645 L7 9 9.3 0.354 0.366 O 3 3.2 0.118 0.126 B D A E L4 L3 L6 F F1 L7 F2 H G G1 1 2 3 L2 8/9 L4 STP20NE06L/FP Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibil ity for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specific ation mentioned in this publication are subjec t to change without notice. This publication supersedes and replaces all information previously supplied. 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