UPD78F9468GB-8ET-A - NEC - Datasheet.Live

The information contained in this document is being issued in advance of the production cycle for the

device. The parameters for the device may change before final production or NEC Corporation, at its own

discretion, may withdraw the device prior to its production.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

MOS INTEGRATED CIRCUIT

µµ

PD78F9468

8-BIT SINGLE-CHIP MICROCONTROLLER

Document No. U14558EJ1V0PM00 (1st edition)

Date Published February 2000 N CP(K)

Printed in Japan

PRELIMINARY PRODUCT INFORMATION

2000

The

PD78F9468 is a

PD789467 Subseries (designed for remote controller with on-chip LCD) product in the

78K/0S Series, featuring expanded flash memory in place of the internal ROM of the

PD789462, 789464, 789466,

and 789467.

Because flash memory allows the program to be written and erased with the device mounted on the target board,

this product is ideal for development trials, small-scale production, or for applications that require frequent upgrades.

Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before

designing.

µµ

PD789327, 789467 Subseries User’s Manual: To be prepared

78K/0S Series User’s Manual Instructions: U11047E

FEATURES

• Pin-compatible with mask ROM product (except VPP)

• Fl ash memory: 32 KB

• Internal high-speed RAM: 512 bytes

• LCD display RAM: 24 bytes

• Variable minimum instruction execution time: High speed (0.4

s: @5.0 MHz operation with main system clock),

low speed (1.6

s: @5.0 MHz operation with main system clock), and ultra low speed (122

s: @32.768 kHz

operation with subsystem clock)

• I/O ports: 18

• 8-bit resolution A/D converter: 1 channel

• LCD controller/driver

Segment signals: 23

Common signals: 4

• Timer: 4 channels

• Supply voltage: VDD = 1.8 to 5.5 V

APPLICATIONS

Remote-control devices, healthcare equipment, etc.

ORDERING INFORMATION

Part Number Package

PD78F9468GB-8ET 52-pin plastic LQFP (10 mm × 10 mm)

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

78K/0S SERIES LINEUP

The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.

Products under development

Products in mass production

PD789014

42/44-pin

Small-scale package, general-purpose applications

PD789146

PD789156

44-pin

78K/0S

Series

44/48-pin

Small-scale package, general-purpose applications + A/D

28-pin

44-pin

PD789026

44-pin

µµ

PD789046

PD789014 with enhanced timer and expanded ROM, RAM

On-chip UART. Capable of low-voltage (1.8 V) operation

PD789026 with internal subsystem clock

30-pin

PD789124A

PD789134A

PD789177

PD789167

30-pin

PD789104A

PD789114A

RC oscillation version of the PD789197AY

PD789177 with on-chip EEPROM

PD789167 with enhanced A/D converter

PD789104A with enhanced timer

PD789124A with enhanced A/D converter

RC oscillation version of the PD789104A

PD789104A with enhanced A/D converter

PD789026 with added A/D and multiplier

PD789104A with EEPROM

PD789146 with enhanced A/D converter

LCD drive

Inverter control

44-pin

PD789842 On-chip inverter controller and UART

88-pin

PD789830

Dot LCD drive

144-pin

PD789835 Segment: 40, common: 16

Segment/common outputs: 96

80-pin

PD789446

PD789456

PD789436

PD789417A

PD789407A

PD789426

PD789306

PD789316

PD789426 with enhanced A/D converter

PD789446 with enhanced A/D converter

PD789456 with enhanced I/O

RC oscillation version of the PD789426

PD789407A with enhanced A/D converter

PD789306 with A/D converter

RC oscillation version of the PD789306

Basic subseries for LCD drive

64-pin

20-pin

44-pin

ASSP

44-pin

64-pin

20-pin For keyless entry, on-chip POC and key return circuit

For key pad, on-chip POC

For PC keyboard, on-chip USB function

For remote-controller. On-chip LCD controller/driver.

PD789327 with A/D converter

RC oscillation version of the PD789860

PD789177Y

PD789167Y

PD789

217AY

PD789

197AY

Y subseries products support SMB.

µµµµ

µµµµµµµ

µµµµµµµµ

PD789860

PD789861

µµ

µµµµµµ

µµ

µµµ

µµ

PD789840

PD789327

PD789467

PD789800

µµµµ

Preliminary Product Information U14558EJ1V0PM00 3

µµ

PD78F9468

The major functional differences among the subseries are listed below.

TimerFunction

Subseries Name

ROM

Capacity 8-Bit 16-Bit Watch WDT

8-Bit

A/D 10-Bit

A/D Serial Interface I/O VDD Min.

Value Remarks

PD789046 16 K 1 ch

PD789026 4 K to 16 K

1 ch 1 ch 34

Small-scale

package,

general-

purpose

applications

PD789014 2 K to 4 K 2 ch −

−

−−

1 ch (UART: 1 c h)

−

PD789177 −8 ch

PD789167

16 K to 24 K 3 ch 1 ch

8 ch −

31 −

PD789156 −4 ch

PD789146

8 K to 16 K

4 ch −

On-chip

EEPROM

PD789134A −4 ch

PD789124A

4 ch −

RC oscillation

version

PD789114A

−4 ch

Small-scale

package,

general-

purpose

applications

+ A/D

PD789104A

2 K to 8 K

1 ch

−

1 ch

4 ch −

1 ch (UART: 1 c h)

1.8 V

−

Inverter

control

PD789842 8 K t o 16 K 3 ch Note 1 ch 1 ch 8 ch −1 ch (UART: 1 ch) 30 4.0 V −

PD789417A −7 ch

PD789407A

12 K to 24 K 3 ch

7 ch −

PD789456 −6 ch

PD789446 6 ch −

PD789436 −6 ch

PD789426

12 K to 16 K

6 ch

1 ch (UART: 1 ch)

−

PD789316 RC oscillation

version

LCD drive

PD789306

8 K to 16 K

2 ch

1 ch 1 ch 1 ch

−

2 ch (UART: 1 ch) 23

1.8 V

−

PD789835 24 K t o 60 K 6 ch – 3 ch 28 1.8 VDot LCD

drive

PD789830 24 K 1 ch 1 ch

1 ch 1 ch

–

−1 ch (UART: 1 ch)

30 2.7 V

−

PD789467 2 ch 1 ch –

PD789327

4 K to 24 K

3 ch

– 1 ch 1 ch

–1 ch

18 1.8 V On-chip LCD

PD789800 −2 ch (USB: 1 ch) 31 4.0 V

PD789840

8 K 1 ch

4 ch 1 ch 29 2.8 V

−

PD789861 RC oscillation

version, on-chip

EEPROM

ASSP

PD789860

4 K

2 ch

−

−1 ch

−

–

−14 1.8 V

On-chip

EEPROM

Note 10-bit timer: 1 channel

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

OVERVIEW OF FUNCTIONS

Item Description

Flash memory 32 KB

High-speed RAM 512 bytes

Internal memory

LCD display RAM 24 bytes

Main system clock

(oscillati on f requency) Ceramic/ crystal resonat or (1.0 to 5.0 M Hz)

Subsystem clock

(oscillati on f requency) Cryst al res onator (32.768 kHz)

0.4

s/1.6

s (@5.0 MHz operation wit h m ai n system clock)Minimum i nstruction exec ution tim e

122

s (@32.768 k Hz operation with subsystem clock)

General-purpose regis ters 8 bits × 8 regi sters

Instruction set •16-bit operati ons

• Bit m ani pul at i on (set, reset, test) etc.

I/O ports Total: 18

CMOS I/O: 18

Timers • 8-bit tim er: 2 channels

•Watch ti mer: 1 channel

• Watchdog ti mer: 1 channel

Timer outputs 1

A/D c onverter 8-bit resolut i on × 1 channel

LCD controll e r/ driver • Segment s i gnal outputs: 23

•Common signal outputs: 4

Maskabl e Internal: 6, External: 2Vectored i nterrupt

sources Non-maskable Internal: 1

Reset • Reset by RESET signal input

•Internal res et by watchdog tim er

• Reset v i a power-on-clear circuit

Supply v ol tage VDD = 1.8 to 5.5 V

Operating ambient temperat ure TA = −40 to +85°C

Package 52-pin plastic LQFP (10 mm × 10 m m )

Preliminary Product Information U14558EJ1V0PM00 5

µµ

PD78F9468

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 7

2. BLOCK DIAGRAM................................................................................................................................ 8

3. PIN FUNCTIONS................................................................................................................................... 9

3.1 Port Pins....................................................................................................................................... 9

3.2 Non-Port Pins............................................................................................................................. 10

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................ 11

4. CPU ARCHITECTURE........................................................................................................................ 13

4.1 Memory Space........................................................................................................................... 13

4.2 Data Memory Addressing......................................................................................................... 14

4.3 Processor Registers.................................................................................................................. 15

5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 19

5.1 Ports ............................................................................................................................................. 19

5.2 Clock Generator......................................................................................................................... 25

5.3 8-Bit Timer 30, 40....................................................................................................................... 30

5.4 Watch Timer............................................................................................................................... 40

5.5 Watchdog Timer ........................................................................................................................ 43

5.6 A/D Converter ............................................................................................................................ 45

5.7 LCD Controller/Driver................................................................................................................ 49

6. INTERRUPT FUNCTION..................................................................................................................... 55

6.1 Interrupt Types .......................................................................................................................... 55

6.2 Interrupt Sources and Configuration ...................................................................................... 55

6.3 Interrupt Function Control Registers...................................................................................... 58

7. STANDBY FUNCTION........................................................................................................................ 64

7.1 Standby Function...................................................................................................................... 64

7.2 Standby Function Control Register......................................................................................... 66

8. RESET FUNCTION ............................................................................................................................. 67

8.1 Reset Function .......................................................................................................................... 67

8.2 Power Failure Detection Function........................................................................................... 69

9. FLASH MEMORY PROGRAMMING .................................................................................................70

9.1 Selection of Communication Mode ......................................................................................... 70

9.2 Flash Memory Programming Functions.................................................................................. 71

9.3 Flashpro III Connection Example............................................................................................. 71

9.4 Setting Example Using Flashpro III (PG-FP3)......................................................................... 72

10. INSTRUCTION SET OVERVIEW..................................................................................................... 73

10.1 Conventions............................................................................................................................... 73

10.2 Operations.................................................................................................................................. 75

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

11. ELECTRICAL SPECIFICATIONS.....................................................................................................80

APPENDIX A. DIFFERENCES BETWEEN

µµ

PD78F9468 AND MASK ROM VERSIONS............... 89

APPENDIX B. DEVELOPMENT TOOLS ...............................................................................................90

APPENDIX C. RELATED DOCUMENTS...............................................................................................92

Preliminary Product Information U14558EJ1V0PM00 7

µµ

PD78F9468

1. PIN CONFIGURATION (TOP VIEW)

52-pin plastic LQFP (10 mm ×

××

× 10 mm)

µµ

PD78F9468GB-8ET

RESET

P60/TO40

P43/KR03

P42/KR02

P41/KR01

P40/KR00

P03

P02

P01

P00

INT/ANI0/P61

XT2

XT1

LC2

CAPL

CAPH

LC1

52 51 50 49 48 47 46 45 44 43 42

14 15 16 17 18 19 20 21 21 23 24

P11

P10

P81/S21

P82/S20

P83/S19

P84/S18

P85/S17

S16

S15

S14

S13

S12

S11

S10

COM0

COM1

COM2

COM3

LC0

P80/S22

13 28

41 40

25 26

Caution In normal operation mode, directly connect the VPP pin to VSS.

ANI0: Analog Input RESET: Reset

CAPH, CAPL: LCD Power Supply Capacitance Control S0 to S22: Segment Output

COM0 to COM3: Common Output TO40: Timer Output

INT: Interrupt from Peripherals VDD: Power Supply

KR00 to KR03: Key Return VLC0 to VLC2: Power Supply for LCD

P00 to P03: Port 0 VPP: Programming Power Supply

P10, P11: Port 1 VSS: Ground

P40 to P43: Port 4 X1, X2: Crystal (Main system clock)

P60, P61: Port 6 XT1, XT2: Crystal (Subsystem clock)

P80 to P85: Port 8

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

2. BLOCK DIAGRAM

78K/0S

CPU core

Flash

memory

8-bit

timer

P00 to P03

Port 0

P10, P11

Port 1

Port 4 P40 to P43

Port 6 P60, P61

Port 8

Watchdog

timer

S0 to S22

COM0 to COM3

RAM

RAM space

for LCD

data

8-bit

timer

Cascaded

16-bit

timer

A/D converter

ANI0/INT/P61

LC0

LCD

controller

driver

System

control

RESET

XT1

XT2

Interrupt

control KR00/P40 to

KR03/P43

INT/ANI0/P61

P80 to P85

Watch

timer

TO40/P60

Power-on clear

LC1

LC2

CAPH

CAPL

Preliminary Product Information U14558EJ1V0PM00 9

µµ

PD78F9468

3. PIN FUNCTIONS

3.1 Port Pins

Pin Name I/O Function After Reset Alternat e Function

P00 to P03 I/O Port 0.

4-bit I/O port.

Input/output can be specif i ed i n 1-bi t units .

When used as an input port, on-chip pull-up res i stors can be

specified for t he whol e port using pull-up resis tor option

Input −

P10, P11 I/O Port 1.

2-bit I/O port.

Input/output can be specif i ed i n 1-bi t units .

When used as an input port, on-chip pull-up res i stors can be

specified for t he whol e port using pull-up resis tor option

Input −

P40 to P43 I/O Port 4.

4-bit I/O port.

Input/output can be specif i ed i n 1-bi t units .

When used as an input port, on-chip pull-up res i stors can be

specified for t he whol e port using pull-up resist or option

Input KR00 to KR03

P60 TO40

P61

I/O Port 6.

2-bit I/O port.

Input/output can be specif i ed i n 1-bi t units .

Input

INT/ANI0

P80 to P85 I/O Port 8.

6-bit I/O port.

Input/output can be specif i ed i n 1-bi t units .

Low-level

output S22 to S17

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

3.2 Non-Port Pins

Pin Name I/O Function After Reset Alternat e Function

INT Input External i nterrupt input for which t he valid edge (rising edge,

falling edge, or both ris i ng and falling edges) can be s pecified. Input P61/ANI0

KR00 to KR03 Input Key ret urn signal det ec tion Input P40 to P43

TO40 Output 8-bit t i m er 40 output Input P60

ANI0 Input A/D converter analog i nput Input P61/INT

S0 to S16 −

S17 to S22

Output LCD control l er/driver s egm ent signal out puts Low-level

output P85 to P80

COM0 to COM3 Output LCD control l er/driver c om m on signal out put s Low-level

output −

VLC0 to VLC2 −LCD drive voltage −−

CAPH, CAPL −Voltage am pl i f i er capacit or for LCD drive connecti on pi ns −−

X1 Input −−

X2 −

Connecting crystal resonat or for main system clock oscillation

−−

XT1 Input −−

XT2 −

Connecting crystal resonat or for subsystem clock oscillation

−−

RESET Input System reset input Input −

VDD −Posit i ve power supply −−

VSS −Ground potential −−

VPP −Flash memory programming mode setting.

High-volt age appl i cation f or program wri te/veri fy.

In normal operat i on m ode, connect direct l y to VSS.

−−

Preliminary Product Information U14558EJ1V0PM00 11

µµ

PD78F9468

3.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins is shown in Table 3-1.

For the input/output circuit configuration of each type, refer to Figure 3-1.

Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins

Pin Name I/O Circuit Ty pe I / O Recommend Connec tion of Unus ed Pins

P00 to P03

P10, P11

5-A I/O

P40/KR00 t o P43/KR03 8-A

P60/TO40 5

Input: Independently connect to VDD or VSS via a resistor.

Output: Leave open.

P61/INT/ANI0 8 Input: Independently connect to VSS via a resistor.

Output: Leave open.

P80/S22 to P85/S 17 17-G Input: Independently connect to VDD or VSS via a resistor.

Output: Leave open.

S0 to S16 17-D

COM0 to COM3 18-B

Output

CAPH, CAPL

VLC0 to VLC2

−

Leave open.

XT1 Input Connect to VSS.

XT2

−

−Leave open.

RESET 2 Input −

VPP −−

Connect directly to VSS.

Figure 3-1. I/O Circuit Types (1/2)

Type 2 Type 5

Schmitt-triggered input with hysteresis characteristics.

P-ch

IN/OUT

Data

Output

disable

Input

enable

N-ch

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

Figure 3-1. I/O Circuit Types (2/2)

Type 5-A Type 8

Pull-up

enable

P-ch

IN/OUT

Data

Output

disable

Input

enable

N-ch

Data

P-ch

Output

disable

IN/OUT

N-ch

Type 8-A Type 17-D

Pull-up

enable

P-ch

Data

P-ch

Output

disable

IN/OUT

N-ch

P-ch

N-ch

P-ch

N-ch

data OUT

VLC0

VLC3

SEG

VLC2

P-ch

VSS

Type 17-G Type 18-B

P-ch

N-ch

P-ch

N-ch

data

LC0

VLC1

SEG

VLC2

P-ch

IN/OUT

Data

Output

disable

Input

enable

VDD

N-ch

VSS

P-ch

N-ch

P-ch

N-ch

P-ch

N-ch P-ch

N-ch

data

P-ch N-ch

LC1

LC0

LC2

OUT

COM

Preliminary Product Information U14558EJ1V0PM00 13

µµ

PD78F9468

4. CPU ARCHITECTURE

4.1 Memory Space

The

PD78F9468 is provided with 64 KB of accessible memory space. Figure 4-1 shows the memory map.

Figure 4-1. Memory Map

8 0 0 0 H

7 F F F H

Special function registers

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

LCD display RAM

23 × 8 bits

F F F F H

F F 0 0 H

F E F F H

F D 0 0 H

F C F F H

0 0 0 0 H

Program

memory space

Data memory

space

7 F F F H

0 0 0 0 H

Program area

0 0 8 0 H

0 0 7 F H

Program area

0 0 4 0 H

0 0 3 F H

CALLT table area

Reserved

0 0 1 4 H

0 0 1 3 H

Vector table area

Flash memory

32 K × 8 bits

F A 1 7 H

F A 1 6 H

F A 0 0 H

F 9 F F H

Reserved

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

4.2 Data Memory Addressing

The

PD78F9468 is provided with a variety of addressing modes to improve the operability of the memory. In the

area that incorporates data memory (FD00H to FFFFH) in particular, specific addressing modes that correspond to

the particular functions of an area, such as the special function registers (SFRs), are available. Figure 4-2 shows the

data memory addressing modes.

Figure 4-2. Data Memory Addressing Modes

Special function registers (SFRs)

256 × 8 bits

Internal high-speed RAM

512 × 8 bits

LCD display RAM

23 × 8 bits

Flash memory

32 K × 8 bits

F F F F H

8 0 0 0 H

7 F F F H

0 0 0 0 H

Direct addressing

addressing

Based addressing

F F 0 0 H

F E F F H

F F 2 0 H

F F 1 F H

F E 2 0 H

F E 1 F H

SFR addressing

Short direct

addressing

F D 0 0 H

F C F F H

F A 1 7 H

F A 1 6 H

Reserved

F A 0 0 H

F 9 F F H

Reserved

Preliminary Product Information U14558EJ1V0PM00 15

µµ

PD78F9468

4.3 Processor Registers

4.3.1 Control registers

(1) Program counter (PC)

The PC is a 16-bit register that holds the address information of the next program to be executed.

Figure 4-3. Program Counter Configuration

015

PC14PC15PC PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The PSW is an 8-bit register that indicates the status of the CPU according to the results of instruction execution.

Figure 4-4. Program Status Word Configuration

IE Z 0 AC 0 0 1 CY

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledgement of the CPU.

(b) Zero flag (Z)

This flag is set (1) if the result of an operation is zero; otherwise it is reset (0).

AC is set (1) if the result of the operation has a carry from bit 3 or a borrow at bit 3; otherwise it is reset (0).

(d) Carry flag (CY)

CY is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or

add instruction.

(3) Stack pointer (SP)

The SP is a 16-bit register that holds the start address of the stack area. Only the internal RAM area (FD00H to

FEFFH) can be specified as the stack area.

Figure 4-5. Stack Pointer Configuration

015

SP14SP15SP SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

Caution RESET input makes the SP contents undefined, so be sure to initialize the SP before instruction

execution.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

4.3.2 General-purpose registers

The

PD78F9468 has eight 8-bit general-purpose registers (X, A, C, B, E, D, L, and H).

These registers can be used either singly as 8-bit registers or in pairs as 16-bit registers (AX, BC, DE, and HL),

and can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names

(R0 to R7 and RP0 to RP3).

Figure 4-6. General-Purpose Register Configuration

(a) Absolute register names

8-bit processing

RP3

RP2

RP1

RP0

16-bit processing

15 0

(b) Functional register names

8-bit processing

16-bit processing

15 0

Preliminary Product Information U14558EJ1V0PM00 17

µµ

PD78F9468

4.3.3 Special function registers (SFRs)

Special function registers are used as peripheral hardware mode registers and control registers, and are mapped

in the 256-byte space from FF00H to FFFFH.

Note that the bit number of a bit name that is a reserved word in the RA78K0S and defined under the header file

“sfrbit.h” in the CC78K0S appears enclosed in a circle in the register formats. Refer to the register formats in 5.

PERIPHERAL HARDWARE FUNCTIONS.

Table 4-1. Special Function Registers (1/2)

Bit Unit for Mani pul at i onAddress Special Func tion Regis t er (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

After

Reset

FF00H Port 0 P0 √√−

FF01H Port 1 P1 √√−

FF03H port 4 P4 √√−

FF05H Port 6 P6 √√−

FF08H Port 8 P8

R/W

√√−

00H

FF15H A/D conversion result regi ster ADCR0 R −√−

Undefined

FF20H Port mode regist er 0 PM0 √√−

FF21H Port mode regist er 1 PM1 √√−

FF24H Port mode regist er 4 PM4 √√−

FF26H Port mode regist er 6 PM6 √√−

FF28H Port mode regist er 8 PM8 √√−

FFH

FF4AH Watch ti m er m ode control register WTM √√−

FF58H Port function regi ster 8 PF8

R/W

√√−

00H

FF63H 8-bit compare regis ter 30 CR30 W −√−

Undefined

FF64H 8-bit timer count er 30 TM30 R −√−

FF65H 8-bit timer mode control register 30 TMC30 R/W √√−

00H

FF66H 8-bit compare regis ter 40 CR40 −√−

FF67H 8-bit H widt h compare regis ter 40 CRH40

−√−

Undefined

FF68H 8-bit timer count er 40 TM40 R −√−

FF69H 8-bit timer mode control register 40 TMC40 R/W √√−

FF6AH Carrier generator output control register 40 TCA40 W √√−

FF80H A/D convert er m ode regi ster 0 ADM0 √√−

FF84H A/D input sel ection register 0 ADS0 √√−

FFB0H LCD display mode regist er 0 LCDM0 √√−

FFB2H LCD clock c ontrol regis ter 0 LCDC0 √√−

FFB3H LCD voltage ampl i ficat i on control regi s ter 0 LCDVA0 √√−

00H

FFDDH Power-on-clear regis ter 1 POCF1

R/W

√√−

00HNote

Note This value is 04H only after a power-on-clear reset.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

Table 4-1. Special Function Registers (2/2)

Bit Unit for Mani pul at i onAddress Special Func tion Regis t er (SFR) Name Symbol R/W

1 Bit 8 Bits 16 Bits

After

Reset

FFE0H Interrupt reques t flag register 0 IF0 √√−

00H

FFE4H Interrupt mask fl ag register 0 MK0 √√−

FFH

FFECH E xternal interrupt mode register 0 INTM0 −√−

FFF0H Subclock os c illation mode register SCKM √√−

FFF2H Subclock control regist er CSS √√−

FFF5H Key return mode regist er 00 KRM00 √√−

FFF7H Pull-up resistor option register 0 PU0 √√−

FFF9H Watchdog timer mode regis ter WDTM √√−

00H

FFFAH Oscillation stabilization time selection register OSTS −√−

04H

FFFBH Processor clock control register PCC

R/W

√√−

02H

Preliminary Product Information U14558EJ1V0PM00 19

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PD78F9468

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 Ports

5.1.1 Port functions

Various kinds of control operations are possible using the ports provided in the

PD78F9468. These ports are

illustrated in Figure 5-1 and their functions are listed in Table 5-1.

A number of alternate functions are also provided, except for those ports functioning as digital I/O ports. Refer to

3. PIN FUNCTIONS for details of the alternate function pins.

Figure 5-1. Ports

P00

P03

Port 0

Port 1

P10

P11

Port 4

P40

P43

Port 6 P60

P61

P80

Port 8

P85

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

Table 5-1. Port Functions

Port Name Pin Name Function

Port 0 P00 to P 03 I/O port. Input and output can be specifi ed i n 1-bi t uni ts.

When used as an input port, on-chip pull-up res i stors can be spec i f i ed using pull-up

resistor option register 0 (PU0).

Port 1 P10, P 11 I/O port . Input and output can be specifi ed i n 1-bi t uni ts.

When used as an input port, on-chip pull-up res i stors can be spec i f i ed using pull-up

resistor option register 0 (PU0).

Port 4 P40 to P 43 I/O port. Input and output can be specifi ed i n 1-bi t uni ts.

When used as an input port, on-chip pull-up res i stors can be spec i f i ed using pull-up

resistor option register 0 (PU0), or key return mode regis t er 00 (KRM00).

Port 6 P60, P 61 I/O port . Input and output can be specifi ed i n 1-bi t uni ts.

Port 8 P80 to P 85 I/O port. Input and output can be specifi ed i n 1-bi t uni ts.

Preliminary Product Information U14558EJ1V0PM00 21

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PD78F9468

5.1.2 Port configuration

The ports consist of the following hardware.

Table 5-2. Port Configuration

Item Configuration

Control regis t ers Port mode regi s ters (PM m: m = 0, 1, 4, 6, 8)

Pull-up resistor option register 0 (PU0)

Port function register 8 (PF8)

Ports Total: 18 (CMOS I/O: 18)

Pull-up resi stors Total: 10 (software control: 10)

Figure 5-2. Basic Configuration of CMOS Port

PUm

PU×

PORTm

PMm

Output latch

Pmn

PMmn

P-ch

Pmn

Internal bus

Selector

Caution Figure 5-2 shows the basic configuration of a CMOS I/O port. This configuration differs

depending on the functions of alternate function pins. Also, an on-chip pull-up resistor can be

connected to port 4 by means of a setting in key return mode register 00 (KRM00).

Remark PU0: Pull-up resistor option register 0

PMmn: Bit n of port mode register m (m = 0, 1, 4, 6, 8, n = 0 to 5)

Pmn: Bit n of port m

RD: Port read signal

WR: Port write signal

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

5.1.3 Port function control registers

The ports are controlled by the following three types of registers.

•Port mode registers (PM0, PM1, PM4, PM6, PM8)

•Pull-up resistor option register 0 (PU0)

•Port function register 8 (PF8)

(1) Port mode registers (PM0, PM1, PM4, PM6, PM8)

Input and output can be specified in 1-bit units.

These registers can be set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

When using the port pins as their alternate functions, set the output latch as shown in Table 5-3.

Caution Because P61 functions alternately as an external interrupt input, when the output level

changes after the output mode of the port function is specified, the interrupt request flag will

be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0) before

using the port in output mode.

Figure 5-3. Port Mode Register Format

Symbol76543210AddressAfter resetR/W

PM0 1 1 1 1 PM03 PM02 PM01 PM00 FF20H FFH R/W

PM1111111PM11PM10FF21HFFHR/W

PM4 1 1 1 1 PM43 PM42 PM41 PM40 FF24H FFH R/W

PM6111111PM61PM60FF26HFFHR/W

PM8 1 1 PM85 PM84 PM83 PM82 PM81 PM80 FF28H FFH R/W

PMmn Pmn pin input/output mode selec tion

(m = 0, 1, 4, 6, 8, n = 0 to 5)

0 Output mode (output buffer on)

1 Input mode (out put buffer off)

Preliminary Product Information U14558EJ1V0PM00 23

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PD78F9468

Table 5-3. Port Mode Registers and Output Latch Settings When Using Alternate Functions

Alternat e FunctionPin Name

Name I/O

PM×× P××

P40 to P43 KR00 to KR03 Input 1 ×

P60 TO40 Output 0 0

P61 INT/ANI0 Input 1 ×

P80 to P85 S22 to S17Note Output ××

Note When using pins P80 to P85 as S22 to S17, set port function register 8 (PF8) to 3FH.

Remark ×: don’t care

PM××: Port mode register

P××: Port output latch

(2) Pull-up resistor option register 0 (PU0)

This register sets whether to use on-chip pull-up resistors for ports 0, 1, and 4. An on-chip pull-up resistor can

be used only for those bits set to the input mode of a port for which the use of the on-chip pull-up resistor has

been specified using PU0.

For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting of

PU0. This also applies to alternate-function pins used as output pins.

PU0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-4. Format of Pull-up Resistor Option Register 0

Symbol 7 6 5 <4> 3 2 <1> <0> Address After reset R/W

PU0 0 0 0 PU04 0 0 PU01 PU00 FFF7H 00H R/W

PU0m Port m on-c hi p pul l -up resist or selection

(m = 0, 1, 4)

0 An on-chip pul l -up res i stor is not connec t ed

1 An on-chip pul l -up res i stor is connect ed

Caution Always set bits 2, 3, and 5 to 7 to 0.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

(3) Port function register 8 (PF8)

This register sets the port function of port 8 in 1-bit units.

The pins of port 8 are selected as either LCD segment signal outputs or general-purpose port pins according

to the setting of PF8.

PF8 can be set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-5. Format of Port Function Register 8

Symbol76543210AddressAfter resetR/W

PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W

PF8n P8n port function (n = 0 t o 5)

0 Operates as a general -purpose port

1 Operates as an LCD segment s i gnal output

Preliminary Product Information U14558EJ1V0PM00 25

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PD78F9468

5.2 Clock Generator

5.2.1 Clock generator function

The clock generator generates the clock pulse to be supplied to the CPU and peripheral hardware.

There are two types of system clock oscillators:

•Main system clock oscillator (ceramic/crystal resonator)

This circuit generates a frequency of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP

instruction or by means of a processor clock control register (PCC) setting.

•Subsystem clock oscillator

This circuit generates a frequency of 32.768 kHz. Oscillation can be stopped using the subclock oscillation

mode register (SCKM).

5.2.2 Clock generator configuration

The clock generator consists of the following hardware.

Table 5-4. Clock Generator Configuration

Item Configuration

Control regis ters Processor clock cont rol regi ster (PCC)

Subclock oscillat i on mode register (SCK M)

Subcloc k cont rol regi s ter (CSS)

Oscillators Main system clock oscillator

Subsystem clock oscillator

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

Figure 5-6. Clock Generator Block Diagram

Subsystem

clock

oscillatior

XT1

XT2

Main system

clock

oscillator

1/2

Prescaler

Watch timer

LCD controller/driver

Clock to peripheral hardware

CPU clock

CPU

)

Standby

controller Wait

controller

Selector

STOP MCC PCC1 CLS CSS0

Internal bus

Subclock oscillation mode

FRC SCC

Internal bus

Subclock control

Processor clock control

Preliminary Product Information U14558EJ1V0PM00 27

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PD78F9468

5.2.3 Clock generator control registers

The clock generator is controlled by the following three registers.

•Processor clock control register (PCC)

•Subclock oscillation mode register (SCKM)

•Subclock control register (CSS)

(1) Processor clock control register (PCC)

This register is used to select the CPU clock and set the frequency division ratio.

PCC is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 02H.

Figure 5-7. Format of Processor Clock Control Register

Symbol <7> 6 5 4 3 2 1 0 Address Aft er reset R/W

PCC MCC 0 0 0 0 0 PCC1 0 FFFBH 02H R/W

MCC Main system clock oscillator operation c ontrol

0 Operation enabled

1 Operation stopped

CSS0 PCC1 CPU clock (fCPU) selectionNote Minimum i nstruction exec ution tim e: 2fCPU

00f

(0.2

s) 0.4

/22 (0.8

s) 1.6

1×fXT/2 (61

s) 122

Note The CPU clock is selected by a combination of flag settings in the PCC and CSS registers (refer to

5.2.3 (3) Subclock control register (CSS)).

Cautions 1. Always set bits 0 and 2 to 6 to 0.

2. MCC can be set only when the subsystem clock is selected as the CPU clock. Setting

MCC to 1 while the main system clock is operating is invalid.

Remarks 1. f

: Main system clock oscillation frequency

2. f

XT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

4. ×: Don’t care

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

(2) Subclock oscillation mode register (SCKM)

This register is used to select a feedback resistor for the subsystem clock and control the oscillation of the

clock.

SCKM is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-8. Format of Subclock Oscillation Mode Register

Symbol 7 6 5 4 3 2 1 <0> Address Aft er reset R/W

SCKM 0 0 0 0 0 0 FRC SCC FFF0H 00H R/W

FRC Feedback resist or select i on

0 An on-chip f eedback res i s tor is used

1 An on-chip f eedback res i s tor is not used

SCC Control of subsystem clock oscillator operation

0 Operation enabled

1 Operation stopped

Caution Always set bits 2 to 7 to 0.

Preliminary Product Information U14558EJ1V0PM00 29

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PD78F9468

(3) Subclock control register (CSS)

This register is used to specify whether the main system or subsystem clock oscillator is selected and to

indicate the operating status of the CPU clock.

CSS is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-9. Format of Subclock Control Register

Symbol76543210AddressAfter resetR/W

CSS 0 0 CLS CSS0 0 0 0 0 FFF2H 00H R/WNote

CLS CPU cloc k operating s tatus

0 Operating on the output of t he (di vided) main system clock

1 Operating on the output of the subsystem clock

CSS0 Selection of main system clock or subsystem clock oscillator

0 Main system clock oscillator (divided) output

1 Subsystem clock oscillator output

Note Bit 5 is read-only.

Caution Always set bits 0 to 3, 6, and 7 to 0.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

5.3 8-Bit Timer 30, 40

5.3.1 Functions of 8-bit timer 30, 40

The 8-bit timer in the

PD78F9468 has 2 channels (timer 30 and timer 40). The operation modes in the following

table are possible by means of mode register settings.

Table 5-5. List of Modes

Channel

Mode

Timer 30 Timer 40

8-bit ti m er m ode

(discret e mode) √√

16-bit ti m er m ode

(casc ade connecti on m ode) √

Carrier generator mode √

PWM output m ode – √

(1) 8-bit timer mode (discrete mode)

The timer can be used for the following functions in this mode.

•8-bit resolution interval timer

•8-bit resolution square wave output (timer 40 only)

(2) 16-bit timer mode (cascade connection mode)

These timers can be used for 16-bit timer operations via a cascade connection.

The timer can be used for the following functions in this mode.

•16-bit resolution interval timer

•16-bit resolution square wave output

(3) Carrier generator mode

In this mode the carrier clock generated by timer 40 is output in the cycle set by timer 30.

(4) PWM output mode

In this mode, a pulse with an arbitrary duty ratio, which is set by timer 40, is output.

Preliminary Product Information U14558EJ1V0PM00 31

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PD78F9468

5.3.2 Configuration of 8-bit timer 30, 40

8-bit timers 30 and 40 consist of the following hardware.

Table 5-6. Configuration of 8-Bit Timer 30, 40

Item Configuration

Timer counter 8 bits × 2 (TM30, TM 40)

Registers Compare regist ers : 8 bits × 3 (CR30, CR40, CRH40)

Timer outputs 1 (TO40)

Control regis t ers 8-bit ti m er m ode control register 30 (TMC30)

8-bit ti m er m ode control register 40 (TMC40)

Carrier generator output control regi s ter 40 (TCA40)

Port mode regi s ter 6 (PM6)

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

TCE30

TCL300

TMD300

TCL301

8-bit timer mode control register 30

(TMC30)

Selector

Decoder

Selector

8-bit compare register 30

(CR30)

8-bit timer counter 30

(TM30)

Selector

Internal reset signal

Timer 40 match signal

(in cascade connection mode)

Timer 30 match signal

(in cascade connection mode)

From Figure 5-11 (D)

Count operation start signal

(for cascade connection) INTTM30

Timer 40 interrupt request signal

(from Figure 5-11 (B))

Carrier clock (in carrier generator mode)

or timer 40 output signal

(in other than carrier generator mode)

(from Figure 5-11 (C))

Clear

Cascade connection mode

Match

From Figure 5-11 (E)

To Figure 5-11 (F)

To Figure 5-11 (G)

Figure 5-10. Block Diagram of Timer 30

Internal bus

OVF

Timer 30 match signal

(in carrier generator mode)

Bit 7 of TM40

(from Figure

5-11 (A))

Preliminary Product Information U14558EJ1V0PM00 33

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PD78F9468

TCE40

TCL402 TCL401 TCL400

TMD401

TMD400

TOE40

8-bit timer mode control

Decoder

8-bit timer counter 40

(TM40)

F/F

TM30 match signal

(in cascade connection mode)

Count operation start signal to timer 30

(in cascade connection mode)

TM40 timer counter match signal

(in cascade connection mode)

Clear

8-bit compare

Selector

Output

controller

Note

RMC40

NRZB40

NRZ40

Carrier generator output

control register 40 (TCA40)

To Figure 5-10 (D)

count clock input

signal to TM30

Internal reset signal

INTTM40

Bit 7 of TM40

(in cascade connection mode)

To Figure 5-10 (A)

To Figure 5-10 (F)

To Figure 5-10 (E)

Match TO40/P60

To Figure 5-10 (C)

Carrier clock (in carrier generator mode)

or timer 40 output signal

(in other than carrier generator mode)

Reset

Carrier generator mode

PWM mode

Cascade connection mode

Figure 5-11. Block Diagram of Timer 40

Note Refer to Figure 5-12 for details.

8-bit H width compare

Internal bus

Selector

OVF

Prescaler

/2 f

Timer 40 interrupt request signal

To Figure 5-10 (B)

Timer counter match signal from

timer 30 (in carrier generator mode)

From Figure 5-10 (G)

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

Figure 5-12. Block Diagram of Output Controller (Timer 40)

F/F

RMC40 NRZ40

TOE40

PM60

P60

output latch

Selector

TO40/P60

Carrier generator mode

Carrier clock (in carrier generator mode)

or timer 40 output signal

(in other than carrier generator mode)

(1) 8-bit compare register 30 (CR30)

A value specified in CR30 is compared with the count value in 8-bit timer counter 30 (TM30), and if they

match, an interrupt request (INTTM30) is generated.

CR30 is set using an 8-bit memory manipulation instruction.

RESET input makes this register undefined.

Caution CR30 cannot be used in carrier generator mode or PWM output mode.

(2) 8-bit compare register 40 (CR40)

A value specified in CR40 is compared with the count value in 8-bit timer counter 40 (TM40), and if they

match, an interrupt request (INTTM40) is generated. When operating as a 16-bit timer in cascade

connection with TM30, an interrupt request (INTTM40) is only generated if both CR30 and TM30, and CR40

and TM40 match simultaneously (INTTM30 is not issued).

CR40 is set using an 8-bit memory manipulation instruction.

RESET input makes this register undefined.

(3) 8-bit H width compare register (CRH40)

In carrier generator mode or PWM output mode, a timer output high-level width can be set by writing a value

to CRH40.

CRH40 is set using an 8-bit memory manipulation instruction.

RESET input makes this register undefined.

Preliminary Product Information U14558EJ1V0PM00 35

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PD78F9468

(4) 8-bit timer counter 30, 40 (TM30, TM40)

These are 8-bit registers for counting the count pulses.

TM30 and TM40 can be read with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to 00H.

The conditions under which TM30 and TM40 are cleared to 00H are listed below.

(a) Discrete mode

(i) TM30

•Upon a reset

•When TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30)) is cleared to 0

•Upon a match between TM30 and CR30

•If the TM30 count value overflows

(ii) TM40

•Upon a reset

•When TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40)) is cleared to 0

•Upon a match between TM40 and CR40

•If the TM40 count value overflows

(b) Cascade connection mode (TM30 and TM40 cleared to 00H simultaneously)

•Upon a reset

•When the TCE40 flag is cleared to 0

•Upon a simultaneous match between TM30 and CR30, and TM40 and CR40

•If the TM30 and TM40 count values overflow simultaneously

•Upon a reset

•When the TCE40 flag is cleared to 0

•Upon a match between TM40 and CR40

•Upon a match between TM40 and CRH40

•If the TM40 count value overflows

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

5.3.3 8-bit timer 30, 40 control registers

8-bit timers 30 and 40 are controlled by the following 4 registers.

•8-bit timer mode control register 30 (TMC30)

•8-bit timer mode control register 40 (TMC40)

•Carrier generator output control register 40 (TCA40)

•Port mode register 6 (PM6)

Preliminary Product Information U14558EJ1V0PM00 37

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PD78F9468

(1) 8-bit timer mode control register 30 (TMC30)

This register is used to control the timer 30 count clock and operation mode settings.

TMC30 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-13. Format of 8-Bit Timer Mode Control Register 30

Symbol <7> 6 5 4 3 2 1 0 Address After res et R/W

TMC30 TCE30 0 0 TCL301 TCL300 0 TMD300 0 FF65H 00H R/W

TCE30 TM30 count c ont rol operationNote 1

0 TM30 count v al ue cleared and operation stopped

1 Count operation st arts

TCL301 TCL300 Timer 30 count clock s el ection

/26 (78.1 kHz)

/28(19.5 kHz)

1 0 Timer 40 match si gnal

1 1 Carrier clock (i n carrier generator mode) or timer 40 out put signal (in other than carri er generator

mode)

TMD300 TMD401 TMD400 Timer 30, timer 40 operation mode select i on Note 2

0 0 0 Disc ret e m ode

1 0 1 Cascade connecti on m ode

0 1 1 Carrier generator mode

0 1 0 PWM output mode

Other than above Setti ng prohi bi ted

Notes 1. The TCE30 setting will be ignored in cascade mode because in this case the count operation is

controlled by TCE40 (bit 7 of TMC40).

2. The operation mode selection is made using a combination of TMC30 and TMC40 register settings.

Caution In cascade connection mode, the timer 40 output signal is forcibly selected for the count

clock.

Remarks 1. fX: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

(2) 8-bit timer mode control register 40 (TMC40)

This register is used to control the timer 40 count clock and operation mode settings.

TMC40 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-14. Format of 8-Bit Timer Mode Control Register 40

Symbol <7> 6 5 4 3 2 1 <0> Address After reset R/W

TMC40 TCE40 0 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40 FF69H 00H R/W

TCE40 TM40 count c ont rol operationNote 1

0 TM40 count v al ue cleared and operation stopped (in c ascade connection m ode, the count value of TM 30 i s

cleared at t he same ti m e)

1 Count operation st arts (in c ascade connection m ode, the count operation of TM 30 starts at the same tim e)

TCL402 TCL401 TCL400 Timer 40 count clock s el ection

000f

(5 MHz)

001

/22 (1.25 MHz)

010f

/2 (2.5 MHz)

011

/22 (1.25 MHz)

100

/23 (625 kHz)

101

/24 (313 kHz)

Other than above Setti ng prohi bi ted

TMD300 TMD401 TMD400 Timer 30, timer 40 operation mode select i on Note 2

0 0 0 Disc ret e m ode

1 0 1 Cascade connecti on m ode

0 1 1 Carrier generator mode

0 1 0 PWM output mode

Other than above Setti ng prohi bi ted

TOE40 Timer output control

0 Output disabl ed (port mode)

1 Output enabled

Notes 1. The TCE30 setting will be ignored in cascade mode because in this case the count operation is

controlled by TCE40 (bit 7 of TMC40).

2. The operation mode selection is made using a combination of TMC30 and TMC40 register settings.

Remarks 1. fX: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz

Preliminary Product Information U14558EJ1V0PM00 39

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PD78F9468

(3) Carrier generator output control register 40 (TCA40)

This register is used to set the timer output data in the carrier generator mode.

TCA40 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-15. Format of Carrier Generator Output Control Register 40

Symbol76543<2><1><0>AddressAfter resetR/W

TCA4000000RMC40NRZB40NRZ40FF6AH00HW

RMC40 Remot e controll er out put control

0 When NRZ40 = 1, a carrier puls e i s output t o the TO40/P60 pi n

1 When NRZ40 = 1, a high level i s output to the TO40/P 60 pi n

NRZB40 This bit stores the data t hat NRZ40 will output next . Data is t ransferred to NRZ40 upon t he generat ion of a

timer 30 match si gnal .

NRZ40 No return, z ero data

0 A low level i s output (t he carrier cl ock is stopped)

1 A carrier puls e i s output

(4) Port mode register 6 (PM6)

This register is used to set port 6 to input or output in 1-bit units.

When the TO40/P60 pin is used as a timer output, set the PM60 and P60 output latches to 0.

PM6 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 5-16. Format of Port Mode Register 6

Symbol76543210AddressAfter resetR/W

PM6111111PM61PM60FF26HFFHR/W

PM6n Input/output mode of pi n P6n (n = 0, 1)

0 Output mode (output buffer on)

1 Input mode (output buffer off)

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

5.4 Watch Timer

5.4.1 Watch timer functions

The watch timer has the following functions.

•Watch timer

•Interval timer

The watch and interval timers can be used at the same time.

Figure 5-17 shows a block diagram of the watch timer.

Figure 5-17. Watch Timer Block Diagram

Selector

Clear

9-bit prescaler

Selector

Clear

5-bit counter INTWT

INTWTI

WTM7 WTM6 WTM5 WTM4 WTM1 WTM0

Watch timer mode control

Internal bus

Preliminary Product Information U14558EJ1V0PM00 41

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PD78F9468

(1) Watch timer

An interrupt request (INTWT) is generated at 0.5-second intervals using the 4.19 MHz main system clock or

32.768 kHz subsystem clock.

Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a 0.5-second

interval. In this case, the subsystem clock, which operates at 32.768 kHz, should be used

instead.

(2) Interval timer

The interval timer is used to generate an interrupt request (INTWTI) at preset intervals.

Table 5-7. Interval Time of Interval Timer

Interval Time At fX = 5.0 MHz Operation At fX = 4.19 MHz Operat i on At fXT = 32. 768 kHz Operati on

24 × 1/fW409.6

s 488

25 × 1/fW819.2

s 977

26 × 1/fW1.64 ms 1.95 ms 1.95 ms

27 × 1/fW3.28 ms 3.91 ms 3.91 ms

28 × 1/fW6.55 ms 7.81 ms 7.81 ms

29 × 1/fW13.1 ms 15.6 ms 15.6 ms

Remarks 1. f

W: Watch timer clock frequency (fX/27 or fXT)

2. f

X: Main system clock oscillation frequency

3. f

XT: Subsystem clock oscillation frequency

5.4.2 Watch timer configuration

The watch timer consists of the following hardware.

Table 5-8. Watch Timer Configuration

Item Configuration

Counter 5 bits × 1

Prescaler 9 bits × 1

Control regis t er Watch ti mer mode cont rol regi ster (WTM)

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

5.4.3 Watch timer control register

The following register controls the watch timer.

•Watch timer mode control register (WTM)

(1) Watch timer mode control register (WTM)

This register is used to enable/disable the count clock and operation of the watch timer and set the interval

time of the prescaler and operation control of the 5-bit counter.

WTM is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-18. Format of Watch Timer Mode Control Register

Symbol 7 6 5 4 3 2 <1> <0> Address After reset R/W

WTM WTM7 WTM6 WTM5 WTM4 0 0 WTM1 WTM0 FF4AH 00H R/W

WTM7 Watch tim er count clock (fW) selection

0fX/27(39.1 kHz)

XT (32.768 kHz)

WTM6 WTM5 WTM4 Prescaler i nterval ti m e selecti on

000

24/fW

001

25/fW

010

26/fW

011

27/fW

100

28/fW

101

29/fW

Other than above Setti ng prohi bi ted

WTM1 5-bit counter operati on control

0 Cleared after operation st opped

1Start

WTM0 Watch timer operati on enabl e

0 Operation s topped (both prescaler and tim er cleared)

1 Operation enabled

Remarks 1. fW: Watch timer clock frequency (fX/27 or fXT)

2. fX: Main system clock oscillation frequency

3. fXT: Subsystem clock oscillation frequency

4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.

Preliminary Product Information U14558EJ1V0PM00 43

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PD78F9468

5.5 Watchdog Timer

5.5.1 Watchdog timer functions

The watchdog timer has the following functions.

(1) Watchdog timer

The watchdog timer is used to detect a program runaway. If a runaway is detected, either a non-maskable

interrupt or the RESET signal can be generated.

(2) Interval timer

The interval timer is used to generate interrupts at preset intervals.

5.5.2 Watchdog timer configuration

The watchdog timer consists of the following hardware.

Table 5-9. Watchdog Timer Configuration

Item Configuration

Control regis t er Watchdog ti mer mode register (WDTM)

Figure 5-19. Watchdog Timer Block Diagram

Internal bus

7-bit counter

Controller

Clear

WDTIF

WDTMK

Watchdog timer mode register

(WDTM)

WDTM4 WDTM3

INTWDT

maskable

interrupt request

RESET

INTWDT

non-maskable

interrupt request

RUN

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

5.5.3 Watchdog timer control register

The watchdog timer is controlled by the following register.

•Watchdog timer mode register (WDTM)

(1) Watchdog timer mode register (WDTM)

This register is used to set the watchdog timer operation mode and whether to enable or disable counting.

WDTM is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-20. Format of Watchdog Timer Mode Register

Symbol <7> 6 5 4 3 2 1 0 Addres s Af ter reset R/W

WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 FFF9H 00H R/W

RUN Watchdog timer operation select ionNote 1

0 Counting stopped

1 Counter cleared and counting s tarts

WDTM4 WDTM3 Watchdog timer operation m ode selectionNote 2

0 0 Operation stopped

Interval timer m ode (when an overflow occurs, a maskable interrupt is generat ed) Note 3

1 0 Watchdog tim er m ode 1 (when an overflow oc curs, a non-m askable i nterrupt is generated)

1 1 Watchdog tim er m ode 2 (when an overflow oc curs, a reset operati on i s acti vated)

Notes 1. Once the RUN bit has been set (1), it is impossible to clear it (0) by software. Cons equently, once

counting begins, it cannot be stopped by any means other than RESET input.

2. Once WDTM3 and WDTM4 have been set (1), it is impossible to clear them (0) by software.

3. The interval timer starts operating as soon as the RUN bit is set to 1.

Cautions 1. When the RUN bit is set to 1, and the watchdog timer is cleared, the actual overflow time

will be up to 0.8% shorter than the time specified by the watchdog timer clock selection

2. To use watchdog timer mode 1 or 2, be sure to set WDTM4 to 1 after confirming that

WDTIF (bit 0 of interrupt request flag 0 (IF0)) has been set to 0. If WDTIF is 1, selecting

watchdog timer mode 1 or 2 causes a non-maskable interrupt to be generated the instant

rewriting ends.

Preliminary Product Information U14558EJ1V0PM00 45

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PD78F9468

5.6 A/D Converter

5.6.1 A/D converter function

The A/D converter converts analog inputs into digital values with 8-bit resolution and is configured so as to enable

control of 1 channel of analog input (ANI0).

An A/D conversion operation can only be started via a software start.

A/D conversion is repeated, with an interrupt request (INTAD0) generated at the completion of each A/D

conversion operation.

Caution A/D conversion is stopped in the STOP mode.

5.6.2 A/D converter configuration

The A/D converter consists of the following hardware.

Table 5-10. A/D Converter Configuration

Item Configuration

Analog inputs 1 c hannel (A NI0)

Registers Successi ve approximation regis t er (SAR)

A/D c onversion result regi ster 0 (ADCR0)

Control regis t ers A /D converter mode regis t er 0 (ADM0)

A/D input selection regi ster 0 (ADS0)

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

Figure 5-21. A/D Converter Block Diagram

Selector

Tap selector

Sample & hold circuit

Voltage comparator

Successive approximation

Controller

A/D conversion result

A/D input selection

Internal bus

INTAD0

P-ch

ADS00 ADCS0 FR02 FR01 FR00

(1) Successive approximation register (SAR)

The SAR holds the result of comparing an analog input voltage and a voltage at a voltage tap (comparison

voltage), received from the series resistor string, starting from the most significant bit (MSB).

Upon receiving all the bits down to the least significant bit (LSB) (end of A/D conversion), the SAR transfers its

contents to A/D conversion result register.

(2) A/D conversion result register 0 (ADCR0)

ADCR0 holds the result of A/D conversion. Each time A/D conversion ends, the conversion result in the

successiv e approximation register is loaded into ADCR0.

ADCR0 can be read with an 8-bit memory manipulation instruction.

RESET input makes this register undefined.

(3) Sample-and-hold circuit

The sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends

them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.

(4) Voltage comparator

The voltage comparator compares an analog input with the voltage output by the series resistor string.

(5) Series resistor string

The series resistor string is configured between VDD and VSS. It generates the reference voltages against

which analog inputs are compared.

(6) ANI0 pin

The ANI0 pin is a 1-channel analog input pin for the A/D converter. It is used to receive the analog signals for

A/D conversion.

Preliminary Product Information U14558EJ1V0PM00 47

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PD78F9468

5.6.3 A/D converter control registers

The following two registers are used to control the A/D converter.

• A/D converter mode register 0 (ADM0)

• A/D input selection register 0 (ADS0)

(1) A/D converter mode register 0 (ADM0)

ADM0 is used to set the conversion time for analog inputs to be A/D converted and to start and stop A/D

conversion.

ADM0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ADM0 to 00H.

Figure 5-22. Format of A/D Converter Mode Register 0

Symbol <7> 6 5 4 3 2 1 0 Addres s Af ter reset R/W

ADM0 ADCS0 0 FR02 FR01 FR00 0 0 0 FF80H 00H R/W

ADCS0 A/D c onversion control

0 A/D c onv ersion stopped

1 A/D c onv ersion enabled

FR02 FR01 FR00 A/D c onversion time s e l ectionNote 1

00072/f

X (14.4

001

60/fX (setting prohi bi t edNote 2)

010

48/fX (setting prohi bi t edNote 2)

1 0 0 144/fX (28. 8

1 0 1 120/fX (24

11096/f

X (19.2

Other than above Setti ng prohi bi ted

Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least 14

2. These bit combinations must not be used, as the A/D conversion time will fall below 14

Cautions 1. The result of conversion performed immediately after the bit 7 (ADCS0) is set is undefined.

2. The result of conversion performed after the ADCS0 is cleared may become undefined. When

reading the result of conversion, read it during A/D conversion. If reading the result of

conversion after stopping A/D conversion, stop A/D conversion and then read the result

between completion of A/D conversion and starting the next A/D conversion.

3. Always set bits 0 to 2 and bit 6 to 0.

Remarks 1. fX: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

(2) A/D input selection register 0 (ADS0)

ADS0 specifies the port used to input the analog voltage to be A/D converted.

ADS0 is set with a 1-bit or 8-bit memory manipulation instruction.

RESET input sets ADS0 to 00H.

Figure 5-23. Format of A/D Input Selection Register 0

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

ADS0 0 0 0 0 0 0 0 ADS00 FF84H 00H R/W

ADS0 Port function of P61

0 Operates as P61(general-purpos e port pi n) or INT (external i nterrupt pin)

1 Operates as ANI0 (analog i nput pin). E xternal interrupts are prohi bi ted.

Caution Always set bits 1 to 7 to 0.

Preliminary Product Information U14558EJ1V0PM00 49

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PD78F9468

5.7 LCD Controller/Driver

5.7.1 LCD controller/driver functions

The LCD controller/driver incorporated in the

PD78F9468 has the following features.

(1) Segment and common signals based on the automatic reading of the display data memory can be

automatically output

(2) Four types of frame frequencies are selectable

(3) 23 segment signal outputs (S0 to S22), 4 common signal outputs (COM0 to COM3)

(4) Operation with a subsystem clock is possible

(5) A voltage amplifier is incorporated

The maximum number of displayable pixels is shown in Table 5-11 below.

Table 5-11. Maximum Number of Display Pixels

Bias M et hod Time Divi sion Com m on S i gnal s Used Maximum Number of Display P i xels

1/3 4 COM0 to COM3 92 (23 segments × 4 com m ons)Note

Note The LCD panel of the figure consists of 11 rows with 2 segments per row.

5.7.2 LCD controller/driver configuration

The LCD controller/driver consists of the following hardware.

Table 5-12. Configuration of LCD Controller/Driver

Item Configuration

Display outputs S egm ent signal s : 23

Common signal s: 4

Control regis ters LCD display mode regi ster 0 (LCDM0)

LCD clock cont rol regi ster 0 (LCDC0)

LCD voltage am pl i ficat i on control register 0 (LCDVA0)

Port function register 8 (PF8)

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

The correspondence with the LCD display RAM is shown in Figure 5-24 below.

Figure 5-24. Correspondence with LCD Display RAM

Address Bit Segment

76543210

FA16H 0 0 0 0 → S22

FA15H 0 0 0 0 → S21

FA14H 0 0 0 0 → S20

FA13H 0 0 0 0 → S19

FA12H 0 0 0 0 → S18

FA11H 0 0 0 0 → S17

FA10H 0 0 0 0 → S16

FA0FH 0000 → S15

FA0EH 0000 → S14

FA0DH 0000 → S13

FA0CH 0000 → S12

FA0BH 0000 → S11

FA0AH 0000 → S10

FA09H 0 0 0 0 → S9

FA08H 0 0 0 0 → S8

FA07H 0 0 0 0 → S7

FA06H 0 0 0 0 → S6

FA05H 0 0 0 0 → S5

FA04H 0 0 0 0 → S4

FA03H 0 0 0 0 → S3

FA02H 0 0 0 0 → S2

FA01H 0 0 0 0 → S1

FA00H 0 0 0 0 → S0

Common ↑

COM3 ↑

COM2 ↑

COM1 ↑

COM0

Remark Bits 4 to 7 are fixed to 0.

Preliminary Product Information U14558EJ1V0PM00 51

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PD78F9468

Internal bus

LCDC03 LCDC02 LCDC01 LCDC00

Selector

Prescaler

LCD clock

selector

Selector

CLK

LCD clock control

LCDON0

VAON0

LCD display mode

LCD drive voltage controller

LC0

Segment

driver

Common driver

COM0 COM1 COM2 COM3

3210

32106574

FA00H

Display data memory

LCDON0

Selector

Segment

driver

3210

32106574

FA16H

LCDON0

S22/P80

Timing

controller

CLK

PF85 PF84 PF83 PF82 PF80

PF81

Port function

PF80

Selector

Segment

driver

3210

32106574

FA11H

LCDON0

S17/P85

PF85

. . .

. . . .

. . . . . . . . . . . . .

..........

...............

LCD

LIPS0

Voltage

amplifier

GAIN

LCD voltage

amplification control

LC2

CAPH CAPL V

LC1

Figure 5-25. LCD Controller/Driver Block Diagram

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

5.7.3 LCD controller/driver control registers

The LCD controller/driver is controlled by the following four registers.

•LCD display mode register 0 (LCDM0)

•LCD clock control register 0 (LCDC0)

•LCD voltage amplification control register 0 (LCDVA0)

•Port function register 8 (PF8)

(1) LCD display mode register 0 (LCDM0)

This register is used to enable/disable operation, and set the operation mode and the supply of power for LCD

drive.

LCDM0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-26. Format of LCD Display Mode Register 0

Symbol <7> <6> 5 <4> 3 2 1 0 Addres s After reset R/W

LCDM0 LCDON0 VAON0 0 LIPS0 0 0 0 0 FFB0H 00H R/W

LCDON0 LCD display enabl e/disabl e

0 Display off (all segment out puts are uns el ec ted for si gnal output)

1 Display on

VAON0 LCD controller/driver operation m odeNote

0 No internal boos ter

1 Internal booster enabled

LIPS0 Supply of power for LCD driveNote

0 Power not supplied f or LCD dri ve

1 Power suppl i ed for LCD drive

Note To reduce power consumption when the LCD display is not being used, set VAON0 and LIPS0 to 0.

Cautions 1. Always set bits 0 to 3 and 5 to 0.

2. To manipulate VAON0, follow the procedure described below.

A. When stopping voltage amplification after turning the LCD display off:

1) Turn off the LCD display by setting LCDON0 to 0.

2) Set all segment buffers and common buffers to output-disabled by setting LIPS0 to0.

3) Stop voltage amplification by setting VAON to 0.

B. When stopping voltage amplification while the LCD display is on:

Setting is prohibited. Be sure to stop voltage amplification after turning off the LCD

display.

C. When turning on the LCD display after voltage amplification has been stopped:

1) Wait about 500 ms after starting voltage amplification by setting VAON0 to 1.

2) Set all segment buffers and common buffers outputs to a non-display output state

by setting LIPS0 to 1.

3) Turn on the LCD display by setting LCDON0 to 1.

Preliminary Product Information U14558EJ1V0PM00 53

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PD78F9468

(2) L CD clock control register (LCDC0)

This register is used to set the internal and LCD clocks. The frame frequency is determined by the number of

LCD clock time divisions.

LCDC0 is set usi ng a 1-bit or 8-bit memory manipulat ion instruction.

RESET input sets this register to 00H.

Figure 5-27. Format of LCD Clock Control Register 0

Symbol 7 6 5 4 3 2 1 0 Address Af ter reset R/W

LCDC0 0 0 0 0 LCDC03 LCDC02 LCDC01 LCDC00 FFB2H 00H R/W

LCDC03 LCDC02 Internal clock (fCLK) selectionNote

00f

XT (32.768 kHz)

fX/25(156.3 kHz)

fX/26(78.1 kHz)

fX/27(39.1 kHz)

LCDC01 LCDC00 LCD cloc k (fLCD) selection

fCLK/26

fCLK/27

fCLK/28

fCLK/29

Note Select a clock of at least 32 kHz for the internal clock (fCLK).

Remarks 1. f

X: Main system clock oscillation frequency

2. fXT: Subsystem clock oscillation frequency

3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz

Cautions 1. Always set bits 4 to 7 to 0.

2. Be sure to change the LCDC0 setting after setting VAON0 to 0.

Examples of the frame frequencies when the internal clock (fCLK) is connected to fXT (32.768 kHz) are shown

in Table 5-13 below.

Table 5-13. Frame Frequency (Hz)

LCD Clock (fLCD)

Time Division fXT/29

(64 Hz) fXT/28

(128 Hz) fXT/27

(256 Hz) fXT/26

(512 Hz)

4 163264128

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

(3) LCD voltage amplification control register 0 (LCDVA0)

This register is used to select voltage amplification level when the voltage amplifier is operating.

LCDVA0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-28. Format of LCD Voltage Amplification Control Register 0

Symbol7654321<0>AddressAfter resetR/W

LCDVA00000000GAINFFB3H00HR/W

GAIN Selection of voltage am pl i fication levelNote

0 1.5 t i m es (when using a 4. 5 V speci ficat i on panel )

1 1.0 t i m es (when using a 3 V specif i cation panel )

Note Switch the level based on the specification of the panel used.

Caution Be sure to change the LCDVA0 setting after setting VAON0 to 0.

(4) Port function register 8 (PF8)

This register is used to select whether S17/P85 to S22/P80 are used as LCD segment signal outputs or

general-purpose ports.

PF8 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 5-29. Format of Port Function Register 8

Symbol76543210AddressAfter resetR/W

PF8 0 0 PF85 PF84 PF83 PF82 PF81 PF80 FF58H 00H R/W

PF8n P ort functi on of P8n (n = 0 to 5)

0 Operates as a general-purpose port

1 Operates as an LCD segment signal output

Preliminary Product Information U14558EJ1V0PM00 55

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PD78F9468

6. INTERRUPT FUNCTION

6.1 Interrupt Types

Two types of interrupts are supported.

(1) Non-maskable interrupts

Non-maskable interrupt requests are acknowledged unconditionally, i.e. even when interrupts are disabled.

These interrupts take precedence over all other interrupts and are not subject to interrupt priority control.

A non-maskable interrupt causes the generation of the standby release signal

An interrupt from the watchdog timer is the only non-maskable interrupt source supported in the

PD78F9468.

(2) Maskable interrupts

Maskable interrupts are subject to mask control. If two or more maskable interrupts occur simultaneously, the

default priority listed in Table 6-1 applies.

A maskable interrupt causes the generation of the standby release signal.

Maskable interrupts from 2 external and 6 internal sources are supported in the

PD78F9468.

6.2 Interrupt Sources and Configuration

The

PD78F9468 supports a total of 9 maskable and non-maskable interrupt sources (see Table 6-1).

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

Table 6-1. Interrupt Sources

Interrupt SourceInterrupt Type Default

PriorityNote 1 Name Trigger

Internal/

External Vector Table

Address Basic

Configuration

TypeNote 2

Non-maskable −INTWDT Watchdog ti m er overflow (with

watchdog ti mer mode 1 selected) (A)

0 INTWDT Watchdog t i m er overflow (wi t h

interval t i mer mode selected)

Internal 0004H

(B)

1 INTP0 Pin input edge det ection Ext ernal 0006H (C)

2 INTAD0 Si gnal i ndi cating end of A/D

conversion 0008H

3 INTWT Watch t i m er i nterrupt 000AH

4 INTTM30 Generati on of 8-bit t i m er 30

match signal 000CH

5 INTTM40 Generati on of 8-bit t i m er 40

match signal

Internal

000EH

(B)

6 INTKR00 K ey return si gnal detecti on External 0010H (C)

Maskable

7 INTWTI Watch timer interval timer

interrupt Internal 0012H (B)

Notes 1. Default priority is the priority order when more than one maskable interrupt request is generated at the

same time. 0 is the highest priority and 7 is the lowest.

2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1.

Remark Only one of the two watchdog timer interrupt sources, non-maskable or maskable (internal), can be

selected.

Preliminary Product Information U14558EJ1V0PM00 57

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PD78F9468

Figure 6-1. Basic Configuration of Interrupt Function

(A) Internal non-maskable interrupt

Internal bus

Interrupt request Vector table

address generator

Standby release signal

(B) Internal maskable interrupt

Internal bus

Interrupt request

Vector table

address generator

Standby release signal

Internal bus

INTM0, KRM00 MK

Vector table

address generator

Standby release signal

Edge

detector

Interrupt request

INTM0: External interrupt mode register 0

KRM00: Key return mode register 00

IF: Interrupt request flag

IE: Interrupt enable flag

MK: Interrupt mask flag

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

6.3 Interrupt Function Control Registers

Interrupts are controlled by the following five registers.

•Interrupt request flag register 0 (IF0)

•Interrupt mask flag register 0 (MK0)

•External interrupt mode register 0 (INTM0)

•Program status word (PSW)

•Key return mode register 00 (KRM00)

Table 6-2 lists the interrupt requests and the corresponding interrupt request and interrupt mask flags.

Table 6-2. Interrupt Request Signals and Corresponding Flags

Interrupt Request Si gnal Interrupt Request Flag Interrupt Mas k Flag

INTWDT

INTP0

INTAD0

INTWT

INTTM30

INTTM40

INTKR00

INTWTI

WDTIF

PIF0

ADIF0

WTIF

TMIF30

TMIF40

KRIF00

WTIIF

WDTMK

PMK0

ADMK0

WTMK

TMMK30

TMMK40

KRMK00

WTIMK

Preliminary Product Information U14558EJ1V0PM00 59

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PD78F9468

(1) Interrupt request flag register 0 (IF0)

An interrupt request flag is set (1) when the corresponding interrupt request is generated, or when an

instruction is executed. It is cleared (0) when the interrupt request is acknowledged, when the RESET signal

is input, or when an instruction is executed.

IF0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 6-2. Format of Interrupt Request Flag Register 0

Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address Af ter reset R/W

IF0 WTIIF KRIF00 TMIF40 TMIF30 WTIF ADIF0 PIF0 WDTIF FFE0H 00H R/W

××IF× Interrupt reques t flag

0 No interrupt request si gnal generated

1 An interrupt request signal is generated and an int errupt request m ade

Cautions 1. The WDTIF flag can be read/written only when the watchdog timer is being used as an

interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog timer

mode 1 or 2.

2. Because P61 functions alternately as an external interrupt, when the output level

changes after the output mode of the port function is specified, the interrupt request flag

will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0)

before using the port in output mode.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

(2) Interrupt mask flag register 0 (MK0)

Interrupt mask flags are used to enable and disable the corresponding maskable interrupts.

MK0 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 6-3. Format of Interrupt Mask Flag Register 0

Symbol <7> <6> <5> <4> <3> <2> <1> <0> Address Af ter reset R/W

MK0 WTIMK KRMK00 TMMK40 TMMK30 WTMK ADMK0 PMK0 WDTMK FFE4H FFH R/W

××MK Interrupt serv i cing cont rol

0 Interrupt servic i ng enabl ed

1 Interrupt servic i ng di sabled

Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to

read the WDTMK flag results in an undefined value being detected.

2. Because P61 functions alternately as an external interrupt, when the output level

changes after the output mode of the port function is specified, the interrupt request flag

will be inadvertently set. Therefore, be sure to preset the interrupt mask flag (PMK0)

before using the port in output mode.

Preliminary Product Information U14558EJ1V0PM00 61

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PD78F9468

(3) External interrupt mode register 0 (INTM0)

This register is used to specify the valid edge for INTP0.

INTM0 is set using an 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 6-4. Format of External Interrupt Mode Register 0

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

INTM0 0 0 0 0 ES01 ES00 0 0 FFECH 00H R/W

ES01 ES00 INTP0 val i d edge select i on

0 0 Falling edge

0 1 Rising edge

1 0 Setti ng prohi bi ted

1 1 Both rising and f alling edges

Cautions 1. Always set bits 0, 1, and 4 to 7 to 0.

2. Before setting INTM0, set (1) the interrupt mask flag (PMK0) to disable interrupts.

To enable interrupts, clear (0) the interrupt request flag (PIF0), then clear (0) the interrupt

mask flag (PMK0).

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

(4) Program status word (PSW)

The program status word is used to hold the instruction execution results and the current status of the

interrupt requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW.

The PSW can be read and written in 8-bit units, as well as in 1-bit units by using bit manipulation instructions

and dedicated instructions (EI and DI). When a vector interrupt is acknowledged, the PSW is automatically

saved to the stack, and the IE flag is reset (0).

RESET input sets the PSW to 02H.

Figure 6-5. Program Status Word Configuration

IE Z 0 AC 0 0 1 CYPSW

Symbol After reset

02H

76543210

Used in the execution of ordinary instructions

Disabled

Enabled

Interrupt acknowledgement enable/disable

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PD78F9468

(5) Ke y return mode register 00 (KRM00)

This register is used to set the pin that is to detect the key return signal (rising edge of port 4).

KRM00 is set using a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 6-6. Format of Key Return Mode Register 00

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

KRM00 0 0 0 0 0 0 0 KRM000 FFF5H 00H R/W

KRM000 Key ret urn signal det ec tion cont rol

0 Key return si gnal not detected

1 Key return si gnal detected (port 4 falling edge detection)

Cautions 1. Always set bits 1 to 7 to 0.

2. Before setting KRM00, set (1) bit 6 of MK0 (KRMK00) to disable interrupts. To enable

interrupts, clear (0) KRMK00 after clearing (0) bit 6 of IF0 (KRIF00).

3. On-chip pull-up resistors are automatically connected in input mode to the pins specified

for key return signal detection (P40 to P43). Although these resistors are disconnected

when the mode changes to output, key return signal detection continues unchanged.

Figure 6-7. Block Diagram of Falling Edge Detector

Falling edge

detector

KRMK00

KRIF00 setting signal

Standby release signal

Key return mode register 00

(KRM00)

Note

Selector

P40/KR00

P41/KR01

P42/KR02

P43/KR03

Note For selecting the pin to be used as falling edge input.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

7. STANDBY FUNCTION

7.1 Standby Function

A standby function is incorporated to minimize the system’s power consumption. There are two standby modes:

HALT and STOP.

The HALT and STOP modes are selected using the HALT and STOP instructions.

(1) HALT mode

In this mode, the CPU operating clock is stopped. The average current consumption can be reduced by

intermittent operation combining this mode with the normal operation mode.

(2) STOP mode

In this mode, main system clock oscillation is stopped. All operations performed with the main system clock

are suspended, thus minimizing power consumption.

Caution When shifting to STOP mode, execute the STOP instruction after first stopping the operation

of the hardware.

Preliminary Product Information U14558EJ1V0PM00 65

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PD78F9468

Table 7-1. Operation Statuses in HALT Mode

HALT Mode Operati on S tatus During Main

System Cloc k Operation HALT Mode Operation Stat us During Subsystem

Clock Operation

Item

Subsystem Clock

Operating Subsystem Clock

Stopped Mai n Sys tem Cloc k

Operating Mai n S yst em Clock

Stopped

Main system clock Can be oscillated Oscillation stopped

CPU Operation s topped

Ports (output lat ches) Status before HA LT m ode setti ng retained

8-bit ti m er 30, 40 Operable Operation stopped

Watch ti mer Operable OperableNote 1 Operable OperableNote 2

Watchdog ti mer Operable Operation stopped

Power-on-clear c i rcuit Operabl e

Key return circui t Operable

A/D converter Operable Operation stopped

LCD controll e r/ driver OperableNote 3 OperableNotes 1, 3 OperableNote 3 OperableNotes 2, 3

External i nterrupts OperableNote 4

Notes 1. Operation is enabled when the main system clock is selected

2. Operation is enabled when the subsystem clock is selected

3. The HALT instruction can be set after display instruction execution

4. Operation is enabled only for a maskable interrupt that is not masked

Table 7-2. Operation Statuses in STOP Mode

STOP Mode Operation St atus During M ai n System Clock OperationItem

Subsystem Clock Operating Subsystem Clock Stopped

Main system clock Oscillation stopped

CPU Operation s topped

Ports (output lat ches) Status before S T OP mode set ting retained

8-bit ti m er 30, 40 Operation st opped

Watch ti mer OperableNote 1 Operati on stopped

Watchdog ti mer Operati on stopped

Power-on-clear c i rcuit Operabl e

Key return circui t Operable

A/D converter Operation stopped

LCD controll e r/ driver OperableNote 1 Operation st opped

External i nterrupts OperableNote 2

Notes 1. Operation is enabled when the subsystem clock is selected.

2. Operation is enabled only for a maskable interrupt that is not masked

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

7.2 Standby Function Control Register

The oscillation stabilization time selection register (OSTS) is used to control the wait time from the time STOP

mode is released by an interrupt request until oscillation stabilizes.

OSTS is set using an 8-bit memory manipulation instruction.

RESET input sets this register to 04H. Note that the time required for oscillation to stabilize after RESET input will

be 215/fX, rather than 217/fX.

Figure 7-1. Format of Oscillation Stabilization Time Selection Register

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 FFFAH 04H R/W

OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection

000

212/fX(819

010

215/fX(6.55 ms)

100

217/fX(26.2 ms)

Other than above Setti ng prohi bi ted

Caution The wait time required after releasing STOP mode does not include the time (“a” in the following

figure) required for the clock oscillation to restart after STOP mode is released, regardless of

whether STOP mode is released by RESET input or interrupt.

STOP mode release

X1 pin voltage

waveform

Remarks 1. f

X: Main system clock oscillation frequency

2. The parenthesized values apply to operation at fX = 5.0 MHz.

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PD78F9468

8. RESET FUNCTION

8.1 Reset Function

The

PD78F9468 can be reset using the following three signals.

(1) External reset signal input via RESET pin

(2) Internal reset by watchdog timer runaway time detection

(3) Internal reset using power-on-clear circuit (POC)

The external and internal reset signals are functionally equivalent. When RESET is input, program execution

begins from the addresses written at addresses 0000H and 0001H.

If a low-level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each

item of the hardware to enter the states listed in Table 8-1. While a reset is being applied, or while the oscillation

frequency is stabilizing immediately after the end of a reset sequence, each pin remains in the high-impedance state.

If a high-level signal is applied to the RESET pin, the reset sequence is terminated, and program execution begins

once the oscillation stabilization time (215/fX) has elapsed. A reset sequence caused by a watchdog timer overflow is

terminated automatically and again program execution begins upon the elapse of the oscillation stabilization time

(215/fX).

Cautions 1. To use an external reset sequence, input a low-level signal to the RESET pin for at least 10

µµ

2. When a reset is used to release STOP mode, the data of when STOP mode was entered is

retained during the reset sequence, except for the port pins, which are in the high-impedance

state.

Figure 8-1. Reset Function Block Diagram

RESET

Count clock

Reset controller

Watchdog timer

Stop

Over-

flow

Reset signal

Interrupt function

Power-on-clear circuit

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

Table 8-1. Status of Hardware After Reset

Hardware Stat us After Reset

Program counter (PC)Note 1 Contents of reset

vect or t abl e (0000H,

0001H) set

Stack pointer (S P) Undefined

Program st atus word (PSW) 02H

Data memory UndefinedNote 2

RAM

General-purpose regis ters UndefinedNote 2

Ports (P0, P1, P4, P6, P8) (output l atches) 00H

Port mode regi s ters (PM 0, PM1, PM4, P M 6, PM8) FFH

Port function register 8 (PF8) 00H

Pull-up resi stor opti on regi sters (P U0) 00H

Proces sor clock c ontrol regis ter (PCC) 02H

Subclock oscillat i on mode register (SCK M) 00H

Subcloc k cont rol regi s ter (CSS) 00H

Oscillation stabilization time selection register (OSTS) 04H

Timer counters (TM30, TM40) 00H

Compare registers (CR30, CR40, CRH40) Undefined

Mode control regi sters (TM C30, TMC40) 00H

8-bit ti m er 30, 40

Carrier generator output control regi s ter 00H

Watch ti mer Mode control regi ster (WTM) 00H

Watchdog ti mer Mode register (WDTM) 00H

Mode regist er 0 (A DM0) 00H

Input channel specificat i on regi ster 0 (ADS 0) 00H

A/D c onverter

A/D conversion result register 0 (ADCR0) Undefined

Display mode regis ter 0 (LCDM0) 00H

Clock control regi ster 0 (LCDC0) 00H

LCD controll e r/ driver

LCD voltage am pl i ficat i on control register 0 (LCDVA0) 00H

Power-on-clear c i rcuit P ower-on-clear regis t er 1 (POCF1) 00HNote 3

Request fl ag regi ster 0 (IF0) 00H

Mask f l ag regi s ter 0 (MK0) FFH

External i nterrupt mode regi s ter 0 (INTM0) 00H

Interrupts

Key return m ode regi ster 00 (KRM 00) 00H

Notes 1. While a reset signal is being input, and during the oscillation stabilization period, only the contents of

the PC will be undefined; the remainder of the hardware will be the same state as after reset.

2. In standby mode, RAM enters the hold state after reset.

3. The value is 04H only after a power-on-clear reset.

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PD78F9468

8.2 Power Failure Detection Function

When a reset is generated via the power-on-clear circuit, bit 2 (POCOF1) of the power-on-clear register (POCF1)

is set (1). This bit is then cleared (0) by an instruction written to POCF1. After a power-on-clear reset (i.e. after

program execution has started from address 0000H), a power failure can be detected by detecting POCOF1.

Figure 8-2. Format of Power-on-Clear Register 1

Symbol 7 6 5 4 3 2 1 0 Address After reset R/W

POCF1 0 0 0 0 0 POCOF1 0 0 FFDDH 00HNote R/W

POCOF1 Power-on-clear generat i on status detection

0 Power-on-clear not generat ed, or cleared by wri te operation

1 Power-on-clear reset generated

Note The value is 04H only after a power-on-clear reset.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

9. FLASH MEMORY PROGRAMMING

The program memory incorporated in the

PD78F9468 is flash memory.

Writing to flash memory can be performed with the device mounted in the target system (on-board programming).

Writing is performed with a dedicated flash memory programmer (Flashpro III (part number: FL-PR3 and PG-FP3))

connected to the host machine and the target system.

Remark FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.

9.1 Selection of Communication Mode

Writing to flash memory is performed via serial communication using Flashpro III. Select one of the

communication modes from those in Table 9-1. The selection of the communication mode is made by using the

format shown in Figure 9-1. The communication mode is selected by the number of VPP pulses shown in Table 9-1.

Table 9-1. Communication Modes

Communication Mode Pin Used Number of VPP Pulses

Pseudo 3-wire m odeNote P00 (serial c l ock input )

P01 (serial dat a output)

P02 (serial dat a i nput)

Note Ports are controlled by software and serial transfer is performed.

Caution Always select the communication mode using the number of pulses shown in Table 9-1.

Figure 9-1. Communication Mode Selection Format

10 V

RESET

12 n

Preliminary Product Information U14558EJ1V0PM00 71

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PD78F9468

9.2 Flash Memory Programming Functions

Operations such as writing to flash memory are performed by various command/data transmission and reception

operations according to the selected communication mode. Table 9-2 shows the major functions of flash memory

programming.

Table 9-2. Major Functions of Flash Memory Programming

Function Description

Batch erase Deletes t he entire memory contents.

Batch blank check Checks the deletion status of the entire memory.

Data write Writes to flas h m em ory based on the wri te start address and t he num ber of data to

be written (num ber of bytes ).

Batch verify Checks the entire memory contents and the input data.

9.3 Flashpro III Connection Example

An example of the connection between the

PD78F9468 and Flashpro III is shown in Figure 9-2.

Figure 9-2. Connection of Flashpro III Using Pseudo 3-Wire Mode

Note

RESET

SCK

GND

RESET

P00

CLK X1

P02

P01

Flashpro III PD78F9468

Note n = 1, 2

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

9.4 Setting Example Using Flashpro III (PG-FP3)

When using Flashpro III (PG-FP3) to write to flash memory, set as follows.

<1> Download the parameter file

<2> Select the serial mode and serial clock with the type command

<3> A setting example using the PG-FP3 is shown below

Table 9-3. Setting Example Using PG-FP3

Communication Mode Setting Exam pl e Using PG-FP 3 Number of VPP

PulsesNote

COMM PORT Port A

On Target BoardCPU CLK

In Flashpro

On Target Board 4.1943 MHz

SIO CLK 1 kHz

In Flashpro 4.0 MHz

Pseudo 3-wire m ode

SIO CLK 1 kHz

Note The number of VPP pulses supplied from Flashpro III during the initialization of serial communication. The

pins to be used in communication are determined by this number.

Remark COMM PORT: Selection of the serial port

SIO CLK: Selection of the serial clock frequency

CPU CLK: Selection of the input CPU clock source

Preliminary Product Information U14558EJ1V0PM00 73

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PD78F9468

10. INSTRUCTION SET OVERVIEW

The instruction set for the

PD78F9468 is listed in this section.

10.1 Conventions

10.1.1 Operand formats and descriptions

The description made in the operand field of each instruction conforms to the operand format for the instructions

listed below (the details conform to the assembly specification). If more than one operand format is listed for an

instruction, one is selected. Uppercase letters, #, !, $, and brackets [ ] are used to specify keywords, which must be

written exactly as they appear. The meanings of these special characters are as follows:

•#: Immediate data specification

•$: Relative address specification

•!: Absolute address specification

•[ ]: Indirect address specification

Immediate data should be described using appropriate values or labels. The specification of values and labels

must be accompanied by #, !, $, or [ ].

Operand registers, expressed as r or rp in the formats, can be described using both functional names (X, A, C,

etc.) and absolute names (R0, R1, R2, and other names listed in Table 10-1 below).

Table 10-1. Operand Formats and Descriptions

Format Description

sfr

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2 ), HL (RP3)

Special f unction regi s ter sy m bol

saddr

saddrp FE20H to FF1FH Immediate data or label

FE20H to FF1FH Immediat e data or label (even addres ses only )

addr16

addr5

0000H to FFFFH Immediate data or label

(only even addresses for 16-bit dat a transfer i nstructions)

0040H to 007FH Immediate data or l abel (even addresses only)

word

byte

bit

16-bit imm edi ate data or label

8-bit imm edi ate data or label

3-bit imm edi ate data or label

Remark For details concerning special function register symbols, refer to Table 4-1 Special Function

Registers.

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

10.1.2 Operation field definitions

A: A register (8-bit accumulator)

X: X register

B: B register

C: C register

D: D register

E: E register

H: H register

L: L register

AX: AX register pair (16-bit accumulator)

BC: BC register pair

DE: DE register pair

HL: HL register pair

PC: Program counter

SP: Stack pointer

PSW: Program status word

CY: Carry flag

AC: Auxiliary carry flag

Z: Zero flag

IE: Interrupt request enable flag

NMIS: Flag to indicate that a non-maskable interrupt is being processed

(): Contents of a memory location indicated by a parenthesized address or register name

XH, XL: Higher and lower 8 bits of a 16-bit register

∧: Logical product (AND)

∨: Logical sum (OR)

∀: Exclusive OR

: Inverted data

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

10.1.3 Flag operation field definitions

(Blank): No change

0: Clear to 0

1: Set to 1

×: Set or clear according to the result

R: Restore to the previous value

Preliminary Product Information U14558EJ1V0PM00 75

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PD78F9468

10.2 Operations

FlagMnemonic Operand Byte Clock Operation

ZACCY

r, #byt e 3 6 r ← byte

saddr , #by t e 3 6 (saddr) ← byte

sfr, #byte 3 6 sfr ← byte

A, r Note 1 24A

←

r, A Note 1 24r

←

A, saddr 2 4 A ← (saddr)

saddr, A 2 4 (saddr) ← A

A, sfr 2 4 A ← sfr

sfr, A 2 4 sfr ← A

A, !addr16 3 8 A ← (addr16)

!addr16, A 3 8 (addr16) ← A

PSW, #byte 3 6 PSW ← byte ×××

A, PSW 2 4 A ← PSW

PSW, A 2 4 PSW ← A ×××

A, [DE] 1 6 A ← (DE)

[DE], A 1 6 (DE) ← A

A, [HL] 1 6 A ← (HL)

[HL], A 1 6 (HL) ← A

A, [HL + byte] 2 6 A ← (HL + byte)

MOV

[HL + byte], A 2 6 (HL + byte) ← A

A, X 1 4 A ↔ X

A, r Note 2 26A

↔

A, saddr 2 6 A ↔ (saddr)

A, sfr 2 6 A ↔ (sfr)

A, [DE] 1 8 A ↔ (DE)

A, [HL] 1 8 A ↔ (HL)

XCH

A, [HL + byte] 2 8 A ↔ (HL + byte)

rp, #word 3 6 rp ← word

AX, saddrp 2 6 AX ← (s addrp)

saddrp, AX 2 8 (saddrp) ← AX

AX, rp Note 3 1 4 AX ← rp

MOVW

rp, AX Note 3 14rp

←

XCHW AX, rp Note 3 1 8 AX ↔ rp

Notes 1. Except when r = A.

2. Except when r = A or X.

3. Only when rp = BC, DE, or HL.

Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

FlagMnemonic Operand Byte Clock Operation

ZACCY

A, #byte 2 4 A, CY ← A + byte ×××

saddr, #by te 3 6 (saddr), CY ← (saddr) + byt e ×××

A, r 2 4 A, CY ← A + r ×××

A, s addr 2 4 A, CY ← A + (s addr) ×××

A, ! addr16 3 8 A, CY ← A + (addr16) ×××

A, [HL] 1 6 A, CY ← A + (HL) ×××

ADD

A, [HL + byte] 2 6 A, CY ← A + (HL + by te) ×××

A, #byte 2 4 A, CY ← A + byte + CY ×××

saddr, #by te 3 6 (saddr), CY ← (saddr) + byt e + CY ×××

A, r 2 4 A, CY ← A + r + CY ×××

A, s addr 2 4 A, CY ← A + (s addr) + CY ×××

A, ! addr16 3 8 A, CY ← A + (addr16) + CY ×××

A, [HL] 1 6 A, CY ← A + (HL) + CY ×××

ADDC

A, [HL + byte] 2 6 A, CY ← A + (HL + byte) + CY ×××

A, #byte 2 4 A, CY ← A − byte ×××

saddr, #by te 3 6 (saddr), CY ← (saddr) − byte ×××

A, r 2 4 A, CY ← A − r ×××

A, s addr 2 4 A, CY ← A − (saddr) ×××

A, ! addr16 3 8 A, CY ← A − (addr16) ×××

A, [HL] 1 6 A, CY ← A − (HL) ×××

SUB

A, [HL + byte] 2 6 A, CY ← A − (HL + byt e) ×××

A, #byte 2 4 A, CY ← A − byte − CY ×××

saddr, #by te 3 6 (saddr), CY ← (saddr) − byte − CY ×××

A, r 2 4 A, CY ← A − r − CY ×××

A, s addr 2 4 A, CY ← A − (saddr) − CY ×××

A, ! addr16 3 8 A, CY ← A − (addr16) − CY ×××

A, [HL] 1 6 A, CY ← A − (HL) − CY ×××

SUBC

A, [HL + byte] 2 6 A, CY ← A − (HL + byt e) − CY ×××

A, #byte 2 4 A ← A ∧ byte ×

saddr, #by t e 3 6 (saddr) ← (saddr) ∧ byte ×

A, r 2 4 A ← A ∧ r ×

A, saddr 2 4 A ← A ∧ (saddr) ×

A, !addr16 3 8 A ← A ∧ (addr16) ×

A, [HL] 1 6 A ← A ∧ (HL) ×

AND

A, [HL + byte] 2 6 A ← A ∧ (HL + byte) ×

Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control

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PD78F9468

FlagMnemonic Operand Byte Clock Operation

ZACCY

A, #byte 2 4 A ← A ∨ byte ×

saddr, #by t e 3 6 (saddr) ← (saddr) ∨ byte ×

A, r 2 4 A ← A ∨ r×

A, saddr 2 4 A ← A ∨ (saddr) ×

A, !addr16 3 8 A ← A ∨ (addr16) ×

A, [HL] 1 6 A ← A ∨ (HL) ×

A, [HL + byte] 2 6 A ← A ∨ (HL + byte) ×

A, #byte 2 4 A ← A ∀ byte ×

saddr, #by t e 3 6 (saddr) ← (saddr) ∀ byte ×

A, r 2 4 A ← A ∀ r×

A, saddr 2 4 A ← A ∀ (saddr) ×

A, !addr16 3 8 A ← A ∀ (addr16) ×

A, [HL] 1 6 A ← A ∀ (HL) ×

XOR

A, [HL + byte] 2 6 A ← A ∀ (HL + byte) ×

A, #byte 2 4 A − byte ×××

saddr, #by t e 3 6 (saddr) − byte ×××

A, r 2 4 A − r ×××

A, saddr 2 4 A − (s addr) ×××

A, !addr16 3 8 A − (addr16) ×××

A, [HL] 1 6 A − (HL) ×××

CMP

A, [HL + byte] 2 6 A − (HL + byt e) ×××

ADDW AX, #word 3 6 AX, CY ← AX + word ×××

SUBW AX, #word 3 6 AX, CY ← AX − word ×××

CMPW AX, #word 3 6 AX − word ×××

r24r

←

r + 1 ××

INC

saddr 2 4 (saddr) ← (saddr) + 1 ××

r24r

←

r − 1 ××

DEC

saddr 2 4 (saddr) ← (saddr) − 1 ××

INCW rp 1 4 rp ← rp + 1

DECW rp 1 4 rp ← rp − 1

ROR A, 1 1 2 (CY, A7 ← A0, Am−1 ← Am) × 1 ×

ROL A, 1 1 2 (CY, A0 ← A7, Am+1 ← Am) × 1 ×

RORC A, 1 1 2 (CY ← A0, A7 ← CY, Am−1 ← Am) × 1 ×

ROLC A, 1 1 2 (CY ← A7, A0 ← CY, Am+1 ← Am) × 1 ×

Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

FlagMnemonic Operand Byte Clock Operation

ZACCY

saddr.bit 3 6 (saddr.bit) ← 1

sfr.bit 3 6 sfr.bit ← 1

A.bit 2 4 A.bit ← 1

PSW.bit 3 6 PSW bit ← 1 ×××

SET1

[HL].bit 2 10 (HL).bit ← 1

saddr.bit 3 6 (saddr.bit) ← 0

sfr.bit 3 6 sfr.bit ← 0

A.bit 2 4 A.bit ← 0

PSW.bit 3 6 PSW.bit ← 0 ×××

CLR1

[HL].bit 2 10 (HL).bit ← 0

SET1 CY 1 2 CY ← 11

CLR1 CY 1 2 CY ← 00

NOT1 CY 1 2 CY ← CY ×

CALL !addr16 3 6 (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,

PC ← addr16, SP ← SP − 2

CALLT [addr5] 1 8 (SP − 1) ← (P C + 1)H, (SP − 2) ← (PC + 1)L,

PCH ← (00000000, addr5 + 1),

PCL ← (00000000, addr5),

SP ← SP − 2

RET 1 6 PCH ← (SP + 1), PCL ← (SP),

SP ← SP + 2

RETI 1 8 PCH ← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3,

NMIS ← 0

RRR

PSW 1 2 (SP − 1) ← PSW, SP ← SP − 1PUSH

rp 1 4 (SP − 1) ← rpH, (SP − 2) ← rpL,

SP ← SP − 2

PSW 1 4 PSW ← (SP), SP ← SP + 1 R R RPOP

rp 1 6 rpH ← (SP + 1), rpL ← (SP),

SP ← SP + 2

SP, AX 2 8 SP ← AXMOVW

AX, SP 2 6 AX ← SP

!addr16 3 6 PC ← addr16

$addr16 2 6 PC ← PC + 2 + jdisp8

AX 1 6 PCH ← A, PCL ← X

Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control

Preliminary Product Information U14558EJ1V0PM00 79

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PD78F9468

FlagMnemonic Operand Byte Clock Operation

ZACCY

BC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 1

BNC $addr16 2 6 PC ← PC + 2 + jdisp8 if CY = 0

BZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 1

BNZ $addr16 2 6 PC ← PC + 2 + jdisp8 if Z = 0

saddr.bit , $addr16 4 10 P C ← P C + 4 + jdis p8

if (saddr. bi t) = 1

sfr. bi t, $addr16 4 10 PC ← PC + 4 + j disp8 if s f r.bit = 1

A.bit , $addr16 3 8 PC ← PC + 3 + jdisp8 if A . bi t = 1

PSW. bi t, $addr16 4 10 PC ← PC + 4 + jdisp8 if PSW.bit = 1

saddr.bit , $addr16 4 10 P C ← P C + 4 + jdis p8

if (saddr. bi t) = 0

sfr. bi t, $addr16 4 10 PC ← PC + 4 + j disp8 if s f r.bit = 0

A.bit , $addr16 3 8 PC ← PC + 3 + jdisp8 if A . bi t = 0

PSW. bi t, $addr16 4 10 PC ← PC + 4 + disp8 if PSW. bit = 0

B, $addr16 2 6 B ← B − 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0

C, $addr16 2 6 C ← C − 1, then

PC ← PC + 2 + jdisp8 if C ≠ 0

DBNZ

saddr, $addr16 3 8 (s addr) ← (saddr) − 1, t hen

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

NOP 1 2 No Operation

EI 3 6 IE ← 1 (Enable Interrupt)

DI 3 6 IE ← 0 (Disable Int errupt)

HALT 1 2 Set HALT Mode

STOP 1 2 Set STOP Mode

Remark The instruction clock cycle is based on the CPU clock (fCPU) specified by the processor clock control

Preliminary Product Information U14558EJ1V0PM00

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PD78F9468

11. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°

°°

°C)

Parameter Symbol Conditions Ratings Unit

VDD −0.3 to +6.5 V

Supply v ol tage

VPP −0.3 to +10.5 V

Input vol tage V I−0.3 to VDD + 0. 3Note V

VO1 P00 to P03, P10, P 11, P40 to P 43,

P60, P61 −0.3 to VDD + 0.3Note VOutput vol tage

VO2 COM0 to COM3, S0 to S16,

P80/S22 to P85/S 17 −0.3 to VLC0 + 0.3Note V

Pin P60/TO40 −36 mA

Per pin (exc ept P60/TO40) −10 mA

Output current, high IOH

Total for al l pi ns (except P 60/TO40) −30 mA

Per pin 30 mAOutput current, low IOL

Total for al l pi ns 80 mA

Normal operation −40 to +85 °COperating ambient temperat ure TA

Flash memory programming 10 to 40 °C

Storage tem perature Tstg −40 t o +125 °C

Note 6.5 V or lower

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

Preliminary Product Information U14558EJ1V0PM00 81

µµ

PD78F9468

Main System Clock Oscillator Characteristics (TA = −

−−

−40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator Rec om m ended Ci rcuit Parameter Conditions MIN. TYP . MAX . Unit

Oscillati on f requency

(fX)Note 1 1.0 5.0 MHzCeramic

resonator

X1X2V

C1C2

Oscillation

stabilization timeNote 2 After VDD has reached the

oscillation voltage range MIN. 4ms

Oscillation

frequency Note 1 1.0 5.0 MHzCrystal

resonator

X1X2V

C1C2

Oscillation

stabilization timeNote 2 30 ms

X1 input f requency

(fX)Note 1 1.0 5.0 MHzExternal

clock

X1 X2

X1 input high-/low-

level width (tXH, tXL)85 500 ns

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. Time required to stabilize oscillation after reset or STOP mode release.

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

•

••

• Keep the wiring length as short as possible.

•

••

• Do not cross the wiring with other signal lines.

•

••

• Do not route the wiring near a signal line through which a high fluctuating current flows.

•

••

• Always make the ground point of the oscillator capacitor the same potential as VSS.

•

••

• Do not ground the capacitor to a ground pattern through which a high current flows.

•

••

• Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

Subsystem Clock Oscillator Characteristics (TA = −

−−

−40 to +85°C, VDD = 1.8 to 5.5 V)

Resonator Rec om m ended Ci rcuit Parameter Conditions MIN. TYP . MAX . Unit

Oscillati on f requency

(fXT)Note 1 32 32.768 35 kHz

VDD = 4.5 to 5.5 V 1.2 2

Crystal

resonator

XT2XT1V

Oscillation

stabilization timeNote 2 10

XT1 input frequency

(fXT)Note 1 32 35 kHzExternal

clock

XT1 XT2

XT1 input hi gh-/low-

level width (tXTH, tXTL)14.3 15.6

Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

2. The time required for oscillation to stabilize after VDD reaches the MIN. oscillation voltage range. Use a

resonator to stabilize oscillation during the oscillation wait time.

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

•

••

• Keep the wiring length as short as possible.

•

••

• Do not cross the wiring with the other signal lines.

•

••

• Do not route the wiring near a signal line through which a high fluctuating current flows.

•

••

• Always make the ground point of the oscillator capacitor the same potential as VSS.

•

••

• Do not ground the capacitor to a ground pattern through which a high current flows.

•

••

• Do not fetch signals from the oscillator.

2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current

consumption, and is more prone to malfunction due to noise than the main system clock

oscillator. Particular care is therefore required with the wiring method when the subsystem

clock is used.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Preliminary Product Information U14558EJ1V0PM00 83

µµ

PD78F9468

DC Characteristics (TA = −

−−

−40 to +85°C, VDD = 1.8 to 5.5 V) (1/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Per pin 10 mAOutput current, low IOL

Total for al l pi ns 80 m A

Per pin (exc ept P60/TO40) −1mA

P60/TO40 VDD = 3. 0 V, VOH = 1.0 V −7−15 −24 mA

Output current, high IOH

Total for al l pi ns (except P 60/TO40) −15 mA

VDD = 2.7 to 5.5 V 0.7VDD VDD VVIH1 P00 to P03, P 10, P11, P 60

0.9VDD VDD V

VDD = 2.7 to 5.5 V 0.8VDD VDD VVIH2 RESET, P40 to P43, P61

0.9VDD VDD V

VIH3 X1, X2 VDD − 0.1 VDD V

Input vol tage, high

VIH4 XT1, XT2 VDD − 0.1 VDD V

VDD = 2.7 to 5.5 V 0 0.3V DD VVIL1 P00 to P03, P 10, P11, P 60

00.1V

DD V

VDD = 2.7 to 5.5 V 0 0.2V DD VVIL2 RESET, P4 0 to P43, P61

00.1V

DD V

VIL3 X1, X2 0 0.1 V

Input vol tage, low

VIL4 XT1, XT2 0 0.1 V

VOH11 1.8 ≤ VDD ≤ 5.5 V,

IOH = −100

AVDD − 0.5 V

VOH12

P00 to P03, P10, P 11,

P40 to P43, P61

1.8 ≤ VDD ≤ 5.5 V,

IOH = −500

AVDD − 0.7 V

VOH21 1.8 ≤ VDD ≤ 5.5 V,

IOH = −400

AVDD − 0.5 V

VOH22

P60/TO40

1.8 ≤ VDD ≤ 5.5 V,

IOH = −2 mA VDD − 0.7 V

VOH31 1.8 ≤ VDD ≤ 5.5 V,

IOH = −100

AVLC0 − 0.5 V

Output vol tage, high

VOH32

P80/S22 to P85/S 17

1.8 ≤ VDD ≤ 5.5 V,

IOH = −500

AVLC0 − 0.7 V

VOL11 1.8 ≤ VDD ≤ 5.5 V,

IOL = 400

A0.5 V

VOL12

P00 to P03, P10, P 11,

P40 to P43, P60, P 61

1.8 ≤ VDD ≤ 5.5 V,

IOL = 2 mA 0.7 V

VOL21 1.8 ≤ VLC0 ≤ 5.5 V,

IOL = 400

A0.5 V

Output vol tage, low

VOL22

P80/S22 to P85/S 17

1.8 ≤ VLC0 ≤ 5.5 V,

IOL = 2 mA 0.7 V

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V) (2/2)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

ILIH1 P00 to P03, P10,

P11, P40 to P43,

P60, P61, RESET

AInput leak age current,

high

ILIH2

VIN = VDD

X1, X2, XT1, XT2 20

ILIL1 P00 to P03, P10,

P11, P40 to P43,

P60, P61, RESET

−3

AInput leak age current,

low

ILIL2

VIN = 0 V

X1, X2, XT1, XT2 −20

Output leak age current,

high ILOH VOUT = VDD 3

Output leak age current,

low ILOL VOUT = 0 V −3

Software pul l -up

resistors R1VIN = 0 V P00 to P03, P10,

P11, P40 to P43 50 100 200 kΩ

GAIN = 0 0.9 1.0 1.1 VVLC2 output vol tage

characteristics VLC2

GAIN = 1 1.35 1.5 1.65 V

VLC1 output vol tage

characteristics VLC1 2VLC2

– 0.2 2VLC2

– 0.1 2VLC2 V

VLC0 output vol tage

characteristics VLC0 3VLC2

– 0.3 3VLC2

– 0.15 3VLC2 V

VDD = 5.5 VNote 2 5.0 15.0 mAIDD1 5.0 MHz crystal oscillation

operating mode VDD = 3.3 VNote 3 2.0 5.0 mA

VDD = 5.5 V 1.2 3.6 mAIDD2 5.0 MHz crystal oscillation

HALT mode VDD = 3.3 V 0.5 1.5 mA

VDD = 5.5 V 25 55

AIDD4 32.768 kHz crystal

oscillation HALT modeNote 4 VDD = 3.3 V 5 25

VDD = 5.5 V 2 30

Supply c urrentNote 1

Ceramic/crystal

oscillation

IDD5 STOP mode

VDD = 3.3 V 1 10

Notes 1. Current flowing through ports (including current flowing through on-chip pull-up resistors) is not

included.

2. High-speed operation (when the processor clock control register (PCC) is set to 00H).

3. Low-speed operation (when PCC is set to 02H)

4. When the main system clock is stopped.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port

pins.

Preliminary Product Information U14558EJ1V0PM00 85

µµ

PD78F9468

AC Characteristics

(1) Basic operation (TA = −

−−

−40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

VDD = 2.7 to 5.5 V 0.4 8.0

sCycle time

(Min. instruction exec ution ti m e) TCY

1.6 8.0

Interrupt i nput

high-/low-l evel widt h tINTH,

tINTL

INT 10

Key return pi n

low-level width tKRIL KR00 to KR03 10

RESET low-level width tRSL 10

TCY vs. VDD (Main System Clock)

Supply voltage V

(V)

123456

0.1

0.4

0.5

1.0

2.0

Cycle time T

[ s]

Guaranteed

operation

range

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

AC Timing Measurement Point (Excluding X1, XT1 Input)

0.8V

0.2V

Point of measurement

0.8V

0.2V

Clock Timing

1/f

X1 input V

IH3

(MIN.)

IL3

(MAX.)

1/f

XTL

XTH

XT1 input V

IH4

(MIN.)

IL4

(MAX.)

Interrupt Input Timing

INT

INTL

INTH

Key Return Input Timing

KR00 to KR03

KRIL

RESET Input Timing

RESET

RSL

Preliminary Product Information U14558EJ1V0PM00 87

µµ

PD78F9468

8-Bit A/D Converter Characteristics (TA = −

−−

−40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Resolution 888bit

VDD = 2.7 to 5.5 V ±1.0 ±1.5 %FSR

Overall errorNote

±1.5 ±2.0 %FSR

VDD = 2.7 to 5.5 V 14 100

sConversion time tCONV

28 100

Note Excludes quantization error (±0.2%)

Remark FSR: Full scale range

LCD Characteristics (TA = −

−−

−40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

LCD drive vo l tage VLCD 1.8 5.5 V

LCD division resi stance RLCD 50 100 200 kΩ

LCD output voltage dif ferentialNote

(common) VODC IO = ±5

LCD = VLC0,

VLC1 = 2/3 • VLC0,

VLC2 = 1/3 • VLC0

0±0.2 V

LCD output voltage dif ferentialNote

(segment) VODS IO = ±1

LCD = VLC0,

VLC1 = 2/3 • VLC0,

VLC2 = 1/3 • VLC0

0±0.2 V

Note The voltage differential is the difference between the output voltage and the ideal value of the segment and

common signal outputs.

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics

(TA = −

−−

−40 to +85°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Data retenti on supply voltage VDDDR 1.8 3.6 V

Low voltage det ection (P OC) voltage VPOC Response t i me: 2 ms Note 1 1.8 1.9 2.0 V

Power supply rise time tPth VDD: 0 V → 1.8 V 0.01 100 ms

Release si gnal set ti m e tSREL STOP released by RESET 10

Cancelled by RESET 215/fXs

Oscillation stabilization wait timeNote 2 tWAIT

Cancelled by i nterrupt request Note 3 s

Notes 1. The response time is the time until the output is inverted following detection of voltage by POC, or the

time until operation stabilizes after the shift from the operation stopped state to the operating state.

2. The oscillation stabilization time is the amount of time the CPU operation is stopped in order to avoid

unstable operation at the start of oscillation. Program operation does not start until both the oscillation

stabilization time and the time until oscillation starts have elapsed.

3. Selection of 212/fX, 215/fX, and 217/fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation

stabilization time selection register (OSTS) (refer to 7.2 Standby Function Control Register).

Remark fX: Main system clock oscillation frequency

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

Data Retention Timing

Data retention mode

STOP mode

HALT mode

Internal reset operation

Operating mode

SREL

WAIT

STOP instruction execution

DDDR

RESET

Data retention mode

STOP mode

HALT mode

Operating mode

SREL

WAIT

STOP instruction execution

DDDR

Standby release signal

(interrupt request)

Writing and Erasing Characteristics (TA = 10 to 40°

°°

°C, VDD = 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Write current (V DD pin) IDDW When VPP supply voltage = V PP1

(at 5.0 MHz operation) 18Note mA

Write current (V PP pi n) IPPW When VPP suppl y volt age = VPP1 7.5 mA

Erase current (VDD pin) IDDE When VPP supply voltage = V PP1

(at 5.0 MHz operation) 18Note mA

Erase current (VPP pin) IPPE When VPP suppl y volt age = VPP1 100 mA

Unit erase t i me ter 111s

Total erase t i me tera 20 s

Number of overwri tes Erase and writ e i s consi dered as 1

cycle 20 Times

VPP0 Normal operation 0 0.2VDD VVPP supply v ol tage VPP1 Flash memory programming 9.7 10.0 10.3 V

Note Excludes current flowing through ports (including on-chip pull-up resistors)

Preliminary Product Information U14558EJ1V0PM00 89

µµ

PD78F9468

APPENDIX A. DIFFERENCES BETWEEN

µµ

PD78F9468 AND MASK ROM VERSIONS

The

PD78F9468 is a product provided with flash memory in place of the internal ROM of the mask ROM

versions. Table A-1 shows the differences between the flash memory (

PD78F9468) and the mask ROM versions.

Table A-1. Differences Between

µµ

PD78F9468 and Mask ROM Versions

Flash Memory Version Mask ROM VersionItem

PD78F9468

PD789462

PD789464

PD789466

PD789467

ROM 32 KB

(flash memory) 4 KB 8 KB 16 KB 24 KB

High-speed RAM 512 bytes

Internal

memory

LCD display RAM 24 bytes

IC0 pin Not provided P rovided

VPP pin Provided Not provided

Elect ri cal spec i ficat i ons There may be di fferences between mask ROM and f l ash memory versions .

Caution There are differences in the amount of noise tolerance and noise radiation between flash

memory versions and mask ROM versions. When considering changing from a flash memory

version to a mask ROM version during the process from experimental manufacturing to mass

production, make sure to sufficiently evaluate commercial samples (CS) (not engineering

samples (ES)) of the mask ROM versions.

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD78F9468.

Language Processing Software

RA78K0SNotes 1, 2, 3 Assembl er package com mon to 78K/ 0S Series

CC78K0SNo t es 1, 2 ,3 C compil er package c om m on to 78K/0S Series

DF789468Notes 1, 2, 3, 5 Device file for

PD789467 Subseri es

CC78K0S–LNotes 1, 2, 3 C compil er library source f i l e common to 78K/0S Series

Flash Memory Writing Tools

Flashpro II I

(Part number: FL-PR3Note 4, PG-FP3) Dedicated f l ash memory program m er

FA-52GBNotes 4, 5 Adapter f or wri ting to f l ash memory designed for 52-pin pl astic LQFP (GB-8ET t ype)

Debugging Tools

IE-78K0S-NS

In-circ ui t emulat or In-circuit em ul at or to debug hardware or software when application systems using the

78K/0S S eri es are developed. The IE-78K 0S-NS support s an integrat ed debugger

(ID78K0S-NS ). The IE-78K 0S-NS is used in com bi nat i on wi th an interf ace adapter for

connect i on t o an AC adapter, em ul at i on probe, or host machine.

IE-70000-MC-PS-B

AC adapter AC adapter to supply power f rom a 100- to 240-V AC out l et .

IE-70000-98-IF-C

Interface adapter Interface adapter required when us i ng a PC-9800 series computer (ex cept notebook ty pe)

as the hos t m achine for t he IE-78K0S -NS (C bus supported).

IE-70000-CD-IF-A

PC card interface PC card and int erface cabl e requi red when a notebook PC i s used as t he hos t machi ne for

the IE -78K 0S-NS (PCM CIA s ocket supported).

IE-70000-PC-IF-C

Interface adapter Interface adapter required when us i ng an IBM P C/ AT™ or compat i bl e as the hos t m achine

for the IE-78K0S-NS (ISA bus supported).

IE-70000-PCI-IF

Interface adapter Interface adapter required when us i ng a PC incorporat i ng a P CI bus as the host m achine

for the IE-78K0S-NS .

IE-789468-NS-EM1Note 5

Emulat i on board Emulation board to emulat e t he peri pheral hardware specif i c to the device. The IE-

789468-NS-EM1 is used in combinati on wi th the in-c i rcuit em ul at or.

NP-52GBNo t es 4, 5 Board to connect an in-circuit em ul at or to the target system. This board is dedicated for a

52-pin plasti c LQFP (GB-8ET type).

SM78K0SNotes 1, 2 System simulator c om m on to 78K/0S Series

ID78K0S-NSNotes 1, 2 Int egrated debugger comm on to 78K/0S Series

DF789468Notes 1, 2, 5 Device file for

PD789467 Subseri es

Notes 1. Based on the PC-9800 series (Japanese Windows™)

2. Based on IBM PC/AT or compatibles (Japanese/English Windows)

3. Based on the HP9000 series 700™ (HP-UX™), SPARCstation™ (SunOS™, Solaris™), and NEWS™

(NEWS-OS™)

4. Manufactured by Naito Densei Machida Mfg. Co, Ltd. (+81-44-822-3813). Contact an NEC distributor

regarding the purchase of these products.

5. Under development

Remark The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789468 device file.

Preliminary Product Information U14558EJ1V0PM00 91

µµ

PD78F9468

Real-Time OS

MX78K0SNotes 1, 2 OS for 78K/0S Series

Notes 1. Based on the PC-9800 series (Japanese Windows)

2. Based on IBM PC/AT or compatibles (Japanese/English Windows)

Preliminary Product Information U14558EJ1V0PM00

µµ

PD78F9468

APPENDIX C. RELATED DOCUMENTS

Documents Related to Devices

Document No.Document Nam e

Japanese English

PD789462, 789464, 789466, 789467 Prelimi nary Product Informat i on To be prepared To be prepared

PD78F9468 Prelim i nary Product Informat i on U14558J This document

PD789327, 789467 Subs eri es User’s Manual To be prepared To be prepared

78K/0S S eri es User’s Manual Instruc t i ons U11047J U11047E

78K/0, 78K/0S S eri es Application Not e Fl ash Memory Wri te U14458J To be prepared

Documents Related to Development Tools (User’s Manuals)

Document No.Document Nam e

Japanese English

Operation U11622J U11622E

Assembly Language U11599J U11599E

RA78K0S Ass em bler Package

Structured Assembly Language U11623J U11623E

Operation U11816J U11816ECC78K0S C Compi l e r

Language U11817J U11817E

SM78K0S S yst em S i m ul ator Windows B ased Referenc e U11489J U11489E

SM78K S eri es System S i m ul ator External Part User Open

Interface Speci ficat i ons U10092J U10092E

ID78K0S-NS Integrated Debugger Wi ndows Based Ref erence U12901J U12901E

IE-78K0S -NS In-ci rcuit E m ul ator U13549J U13549E

IE-789468-NS-E M1 Emulation Board To be prepared To be prepared

Documents Related to Embedded Software (User’s Manuals)

Document No.Document Nam e

Japanese English

78K/0S S eri es OS MX 78K0S Fundamental U12938J U12938E