Automotive Power
Data Sheet
Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
coreFLEX
Data Sheet 2 V3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2 Description of Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.3 Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1 Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Functional Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5 Electrical and Functional Description of Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Power Supply & Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.3 Power Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3.1 Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Diagnostic Functions and FAULT-Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.5 SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Control of the Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1 Output Stage Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.1 Parallel Control and PRG - Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.2 Serial Control of the Outputs: SPI Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1.4 Control- and Data Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.1.5 Control Byte - Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.5.1 Control Byte No.1 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1.5.2 Control Byte No. 2 and 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1.5.3 Control Byte No. 3 and 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.5.4 Control Byte No. 4 and 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.5.5 Control Byte No. 5 and 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.5.6 Example for an access to channel 1 to 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.2.1 Diagnosis Read-out options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7 Application Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.1 Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2 Engine Management Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.3 Daisy Chain Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
8 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table of Contents
PG-DSO-36
Type Package Marking
TLE6240GP PG-DSO-36 TLE6240GP
Data Sheet 3 Rev.3.3, 2010-02-15
Smart 16-Channel Low-Side Switch
coreFLEX
TLE6240GP
1Overview
Features
• Short Circuit Protection
• Overtemperature Protection
• Overvoltage Protection
• 16 bit Serial Data Input and Diagnostic Output
(2 bit/channel for Open Load- and Short to GND detection)
• Direct Parallel Control of eight channels for PWM Applications
• Parallel Inputs High or Low Active programmable
• General Fault Flag
• Low Quiescent Current
• Compatible with 3 V Microcontrollers
• Electrostatic discharge (ESD) Protection
• Green Product (RoHS compliant)
• AEC Qualified
Applications
• Automotive and Industrial Systems
• Solenoids, Relays and Resistive Loads
General Description
16-fold Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and 16 open
drain DMOS output stages. The TLE6240GP is protected by embedded protection functions and designed for
automotive and industrial applications. The output stages are controlled via SPI Interface. Additionally 8 channels
can be controlled direct in parallel for PWM applications. Therefore the TLE6240GP is particularly suitable for
engine management and powertrain systems, safety and body applications.
TLE6240GP
Smart 16-Channel Low-Side Switch
Overview
Data Sheet 4 Rev.3.3, 2010-02-15
Product Summary
Block Diagram
Figure 1 Application Block Diagram
Parameter Symbol Value Unit
Supply voltage VS4.5 … 5.5 V
Drain source clamping voltage VDS(AZ)max 45 .... 60 V
On resistance RON1-8 (max @ 150°C) 2.2 Ω
RON10,11,14,15 (max @ 150°C) 0.7 Ω
RON9,12,13,16 (max @ 150°C) 0.6 Ω
Nominal Output current (channel 1 - 8) ID0.5 A
Nominal Output current (channel 9 - 16) ID1A
Minimum Output current Limit (channel 1 - 8) ID(lim)_min 1A
Minimum Output current Limit (channel 9 - 16) ID(lim)_min 3A
Data Sheet 5 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Block Diagram
2BlockDiagram
2.1 Detailed Block Diagram
Figure 2 Detailed Block Diagram
2.2 Description of Block Diagram
All 16 channels can be controlled via the serial interface (SPI). In addition to the serial control it is possible to
control channel 1 to 4 and 9 to 12 direct in parallel with a separate input pin. The parallel input signal is either OR
- operated or AND - operated with the respective SPI data bit. This boolean operation can be programmed via SPI
control byte (see Chapter 5). The SPI interface also performs a diagnostic information for each channel.
TLE6240GP
Smart 16-Channel Low-Side Switch
Block Diagram
Data Sheet 6 Rev.3.3, 2010-02-15
2.3 Terms
Figure 3 Terms for Voltages and Currents
D SO -36 ( Power )_ ter m s_T LE 6240 . vs d
V
OUT10
V
OUT2
V
IN 1
V
IN 2
V
S
V
RESET
V
CS
V
PR G
V
IN 3
V
IN 4
V
OUT3
V
OUT11
V
OUT4
V
IN 4
V
OUT16
V
SO
V
FAULT
V
OUT6
V
Ba tt
I
OUT7
I
OUT6
I
IN 1 1
I
IN 1 0
I
SI
I
SC L K
I
SO
I
FAULT
I
OUT10
I
OUT2
I
OUT3
I
OUT11
I
IN 1
I
IN 2
I
S
I
R ESET
I
CS
I
PR G
I
IN 3
I
IN 4
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
18
36
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
12
35
PG-DSO-36
GND
OUT9
OUT10
OUT1
OUT2
IN1
IN2
VS
RESET
CS
PRG
IN3
IN4
OUT3
OUT4
OUT11
OUT12
GND
GND
OUT16
OUT15
OUT8
OUT7
IN12
IN11
SI
SCLK
SO
FAULT
IN10
IN9
OUT6
OUT5
OUT14
OUT13
GND
I
OUT9
I
OUT1
I
OUT4
I
OUT12
V
OUT9
V
OUT1
V
OUT4
V
OUT12
I
OUT16
I
OUT15
I
OUT8
I
IN 1 2
I
IN 9
I
OUT5
I
OUT14
I
OUT13
V
OUT15
V
OUT8
V
OUT7
V
IN 1 2
V
IN 1 1
V
SI
V
SC L K
V
IN 1 0
V
IN 9
V
OUT5
V
OUT14
V
OUT13
Data Sheet 7 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 4 Pin Configuration (top view)
3.2 Pin Definitions and Functions
Pin Symbol Function
1GND Ground
2OUT9 Power Output Channel 9
3OUT10 Power Output Channel 10
4OUT1 Power Output Channel 1
5OUT2 Power Output Channel 2
6IN1 Input Channel 1
7IN2 Input Channel 2
8VSSupply Voltage
9 RESET Reset
10 CS Chip Select
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
36
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
11
35
PG-DSO-36
D SO- 36(Pow er )_ TLE 6240 . vsd
GND
OUT9
OUT10
OUT1
OUT2
IN1
IN2
VS
RESET
CS
PRG
IN3
IN4
OUT3
OUT4
OUT11
OUT12
GND
GND
OUT16
OUT15
OUT8
OUT7
IN12
IN11
SI
SCLK
SO
FAULT
IN10
IN9
OUT6
OUT5
OUT14
OUT13
GND
TLE6240GP
Smart 16-Channel Low-Side Switch
Pin Configuration
Data Sheet 8 Rev.3.3, 2010-02-15
Heat Slug internally connected to ground pins
11 PRG Program (inputs high or low-active)
12 IN3 Input Channel 3
13 IN4 Input Channel 4
14 OUT3 Power Output Channel 3
15 OUT4 Power Output Channel 4
16 OUT11 Power Output Channel 11
17 OUT12 Power Output Channel 12
18 GND Ground
19 GND Ground
20 OUT13 Power Output Channel 13
21 OUT14 Power Output Channel 14
22 OUT5 Power Output Channel 5
23 OUT6 Power Output Channel 6
24 IN9 Input Channel 9
25 IN10 Input Channel 10
26 FAULT General Fault Flag
27 SO Serial Data Output
28 SCLK Serial Clock
29 SI Serial Data Input
30 IN11 Input Channel 11
31 IN12 Input Channel 12
32 OUT7 Power Output Channel 7
33 OUT8 Power Output Channel 8
34 OUT15 Power Output Channel 15
35 OUT16 Power Output Channel 16
36 GND Ground
Pin Symbol Function
Data Sheet 9 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Maximum Ratings and Operating Conditions
4 Maximum Ratings and Operating Conditions
4.1 Absolute Maximum Ratings
Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the
data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are
not designed for continuous repetitive operation.
Absolute Maximum Ratings 1)
Tj = -40 °C to +150 °C; all voltages with respect to ground, positive current flowing into pin
(unless otherwise specified)
1) Not subject to production test, specified by design.
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Max.
Voltages
4.1.1 Supply voltage VS-0.3 7 V –
4.1.2 Continuous Drain Source Voltage
(OUT1 to OUT16)
VDS –45V–
4.1.3 Input Voltage, All Inputs and Data Lines VIN -0.3 7 V –
Currents
4.1.4 Output current per Channel
(see Chapter 5)
ID(lim) –ID(lim) min A–
4.1.5 Output current per Channel
(All 16 Channels ON; Mounted on PCB)2)
2) Output current rating so long as maximum junction temperature is not exceeded. At TA = 125 °C the output current has to
be calculated using RthJA according mounting conditions.
ID 1-8 –0.3ATA = 25 °C
ID 9-16 –0.5ATA = 25 °C
4.1.6 Output current
(Max. total current of all channels on; Heat
Sink required)
IDmax –14A–
ESD Susceptibility
4.1.7 Electrostatic Discharge Voltage VESD – 2000 V HBM3)
3) Human Body Model according to EIA/JESD22-A114-E.
TLE6240GP
Smart 16-Channel Low-Side Switch
Maximum Ratings and Operating Conditions
Data Sheet 10 Rev.3.3, 2010-02-15
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical
characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
Temperature Range
4.2.1 Operating Temperature Range Tj-40 – 150 °C–
4.2.2 Storage Temperature Range Tstg -55 – 150 °C–
Single Pulse Inductive Energy
4.2.3 Single pulse inductive Energy (internal
clamping)
EAS ––50mJTJ = 25 °C;
ID1-8 = 0.5 A;
ID9-16 = 1 A
Power Dissipation
4.2.4 Power Dissipation (mounted on PCB) Ptot –3.3–WTA = 25 °C
all Channel
active
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
4.3.1 Junction to Case (die soldered on heat
slug)1)
1) Not subject to production test, specified by design.
RthJSp – 0.5 1 K/W Pv = 3W
4.3.2 Junction to ambient (see Figure 51)); all
channels active
RthjA –12– K/WPv = 3W
Data Sheet 11 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Maximum Ratings and Operating Conditions
Figure 5 Thermal Simulation - PCB set-up
70µm modeled (traces)
35µm, 90% metalization
35µ
m
,
90%
m
e
talizati
on
1
,5
mm
70
µ
m
,
5% metalization
Dimensions: 76.2 x 114.3 x 1.5 mm³ ; Material: FR4
Thermal Vias: diameter= 0.3 mm; plating 25 µm; 61 pcs.
Metalization accodring: JEDEC 2s2p (JESD 51-7) + (JESD 51-5)
Ther mal_Setup.vsd
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Data Sheet 12 Rev.3.3, 2010-02-15
5 Electrical and Functional Description of Blocks
The TLE6240GP is an 16-fold low-side power switch which provides a serial peripheral interface (SPI) to control
the 16 power DMOS switches, and diagnostic feedback. The power transistors are protected against short to VBB,
overload, overtemperature and against overvoltage by active zener clamp.
The diagnostic logic recognizes a fault condition which can be read out via the serial diagnostic output (SO).
5.1 Power Supply & Reset
RESET - Reset pin. If the reset pin is in a logic low state, it clears the SPI shift register and switches all outputs
OFF. An internal pull-up structure is provided on chip. In case the RESET Pin is pulled down statically, the device
remains in Stand-by Mode
5.2 Digital Inputs
In this chapter is the electrical behavior of the following Digital Input Pins described:
• parallel Input Pin INx
• Reset Pin RESET
• Program Pin PRG
Electrical Characteristics: Power Supply
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.1.1 Supply Voltage1)
1) For VS < 4.5 V the power stages are switched according the input signals and data bits or are definitely switched off. This
undervoltage reset gets active at VS = 3 V (typ. value) and is specified by design and not subject to production test.
VS4.5 – 5.5 V –
5.1.2 Supply Current IS–510mA–
5.1.3 Supply Current in Standby Mode IS(stdy) –1050µA (RESET = L)
Electrical Characteristics: Digital Inputs
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.2.1 Input Low Voltage VINL -0.3 – 1.0 V –
5.2.2 Input High Voltage VINH 2.0 – – V –
5.2.3 Input Voltage Hysteresis VINHys 50 100 200 mV –
5.2.4 Input Pull-down/up Current
(IN1 to IN4, IN9 to IN12)
IIN(1..4,9..12) 20 50 100 µAVIN = 5 V
5.2.5 PRG, Reset Pull-up Current IIN(PRG,Res) 20 50 100 µA–
5.2.6 Minimum Reset Duration
(After a reset all parallel inputs are
ORed with the SPI data bits)
tReset,min 10 – – µs–
Data Sheet 13 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
5.3 Power Outputs
Power Transistor Protection Functions1)
Each of the 16 output stages has its own zener clamp, which causes a voltage limitation at the power transistor
when solenoid loads are switched off. The outputs are provided with a current limitation set to a minimum of 1 A
for channels 1 to 8 and 3 A for channels 9 to 16.
In the event of an overload or short to supply, the current is internally limited and the corresponding diagnosis bit
combination is set. If this operation leads to an overtemperature condition, a second protection level will change
the output into a low duty cycle PWM (selective thermal shut-down with restart) to prevent critical chip
temperatures.
1) The integrated protection functions prevent an IC destruction under fault conditions and may not be used in normal
operation or permanently.
Electrical Characteristics: Power Outputs
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.3.1 ON Resistance VS = 5 V;
Channel 1-8
RDS(ON) –1–ΩTJ = 25 °C1)
1) Specified by design and not subject to production test.
–1.72.2ΩTJ = 150 °C
5.3.2 ON Resistance VS = 5 V;
Channel 10, 11, 14, 15
RDS(ON) –0.35–ΩTJ = 25 °C1)
–0.600.70ΩTJ = 150 °C
5.3.3 ON Resistance VS = 5 V;
Channel 9, 12, 13, 16
RDS(ON) –0.30–ΩTJ = 25 °C1)
–0.500.60ΩTJ = 150 °C
5.3.4 Output Clamping Voltage
Channel 1-8
VDS(AZ) 45 50 60 V Output OFF
5.3.5 Output Clamping Voltage
Channel 9-16
VDS(AZ) 45 52.5 60 V Output OFF
5.3.6 Current Limit Channel 1-8 ID(lim) 11.52A–
5.3.7 Current Limit Channel 9-16 ID(lim) 34.56A–
5.3.8 Output Leakage Current ID(lkg) ––10µAVReset = L
5.3.9 Turn-On Time tON –612µsID = 0.5 A,
resistive load
5.3.10 Turn-Off Time tOFF –612µs
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Data Sheet 14 Rev.3.3, 2010-02-15
Figure 6 Timing
5.3.1 Typical Characteristics
Drain-Source On-Resistance
RDS(ON) = f(Tj); VS = 5 V
Figure 7 Typical ON Resistance versus Junction-Temperature (Channel 1-8)
Figure 8 Typical ON Resistance versus Junction-Temperature (Channel 10, 11, 14, 15)
t
t
tON tOFF
80%
VDS
VIN
20%
Typical Drain-Source ON- Resistance
0,6
0,7
0,8
0,9
1
1,1
1,2
1,3
1,4
1,5
1,6
1,7
1,8
-50 -25 0 25 50 75 100 125 150 175
Tj [°C]
RDS(ON) [Ohm]
Channel 1 - 8
Typical Drain-Source ON- Resistance
0,2
0,25
0,3
0,35
0,4
0,45
0,5
0,55
0,6
0,65
-50 -25 0 25 50 75 100 125 150 175
Tj [°C]
RDS(ON) [Ohm]
Channel 10,11,14,15
Data Sheet 15 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Figure 9 Typical ON Resistance versus Junction-Temperature (Channel 9, 12, 13, 16)
Output Clamping Voltage
VDS(AZ) = f(Tj); VS = 5 V
Figure 10 Typical Clamping Voltage versus Junction Temperature (Channel 1-8)
Typical Drain-Source ON- Resistance
0,15
0,2
0,25
0,3
0,35
0,4
0,45
0,5
0,55
-50 -25 0 25 50 75 100 125 150 175
Tj [°C]
RDS(ON) [Ohm]
Channel 9,12,13,16
Typical Clamping Voltage
46
47
48
49
50
51
52
53
54
-50 -25 0 25 50 75 100 125 150 175
Tj [°C]
V
DS(AZ) [V]
Channel 1-8
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Data Sheet 16 Rev.3.3, 2010-02-15
Figure 11 Typical Clamping Voltage versus Junction Temperature (Channel 9-16)
Typical Clamping Voltage
48
49
50
51
52
53
54
55
56
-50 -25 0 25 50 75 100 125 150 175
T
j
[
°C
]
V
DS(AZ) [V]
Channel 9-16
Data Sheet 17 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
5.4 Diagnostic Functions and FAULT-Pin
The device provides diagnosis information about the device and about the load. There are following diagnosis
flags implemented for each channel:
• The diagnosis information of the protective functions, such as “over current” and “over temperature”
• The open load diagnosis
• The short to ground information.
For further details, refer to the Chapter “Control of the device”
FAULT - Fault pin. There is a general fault pin (open drain) which shows a high to low transition as soon as an
error occurs for any one of the sixteen channels. This fault indication can be used to generate a µC interrupt.
Therefore a ‘diagnosis’ interrupt routine need only be called after this fault indication. This saves processor time
compared to a cyclic reading of the SO information.
As soon as a fault occurs, the fault information is latched into the diagnosis register. A new error will overwrite the
old error report. Serial data out pin (SO) is in a high impedance state when CS is high. If CS receives a LOW signal,
all diagnosis bits can be shifted out serially.
Electrical Characteristics: Diagnostic Functions
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.4.1 Open Load Detection Voltage VDS(OL) VS - 2.5 VS - 2 VS - 1.3 V –
5.4.2 Output Pull-down Current IPD(OL) 50 90 150 µAVReset = H
5.4.3 Fault Delay Time td(fault) 50 100 200 µs–
5.4.4 Short to Ground Detection Voltage VDS(SHG) VS - 3.3 VS - 2.9 VS - 2.5 V –
5.4.5 Short to Ground Detection Current ISHG -50 -100 -150 µAVReset = H
5.4.6 Overload Detection Threshold ID(lim) 1-8 11.32A–
ID(lim) 9-16 346A–
5.4.7 Overtemperature Shutdown
Threshold1)
1) Specified by design and not subject to production test.
Tth(sd) 170 – 200 °C–
5.4.8 Overtemperature Hysteresis1) Thys –10–K–
5.4.9 FAULT Output Low Voltage VfaultL ––0.4VIfaultL = 1.6 mA
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Data Sheet 18 Rev.3.3, 2010-02-15
5.5 SPI Interface
Electrical Characteristics: SPI Interface
VS = 4.5 V to 5.5 V, Tj = -40 °C to +150 °C, Reset = H (unless otherwise specified)
all voltages with respect to ground, positive current flowing into pin
Pos. Parameter Symbol Limit Values Unit Conditions
Min. Typ. Max.
5.5.1 Input Pull-down Current (SI, SCLK) IIN(SI,SCLK) 10 20 50 µA–
5.5.2 Input Pull-up Current (CS)IIN(CS) 10 20 50 µA–
5.5.3 SO High State Output Voltage VSOH VS - 0.4 – – V ISOH = 2 mA
5.5.4 SO Low State Output Voltage VSOL ––0.4VISOL = 2.5 mA
5.5.5 Output Tri-state Leakage Current ISOlkg -10 0 10 µACS = H;
0 ≤ VSO ≤ VS
5.5.6 Serial Clock Frequency
(depending on SO load)
fSCK DC – 5 MHz –
5.5.7 Serial Clock Period (1/fclk)tp(SCK) 200 – – ns –
5.5.8 Serial Clock High Time tSCKH 50 – – ns –
5.5.9 Serial Clock Low Time tSCKL 50 – – ns –
5.5.10 Enable Lead Time (falling edge of
CS to rising edge of CLK)
tlead 200 – – ns –
5.5.11 Enable Lag Time (falling edge of
CLK to rising edge of CS)
tlag 200 – – ns –
5.5.12 Data Setup Time (required time SI
to falling of CLK)
tSU 20 – – ns –
5.5.13 Data Hold Time (falling edge of
CLK to SI)
tH20 – – ns –
5.5.14 Disable Time (@ CL = 50 pF)1)
1) This parameter will not be tested but specified by design
tDIS ––150ns–
5.5.15 Transfer Delay Time2)
(CS high time between two
accesses)
2) This time is necessary between two write accesses to control e.g. channel 1 to 8 during the first access and channel 9 to
16 during the second access. To get the correct diagnostic information, the transfer delay time has to be extended to the
maximum fault delay time td(fault)max = 200 µs.
tdt 200 – – ns –
5.5.16 Data Valid Time tvalid ––100nsCL = 50 pF1)
––120nsCL = 100 pF1)
––150nsCL = 220 pF1)
Data Sheet 19 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Figure 12 Input Timing Diagram
Figure 13 SO Valid Time Waveforms and Enable and Disable Time Waveforms
SPI Signal Description
CS - Chip Select. The system microcontroller selects the TLE6240GP by means of the CS pin. Whenever the pin
is in a logic low state, data can be transferred from the µC and vice versa.
•CS High to Low Transition:
– diagnostic status information is transferred from the power outputs into the shift register
– serial input data can be clocked in from then on
– SO changes from high impedance state to logic high or low state corresponding to the SO bits
•CS Low to High Transition:
– transfer of SI bits from shift register into output buffers
To avoid any false clocking the serial clock input pin SCLK should be logic low state during high to low transition
of CS. When CS is in a logic high state, any signals at the SCLK and SI pins are ignored and SO is forced into a
high impedance state.
SCLK - Serial Clock. The system clock pin clocks the internal shift register of the TLE6240GP. The serial input
(SI) accepts data into the input shift register on the falling edge of SCLK while the serial output (SO) shifts
tlead
tSCKH
0.2VS
tlag
tH
tSCKL
0.2 VS
tSU
0.7VS
0.2VS
CS
SCLK
SI
0.7VS
tdt
0.7VS
tvalid
SCLK
CS
SO
tDis
0.2 VS
SO
0.7 VS
0.7 VS
0.2 VS
SO
0.7 VS
0.2 VS
TLE6240GP
Smart 16-Channel Low-Side Switch
Electrical and Functional Description of Blocks
Data Sheet 20 Rev.3.3, 2010-02-15
diagnostic information out of the shift register on the rising edge of serial clock. It is essential that the SCLK pin is
in a logic low state whenever chip select CS makes any transition.
SI - Serial Input. Serial data bits are shifted in at this pin, the most significant bit first. SI information is read in on
the falling edge of SCLK. Input data is latched in the shift register and then transferred to the control buffer of the
output stages.
The input data consist of 16 bit, made up of one control byte and one data byte. The control byte is used to program
the device, to operate it in a certain mode as well as providing diagnostic information (see Chapter 6.2). The eight
data bits contain the input information for the eight channels, and are high active.
SO - Serial Output. Diagnostic data bits are shifted out serially at this pin, the most significant bit first. SO is in a
high impedance state until the CS pin goes to a logic low state. New diagnostic data will appear at the SO pin
following the rising edge of SCLK.
Data Sheet 21 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6 Control of the Device
6.1 Output Stage Control
The 16 outputs of the TLE6240GP can be controlled via serial interface. Additionally eight of these 16 channels
can alternatively be controlled in parallel (Channel 1 to 4 and 9 to 12) for PWM applications.
6.1.1 Parallel Control and PRG - Pin
A Boolean operation (either AND or OR) is performed on each of the parallel inputs and respective SPI data bits,
in order to determine the states of the respective outputs. The type of Boolean operation performed is programmed
via the serial interface.
The parallel inputs are high or low active depending on the PRG pin. If the parallel input pins are not connected
(independent of high or low activity) it is guaranteed that the outputs 1 to 4 and 9 to 12 are switched off. The PRG
pin itself is internally pulled up when it is not connected.
PRG - Program pin.
• PRG = High (VS): Parallel inputs Channel 1 to 4 and 9 to 12 are high active
• PRG = Low (GND): Parallel inputs Channel 1 to 4 and 9 to 12 are low active
6.1.2 Serial Control of the Outputs: SPI Protocol
6.1.3 Overview
Each output is independently controlled by an output latch and a common reset line, which disables all outputs.
The Serial Input (SI) is read on the falling edge of the serial clock. A logic high input ‘data bit’ turns the respective
output channel ON, a logic low ‘data bit’ turns it OFF.
CS must be low whilst shifting all the serial data into the device. A low-to-high transition of CS transfers the serial
data input bits to the output control buffer.
The 16 channels of the TLE6240GP are divided up into two parts for the control of the outputs (ON, OFF) and the
diagnosis information.
Serial Input (SI) information consists of 16 bit. 8 bit contain the input driver information for channel 1 to 8 or for
channel 9 to 16. The remaining 8 bits are used to program a certain operation mode.
Serial Output (SO) data consists of 16 bit containing the diagnosis information for channels 1 to 8 or channels 9
to 16 with two bits per channel.
Channel 1 to 8:
•Control Byte 1: Operation mode and diagnosis select for channels 1 to 8
•Data Byte1: ON/OFF information for channel 1 to 8
•DIAG_1: Diagnosis data for channels 1 to 8
Channel 9 to 16:
•Control Byte 2: Operation mode and diagnosis select for channels 9 to 16
•Data Byte2: ON/OFF information for channel 9 to 16
•DIAG_2: Diagnosis data for channels 9 to 16
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
Data Sheet 22 Rev.3.3, 2010-02-15
To drive all 16 channels and to get the complete diagnosis data of the TLE6240GP a two step access has to be
performed as follows:
Figure 14 First Access
Figure 15 Second Access
SI
SO
CS
SI command: Control Byte 1 programs the
operation mode of channels 1 to 8.
Data Byte 1 gives the input information (on
or off) for Channel 1 to 8.
SO diagnosis: Diagnosis information of
channel 1 to 8 or 9 to 16, depending on the
SI control word before.
Control Byte1 Data Byte1
16 bit Diagnosis
SI
SO
CS
Control Byte1 Data Byte1
DIAG_1 (Ch. 1 to 8)
SI command: Control Byte 1 programs the
operation mode of Channels 1 to 8.
Data Byte 1 gives the input information (on
or off) for Channel 1 to 8.
SO diagnosis: 16 bit diagnosis information
(two bit per channel) of channels 1 to 8
SI
SO
CS
SI command: Control Byte 2 programs the
operation mode of channels 9 to 16.
Data Byte 2 gives the input information (on
or off) for Channel 9 to 16.
SO diagnosis: Diagnosis information of
channel 1 to 8 or 9 to 16, depending on the
SI control word before.
Control Byte2 Data Byte2
16 bit Diagnosis
SI
SO
CS
Control Byte2 Data Byte2
DIAG_2 (Ch. 9 to 16)
SI command: Control Byte 2 programs the
operation mode of Channels 9 to 16.
Data Byte 2 gives the input information (on
or off) for Channel 9 to 16.
SO diagnosis: 16 bit diagnosis information
(two bit per channel) of channels 9 to 16
Data Sheet 23 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6.1.4 Control- and Data Byte
As mentioned above, the serial input information consist of a control byte and a data byte. Via the control byte, the
specific mode of the device is programmable.
Ten specific control words are recognized, having the following functions:
Table 2 Commands
Control words beside No. 1- 10
Not specified Control words are not executed (cause no function) and the shift register (SO Data) is reset after the
CS signal (all ‘0’).
Table 1 Control and Data Byte
MSB LSB
CCCCCCCCDDDDDDDD
Control Byte Data Byte
No. Control Byte Data Byte Function
Channel 1 to 8
1 LLLL LLLL1) XXXX XXXX2) ‘Full Diagnosis’ (two bits per channel) performed for channels 1 to 8. No
change to output states.
2 HHLL LLLL XXXX XXXX State of the eight parallel inputs and ‘1-bit Diagnosis’ for channel 1 to 8 is
provided.
3 HLHL LLLL XXXX XXXX Echo-function of SPI; SI direct connected to SO.
4 LLHH LLLL DDDDDDDD2) IN1 … 4 and serial data bits ‘OR’ed. ‘Full Diagnosis’ performed for
channels 1 to 8.
5 HHHH LLLL DDDDDDDD IN1 … 4 and serial data bits ‘AND’ed. ‘Full Diagnosis’ performed for
channels 1 to 8.
Channel 9 to 16
6 LLLL HHHH1) XXXX XXXX ‘Full Diagnosis’ (two bits per channel) performed for channels 9 to 16. No
change to output states.
7 HHLL HHHH XXXX XXXX State of the eight parallel inputs and ‘1-bit Diagnosis’ for channel 9 to 16 is
provided.
8 HLHL HHHH XXXX XXXX Echo-function of SPI; SI direct connected to SO.
9 LLHH HHHH DDDDDDDD IN9 … 12 and serial data bits ‘OR’ed. ‘Full Diagnosis’ performed for
channels 9 to 16.
10 HHHH HHHH DDDDDDDD IN9 … 12 and serial data bits ‘AND’ed. ‘Full Diagnosis’ performed for
channels 9 to 16.
1) Control Byte: Channel Selection via Bit 0 to 3
Bits 0 to 3 = L, Channels 1 to 8 selected
Bits 0 to 3 = H, Channels 9 to 16 selected
2) Data Byte: ‘X’ means ‘don’t care’, because this data bits will be ignored.
‘D’ represents the data bits, either being H (= ON) or L (= OFF).
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
Data Sheet 24 Rev.3.3, 2010-02-15
6.1.5 Control Byte - Detailed description
In the following section the different control bytes will be described. X used within the control byte means:
The following Control Byte descriptions are referring to the Overview Table 2.
6.1.5.1 Control Byte No.1 and 6
By clocking in this control byte, it is possible to get pure diagnostic information (two bits per channel) in accordance
with Figure 21. The data bits are ignored, so that the state of the outputs are not influenced. This command is only
active once unless the next control command is again “Diagnosis only”. Diagnostic information can be read out at
any time with no change of the switching conditions.
Figure 16 Example for two Consecutive Chip Select Cycles
Table 3 Control Byte - Channel Group selection
MSB Comment
X X X X L L L L Command is valid for Channels 1 to 8
XXXXHHHHCommand is valid for Channels 9 to 16
Control Byte
Table 4 Control Byte No. 1 to 6
MSB Comment
LLLLXXXX
Diagnosis only
Control Byte
SI L L L L L L L L X X X X X X X X
SO H H H H H H H H H H H H H H H H
CS
SI command: Diagnosis only for channels 1 to 8. No change of
the output states
SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to
16 depending on previous SI command
SI L L L L H H H H X X X X X X X X
SO
CS
SI command: Diagnosis only for channels 9 to 16. No change of
the output states ⇒ DIAG_2 provided during next chip select cycle
SO diagnosis: 2 bit diagnosis performed for channels 1 to 8
DIAG_1
Data Sheet 25 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6.1.5.2 Control Byte No. 2 and 7
If the TLE6240GP is used as bare die in a hybrid application, it is necessary to know if proper connections exist
between the µC-port and parallel inputs. By entering ‘HHLL’ as the control word, the first eight bits of the SO give
the state of the parallel inputs, depending on the µC signals. By comparing the IN-bits with the corresponding
µC-port signal, the necessary connection between the µC and the TLE6240GP can be verified - i.e. ‘read back of
the inputs’.
The second 8-bits fed out at the serial output contains ‘1-bit’ fault information of the outputs (H = no fault, L = fault).
In the expression given below for the output byte, ‘FX’ is the fault bit for channel X.
Figure 17 Example for two Consecutive Chip Select Cycles
Table 5 Control Byte No. 2 and 7
MSB Comment
HHLLXXXX
Reading back of the eight inputs and ‘1-bit
Diagnosis’ provided
Control Byte
Table 6 Serial Output
MSB LSB
IN12 IN11 IN10 IN9 IN4 IN3 IN2 IN1 FX FX FX FX FX FX FX FX
Parallel Input Signals Fault Bits Channel 1 to 8 or 9 to 16
SI H H L L L L L L X X X X X X X X
SO H H H H H H H H H H H H H H H H
CS
SI command: No change of the output states; reading back of
the 8 inputs and 1bit diagnosis for channels 1 to 8
SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to
16 depending on previous SI command
SI H H L L H H H H X X X X X X X X
SO
CS
SI command: No change of the output states; reading back of
the 8 inputs and 1bit diagnosis for channels 9 to 16 provided
during next chip select cycle
SO diagnosis: State of eight parallel inputs and 1 bit diagnosis
performed for channels 1 to 8
State of 8 par. inputs 1bit diagnosis Ch.1..8
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
Data Sheet 26 Rev.3.3, 2010-02-15
6.1.5.3 Control Byte No. 3 and 8
To check the proper function of the serial interface the TLE6240GP provides a “SPI Echo Function”. By entering
HLHL as control word, SI and SO are connected during the next CS period. By comparing the bits clocked in with
the serial output bits, the proper function of the SPI interface can be verified. This internal loop is only closed
once (for one CS period). The “Echo Function” does not cause any internal processing of data and after the next
CS signal the SO data is ‘0’ (all registers reset).
Figure 18 Echo-function of SPI
6.1.5.4 Control Byte No. 4 and 9
With LLHH LLLL as the control word, each of the input signals IN1 to IN4 are ‘OR’ed with the corresponding SI
data bits.
With LLHH HHHH as the control word, each of the input signals IN9 to IN12 are ‘OR’ed with the corresponding SI
data bits.
Table 7 Control Byte No. 3 and 8
MSB Comment
HLHLXXXX
Echo-function of SPI
Control Byte
Table 8 Control Byte No. 4 and 9
MSB Comment
LLHHXXXX
OR operation, and ‘full diagnosis’
Control Byte
SI SI and SO int. connected
Echo-function of SPI, i.e. SI
directly connected to SO.
SI information will not be
accepted during this cycle.
SI H L H L L L L L X X X X X X X X
SO H H H H H H H H H H H H H H H H
CS
SI command: No change of the output states; Echo function of
SPI
SO diagnosis: No fault, normal function of channels 1 to 8 or 9 to
16 depending on previous SI command
SO
CS
Data Sheet 27 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
Figure 19 OR Operation between IN and Serial Input
This OR operation enables the serial interface to switch the channel ON, even though the corresponding parallel
input might be in the off state.
SPI Priority for ON-State
Also parallel control of the outputs is possible without an SPI input.
The OR-function is the default Boolean operation if the device restarts after a Reset, or when the supply voltage
is switched on for the first time.
If the OR operation is programmed it is latched until it is overwritten by the AND operation.
6.1.5.5 Control Byte No. 5 and 10
With HHHH LLLL as the control word, each of the input signals IN1 to IN4 are ‘AND’ed with the corresponding SI
data bits.
With HHHH HHHH as the control word, each of the input signals IN9 to IN12 are ‘AND’ed with the corresponding
SI data bits.
Figure 20 AND Operation between IN and Serial Input
Table 9 Control Byte No. 5 and 10
MSB Comment
HHHHXXXX
AND operation, and ‘full diagnosis’
Control Byte
≥ 1 Output
Driver
IN 1...4/9...12
Serial Input,
data bits 0...3
&Output
Driver
IN 1...4/9...12
Serial Input,
data bits 0...3
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
Data Sheet 28 Rev.3.3, 2010-02-15
The AND operation implies that the output can be switched off by the SPI data bit input, even if the corresponding
parallel input is in the ON state.
SPI Priority for OFF-State
This also implies that the serial input data bit can only switch the output channel ON if the corresponding parallel
input is in the ON state.
If the AND operation is programmed it is latched until it is overwritten by the OR operation.
6.1.5.6 Example for an access to channel 1 to 8
LLHH LLLL HLLH LLLH: OR operation between parallel inputs and data bits, i.e channel 1, 5 and 8 will be switched
on.
The next command is now: LHHH LLLL HHHH LLLL
LHHH LLLL as command word has no special meaning and will not be accepted. The output states will not be
changed and the shift register will be reset (at the next CS SO Data all ‘0’).
6.2 Diagnostics
For full diagnosis there are two diagnostic bits per channel configured as shown in Figure 21.
Figure 21 Two Bits per Channel Diagnostic Feedback
•Normal function: The bit combination HH indicates that there is no fault condition, i.e. normal function.
•Overload, Short Circuit to Battery (SCB) or Overtemperature: HL is set when the current limitation gets
active, i.e. there is a overload, short to supply or overtemperature condition.
•Open load: An open load condition is detected when the drain voltage decreases below 3 V (typ.). LH bit
combination is set.
•Short Circuit to GND: If a drain to ground short circuit exists and the drain to ground current exceeds 100 µA,
short to ground is detected and the LL bit combination is set.
A definite distinction between open load and short to ground is specified by design.
The standard way of obtaining diagnostic information is as follows:
Clock in serial information into SI pin and wait approximately 150 µs to allow the outputs to settle. Clock in the
identical serial information once again - during this process the data coming out at SO contains the bit
combinations representing the diagnosis conditions as described in Figure 21.
Reset of the Diagnosis Register
The diagnosis register is reset after reading the diagnosis data (after the falling CS edge). This is done for
channels 1-8 and channels 9-16 separately depending on the previous command.
Diagnostic Serial Data OUT SO
HH Normal function
HL Overload, Shorted Load or Overtemperature
LH Open Load
LL Shorted to Ground
Ch.8 Ch.7 Ch.6 Ch.5
15 14 13 12 11 10 9 8 7 6- - - - -
Ch.16 Ch.15 Ch.14 Ch.13
Data Sheet 29 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
6.2.1 Diagnosis Read-out options
By means of the control byte it is possible either to:
1. control the outputs according to the data byte, as well as being able to read the diagnostic information (two bits
per channel)
2. or purely get diagnostic information without changing the state of the outputs
3. or read back the parallel inputs plus a simple diagnosis (one bit per channel)
4. or SPI “Echo Function” as a diagnosis of proper SPI function.
Diagnosis Read-Out Option 1): Serial Control of Outputs
SI information: OR-operation valid for channels 1 to 8
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle
SI information: OR-operation valid for channels 9 to 16
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle
SI information: AND-operation valid for channels 1 to 8
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle
SI information: AND-operation valid for channels 9 to 16
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle
Table 10 OR-operation valid for channels 1 to 8
MSB LSB
LLHHLLLLLHLHHLLL
Control Byte Data Byte
Table 11 OR-operation valid for channels 9 to 16
MSB LSB
LLHHHHHHHLHLHLLL
Control Byte Data Byte
Table 12 AND-operation valid for channels 1 to 8
MSB LSB
HHHHL LLLLHLHHLLL
Control Byte Data Byte
Table 13 AND-operation valid channels 9 to 16
MSB LSB
HHHHHHHHLHLHHLL L
Control Byte Data Byte
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
Data Sheet 30 Rev.3.3, 2010-02-15
Diagnosis Read-Out Option 2): Diagnosis only
SI information: Full diagnosis for channels 1 to 8. No change of output states
SO: 16 bit diagnosis for channels 1 to 8 performed during next chip select cycle
SI information: Full diagnosis for channels 9 to 16. No change of output states
SO: 16 bit diagnosis for channels 9 to 16 performed during next chip select cycle
Diagnosis Read-Out Option 3): Read back of parallel inputs plus simple diagnosis
SI information: No change of the output states. Read back of parallel inputs and 1 bit diagnosis for channels 1 to 8
SO: State of eight inputs plus 1 bit diagnosis for channel 1 to 8 during next chip select cycle
SI information: No change of the output states. Read back of parallel inputs and 1 bit diagnosis for channels 9 to 16
SO: State of eight inputs plus 1 bit diagnosis for channel 9 to 16 during next chip select cycle
Diagnosis Read-Out Option 4): SPI Echo function
Table 14 diagnosis - No change of output states
MSB LSB
LLLLLLLLXXXXXXXX
Control Byte Data Byte
Table 15 diagnosis - No change of output states
MSB LSB
LL L LHHHHXXXXXXXX
Control Byte Data Byte
Table 16 No change of output states - read
MSB LSB
HHLLLLLLXXXXXXXX
Control Byte Data Byte
Table 17 No change of output states - read
MSB LSB
HHL LHHHHXXXXXXXX
Control Byte Data Byte
Table 18 No change of output states - Echo
MSB LSB
HLHLLLLLXXXXXXXX
Control Byte Data Byte
Data Sheet 31 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Control of the Device
SI information: Echo function of SPI interface. No change of the output states
SO: During next chip select cycle the SI bits clocked in appear directly at SO because of an internal connection
for this cycle
SI information: Echo function of SPI interface. No change of the output states
SO: During next chip select cycle the SI bits clocked in appear directly at SO because of an internal connection
for this cycle
Figure 22 Serial Interface
Table 19 No change of output states - Echo
MSB LSB
HLHLHHHHXXXXXXXX
Control Byte Data Byte
C O N T R O L Byte 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CS
SCLK
SI
SO
MSB LSB
TLE6240GP
Smart 16-Channel Low-Side Switch
Application Hints
Data Sheet 32 Rev.3.3, 2010-02-15
7 Application Hints
Note: The following information is given as a hint for the implementation of the device only and shall not be
regarded as a description or warranty of a certain functionality, condition or quality of the device.
7.1 Application Circuits
Figure 23 Application Circuit
TLE6240GP
Micro
Controller
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SI
SO
CS
CLK
FAULT
RESET
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SO
SI
CS
CLK
PRG
V
S
OUTx
OUTx
V
Bat
OUTx
47nF*
* Ceramic Capacitor located close to Power Device
10K
Application Ci rcuit .vsd
Data Sheet 33 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Application Hints
7.2 Engine Management Application
TLE6240GP can be used in combination with Multichannel Switches for relays and general purpose loads.
This arrangement covers the numerous loads to be driven in a modern Engine Management/Powertrain system.
From 28 channels in sum 16 can be controlled direct in parallel for PWM applications.
Figure 24 Engine Management Application
Application_Hint_EMS_FLEX.vsd
TLE
6240GP
TLE6240GP
Smart 16-Channel Low-Side Switch
Application Hints
Data Sheet 34 Rev.3.3, 2010-02-15
7.3 Daisy Chain Application
Figure 25 Daisy Chain Application
TL6240GP
16-folds
SI SO
CS CLK
TL6240GP
16-folds
SI SO
CS CLK
TL6240GP
16-folds
SI SO
CS CLK
µC
Px .1
Px .2
MTSR
MRST
Data Sheet 35 Rev.3.3, 2010-02-15
TLE6240GP
Smart 16-Channel Low-Side Switch
Package Outlines
8 Package Outlines
Figure 26 PG-DSO-36 (Plastic Dual Small Outline Package)
Green Product (RoHS compliant)
To meet the world-wide customer requirements for environmentally friendly products and to be compliant with
government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e
Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020).
Bottom View
Does not include plastic or metal protrusion of 0.15 max. per side
118
0.25
±0.1
1.1
36
+0.13
0.25
36x
19
M
(Heatslug)
15.74
0.65
±0.1
CAB
19
C
3.25
3.5 MAX.
+0.1
0
0.1
±0.1
36
2.8 B
11
±0.15 1)
1.3
5˚
0.25
±3˚
-0.02
+0.07
6.3
14.2
(Mold)
±0.3
B
±0.15
0.25
Heatslug
0.95
Heatslug
±0.1
5.9
3.2
(Metal)
±0.1
(Metal)
13.7
(Metal)
10 1
-0.2
Index Marking
(Mold)
15.9
1)
±0.1
A
1 x 45˚
1)
GPS09181
You can find all of our packages, sorts of packing and others in our
Infineon Internet Page “Products”: http://www.infineon.com/products.Dimensions in mm
TLE6240GP
Smart 16-Channel Low-Side Switch
Revision History
Data Sheet 36 Rev.3.3, 2010-02-15
9 Revision History
Version Date Changes
V3.3, 2010-02-15, up-date
V3.3 2010-02-15 Template up-date
ESD standard up-date
Thermal Resistance parameters up-date
Temperature range for functional range added
Package name modified
Edition 2010-02-15
Published by
Infineon Technologies AG
81726 Munich, Germany
© Infineon Technologies AG 2010.
All Rights Reserved.
Legal Disclaimer
The information given in this document shall in no event be regarded as a guarantee of conditions or
characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values
stated herein and/or any information regarding the application of the device, Infineon Technologies hereby
disclaims any and all warranties and liabilities of any kind, including without limitation warranties of
non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
