AR0833CS3C29SMFAD3-E - Aptina

June, 2018 − Rev. 11

1Publication Order Number:

AR0833/D

AR0833

AR0833 1/3.2‐Inch 8 Mp

CMOS Digital Image Sensor

Table 1. KEY PERFORMANCE PARAMETERS

Parameter Typical Value

Array Format 3264 × 2448

Primary Modes Full Resolution: 4:3 − 8 Mp at 30 fps

16:9 − 6 Mp at 30 fps

16:9 − 1080p HD at 30 fps

Pixel Size 1.4 μm Back Side Illuminated (BSI)

Optical Format 1/3.2-inch

Die Size 6.86 mm × 6.44 mm (Area: 44.17 mm2)

Input Clock Frequency 6−27 MHz

Interface MIPI CSI−2 (2−, 3−, 4−lane Modes

Supported.) 800 Mbps Max MIPI Clock

Speed per Lane.

Subsampling Modes X − Bin2, Sum2 Skip: 2×, 4×

Y − Sum2, Skip: 2×, 4×, 8×

Output Data Depth 10 bits Raw or 8/6−bit DPCM

Analog Gain 1×, 2×, 3×, 4×, 6×, 8×

High Quality Bayer Scalar Adjustable Scaling Up to 1/6x scaling

Temperature Sensor 10-bit, Single Instance on Chip,

Controlled by Two-wire Serial I/F

VCM AF Driver 8-bit Resolution With Slew Rate Control

3−D Support Frame Rate and Exposure

Synchronization

Supply Voltage Analog 2.5−3.1 V (2.8 V Nominal)

Digital 1.14−1.3 V (1.2 V Nominal)

Pixel 2.5−3.1 V (2.8 V Nominal)

OTPM

Read

1.7−1.9 V (1.8 V Nominal)

I/O 1.7−1.9 V (1.8 V Nominal) or

2.5−3.1 V (2.8 V Nominal)

MIPI 1.14−1.3 V (1.2 V Nominal)

Power Consumption 340 mW at 30 fps, 8 Mp

Responsivity 0.6 V/lux-sec

SNRMAX 36 dB

Dynamic Range 64 dB

Operating Temperature Range

(at Junction) −TJ

−30°C to +70°C

Features

•High-speed Sensor Supporting 8 Mp (4:3) 30 fps Still Images and

Full HD 1080p30 Video

•1.4 μ Pixel with ON Semiconductor A-PixHS™ Technology

Providing Best-in-class Low-light Performance.

•Optional On-chip high-quality Bayer Scaler to Resize Image to

Desired Size

www.onsemi.com

Features (Continued)

•Data Interfaces: Two-, Three-, and Four-lane

Serial Mobile Industry Processor Interface

(MIPI)

•Bit-depth Compression Available for MIPI

Interface: 10-8 and 10-6 to Enable Lower

Bandwidth Receivers for Full Frame Rate

Applications

•On-chip Temperature Sensor

•On-die phase-locked Loop (PLL) Oscillator

•5.6 Kb One-time Programmable Memory

(OTPM) for Storing Module Information

•On-chip 8-bit VCM Driver

•3D Synchronization Controls to Enable

Stereo Video Capture

•Interlaced Multi-exposure Readout Enabling

High Dynamic Range (HDR) Still and Vide

Applications

•Programmable Controls: Gain, Horizontal

and Vertical Blanking, Auto Black Level

Offset Correction, Frame Size/rate, Expo-

sure, Left–right and Top–bottom Image Re-

versal, Window Size, and Panning

•Support for External Mechanical Shutter

•Support for External LED or Xenon Flash

Applications

•Smart phones

•PC cameras

•Tablets

See detailed ordering and shipping information on page 2 of

this data sheet.

ORDERING INFORMATION

CLCC48 10 y 10

CASE 848AJ

AR0833

www.onsemi.com

Table 2. MODES OF OPERATION AND POWER CONSUMPTION AT 100% FOV

Mode

Active Readout

Window (Col y Row)

Sensor Output

Resolution

(Col y Row) Mode FPS

Power

Consumption

[mW] (Note 5)

SNAPSHOT MODE

Full Resolution 4:3 − 8 Mp (Note 1) 3264 x 2448 3264 x 2448 Full mode 30 340

Full Resolution 16:9 − 6 Mp (Note 1) 3264 x 1836 3265 x 1836 Full mode 30 323

4:3 VIDEO MODE

VGA (Note 2) 3264 x 2448 640 x 480 Scaling 30 293

VGA (Note 3) 3264 x 2448 640 x 480 Bin2 + Scaling 30 270

VGA 3264 x 2448 640 x 480 Bin2 + Scaling 60 293

16:9 VIDEO MODE

1080p (Note 2) 3264 x 1836 1920 x 1080 Scaling 30 216

1080p + EIS (Note 2, 4) 3264 x 1836 2304 x 1296 Scaling 30 216

720p (Note 2) 3264 x 1836 1280 x 720 Scaling 30 216

720p (Note 2) 3264 x 1836 1280 x 720 Bin2 + Scaling 60 295

720p + EIS (Note 2) 3264 x 1836 1536 x 864 Scaling 30 216

WVGA (Note 2) 3264 x 1836 8546 x 480 Scaling 30 256

WVGA (Note 2) 3265 x 1836 856 x 480 Bin2 + Scaling 60 293

1. 732 Mbps/lane MIPI data transfer rate

2. Scaled image using internal High Quality Bayer Scaler

3. Low power preview

4. Electronic Image Stabilization

5. Values measured at T = 25°C and nominal voltages

ORDERING INFORMATION

Table 3. AVAILABLE PART NUMBERS

Part Number Product Description Orderable Product Attribute Description

AR0833CS3C12SUAA0−DP 8 MP 1/3″ CIS Dry Pack with Protective Film

See the ON Semiconductor Device Nomenclature

document (TND310/D) for a full description of the naming

convention used for image sensors. For reference

documentation, including information on evaluation kits,

please visit our web site at www.onsemi.com.

GENERAL DESCRIPTION

The ON Semiconductor AR0833 is a 1/3.2-inch BSI

(back side illuminated) CMOS active-pixel digital image

sensor with a pixel array of 3264 (H) x 2448 (V) (3280 (H)

x 2464 (V) including border pixels). It incorporates

sophisticated on-chip camera functions such as mirroring,

column and row skip modes, and context switching for zero

shutter lag snapshot mode. It is programmable through a

simple two-wire serial interface and has very low power

consumption.

The AR0833 digital image sensor features ON

Semiconductor’s breakthrough low-noise 1.4 μm pixel

CMOS imaging technology that achieves near-CCD image

quality (based on signal-to-noise ratio and low-light

sensitivity) while maintaining the inherent size, cost, and

integration advantages of CMOS.

The AR0833 sensor can generate full resolution image at

up to 30 frames per second (fps). An on-chip

analog-to-digital converter (ADC) generates a 10-bit value

for each pixel.

AR0833

www.onsemi.com

FUNCTIONAL OVERVIEW

In order to meet higher frame rates in AR0833 sensor, the

architecture has been re-designed. The analog core has a

column parallel architecture with 4 data paths. Digital block

has been re-architected to have 4 data paths.

The chip is targeted to meet SMIA 85 module size. As a

result, the final die size is 6.86 mm x 6.44 mm (singulated)

which would fit in the intended module with two-sided pad

frame.

Figure 1 shows the block diagram of the AR0833.

Figure 1. Top Level Block Diagram

PLL Timing Control

Two-wire

Serial Interface

Row

Driver

Pixel

Array ADCGain

Imaging Sensor Core Digital Processing Image Output

10-bit

Temperature

Sensor

Gain

Control

Test Pattern

Generator

Data Calibration

Digital Gain

Scaler

MIPI

FIFO&Optional

Compression

VAA,

VAA_PIX

VDD_IO,

DVDD_1V8,

DVDD_1V2

MIPI

Serial Data

Output [3:0]

External

Clock

XSHUTDOWN

GPIO[1:0]

GPI[3:2]

SCLK

SDATA

VCM

Control

DVDD_1V2_

PHY

AR0833

The core of the sensor is an 8 Mp active-pixel array. The

timing and control circuitry sequences through the rows of

the array, resetting and then reading each row in turn. In the

time interval between resetting a row and reading that row,

the pixels in the row integrate incident light. The exposure

is controlled by varying the time interval between reset and

readout. Once a row has been read, the data from the

columns is sequenced through an analog signal chain

(providing gain), and then through an ADC. The output from

the ADC is a 10-bit value for each pixel in the array. The

ADC output passes through a digital processing signal chain

(which provides further data path corrections and applies

digital gain).

The pixel array contains optically active and

light-shielded (“dark”) pixels. The dark pixels are used to

provide data for on-chip offset-correction algorithms

(“black level” control).

The sensor contains a set of control and status registers

that can be used to control many aspects of the sensor

behavior including the frame size, exposure, and gain

setting. These registers can be accessed through a two-wire

serial interface.

The output from the sensor is a Bayer pattern; alternate

rows are a sequence of either green and red pixels or blue and

green pixels. The offset and gain stages of the analog signal

chain provide per-color control of the pixel data.

A flash output signal is provided to allow an external

xenon or LED light source to synchronize with the sensor

exposure time. Additional I/O signals support the provision

of an external mechanical shutter.

Pixel Array

The sensor core uses a Bayer color pattern, as shown in

Figure 2. The even-numbered rows contain green and red

pixels; odd-numbered rows contain blue and green pixels.

Even-numbered columns contain red and green pixels;

odd-numbered columns contain blue and green pixels.

Figure 2. Pixel Color Pattern Detail

(Top Right Corner)

Column Readout Direction

Row Readout Direction

First Pixel

(Col. 0, Row 60)

…

Black Pixels

NOTE: By default the mirror bit is set, so the

read-out direction is from left to right.

AR0833

www.onsemi.com

TYPICAL CONNECTIONS

The chip supports MIPI output protocol. MIPI can be

configured in 4-, 3- or 2-lanes. There are no parallel data

output ports.

Figure 3. Typical Application Circuit − MIPI Connection

1. All power supplies should be adequately decoupled; recommended cap values are:

− 2.8 V: 1.0 mF, 0.1 mF, and then 0.01 mF

− 1.2 V: 1 mF and then 0.1 mF

− 1.8 V: 0.1 mF

2. Resistor value 1.5 kW is recommended, but may be greater for slower two-wire speed.

3. This pull-up resistor is not required if the controller drives a valid logic level on SCLK at all times.

4. VAA and VAA_PIX can be tied together. However, for noise immunity it is recommended to have them separate (i.e. two sets of 2.8 V

decoupling caps).

5. VPP

, 6−7 V, is used for programming OTPM. This pad is left unconnected if OTPM is not being programmed.

6. VDD_1V8 can be combined with VDD_IO, if VDD_IO = 1.8 V.

7. VDD_1V2 and VDD1_1V2_PHY can be tied together.

8. ATEST1 can be left floating.

9. TEST pin must be tied to DGND.

10.DVDD_1V8 is the OTPM read voltage (must always be provided).

Notes:

DATA_P

DATA_N

DATA2_P

DATA2_N

DATA3_P

DATA3_N

2.8 V

AGND

VAA4

(Pixel)

VAA4

(Analog)

VDD_IO

(IO)

DVDD_1V2

(Digital)7

SDATA

SCLK

EXTCLK

(6−27 MHz)

1.5 kW2

1.5 kW2, 3

TEST8

MIPI

Port

Two-wire

Serial

Interface

2.8 V or 1.8 V

XSHUTDOWN

DATA4_N

DATA4_P

CLK_P

CLK_N

DGND

VPP5

(OTPM Write)

(Only Connected while

Programming OTPM)

ATEST8

GPI[3:2]

GPIO[1:0]

General

Purpose

Input/Output

DVDD_1V8

(OTPM Read)6

1.2 V 2.8 V 1.2 V

DVDD1V2_PHY

(MIPI)7

0.01 mF

0.1 mF

1.0 mF

1.2 V

0.1 mF

1.0 mF

1.8 V

ISINK

GND

VCM

GND_IO

GNDPHY

DVDD_1V8

0.1 mF

VDD_IO

0.1 mF

AR0833

www.onsemi.com

SIGNAL DESCRIPTIONS

AR0833 has 67 pads placed in a two sided pad frame. It

has only serial outputs. The part may be configured as MIPI

with different bit depths. The pad description is tabulated in

Table 4:

Table 4. PAD DESCRIPTIONS

Pad Name Pad Type Description

SENSOR CONTROL

EXTCLK Input Master clock input; PLL input clock. 6 MHz−27 MHz

This is a SMIA−compliant pad

GPIO0 Input/Output General Input and one Output function include:

a. (Default Output) Flash

b. (Input) all options in GPI2

High-Z before XSHUTDOWN going high; default value is ‘0’ after all three voltages in place

and XSHUTDOWN being high

After reset, this pad is not powered down since its default use is as Flash pin

If not used, can be left floating

GPIO1 Input/Output General Input and 2 Output functions include:

a. (Default Output) Shutter

b. (Output) 3-D daisy chain communication output

c. (Input) all options in GPI2

High-Z before XSHUTDOWN going high; default value is ‘0’ after all three voltages in place

and XSHUTDOWN being high

After reset, this pad is not powered-down since its default use is as Shutter pin

If not used, can be left floating

GPI2 Input General Input; After reset, these pads are powered down by default; this means that it is not

necessary to bond to these pads. Functions include:

a. SADDR, switch to the second two-wire serial interface device address

(see “Slave Address/Data Direction Byte”)

b. Trigger signal for Slave Mode

c. Standby

If not used, can be left floating

GPI3 Input General Input; After reset, these pads are powered-down by default; this means that it is not

necessary to bond to these pads. Functions include:

a. 3-D daisy chain communication input

b. All options in GPI2

If not used, can be left floating

TWO-WIRE SERIAL INTERFACE

SCLK Input Serial clock for access to control and status registers

SDATA I/O Serial data for reads from and writes to control and status registers

SERIAL OUTPUT

DATA[4:1]P Output Differential serial data (positive).

DATA[4:1]N Output Differential serial data (negative)

CLK_P Output Differential serial clock/strobe (positive)

CLK_N Output Differential serial clock/strobe (negative)

XSHUTDOWN Input Asynchronous active LOW reset. When asserted, data output stops and all internal registers

are restored to their factory default settings. This pin will turn off the digital power domain and

is the lowest power state of the sensor

VCM DRIVER

VCM_ISINK Input/Output VCM Driver current sink output. If not used, it could be left floating

VCM_GND Input/Output Ground connection to VCM Driver. If not used, needs to be connected to ground (DGND).

This ground must be separate from the other grounds

POWER

VPP Input/Output High-voltage pin for programming OTPM, present on sensors with that capability. This pin

can be left floating during normal operation

AR0833

www.onsemi.com

Table 4. PAD DESCRIPTIONS (continued)

Pad Name DescriptionPad Type

POWER (continued)

VAA[7:1], VAA_PIX[2:1],

AGND[9:1],

VDD_IO_[4:1], GND_IO,

DGND_[6:1],

DVDD_1V2_[9:1],

DVDD_1V2_PHY_[2:1],

GNDPHY_[2:1],

DVDD_1V8

Supply Power supply. The domains are specified in the next table. The brackets indicate the number

of individual pins

There are standard GPI and GPIO pads, two each. Chip

can also be communicated to through the two-wire serial

interface.

The chip has three unique power supply requirements: 1.2

V, 1.8 V, and 2.8 V. These are further divided and in all there

are seven power domains and five independent ground

domains from the ESD perspective.

Table 5. INDEPENDENT POWER AND GROUND DOMAINS

Pad Name Power Supply Description

GROUNDS

DGND (GNDPHY, GND_IO) 0 V Digital

VCM_GND 0 V VCM Driver

AGND 0 V Analog

POWER

VAA 2.8 V Analog/VCM Driver/OTPM

VAA_PIX 2.8 V Pixel/Analog

DVDD_1V2 1.2 V Digital

VDD_IO 1.8 V/2.8 V IO

DVDD_1V2_PHY 1.2 V MIPI

DVDD_1V8 1.8 V OTPM

AR0833

www.onsemi.com

SYSTEM STATES

The system states of the AR0833 are represented as a state

diagram in Figure 4 and described in subsequent sections.

The sensor’s operation is broken down into three separate

states: hardware standby, software standby, and streaming.

The transition between these states might take a certain

amount of clock cycles as outlined in Figure 4 and Figure 5.

Figure 4. System States

Powered OFF

Internal

Initialization

Software

Standby

PLL Lock

Streaming Wait for Frame End

Frame in Progress

PLL Locked

Two-wire Serial Interface

Write: mode_select = 1

Timeout

XSHUTDOWN = 1

Powered On

EXTCLK

Cycles

XSHUTDOWN = 0

PLL Not Locked

Streaming

Two-wire Serial Interface

Write: software_reset = 1

Power Supplies Turned Off

(Asynchronous from Any State)

Hardware

Standby

Two-wire Serial Interface

Write: mode_select = 0

AR0833

www.onsemi.com

SENSOR INITIALIZATION

Power-Up Sequence

AR0833 has three voltage supplies divided into several

domains. The three voltages are 1.2 V, 1.8 V, and 2.8 V. For

proper operation of the chip, a power-up sequence is

recommended as shown in Figure 5.

The power sequence is governed by controlled vs

controlling behavior of a power supply and the inrush

current (i.e., current that exists when not all power supplies

are present).

Table 6. INRUSH CONSIDERATION

XSHUTDOWN 1.2 V 1.8 V (VDD_IO) 2.8 V Comment

x Present Absent Absent Not Supported

x Absent Present Absent Supported

x Absent Absent Present Supported

x Present Present Absent Supported

x Present Absent Present Not Supported

x Absent Present Present Supported

0 Present Present Present Powered Down State

1 Present Present Present Powered Up State

Since VDD_IO supply controls the XSHUTDOWN, it

should be turned on first. The sequence of powering up the

other two domains is not too critical. While turning on 2.8 V

supply before 1.2 V supply shouldn’t be an issue as shown

in Table 1, it is still not recommended since the 2.8 V domain

is controlled by 1.2 V signals. The dedicated 1.8 V domain

is used only for OTPM read function, so can turn on along

with 1.8 V supply.

Due to the above considerations, the suggested power-on

sequence is as shown in Figure 5:

Figure 5. Recommended Power-Up Sequence

VDD_IO,

VDD_1V8

VDD_1V2,

VDD_1V2_PHY

VAA,

VAA_PIX

EXTCLK

XSHUTDOWN

SDATA

SCLK

t4t5

Soft Standby StreamingInternal InitHard Reset

First Serial Write

PLL

Lock

AR0833

www.onsemi.com

Table 7. POWER-UP SEQUENCE

Symbol Definition Minimum Typical Maximum Unit

t0VDD_IO to DVDD_1V8 – – 500 ms

t1DVDD_1V8 to DVDD_1V2/DVDD_1V2_PHY 0.2 – 500 ms

t2SDVDD_1V2/DVDD_1V2_PHY to VAA/VAA_PIX 0.2 – 500 ms

t3Active Hard Reset 1 – 500 ms

t4Internal Initialization 2400 – – EXTCLKs

t5PLL Lock Time 1 – 5 ms

Power-Down Sequence

The recommended power-down sequence for the AR0833

is shown in Figure 6. The three power supply domains (1.2

V, 1.8 V, and 2.8 V) must have the separation specified

below.

1. Disable streaming if output is active by setting

standby R0x301a[2] = 0.

2. After disabling the internal clock EXTCLK,

disable XSHUTDOWN.

3. After XSHUTDOWN is LOW disable the

2.8 V/1.8 V supply.

4. After the 2.8 V/1.8 V supply is LOW disable the

1.2 V supply.

5. After the 1.2 V supply is LOW disable the

VDD_IO supply.

Figure 6. Recommended Power-Down Sequence

VDD_IO

VDD_1V8

VDD_1V2,

VDD_1V2_PHY

VAA,

VAA_PIX

EXTCLK

XSHUTDOWN

SDATA

SCLK

Hard Reset

Soft StandbyStreaming Turn Off Power Supplies

Focal Planes

Deactivation

Table 8. POWER-DOWN SEQUENCE

Symbol Definition Minimum Typical Maximum Unit

t0EXTCLK to XSHUTDOWN 100 – – ms

t1XSHUTDOWN to Supply 2.8 V/1.8 V 200 – – ms

t2Supply 2.8 V/1.8 V to Supply 1.2 V 0 200 – ms

t3Supply 1.2 V to VDD_IO 200 – – ms

AR0833

www.onsemi.com

Hard Standby and Hard Reset

The hard standby state is reached by the assertion of the

XSHUTDOWN pad (hard reset). Register values are not

retained by this action, and will be returned to their default

values once hard reset is completed. The minimum power

consumption is achieved by the hard standby state. The

details of the sequence are described below and shown in

Figure 7.

1. Disable streaming if output is active by setting

mode_select 0x301A[2] = 0.

2. The soft standby state is reached after the current

row or frame, depending on configuration, has

ended.

3. Assert XSHUTDOWN (active LOW) to reset the

sensor.

4. The sensor remains in hard standby state if

XSHUTDOWN remains in the logic “0” state.

Figure 7. Hard Standby and Hard Reset

EXTCLK

XSHUTDOWN

mode_select

R0x0100 Logic “1” Logic “0”

New Row/Frame

Streaming Soft Standby Hard Standby Hard Reset

Soft Standby and Soft Reset

The AR0833 can reduce power consumption by switching

to the soft standby state when the output is not needed.

details of the sequence are described below and shown in

Figure 8.

Soft Standby

1. Disable streaming if output is active by setting

mode_select 0x301A[2] = 0.

2. The soft standby state is reached after the current

row or frame, depending on configuration, has

ended.

Soft Reset

1. Follow the soft standby sequence list above.

2. Set software_reset = 1 (R0x3021) to start the

internal initialization sequence.

3. After 2400 EXTCLKs (tentative), the internal

initialization sequence is completed and the

current state returns to soft standby automatically.

Figure 8. Soft Standby and Soft Reset

EXTCLK

mode_select

R0x0100 Logic “1”

Row/Frame

Streaming

software_reset

R0x0103

Logic “0”

Logic “0” Logic “1” Logic “0”

Soft Standby Soft Standby

Soft Reset

480 2400

EXTCLKs

AR0833

www.onsemi.com

TWO-WIRE SERIAL REGISTER INTERFACE

A two-wire serial interface bus enables read/write access

to control and status registers within the AR0833. The

two-wire serial interface is fully compatible with the I2C

standard.

The interface protocol uses a master/slave model in which

a master controls one or more slave devices. The sensor acts

as a slave device. The master generates a clock (SCLK) that

is an input to the sensor and is used to synchronize transfers.

Data is transferred between the master and the slave on a

bidirectional signal (SDATA). SDATA is pulled up to VDD

off-chip by a 1.5 kΩ resistor. Either the slave or master

device can drive SDATA LOW-the interface protocol

determines which device is allowed to drive SDATA at any

given time.

The protocols described in the two-wire serial interface

specification allow the slave device to drive SCLK LOW; the

AR0833 uses SCLK as an input only and therefore never

drives it LOW. The electrical and timing specifications are

further detailed on “Two-Wire Serial Register Interface”.

Protocol

Data transfers on the two-wire serial interface bus are

performed by a sequence of low-level protocol elements:

1. a (repeated) start condition

2. a slave address/data direction byte

3. an (a no) acknowledge bit

4. a message byte

5. a stop condition

The bus is idle when both SCLK and SDATA are HIGH.

Control of the bus is initiated with a start condition, and the

bus is released with a stop condition. Only the master can

generate the start and stop conditions.

Start Condition

A start condition is defined as a HIGH-to-LOW transition

on SDATA while SCLK is HIGH. At the end of a transfer, the

master can generate a start condition without previously

generating a stop condition; this is known as a “repeated

start” or “restart” condition.

Stop Condition

A stop condition is defined as a LOW-to-HIGH transition

on SDATA while SCLK is HIGH.

Data Transfer

Data is transferred serially, 8 bits at a time, with the MSB

transmitted first. Each byte of data is followed by an

acknowledge bit or a no-acknowledge bit. This data transfer

mechanism is used for the slave address/data direction byte

and for message bytes.

One data bit is transferred during each SCLK clock period.

SDATA can change when SCLK is LOW and must be stable

while SCLK is HIGH.

Slave Address/Data Direction Byte

Bits [7:1] of this byte represent the device slave address

and bit [0] indicates the data transfer direction. A “0” in bit

[0] indicates a WRITE, and a “1” indicates a READ. The

default slave addresses used by the AR0833 for the MIPI

configured sensor are 0x6C (write address) and 0x6D (read

address) in accordance with the MIPI specification.

Alternate slave addresses of 0x6E(write address) and

0x6F(read address) can be selected by enabling and

asserting the SADDR signal through the GPI pad.

The alternate slave addresses can also be programmed

through R0x31FC.

Message Byte

Message bytes are used for sending register addresses and

Acknowledge Bit

Each 8-bit data transfer is followed by an acknowledge bit

or a no-acknowledge bit in the SCLK clock period following

the data transfer. The transmitter (which is the master when

writing, or the slave when reading) releases SDATA. The

receiver indicates an acknowledge bit by driving SDATA

LOW.

No-Acknowledge Bit

The no-acknowledge bit is generated when the receiver

does not drive SDATA LOW during the SCLK clock period

following a data transfer. A no-acknowledge bit is used to

terminate a read sequence.

Typical Sequence

A typical READ or WRITE sequence begins by the

master generating a start condition on the bus. After the start

condition, the master sends the 8-bit slave address/data

direction byte. The last bit indicates whether the request is

for a read or a write, where a “0” indicates a write and a “1”

indicates a read. If the address matches the address of the

slave device, the slave device acknowledges receipt of the

address by generating an acknowledge bit on the bus.

If the request was a WRITE, the master then transfers the

16-bit register address to which the WRITE should take

place. This transfer takes place as two 8-bit sequences and

the slave sends an acknowledge bit after each sequence to

indicate that the byte has been received. The master then

transfers the data as an 8-bit sequence; the slave sends an

acknowledge bit at the end of the sequence. The master stops

writing by generating a (re)start or stop condition.

If the request was a READ, the master sends the 8-bit write

slave address/data direction byte and 16-bit register address,

the same way as with a WRITE request. The master then

generates a (re)start condition and the 8-bit read slave

address/data direction byte, and clocks out the register data,

eight bits at a time. The master generates an acknowledge bit

after each 8-bit transfer. The slave’s internal register address

is automatically incremented after every 8 bits are

transferred. The data transfer is stopped when the master

sends a no-acknowledge bit.

AR0833

www.onsemi.com

Single READ from Random Location

This sequence (Figure 9) starts with a dummy WRITE to

the 16-bit address that is to be used for the READ. The

master terminates the WRITE by generating a restart

condition. The master then sends the 8-bit read slave

address/data direction byte and clocks out one byte of

generating a no-acknowledge bit followed by a stop

condition. Figure 9 shows how the internal register address

maintained by the AR0833 is loaded and incremented as the

sequence proceeds.

Figure 9. Single READ from Random Location

Previous Reg Address, N Reg Address, M M+1

S0 1 PASr

Slave Address Reg

Address[15:8]

Reg

Address[7:0] Slave Address

S = Start Condition

P = Stop Condition

Sr = Restart Condition

A = Acknowledge

A = No-acknowledge

Slave to Master

Master to Slave

A A A A Read Data

Single READ from Current Location

This sequence (Figure 10) performs a read using the

current value of the AR0833 internal register address. The

master terminates the READ by generating a

no-acknowledge bit followed by a stop condition. The figure

shows two independent READ sequences.

Figure 10. Single READ from Current Location

Previous Reg Address, N Reg Address, N+1 N+2

S1 PSlave Address A Read Data S1 PSlave Address AARead DataA

Sequential READ, Start from Random Location

This sequence (Figure 11) starts in the same way as the

single READ from random location (Figure 9). Instead of

generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge

bit and continues to perform byte READs until “L” bytes

have been read.

Figure 11. Sequential READ, Start from Random Location

Previous Reg Address, N Reg Address, M

S0Slave Address A AReg Address[15:8]

M+1

A A A1SrReg Address[7:0] Read DataSlave Address

M+LM+L−1M+L−2M+1 M+2 M+3

ARead Data A Read Data ARead Data Read Data

AR0833

www.onsemi.com

Sequential READ, Start from Current Location

This sequence (Figure 12) starts in the same way as the

single READ from current location (Figure 10). Instead of

generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge

bit and continues to perform byte READs until “L” bytes

have been read.

Figure 12. Sequential READ, Start from Current Location

N+LN+L−1N+2N+1Previous Reg Address, N

PAS 1 Read DataASlave Address Read DataRead Data Read DataAAA

Single WRITE to Random Location

This sequence (Figure 13) begins with the master

generating a start condition. The slave address/data

direction byte signals a WRITE and is followed by the HIGH

then LOW bytes of the register address that is to be written.

The master follows this with the byte of write data. The

WRITE is terminated by the master generating a stop

condition.

Figure 13. Single WRITE to Random Location

Previous Reg Address, N Reg Address, M M+1

S0 PSlave Address Reg Address[15:8] Reg Address[7:0] A

AA Write Data

Sequential WRITE, Start at Random Location

This sequence (Figure 14) starts in the same way as the

single WRITE to random location (Figure 13). Instead of

generating a no-acknowledge bit after the first byte of data

has been transferred, the master generates an acknowledge

bit and continues to perform byte WRITEs until “L” bytes

have been written. The WRITE is terminated by the master

generating a stop condition.

Figure 14. Sequential WRITE, Start at Random Location

Previous Reg Address, N Reg Address, M M+1

S0Slave Address A Reg Address[15:8] A A AReg Address[7:0] Write Data

M+LM+L−1M+L−2M+1 M+2 M+3

Write Data AA A

Write Data Write Data Write Data

AR0833

www.onsemi.com

REGISTERS

The AR0833 provides a 16-bit register address space

accessed through a serial interface (“Two-Wire Serial

size.

The address space is divided into the five major regions

shown in Table 9. The remainder of this section describes

these registers in detail.

Table 9. ADDRESS SPACE REGIONS

Address Range Description

0x0000–0x0FFF Configuration registers (read-only and read-write dynamic registers)

0x1000–0x1FFF Parameter limit registers (read-only static registers)

0x2000–0x2FFF Image statistics registers (none currently defined)

0x3000–0x3FFF Manufacturer-specific registers (read-only and read-write dynamic registers)

The underlying mechanism for reading and writing

registers provides byte write capability. However, it is

convenient to consider some registers as multiple adjacent

bytes. The AR0833 uses 8-bit, 16-bit, and 32-bit registers,

all implemented as 1 or more bytes at naturally aligned,

contiguous locations in the address space.

In this document, registers are described either by address

or by name. When registers are described by address, the

size of the registers is explicit. For example, R0x3024 is a

2-bit register at address 0x3024, and R0x3000–1 is a 16-bit

described by name, the size of the register is implicit. It is

necessary to refer to the register table to determine that

model_id is a 16-bit register.

A consequence of the internal architecture of the AR0833

is that some registers are decoded at multiple addresses.

Some registers in “configuration space” are also decoded in

“manufacturer-specific space.” To provide unique names

for all registers, the name of the register within

manufacturer-specific register space has a trailing

underscore. For example, R0x0202 is

coarse_integration_time and R0x3012 is

coarse_integration_time_. The effect of reading or writing

a register through any of its aliases is identical.

Bit Fields

Some registers provide control of several different pieces

of related functionality, and this makes it necessary to refer

to bit fields within registers. As an example of the notation

used for this, the least significant 4 bits of the

chip_version_reg register are referred to as

chip_version_reg[3:0] or R0x0000–1[3:0].

Bit Field Aliases

In addition to the register aliases described above, some

R0x0100 (mode_select) has only one operational bit,

R0x0100[0]. This bit is aliased to R0x301A–B[2]. The

effect of reading or writing a bit field through any of its

aliases is identical.

Byte Ordering

Registers that occupy more than one byte of address space

are shown with the lowest address in the highest−order byte

lane to match the byte-ordering on the data bus. For

example, the chip_version_reg register is R0x0000–1. In the

means that a read from address 0x0000 would return 0x4B,

and a read from address 0x0001 would return 0x00. When

reading this register as two 8-bit transfers on the serial

interface, the 0x4B will appear on the serial interface first,

followed by the 0x00.

Address Alignment

All register addresses are aligned naturally. Registers that

occupy 2 bytes of address space are aligned to even 16-bit

addresses, and registers that occupy 4 bytes of address space

are aligned to 16-bit addresses that are an integer multiple of

Bit Representation

For clarity, 32-bit hex numbers are shown with an

underscore between the upper and lower 16 bits. For

example: 0x3000_01AB.

Data Format

Most registers represent an unsigned binary value or set of

bit fields. For all other register formats, the format is stated

explicitly at the start of the register description. The notation

for these formats is shown in Table 10.

AR0833

www.onsemi.com

Table 10. DATA FORMATS

Name Description

FIX16 Signed fixed-point, 16-bit number: two’s complement number, 8 fractional bits.

Examples:

0x0100 = 1.0

0x8000 = –128

0xFFFF = –0.0039065

UFIX16 Unsigned fixed-point, 16-bit number: 8.8 format.

Examples:

0x0100 = 1.0

0x280 = 2.5

FLP32 Signed floating-point, 32-bit number: IEEE 754 format.

Example:

0x4280_0000 = 64.0

Registers vary from “read-only,” “read/write,” and “read,

write-1-to-clear.”

Double-Buffered Registers

Some sensor settings cannot be changed during frame

readout. For example, changing R0x3004–5 (x_addr_start)

partway through frame readout would result in inconsistent

row lengths within a frame. To avoid this, the AR0833

double-buffers many registers by implementing a “pending”

and a “live” version. Reads and writes access the pending

The value in the pending register is transferred to a live

start. Frame start is defined as the point at which the first

dark row is read out internally to the sensor. In the register

tables the “Frame Sync’d” column shows which registers or

Using grouped_parameter_hold

used to inhibit transfers from the pending to the live

registers. When the AR0833 is in streaming mode, this

any group of registers where a set of changes is required to

take effect simultaneously. When this register is written to

“0,” all transfers from pending to live registers take place on

the next frame start.

An example of the consequences of failing to set this bit

follows:

•An external auto exposure algorithm might want to

change both gain and integration time between two

frames. If the next frame starts between these

operations, it will have the new gain, but not the new

integration time, which would return a frame with the

wrong brightness that might lead to a feedback loop

with the AE algorithm resulting in flickering.

Bad Frames

A bad frame is a frame where all rows do not have the

same integration time or where offsets to the pixel values

have changed during the frame.

Many changes to the sensor register settings can cause a

bad frame. For example, when line_length_pck (R0x300C)

is changed, the new register value does not affect sensor

behavior until the next frame start. However, the frame that

would be read out at that frame start will have been

integrated using the old row width, so reading it out using the

new row width would result in a frame with an incorrect

integration time.

By default, bad frames are masked. If the masked bad

frame option is enabled, both LV and FV are inhibited for

these frames so that the vertical blanking time between

frames is extended by the frame time.

In the register tables, the “Bad Frame” column shows

where changing a register or register field will cause a bad

frame. This notation is used:

•N − No. Changing the register value will not produce a

bad frame.

•Y − Yes. Changing the register value might produce a

bad frame.

•YM − Yes; but the bad frame will be masked out when

mask_corrupted_frames (R0x301A[9]) is set to “1.”

Changes to Integration Time

If the integration time is changed while FV is asserted for

frame n, the first frame output using the new integration time

is frame (n + 2). The sequence is as follows:

1. During frame n, the new integration time is held in

the pending register.

2. At the start of frame (n + 1), the new integration

time is transferred to the live register. Integration

for each row of frame (n + 1) has been completed

using the old integration time.

3. The earliest time that a row can start integrating

using the new integration time is immediately after

that row has been read for frame (n + 1). The

actual time that rows start integrating using the

new integration time is dependent upon the new

value of the integration time.

4. When frame (n + 2) is read out, it will have been

integrated using the new integration time.

If the integration time is changed on successive frames,

each value written will be applied for a single frame; the

latency between writing a value and it affecting the frame

readout remains at two frames.

AR0833

www.onsemi.com

Changes to Gain Settings

Usually, when the gain settings are changed, the gain is

updated on the next frame start. When the integration time

and the gain are changed at the same time, the gain update

is held off by one frame so that the first frame output with the

new integration time also has the new gain applied. In this

case, a new gain should not be set during the extra frame

delay. There is an option to turn off the extra frame delay by

setting extra_delay (R0x3018).

CLOCKING

Default setup gives a physical 73.2 MHz internal clock for

an external input clock of 24 MHz.

The sensor contains a phase-locked loop (PLL) for timing

generation and control. The PLL contains a prescaler to

divide the input clock applied on EXTCLK, a VCO to

multiply the prescaler output, and a set of dividers to

generate the output clocks. The PLL structure is shown in

Figure 15.

Figure 15. Clocking Configuration

pll _multiplier (R0x306)

PLL

Multiplier

(m)

PLL internal VCO

frequency

op_sys_clk

op sys clk

Divider

op pix

clk

Divider

op_pix_clk

clk _op

Divider clk_op

row_speed (R0x3016[10:8])

op_pix_clk_div (R0x308)

op_sys_clk_div (R0x30A)

EXTCLK

Pre PLL

Divider

(n +1)

External input clock

PLL input clock

pll_ip_clk_freq

(4−24 MHz)

pre_pll_clk_div (R0x304)

clk_pixel

Divider

vt_pix_clk

row_speed (R0x3016[2:0])

vt_sys_clk

vt sys clk

vt pix

clk

Divider

clk_pixel

vt_pix_clk_div (R0x300)

vt_sys_clk_div (R0x302)

ext_clk_freq_mhz

Divider

PLL

Figure 15 shows the different clocks and the names of the

registers that contain or are used to control their values. The

vt_pix_clk is divided by two to compensate for the fact that

the design has 2 digital data paths. This divider should

always remain turned on.

AR0833 has 10-to-8 and 10-to-6 compression. The

Framer IP packs two 6-bit pixels into one 12-bit data and

sends it to Physical Layer. The Framer takes the action to

divide word clock into half speed. The word clock should be

divided by 6 from VCO at PLL in order to match Physical

Layer considering one data having 12 bit-clocks.

The usage of the output clocks is shown below:

•clk_pixel (vt_pix_clk / row_speed[2:0]) is used by the

sensor core to readout and control the timing of the

pixel array. The sensor core produces one 10-bit pixel

each vt_pix_clk period. The line length

(line_length_pck) is controlled in increments of the

clk_pixel period.

•clk_op (op_pix_clk / row_speed[10:8]) is used to load

parallel pixel data from the output FIFO (see Figure 40)

to the serializer. The output FIFO generates one pixel

each op_pix_clk period.

•op_sys_clk is used to generate the serial data stream on

the output. The relationship between this clock

frequency and the op_pix_clk frequency is dependent

upon the output data format.

The pixel frequency can be calculated in general as:

pixel_clock_mhz +

ext_clk_freq_mhz pll_multiplier

pre_pll_clk_div vt_sys_clk_div 2 vt_pix_clk_div row_speed[2:0] (eq. 1)

The output clock frequency can be calculated as:

clk_op_freq_mhz +

ext_clk_freq_mhz pll_multiplier

pre_pll_clk_div op_sys_clk_div op_pix_clk_div row_speed[10:8] (eq. 2)

op_sys_clk_freq_mhz +

ext_clk_freq_mhz pll_multiplier

pre_pll_clk_div op_sys_clk_div (eq. 3)

AR0833

www.onsemi.com

PLL Clocking

The PLL divisors should be programmed while the

AR0833 is in the software standby state. After programming

the divisors, it is necessary to wait for the VCO lock time

before enabling the PLL. The PLL is enabled by entering the

streaming state.

An external timer will need to delay the entrance of the

streaming mode by 1 millisecond so that the PLL can lock.

The effect of programming the PLL divisors while the

AR0833 is in the streaming state is undefined.

Clock Control

The AR0833 uses an aggressive clock-gating

methodology to reduce power consumption. The clocked

logic is divided into a number of separate domains, each of

which is only clocked when required.

When the AR0833 enters a soft standby state, almost all

of the internal clocks are stopped. The only exception is that

a small amount of logic is clocked so that the two-wire serial

interface continues to respond to read and write requests.

FEATURES

Interlaced HDR Readout

The sensor enables HDR by outputting frames where even

and odd row pairs within a single frame are captured at

different integration times. This output is then matched with

an algorithm designed to reconstruct this output into an

HDR still image or video.

The sensor HDR is controlled by two shutter pointers

(Shutter pointer1, Shutter pointer2) that control the

integration of the odd (Shutter pointer1) and even (Shutter

pointer 2) row pairs.

Figure 16. HDR Integration Time

Tint 1

Tint 2

I−FRAME 1

I−FRAME 2

Output Frame from Sensor

EXPOSURE

I−FRAME 1

EXPOSURE

I−FRAME 1

Shutter Pointer 1

Shutter Pointer 2

Sample Pointer

Output

I−FRAME 1

and 2

AR0833

www.onsemi.com

INTEGRATION TIME FOR INTERLACED HDR READOUT

Tint1 (Integration Time 1) and Tint2 (Integration Time 2)

The limits for the coarse integration time are defined by:

coarse_integration_time_min vcoarse_integration_time v(frame_length_lines *coarse_integration_time_max_margin) (eq. 4)

coarse_integration_time2_min vcoarse_integration_time2 v(frame_length_lines *coarse_integration_time2_max_margin) (eq. 5)

The actual integration time is given by:

integration_time +

coarse_integration_time line_length_pck

vt_pix_clk_freq_mhz 106(eq. 6)

integration_time2 +

coarse_integration_time2 line_length_pck

vt_pix_clk_freq_mhz 106(eq. 7)

If this limit is broken, the frame time will automatically be

extended to (coarse_integration_time + coarse_

integration_time_max_margin) to accommodate the larger

integration time.

The ratio between even and odd rows is typically adjusted

to 1×, 2×, 4×, and 8×.

Bayer Resampler

The imaging artifacts found from a 2 ×2 binning or

summing will show image artifacts from aliasing. These can

be corrected by resampling the sampled pixels in order to

filter these artifacts. Figure 17 shows the pixel location

resulting from 2 ×2 summing or binning located in the

middle and the resulting pixel locations after the Bayer

re-sampling function has been applied.

Figure 17. Bayer Resampling

The improvements from using the Bayer resampling

feature can be seen in Figure 18. In this example, image

edges seen on a diagonal have smoother edges when the

Bayer re-sampling feature is applied. This feature is only

designed to be used with modes configured with 2 ×2

binning or summing. The feature will not remove aliasing

artifacts that are caused skipping pixels.

Figure 18. Results of Resampling

2 × 2 Binned − Before 2 × 2 Binned − After

Resampling

AR0833

www.onsemi.com

To enable the Bayer resampling feature:

1. Set R0x400 = 2 // Enable the on-chip scalar.

2. Set R0x306E to 0x90B0 // Configure the on-chip

scalar to resample Bayer data.

To disable the Bayer resampling feature:

1. Set R0x400 = 0 // Disable the on-chip scalar.

2. Set R0x306E to 0x9080 // Configure the on-chip

scalar to resample Bayer data.

NOTE: The image readout (rows and columns) has to

have two extra rows and two extra columns

when using the resample feature.

Figure 19. Illustration of Resampling Operation

Image Array Readout

3264 × 2448

Image Size Output

1632 × 1224

Resampled Image Output

1632 × 1224

Resampling2 × 2 Binning

One-Time Programmable Memory (OTPM)

The AR0833 features 5.6 Kb of one-time programmable

memory (OTPM) for storing shading correction

coefficients, individual module, and customer-specific

information. The user may program the data before

shipping. OTPM can be accessed through two-wire serial

interface. The AR0833 uses the auto mode for fast OTPM

programming and read operations.

To read out the OTPM, 1.8 V supply is required. As a

result, a dedicated DVDD_1V8 pad has been

implemented.During the programming process, a dedicated

pin for high voltage needs to be provided to perform the

anti-fusing operation. This voltage (VPP) would need to be

6.5 V. The completion of the programming process will be

communicated by a register through the two-wire serial

interface.

If the VPP pin does not need to be bonded out as a pin on

the module, it should be left floating inside the module.

The programming of the OTPM requires the sensor to be

fully powered and remain in software standby with its clock

input applied. The information will be programmed through

the use of the two-wire serial interface, and once the data is

written to an internal register, the programming host

machine will apply a high voltage to the programming pin,

and send a program command to initiate the anti-fusing

process. After the sensor has finished programming the

OTPM, a status bit will be set to indicate the end of the

programming cycle, and the host machine can poll the

setting of the status bit through the two-wire serial interface.

Only one programming cycle for the 16-bit word can be

performed.

Reading the OTPM data requires the sensor to be fully

powered and operational with its clock input applied. The

data can be read through a register from the two-wire serial

interface.

Programming and Verifying the OTPM

The procedure for programming and verifying the

AR0833 OTPM follows:

1. Apply power to all the power rails of the sensor

(VDD_IO, VAA, VAA_PIX, DVDD_1V2,

DVDD_1V2_PHY, and DVDD_1V8). VAA must be

set to 2.8 V during the programming process. VPP

must be initially floating. All other supplies must

be at their nominal voltage.

2. Provide a 12-MHz EXTCLK clock input.

3. Set R0x301A = 0x18, to put sensor in the soft

standby mode.

4. Set R0x3130 = 0xFF01 (Timing configuration)

5. Set R0x304C[15:8] = Record type (E.g. 0x30)

6. Set R0x304C[7:0] = Length of the record which is

the number of OTPM data registers that are filled

in.

7. Set R0x3054[9] = 0 to ensure that the error

checking and correction is enabled.

8. Write data into all the OTPM data registers:

R0x3800-R0x39FE.

9. Ramp up VPP to 6.5 V.

10. Set the otpm_control_auto_wr_start bit in the

otpm_control register R0x304A[0] = 1, to initiate

the auto program sequence. The sensor will now

program the data into the OTPM.

11. Poll otpm_control_auto_wr_end (R0x304A [1]) to

determine when the sensor is finished

programming the word.

12. Verify that the otpm_control_auto_wr_

success(0x304A[2]) bit is set.

13. If the above bits are not set to 1, then examine

otpm_status register R0x304E[9] to verify if the

OTPM memory is full and 0x304E[10] to verify if

OTPM memory is insufficient.

14. Remove the high voltage (VPP) and float VPP pin.

Reading the OTPM

1. Apply power to all the power rails of the sensor

(VDD_IO, VAA, VAA_PIX, DVDD_1V2,

DVDD_1V2_PHY, and DVDD_1V8) at their

nominal voltage.

2. Set EXTCLK to normal operating frequency.

3. Perform proper reset sequence to the sensor.

4. Set R0x3134 = 0xCD95 (Timing Configuration)

AR0833

www.onsemi.com

5. Set R0x304C[15:8] = Record Type (for example,

0x30)

6. Set R0x304C[7:0] = Length of the record which is

the number of data registers to be read back. This

could be set to 0 during OTPM auto read if length

is unknown.

7. Set R0x3054 = 0x0400

8. Initiate the auto read sequence by setting the

otpm_control_auto_read_start bit (R0x304A[4]) =

9. Poll the otpm_control_auto_rd_end bit

(R0x304A[5]) to determine when the sensor is

finished reading the word(s). When this bit

becomes 1, the otpm_control_auto_rd_success bit

(R0x304A[6]) will indicate whether the memory

was read successfully or not.

10. Data can now be read back from the otpm_data

registers (R0x3800-R0x39FE).

Image Acquisition Modes

The AR0833 supports two image acquisition modes:

1. Electronic rolling shutter (ERS) mode.

This is the normal mode of operation. When the

AR0833 is streaming, it generates frames at a

fixed rate, and each frame is integrated (exposed)

using the ERS. When the ERS is in use, timing

and control logic within the sensor sequences

through the rows of the array, resetting and then

reading each row in turn. In the time interval

between resetting a row and subsequently reading

that row, the pixels in the row integrate incident

light. The integration (exposure) time is controlled

by varying the time between row reset and row

readout. For each row in a frame, the time between

row reset and row readout is fixed, leading to a

uniform integration time across the frame. When

the integration time is changed (by using the

two-wire serial interface to change register

settings), the timing and control logic controls the

transition from old to new integration time in such

a way that the stream of output frames from the

AR0833 switches cleanly from the old integration

time to the new while only generating frames with

uniform integration. See “Changes to Integration

Time”.

2. Global reset release (GRR) mode.

his mode can be used to acquire a single image at

the current resolution. In this mode, the end point

of the pixel integration time is controlled by an

external electromechanical shutter, and the

AR0833 provides control signals to interface to

that shutter. The operation of this mode is

described in detail in “Global Reset Release

(GRR)”.

The benefit for the use of an external electromechanical

shutter is that it eliminates the visual artifacts associated

with ERS operation. Visual artifacts arise in ERS operation,

particularly at low frame rates, because an ERS image

effectively integrates each row of the pixel array at a

different point in time.

Window Control

The sequencing of the pixel array is controlled by the

x_addr_start, y_addr_start, x_addr_end, and y_addr_end

registers. The output image size is controlled by the

x_output_size and y_output_size registers.

Pixel Border

The default settings of the sensor provide a 3264

(H) x 2448 (V) image. A border of up to 8 pixels (4 in

binning) on each edge can be enabled by reprogramming the

x_addr_start, y_addr_start, x_addr_end, y_addr_end,

x_output_size, and y_output_size registers accordingly.

These border pixels can be used but are disabled by default.

Readout Modes

Horizontal Mirror

The horizontal_mirror bit in the image_orientation

of pixel readout within a row is reversed, so that readout

starts from x_addr_end and ends at x_addr_start. Figure 20

shows a sequence of 6 pixels being read out with

horizontal_mirror = 0 and horizontal_mirror = 1. Changing

horizontal_mirror causes the Bayer order of the output

image to change; the new Bayer order is reflected in the

value of the pixel_order register.

Figure 20. Effect of horizontal_mirror on Readout Order

G0[9:0] R0[9:0] G1[9:0] R1[9:0] G2[9:0] R2[9:0]

R2[9:0] G2[9:0] R1[9:0] G1[9:0] R0[9:0] G0[9:0]

LINE_VALID

horizontal_mirror = 0

horizontal_mirror = 1

DOUT[9:0]

AR0833

www.onsemi.com

Vertical Flip

When the vertical_flip bit is set in the image_orientation

reversed, so that row readout starts from y_addr_end and

ends at y_addr_start. Figure 21 shows a sequence of 6 rows

being read out with vertical_flip = 0 and vertical_flip = 1.

Changing vertical_flip causes the Bayer order of the output

image to change; the new Bayer order is reflected in the

value of the pixel_order register.

Figure 21. Effect of vertical_flip on Readout Order

Row0[9:0] Row1[9:0] Row2[9:0] Row3[9:0] Row4[9:0] Row5[9:0]

Row5[9:0] Row4[9:0] Row3[9:0] Row2[9:0] Row0[9:0]

FRAME_VALID

vertical_flip = 0

vertical_flip = 1 Row1[9:0]

DOUT[9:0]

Subsampling

The AR0833 supports subsampling to reduce the amount

of data processed by the signal chains in the AR0833,

thereby allowing the frame rate to be increased and power

consumption reduced. Subsampling is enabled by setting

x_odd_inc and/or y_odd_inc. Values of 1, 3, and 7 can be

supported. Setting both of these variables to 3 reduces the

amount of row and column data processed and is equivalent

to the 2 ×2 skipping readout mode provided by the AR0833.

Setting x_odd_inc = 3 and y_odd_inc = 3 results in a

quarter reduction in output image size. Figure 22 shows a

sequence of 8 columns being read out with x_odd_inc = 3

and y_odd_inc = 1.

Figure 22. Effect of x_odd_inc = 3 on Readout Sequence

G0[9:0] R0[9:0] G1[9:0] R1[9:0] G2[9:0] R2[9:0] G3[9:0] R3[9:0]

G0[9:0] R0[9:0] G2[9:0] R2[9:0]

LINE_VALID

x_odd_inc = 1

LINE_VALID

x_odd_inc = 3

DOUT[9:0]

A 1/16 reduction in resolution is achieved by setting both

x_odd_inc and y_odd_inc to 7. This is equivalent to 4 ×4

skipping readout mode provided by the AR0833. Figure 23

shows a sequence of 16 columns being read out with

x_odd_inc = 7 and y_odd_inc = 1.

Figure 23. Effect of x_odd_inc = 7 on Readout Sequence

G0[9:0] R0[9:0] G1[9:0] R1[9:0] G2[9:0] G7[9:0] R7[9:0]

G0[9:0] R0[9:0] G4[9:0] R4[9:0]

LINE_VALID

x_odd_inc = 1

LINE_VALID

x_odd_inc = 7

...

DOUT[9:0]

AR0833

www.onsemi.com

The effect of the different subsampling settings on the

pixel array readout is shown in Figure 24 through Figure 26.

Figure 24. Pixel Readout (No Subsampling)

X incrementing

Y incrementing

Figure 25. Skip2 Pixel Readout

(x_odd_inc = 3, y_odd_inc = 3)

X incrementing

Y incrementing

Figure 26. Skip4 Pixel Readout (x_odd_inc = 7, y_odd_inc = 7)

X incrementing

Y incrementing

AR0833

www.onsemi.com

Programming Restrictions when Subsampling

When subsampling is enabled and the sensor is switched

back and forth between full resolution and subsampling,

ON Semiconductor recommends that line_length_pck be

kept constant between the two modes. This allows the same

integration times to be used in each mode.

When subsampling is enabled, it may be necessary to

adjust the x_addr_start, x_addr_end, y_addr_start, and

y_addr_end settings: the values for these registers are

required to correspond with rows/columns that form part of

the subsampling sequence. The adjustment should be made

in accordance with these rules:

x_skip_factor = (x_odd_inc + 1) / 2

y_skip_factor = (y_odd_inc + 1) / 2

•x_addr_start should be a multiple of x_skip_factor x 4

•(x_addr_end − x_addr_start + x_odd_inc) should be a

multiple of x_skip_factor x 4

•(y_addr_end − y_addr_start + y_odd_inc) should be a

multiple of y_skip_factor x 4

The number of columns/rows read out with subsampling

can be found from the equation below:

•columns/rows = (addr_end − addr_start + odd_inc) /

skip_factor

Table 11 shows the row or column address sequencing for

normal and subsampled readout. In the 2X skip case, there

are two possible subsampling sequences (because the

subsampling sequence only reads half of the pixels)

depending upon the alignment of the start address. Similarly,

there will be four possible subsampling sequences in the 4X

skip case (though only the first two are shown in Table 11).

Table 11. ROW ADDRESS SEQUENCING DURING SUBSAMPLING

odd_inc = 1 (Normal) odd_inc = 3 (2y Skip) odd_inc = 7 (4y Skip)

Start = 0 Start = 0 Start = 0

0 0 0

1 1 1

4 4

5 5

8 8 8

9 9 9

12 12

13 13

Binning

The AR0833 supports 2 x 1 (column binning, also called

x-binning). Binning has many of the same characteristics as

skipping, but because it gathers image data from all pixels

in the active window (rather than a subset of them), it

achieves superior image quality and avoids the aliasing

artifacts that can be a characteristic side effect of skipping.

Binning is enabled by selecting the appropriate

subsampling settings (in read_mode, the sub-register

x_odd_inc = 3 and y_odd_inc = 1 for x-binning and setting

the appropriate binning bit in read_mode R0x3040[11] = 1

for x_bin_enable). As with skipping, x_addr_end and

y_addr_end may require adjustment when binning is

enabled. It is the first of the two columns/rows binned

together that should be the end column/row in binning, so

the requirements to the end address are exactly the same as

in skipping mode. The effect of the different binning is

shown in Figure 27 below and Figure 28.

Binning can also be enabled when the 4X subsampling

mode is enabled (x_odd_inc = 7 and y_odd_inc = 1 for

x-binning, x_odd_inc = 7 and y_odd_inc = 7 for 4X

xy-binning). In this mode, however, not all pixels will be

used so this is not a 4X binning implementation. An

implementation providing a combination of skip2 and bin2

is used to achieve 4X subsampling with better image quality.

The effect of this subsampling mode is shown in Figure 28.

AR0833

www.onsemi.com

Figure 27. Bin2 Pixel Readout (x_odd_inc = 3, y_odd_inc = 1, x_bin = 1)

X Incrementing

Y Incrementing

Figure 28. Bin2 Pixel Readout (x_odd_inc = 3, y_odd_inc = 3, x_bin = 1)

X Incrementing

Y Incrementing

AR0833

www.onsemi.com

Binning address sequencing is a bit more complicated

than during subsampling only, because of the

implementation of the binning itself.

For a given column n, there is only one other column,

n_bin, that can be binned with, because of physical

limitations in the column readout circuitry. The possible

address sequences are shown in Table 12.

Table 12. COLUMN ADDRESS SEQUENCING DURING BINNING

odd_inc = 1 (Normal) odd_inc = 3 (2y Bin) odd_inc = 7 (2y Skip + 2y Bin)

x_addr_start = 0 x_addr_start = 0 x_addr_start = 0

0 0/2 0/4

1 1/3 1/5

4 4/6

5 5/7

8 8/10 8/12

9 9/11 9/13

12 12/14

13 13/15

There are no physical limitations on what can be binned

together in the row direction. A given row n will always be

binned with row n+2 in 2X subsampling mode and with row

n+4 in 4X subsampling mode. Therefore, which rows get

binned together depends upon the alignment of

y_addr_start. The possible sequences are shown in Table 13.

Table 13. ROW ADDRESS SEQUENCING DURING BINNING

odd_inc = 1 (Normal) odd_inc = 3 (2y Bin) odd_inc = 7 (2y Skip + 2y Bin)

y_addr_start = 0 y_addr_start = 0 y_addr_start = 0

0 0/2 0/4

1 1/3 1/5

4 4/6

5 5/7

8 8/10 8/12

9 9/11 9/13

12 12/14

13 13/15

AR0833

www.onsemi.com

Programming Restrictions When Binning and Summing

Binning and summing require different sequencing of the

pixel array and impose different timing limits on the

operation of the sensor.

As a result, when xy-subsampling is enabled, some of the

programming limits declared in the parameter limit registers

are no longer valid. In addition, the default values for some

of the manufacturer-specific registers need to be

reprogrammed. See “Minimum Frame Time” and

”Minimum Row Time”.

Subsampling/Binning Options:

1. XskipYskip

R0x3040[11], x_bin_en: 0

R0x3040[13], row_sum: 0

R0x0382: x_odd_inc = 3 (xskip2) or

7 (xskip4)

R0x0386: y_odd_inc = 3 (yskip2), 7 (yskip4)

or 15 (yskip8)

2. XbinYskip

R0x3040[11], x_bin_en: 1

R0x3040[13], row_sum: 0

R0x0382: x_odd_inc = 3 (xbin2)

R0x0386: y_odd_inc = 3 (yskip2), 7 (yskip4)

or 15 (yskip8)

3. XskipYsum

R0x3040[11], x_bin_en: 0

R0x3040[13], row_sum: 1

R0x0382: x_odd_inc = 3 (xskip2) or

7 (xskip4)

R0x0386: y_odd_inc = 3 (ysum2)

4. XbinYsum

R0x3040[11], x_bin_en: 1

R0x3040[13], row_sum: 1

R0x0382: x_odd_inc = 3 (xbin2)

R0x0386: y_odd_inc = 3 (ysum2)

5. XsumYsum

R0x3040[11], x_bin_en: 1

R0x3040[13], row_sum: 1

R0x3EE4[0], sreg_colamp_sum2: 1

(cannot write to this bit when streaming −

have to write to entire register)

R0x0382: x_odd_inc = 3 (xsum2)

R0x0386: y_odd_inc = 3 (ysum2)

Binning, Skipping, and Summing Mode

Summing, skipping, and binning can be combined in the

modes listed in Table 14. Unlike binning mode where the

values of adjacent same color pixels are averaged together,

summing adds the pixel values together resulting in better

sensor sensitivity. Summing is supposed to provide two

times the sensitivity compared to the binning only mode.

Table 14. AVAILABLE SKIP, BIN, AND SUM MODES

IN THE AR0833 SENSOR

Subsampling

Method Horizontal Vertical

Skipping 2×, 4×2×, 4×, 8×

Binning 2×

Summing 2×2×

Figure 29. Pixel Binning and Summing

2 y 2 Binning or Summing X-binning Summing

Avg

SvSv

AR0833

www.onsemi.com

Scaler

Scaling reduces the size of the output image while

maintaining the same field−of−view. The input and output of

the scaler is in Bayer format.

When compared to skipping, scaling is advantageous as it

avoids aliasing. The scaling factor, programmable in 1/16

steps, is used for horizontal and vertical scalers.

The AR0833 sensor is capable of horizontal scaling and

full (horizontal and vertical) scaling.

The scale factor is determined by:

•n, which is fixed at 16

•m, which is adjustable with register R0x0404

•Legal values for m are 16 through 96, giving the user

the ability to scale from 1:1 (m = 16) to 1:6 (m = 96)

Frame Rate Control

The formulas for calculating the frame rate of the AR0833

are shown below.

The line length is programmed directly in pixel clock

periods through register line_length_pck. For a specific

window size, the minimum line length can be found from

Equation 8:

minimum line_length_pck +ǒx_addr_end *x_addr_start )1

subsampling factor )min_line_blanking_pckǓ(eq. 8)

Note that line_length_pck also needs to meet the

minimum line length requirement set in register

min_line_length_pck. The row time can either be limited by

the time it takes to sample and reset the pixel array for each

row, or by the time it takes to sample and read out a row.

Values for min_line_blanking_pck are provided in

“Minimum Row Time”.

The frame length is programmed directly in number of

lines in the register frame_line_length. For a specific

window size, the minimum frame length can be found in

Equation 9:

minimum frame_length_lines +ǒy_addr_end *y_addr_start )1

subsampling factor )min_frame_blanking_linesǓ(eq. 9)

The frame rate can be calculated from these variables and

the pixel clock speed as shown in Equation 10:

frame rate +

vt_pixel_clock_mhz 1 106

line_length_pck frame_length_lines (eq. 10)

If coarse_integration_time is set larger than

frame_length_lines the frame size will be expanded to

coarse_integration_time + 1.

Minimum Row Time

Enough time must be given to the output FIFO so it can

output all data at the set frequency within one row time.

There are therefore two checks that must all be met when

programming line_length_pck:

•line_length_pck ≥ min_line_length_pck in Table 15

•The row time must allow the FIFO to output all data

during each row. That is, line_length_pck ≥

(x_output_size × 2 + 0x005E) × “vt_pix_clk period” /

“op_pix_clk period”

Minimum Frame Time

The minimum number of rows in the image is 1, so

min_frame_length_lines will always equal (min_frame

_blanking_lines + 1).

Table 15. MINIMUM FRAME TIME

AND BLANKING NUMBERS

min_frame_blanking_lines 0x008F

min_frame_length_lines 0x0A1F

Integration Time

The integration (exposure) time of the AR0833 is

controlled by the coarse_integration_time register.

The limits for the coarse integration time are defined by:

coarse_integration_time_min vcoarse_integration_time (eq. 11)

The actual integration time is given by:

integration_time +

coarse_integration_time line_length_pck

vt_pix_clk_freq_mhz 106(eq. 12)

It is required that:

coarse_integration_time v(frame_length_lines *coarse_integration_time_max_margin) (eq. 13)

If this limit is broken, the frame time will automatically be

extended to (coarse_integration_time + coarse_integartion_

time_max_margin) to accommodate the larger integration

time.

In binning mode, frame_length_lines should be set larger

than coarse_integration_time by at least 3 to avoid column

imbalance artifact.

AR0833

www.onsemi.com

Flash Timing Control

The AR0833 supports both xenon and LED flash timing

through the FLASH output signal. The timing of the FLASH

signal with the default settings is shown in Figure 30

(xenon) and Figure 31 (LED). The flash and flash_count

registers allow the timing of the flash to be changed. The

flash can be programmed to fire only once, delayed by a few

frames when asserted, and (for xenon flash) the flash

duration can be programmed.

Enabling the LED flash will cause one bad frame, where

several of the rows only have the flash on for part of their

integration time. This can be avoided either by first enabling

mask bad frames (R0x301A[9] = 1) before the enabling the

flash or by forcing a restart (R0x301A[1] = 1) immediately

after enabling the flash; the first bad frame will then be

masked out, as shown in Figure 31. Read-only bit flash[14]

is set during frames that are correctly integrated; the state of

this bit is shown in Figures 30 and Figure 31.

Figure 30. Xenon Flash Enabled

FRAME_VALID

Flash STROBE

State of Triggered Bit

(R0x3046−7[14])

Figure 31. LED Flash Enabled

NOTE: An option to invert the flash output signal through R0x3046[7] is also available.

FRAME_VALID

Flash STROBE

State of Triggered Bit

(R0x3046−7[14])

Flash Enabled

during this Frame

Bad Frame

is Masked

Good Frame Good Frame

Bad Frame

is Masked

Flash Disabled

during this Frame

Global Reset Release (GRR)

Global reset release mode allows the integration time of

the AR0833 to be controlled by an external

electromechanical shutter. GRR mode is generally used in

conjunction with ERS mode. The ERS mode is used to

provide viewfinder information, the sensor is switched into

GRR mode to capture a single frame, and the sensor is then

returned to ERS mode to restore viewfinder operation.

Overview of Global Reset Release Sequence

The basic elements of the GRR sequence are:

1. By default, the sensor operates in ERS mode and

the SHUTTER output signal is LOW. The

electromechanical shutter must be open to allow

light to fall on the pixel array. Integration time is

controlled by the coarse_integration_time register.

2. A global reset sequence is triggered.

3. All of the rows of the pixel array are placed in

reset.

4. All of the rows of the pixel array are taken out of

reset simultaneously. All rows start to integrate

incident light. The electromechanical shutter may

be open or closed at this time.

5. If the electromechanical shutter has been closed, it

is opened.

6. After the desired integration time (controlled

internally or externally to the AR0833), the

electromechanical shutter is closed.

7. A single output frame is generated by the sensor

with the usual LV, FV, PIXCLK, and DOUT timing.

As soon as the output frame has completed (FV

negates), the electromechanical shutter may be

opened again.

8. The sensor automatically resumes operation in

ERS mode.

This sequence is shown in Figure 32. The following

sections expand to show how the timing of this sequence is

controlled.

AR0833

www.onsemi.com

Figure 32. Overview of Global Reset Sequence

ERS Row Reset Integration Readout ERS

Entering and Leaving the Global Reset Sequence

A global reset sequence can be triggered by a register

write to R0x315E global_seq_trigger[0] (global trigger, to

transition this bit from a 0 to a 1) or by a rising edge on a

suitably-configured GPI input).

When a global reset sequence is triggered, the sensor waits

for the end of the current row. When LV negates for that row,

FV is negated 6 PIXCLK periods later, potentially

truncating the frame that was in progress.

The global reset sequence completes with a frame

readout. At the end of this readout phase, the sensor

automatically resumes operation in ERS mode. The first

frame integrated with ERS will be generated after a delay of

approximately ((13 + coarse_integration_time) x

line_length_pck). This sequence is shown in Figure 33.

While operating in ERS mode, double-buffered registers

(“Double-Buffered Registers”) are updated at the start of

each frame in the usual way. During the global reset

sequence, double-buffered registers are updated just before

the start of the readout phase.

Figure 33. Entering and Leaving a Global Reset Sequence

ERS Row Reset Integration Readout ERS

Trigger

Wait for End of Current Row Automatic at End of Frame Readout

Programmable Settings

The registers global_rst_end and global_read_start allow

the duration of the row reset phase and the integration phase

to be controlled, as shown in Figure 34. The duration of the

readout phase is determined by the active image size.

The recommended setting for global_rst_end is 0x3160

(for example, 512 μs total reset time) with default

vt_pix_clk. This allows sufficient time for all rows of the

pixel array to be set to the correct reset voltage level. The

row reset phase takes a finite amount of time due to the

capacitance of the pixel array and the capability of the

internal voltage booster circuit that is used to generate the

reset voltage level.

As soon as the global_rst_end count has expired, all rows

in the pixel array are taken out of reset simultaneously and

the pixel array begins to integrate incident light.

Figure 34. Controlling the Reset and Integration Phases of the Global Reset Sequence

ERS Row Reset Integration Readout ERS

Trigger

Wait for End of Current Row Automatic at End of Frame Readout

global_rst_end

global_read_start

Control of the Electromechanical Shutter

Figure 35 shows two different ways in which a shutter can

be controlled during the global reset sequence. In both cases,

the maximum integration time is set by the difference

between global_read_start and global_rst_end. In shutter

example 1, the shutter is open during the initial ERS

sequence and during the row reset phase. The shutter closes

during the integration phase. The pixel array is integrating

incident light from the start of the integration phase to the

point at which the shutter closes. Finally, the shutter opens

again after the end of the readout phase. In shutter example

2, the shutter is open during the initial ERS sequence and

closes sometime during the row reset phase. The shutter both

opens and closes during the integration phase. The pixel

array is integrating incident light for the part of the

integration phase during which the shutter is open. As for the

previous example, the shutter opens again after the end of

the readout phase.

AR0833

www.onsemi.com

Figure 35. Control of the Electromechanical Shutter

ERS Row Reset Integration Readout ERS

Trigger

Wait for End of Current Row Automatic at End of Frame Readout

global_rst_end

global_read_start

Maximum

Integration Time

Actual Integration Time

Closed Shutter ClosedShutter Open Shutter Open

Shutter Closed Shutter Open

Actual Integration Time

SHUTTER Example 1

Shutter Open (Physical)

SHUTTER Example 2

Shutter Open (Physical)

It is essential that the shutter remains closed during the

entire row readout phase (that is, until FV has negated for the

frame readout); otherwise, some rows of data will be

corrupted (over-integrated).

It is essential that the shutter closes before the end of the

integration phase. If the row readout phase is allowed to start

before the shutter closes, each row in turn will be integrated

for one row-time longer than the previous row.

After FV negates to signal the completion of the readout

phase, there is a time delay of approximately (10 x

line_length_pck) before the sensor starts to integrate

light-sensitive rows for the next ERS frame. It is essential

that the shutter be opened at some point in this time window;

otherwise, the first ERS frame will not be uniformly

integrated.

The AR0833 provides a SHUTTER output signal to

control (or help the host system control) the

electromechanical shutter. The timing of the SHUTTER

output is shown in Figure 36. SHUTTER is negated by

default. The point at which it asserts is controlled by the

programming of global_shutter_start. At the end of the

global reset readout phase, SHUTTER negates

approximately (2 x line_length_pck) after the negation of

FV.

This programming restriction must be met for correct

operation:

•global_read_start > global_shutter_start

Figure 36. Controlling the SHUTTER Output

ERS Row Reset Integration Readout ERS

Trigger

Wait for End of Current Row Automatic at End of Frame Readout

global_rst_end

global_read_start

SHUTTER (Signal)

global_shutter_start

~2 × line_length_pck

AR0833

www.onsemi.com

Using FLASH with Global Reset

If R0x315E global_seq_trigger[2] = 1 (global flash

enabled) when a global reset sequence is triggered, the

FLASH output signal will be pulsed during the integration

phase of the global reset sequence. The FLASH output will

assert a fixed number of cycles after the start of the

integration phase and will remain asserted for a time that is

controlled by the value of the flash_count register. When

flash_count is programmed for value N, (where N is

0–0x3FE) the resulting flash duration is given by

N x 512 x (1/vt_pix_clk_freq_mhz), as shown in Figure 37.

Figure 37. Using FLASH with Global Reset

ERS Row Reset Integration Readout ERS

Trigger

Wait for End of Current Row Automatic at End of Frame Readout

global_rst_end

global_read_start

SHUTTER

global_shutter_start

~2 × line_length_pck

FLASH

(Fixed)

flash_count

When the flash_count = 0x3FF, the flash signal will be

maximized and goes LOW when readout starts, as shown in

Figure 38. This would be preferred if the latency in closing

the shutter is longer than the latency for turning off the flash.

This guarantees that the flash stays on while the shutter is

open.

Figure 38. Extending FLASH Duration in Global Reset (Reference Readout Start)

ERS Row Reset Integration Readout ERS

Trigger

Wait for End of Current Row Automatic at End of Frame Readout

global_rst_end

global_read_start

SHUTTER

global_shutter_start

~2 × line_length_pck

FLASH

(Fixed)

AR0833

www.onsemi.com

External Control of Integration Time

If global_seq_trigger[1] = 1 (global bulb enabled) when

a global reset sequence is triggered, the end of the

integration phase is controlled by the level of trigger

(global_seq_trigger[0] or the associated GPI input). This

allows the integration time to be controlled directly by an

input to the sensor.

This operation corresponds to the shutter “B” setting on a

traditional camera, where “B” originally stood for “Bulb”

(the shutter setting used for synchronization with a

magnesium foil flash bulb) and was later considered to stand

for “Brief” (an exposure that was longer than the shutter

could automatically accommodate).

When the trigger is de-asserted to end integration, the

integration phase is extended by a further time given by

global_read_start – global_shutter_start. Usually this

means that global_read_start should be set to

global_shutter_start + 1.

The operation of this mode is shown in Figure 39. The

figure shows the global reset sequence being triggered by the

GPI2 input, but it could be triggered by any of the GPI inputs

or by the setting and subsequence clearing of the

global_seq_trigger[0] under software control.

The integration time of the GRR sequence is defined as:

Integration Time +

global_scale [global_read_start *global_shutter_start *global_rst_end]

vt_pix_clk_freq_mhz (eq. 14)

where:

global_read_start +ǒ216 global_read_start2[7:0] )global_read_start1[15:0]Ǔ(eq. 15)

global_shutter_start +ǒ216 global_shutter_start2[7:0] )global_shutter_start1[15:0]Ǔ(eq. 16)

The integration equation allows for 24-bit precision when

calculating both the shutter and readout of the image. The

global_rst_end has only 16-bit as the array reset function

and requires a short amount of time.

The integration time can also be scaled using

global_scale. The variable can be set to

0–512, 1–2048, 2–128, and 3–32.

These programming restrictions must be met for correct

operation of bulb exposures:

•global_read_start > global_shutter_start

•global_shutter_start > global_rst_end

•global_shutter_start must be smaller than the exposure

time (that is, this counter must expire before the trigger

is de-asserted)

Figure 39. Global Reset Bulb

ERS Row Reset Integration Readout ERS

Trigger

Wait for End of Current Row Automatic at End of Frame Readout

global_rst_end

GPI2

global_read_start − global_shutter_start

Retriggering the Global Reset Sequence

The trigger for the global reset sequence is edge-sensitive;

the global reset sequence cannot be retriggered until the

global trigger bit (in the R0x315E global_seq_trigger

associated with the trigger function has been negated.

The earliest time that the global reset sequence can be

retriggered is the point at which the SHUTTER output

negates; this occurs approximately (2 x line_length_pck)

after the negation of FV for the global reset readout phase.

Using Global Reset with SMIA Data Path

When a global reset sequence is triggered, it usually

results in the frame in progress being truncated (at the end

of the current output line). The SMIA data path limiter

function (see Figure 40) attempts to extend (pad) all frames

to the programmed value of y_output_size. If this padding

is still in progress when the global reset readout phase starts,

the SMIA data path will not detect the start of the frame

correctly. Therefore, to use global reset with the serial data

path, this timing scenario must be avoided. One possible

way of doing this would be to synchronize (under software

control) the assertion of trigger to an end-of-frame marker

on the serial data stream.

At the end of the readout phase of the global reset

sequence, the sensor automatically resumes operation in

ERS mode.

AR0833

www.onsemi.com

Global Reset and Soft Standby

If the R0x301A[2] mode_select[stream] bit is cleared

while a global reset sequence is in progress, the AR0833 will

remain in streaming state until the global reset sequence

(including frame readout) has completed, as shown in

Figure 40.

Figure 40. Entering Soft Standby During a Global Reset Sequence

ERS Row Reset Integration Readout ERS

Software

Standby

StreamingSystem Style

R0x0100

mode_select[streaming]

Slave Mode

Slave mode is to ensure having an ERS-GRR-ERS

transition without a broken ERS frame before GRR. It

requests to trigger/end the GRR sequence through the pin

which is similar to the GRR Bulb mode. The major

difference to our existing sensor is to start the GRR sequence

after the end of the current frame instead of to start

immediately in the next following row.

Figure 41. Slave Mode Transition

Sensor Readout Sensor Readout Sensor Readout

GRR TRIG ON

Wait for VD,

then Global Reset Sequence Starts

Sensor Starts to Read Out

after VD is Inserted

AR0833

www.onsemi.com

GAIN

AR0833 supports both analog and digital gain.

Analog Gain

Analog gain is provided by colamp and ADC reference

scaling (there is no ASC gain due to column parallel nature

of architecture). Only global (not per-color) coarse gain can

be set by analog gain. Global gain register (R0x305E) sets

the analog gain. Bits [1:0] set the colamp gain while bits

[4:2] are reserved for ADC gain. While the 2-bit colamp gain

provides up to 4x analog gain, only LSB (bit [2]) of ADC

gain bits is utilized to support 2x ADC gain. Table 16 is the

recommended gain setting:

Table 16. RECOMMENDED ANALOG GAIN SETTING

Colamp Gain Codes

(R0x305E[1:0])

ADC Gain Codes

(R0x305E[4:2]) Colamp Gain ADC Gain Total Gain

00000111

01000212

10000313

11000414

10001326

11001428

Digital Gain

Digital gain provides both per-color and fine (sub 1x)

gain. The analog and digital gains are multiplicative to give

the total gain. Digital gain is set by setting bits

R0x305E[15:5] to set global gain or by individually setting

digital color gain R0x3056-C[15:5] where these 11 bits are

designed in 4p7 format i.e. 4 MSB provide gain up to 15x in

step of 1x while 7 LSB provide sub-1x gain with a step size

of 1/128. This sub-1x gain provides the fine gain control for

the sensor.

Total Gain

Max. total gain required by design spec is 8x (analog) and

16x (digital) with min. step size of 1/8. The total gain

equation can be formulated as:

Total Gain +(1 )dec(R0x305D[1:0])) (1 )R0x305E[2]) dec(R0x305X[15:5])

128 (eq. 17)

where X is 6, 8, A, C, for Gr, B, R and Gb, respectively.

NOTE: ON Semiconductor recommends using the

registers mentioned above for gain settings.

Avoid R0x3028 to R0x3038 unless their

mapping to above registers is well understood

and taken into account.

AR0833

www.onsemi.com

TEMPERATURE SENSOR

A standalone PTAT based temperature sensor has been

implemented. The block is controlled independent of sensor

timing and all communication happens through the

two-wire serial interface.

INTERNAL VCM DRIVER

The AR0833 utilizes an internal Voice Coil Motor (VCM)

driver. The VCM functions are register-controlled through

the serial interface.

There are two output ports, VCM_ISINK and

VCM_GND, which would connect directly to the AF

actuator.

Take precautions in the design of the power supply routing

to provide a low impedance path for the ground connection.

Appropriate filtering would also be required on the actuator

supply. Typical values would be a 0.1 μF and 10 μF in

parallel.

Figure 42. VCM Driver Typical Diagram

AR0833 VCM

VVCM

DGND

10 mF

VCM_ISINK

VCM_GND

Table 17. VCM DRIVER TYPICAL

Characteristic Parameter Minimum Typical Maximum Unit

VCM_OUT Voltage at VCM Current Sink 2.5 2.8 3.3 V

WVCM Voltage at VCM Actuator 2.5 2.8 3.3 V

INL Relative Accuracy –±1.5 ±4LSB

RES Resolution – 8 – bits

DNL Differential Nonlinearity −1 – +1 LSB

IVCM Output Current 90 100 110 mA

Slew Rate (User Programmable) – – 13 mA/ms

AR0833

www.onsemi.com

SPECTRAL CHARACTERISTICS

Figure 43. Quantum Efficiency

Wavelength (nm)

Quantum Efficiency (%)

350 400 450 500 550 600 650 700 750

Red

Green

Blue

CRA vs. Image Height Plot

Image Height CRA

(%) (mm) (deg)

Figure 44. Chief Ray Angle (CRA) vs. Image Height

0 102030405060708090100110

CRA (deg)

IMAGE HEIGHT (%)

0 0 0

5 0.143 0.77

10 0.286 1.55

15 0.428 2.33

20 0.571 3.11

25 0.714 3.87

30 0.857 4.62

35 1.000 5.36

40 1.142 6.07

45 1.285 6.77

50 1.428 7.43

55 1.571 8.06

60 1.714 8.66

65 1.856 9.22

70 1.999 9.73

75 2.142 10.19

80 2.285 10.59

85 2.428 10.93

90 2.570 11.18

95 2.713 11.34

100 2.856 11.40

AR0833

www.onsemi.com

ELECTRICAL CHARACTERISTICS

Two-Wire Serial Register Interface

The electrical characteristics of the two-wire serial

Table 18. Table 19 shows the timing specification for the

two-wire serial interface.

ÈÈÈ

ËË

ÍÍÍ

Figure 45. Two-Wire Serial Bus Timing Parameters

NOTE: Read sequence: For an 8-bit READ, read waveforms start after WRITE command and register address are issued.

70%

30%

70%

30% 30% 30%

70% 70%

70%

30% 30%

1st Clock 9th Clock

SDATA

SCLK

tSRTH

tSDS tSDH

tACV

tSDV

SDATA

SCLK

9th Clock

70%

70% 70% 70%

30%

70%

70% 70%

30%

tHIGH

tSRTS

tLOW

30%

tSTPS

tBUF

Table 18. TWO-WIRE SERIAL REGISTER INTERFACE ELECTRICAL CHARACTERISTICS

(fEXTCLK = 25 MHz; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_IO = 1.8 V; VDD (Digital Core) = 1.2 V; VDD_PLL = 1.2 V; VDD_TX = 1.8 V;

Output Load = 68.5 pF; TJ = 55°C)

Symbol Parameter Condition Min Typ Max Unit

VIL Input LOW Voltage −0.5 –0.3 × VDD_IO V

VIH Input HIGH Voltage 0.7 × VDD_IO – VDD_IO + 0.5 V

IIN Input Leakage Current No Pull Up Resistor;

VIN = VDD_IO or DGND

10 – 14 mA

VOL Output LOW Voltage At Specified 2 mA 0.11 – 0.3 V

IOL Output LOW Current At Specified VOL 0.1 V – – 6 mA

CIN Input Pad Capacitance – – 6 pF

CLOAD Load Capacitance – – N/A pF

Table 19. TWO-WIRE SERIAL INTERFACE TIMING SPECIFICATIONS

(VDD = 1.7−1.9 V; VAA = 2.4 −3.1 V; Environment Temperature = −30°C to 50°C)

Symbol Definition Min Max Unit

fSCLK SCLK Frequency 100 400 kHz

tHIGH SCLK High Period 0.6 – ms

tLOW SCLK Low Period 1.3 – ms

tSRTS START Setup Time 0.6 – ms

tSRTH START Hold Time 0.6 – ms

tSDS Data Setup Time 100 – ns

tSDH Data Hold Time 0−ms

tSDV Data Valid Time – 0.9 ms

tACV Data Valid Acknowledge Time – 0.9 ms

tSTPS STOP Setup Time 0.6 – ms

AR0833

www.onsemi.com

Table 19. TWO-WIRE SERIAL INTERFACE TIMING SPECIFICATIONS (continued)

(VDD = 1.7−1.9 V; VAA = 2.4 −3.1 V; Environment Temperature = −30°C to 50°C)

Symbol UnitMaxMinDefinition

tBUF Bus Free Time between STOP and START 1.3 – ms

trSCLK and SDATA Rise Time – 300 ns

tfSCLK and SDATA Fall Time – 300 ns

EXTCLK

The electrical characteristics of the EXTCLK input are

shown in Table 20. The EXTCLK input supports an

AC-coupled sine-wave input clock or a DC-coupled

square-wave input clock.

If EXTCLK is AC-coupled to the AR0833 and the clock

is stopped, the EXTCLK input to the AR0833 must be

driven to ground or to VDD_IO. Failure to do this will result

in excessive current consumption within the EXTCLK input

receiver.

Table 20. ELECTRICAL CHARACTERISTICS (EXTCLK)

(fEXTCLK = 24 MHz; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_IO = 1.8 V; DVDD_1V2 = 1.2 V, Output load = 68.5 pF; TJ = 55°C)

Symbol Parameter Condition Min Typ Max Unit

fEXTCLK1 Input Clock Frequency PLL Enabled 6 24 27 MHz

tRInput Clock Rise Slew Rate CLOAD <20pF – 2.883 – ns

tFInput Clock Fall Slew Rate CLOAD <20pF – 2.687 – ns

VIN_AC Input Clock Minimum Voltage

Swing (AC Coupled)

– 0.5 – – V (p-p)

VIN_DC Input Clock Maximum Voltage

Swing (DC Coupled)

– – – VDD_IO + 0.5 V

fCLKMAX(AC) Input Clock Signaling Frequency

(Low Amplitude)

VIN = VIN_AC (MIN) – – 25 MHz

fCLKMAX(DC) Input Clock Signaling Frequency

(Full Amplitude)

VIN = VDD_IO – – 48 MHz

Clock Duty Cycle – 45 50 55 %

tJITTER Input Clock Jitter Cycle-to-Cycle – 545 600 ps

tLOCK PLL VCO Lock Time – – 0.2 2 ms

CIN Input Pad Capacitance – – 6 – pF

IIH Input HIGH Leakage Current – 0 – 10 mA

VIH Input HIGH Voltage 0.7 × VDD_IO −VDD_IO + 0.5 −V

VIL Input LOW Voltage −0.5 −0.3 × VDD_IO −V

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

AR0833

www.onsemi.com

Serial Pixel Data Interface

The electrical characteristics of the serial pixel data

interface (CLK_P, CLK_N, DATA[4:1]_P, and

DATA[4:1]_N) are shown in Table 21.

Table 21. ELECTRICAL CHARACTERISTICS (SERIAL MIPI PIXEL DATA INTERFACE)

Symbol Parameter Min Typ Max Unit

VOD High speed transmit differential voltage 140 270 mV

VCMTX High speed transmit static common-mode voltage 150 200 250 mV

ΔVOD VOD mismatch when output is Differential-1 or Differential-0 <10 mV

ZOS Single ended output impedance 40 50 62.5 Ω

ΔZOS Single ended output impedance mismatch <14 %

ΔVCMTX(L,F) Common-level variation between 50–450 MHz <25 mV

tRRise time (20–80%) 150 350 380 ps

tFFall time (20–80%) 150 350 380 ps

VOL LP Output LOW level –50 to 50 mV

VOH LP Output HIGH level 1.1 1.3 V

ZOLP Output impedance of low power parameter 140 Ω

TRLP 15–85% rise time 25 ns

TFLP 15–85% fall time 25 ns

Δv/Δdtsr Slew rate (CLOAD = 20–70 pF) 30 mV/ns

Control Interface

The electrical characteristics of the control interface

(RESET_BAR, TEST, GPIO0, GPIO1, GPI2, and GPI3) are

shown in Table 22.

Table 22. DC ELECTRICAL CHARACTERISTICS (CONTROL INTERFACE)

(fEXTCLK = 24 MHz; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_IO = 1.8 V; DVDD_1V2 = 1.2 V, Output Load = 68.5 pF; TJ = 55°C)

Symbol Parameter Condition Min Typ Max Unit

VIH Input HIGH Voltage 0.7 x VDD_IO – VDD_IO + 0.5 V

VIL Input LOW Voltage –0.5 – VDD_IO X 0.3 V

IIN Input Leakage Current No pull-up resistor;

VIN = VDD_IO or DGND

– – 10 μA

CIN Input Pad Capacitance – 6 – pF

Operating Voltages

VAA and VAA_PIX must be at the same potential for

correct operation of the AR0833.

Table 23. MAXIMUM VALUE RANGES

(fEXTCLK = 24 MHz; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_IO = 1.8V; DVDD_1V2 = 1.2 V; Output Load = 68.5 pF; TJ = 70°C;

Mode = Full Resolution (3264 x 2488); Frame rate = 30 fps)

Symbol Parameter Condition Min Typ Max Unit

VAA Analog Voltage 2.5 2.8 3.1 V

VAA_PIX Pixel Supply Voltage 2.5 2.8 3.1 V

DVDD_1V2 Digital Voltage 1.14 1.2 1.3 V

DVDD_1V8 PHY Digital Voltage 1.7 1.8 1.9 V

VDD_IO I/O Digital Voltage 1.7 1.8 1.9 V

2.5 2.8 3.1 V

DVDD_1V2_PHY MIPI Supply 1.14 1.2 1.3 V

AR0833

www.onsemi.com

Table 23. MAXIMUM VALUE RANGES(continued)

(fEXTCLK = 24 MHz; VAA = 2.8 V; VAA_PIX = 2.8 V; VDD_IO = 1.8V; DVDD_1V2 = 1.2 V; Output Load = 68.5 pF; TJ = 70°C;

Mode = Full Resolution (3264 x 2488); Frame rate = 30 fps)

Symbol UnitMaxTypMinConditionParameter

H/W Standby Current

Consumption

– – 30 μA

H/W Standby Power

Consumption

– – 84 μW

Output Driving Strength 10 – – mA

Slew Rate – 0.7 – μV/sec

Programming voltage

for OTPM (VPP)

6 6.5 7 V

TOP Operating Temperature Measure at junction –30 – 70 °C

TSTG Storage Temperature –40 – 85 °C

Typical Operating Current Consumption (MIPI)

Table 24. TYPICAL OPERATING CURRENT CONSUMPTION (MIPI)

(Nominal Voltages: fEXTCLK = 24 MHz; VAA = 2.8 V; VAA_PIX = 2.8 V; DVDD_1V8 = 1.8 V; VDD_IO = 1.8 V; DVDD_1V2 = 1.2 V

High Voltages: fEXTCLK = 24 MHz; VAA = 3.1 V; VAA_PIX = 3.1 V; DVDD_1V8 = 1.9 V; VDD_IO = 1.9 V; DVDD_1V2 = 1.3 V;

TJ = 25°C)

Symbol Parameter Condition Min Typ Max Unit

IAA Analog Supply Current Full resolution 4:3 − 30 fps −55 75 mA

Full resolution 16:9 − 30 fps −55 75 mA

1080p, 30 fps −43 75 mA

720p, 60 fps −55 75 mA

VGA, 60 fps −55 75 mA

IAA_PIX Pixel Supply Current Full resolution 4:3 − 30 fps −14 18 mA

Full resolution 16:9 − 30 fps −14 18 mA

1080p, 30 fps −8 18 mA

720p, 60 fps −14 18 mA

VGA, 60 fps −14 18 mA

IDD_1V8 OTPM Read Supply

Current

Full resolution 4:3 − 30 fps −5 10 mA

Full resolution 16:9 − 30 fps −5 10 mA

1080p, 30 fps −6 10 mA

720p, 60 fps −5 10 mA

VGA, 60 fps −5 10 mA

IDD_IO I/O Supply Current Full resolution 4:3 − 30 fps – 0.02 0.03 mA

Full resolution 16:9 − 30 fps – 0.02 0.03 mA

1080p, 30 fps – 0.03 0.03 mA

720p, 60 fps – 0.02 0.03 mA

VGA, 60 fps – 0.02 0.03 mA

IDD_1V2 Digital Supply Current Full resolution 4:3 − 30 fps – 105 130 mA

Full resolution 16:9 − 30 fps – 93 115 mA

1080p, 30 fps – 53 110 mA

720p, 60 fps – 75 90 mA

VGA, 60 fps – 75 90 mA

AR0833

www.onsemi.com

Table 24. TYPICAL OPERATING CURRENT CONSUMPTION (MIPI) (continued)

(Nominal Voltages: fEXTCLK = 24 MHz; VAA = 2.8 V; VAA_PIX = 2.8 V; DVDD_1V8 = 1.8 V; VDD_IO = 1.8 V; DVDD_1V2 = 1.2 V

High Voltages: fEXTCLK = 24 MHz; VAA = 3.1 V; VAA_PIX = 3.1 V; DVDD_1V8 = 1.9 V; VDD_IO = 1.9 V; DVDD_1V2 = 1.3 V;

TJ = 25°C)

Symbol UnitMaxTypMinConditionParameter

PHY supply

current

PHY Supply Current Full resolution 4:3 − 30 fps – 10 14 mA

Full resolution 16:9 − 30 fps – 8 11 mA

1080p, 30 fps – 1 4 mA

720p, 60 fps – 3 3 mA

VGA, 60 fps – 1 2 mA

Absolute Maximum Ratings

Table 25. ABSOLUTE MAX VOLTAGES

Symbol Parameter Condition Min Typ Max

VDD_1V2 Digital/Analog Voltage −0.3 1.5 V

DVDD_1V8 OTPM −0.3 2.1 V

VDD_IO I/O Digital Voltage −0.3 3.5 V

VAA Analog Voltage −0.3 3.5 V

VAA_PIX Pixel Supply Voltage −0.3 3.5 V

DVDD_1V2_PHY MIPI Supply −0.3 1.5 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

MIPI SPECIFICATION REFERENCE

The sensor design and this documentation is based on the

following MIPI Specifications:

•MIPI Alliance Standard for CSI−2 version 1.0

•MIPI Alliance Standard for D−PHY version 1.0

A−PixHS is a trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.

CLCC48 10x10

CASE 848AJ

ISSUE O DATE 30 DEC 201

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

http://onsemi.com

October, 2002 − Rev. 0 Case Outline Number:

XXX

DOCUMENT NUMBER:

STATUS:

REFERENCE:

DESCRIPTION:

98AON93121F

ON SEMICONDUCTOR STANDARD

CLCC48 10X10

Electronic versions are uncontrolled except when

accessed directly from the Document Repository. Printed

versions are uncontrolled except when stamped

“CONTROLLED COPY” in red.

PAGE 1 OF 2

DOCUMENT NUMBER:

98AON93121F

PAGE 2 OF 2

ISSUE REVISION DATE

ORELEASED FOR PRODUCTION FROM APTINA POD# AR0833 TO ON SEMICON-

DUCTOR. REQ. BY D. TRUHITTE. 30 DEC 2014

December, 2014 − Rev. O Case Outline Number

848A

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, af filiates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.

ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor ’s product/patent

coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.

ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,

regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer

application by customer ’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not

designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification

in a foreign jurisdiction or any devices intended for implantation in the human body . Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized

application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and

expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such

claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This

literature is subject to all applicable copyright laws and is not for resale in any manner.

UBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your loc

Sales Representative

◊