ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 2.2V, 12-Bit, 4-Channel, microPOWERTM ANALOG-TO-DIGITAL CONVERTER WITH I2C INTERFACE Check for Samples: ADS7924 FEATURES DESCRIPTION * Intelligent Monitoring: - Auto-Sequencing of 4-Channel Multiplexer - Individual Alarm Thresholds for Each Channel - Programmable Scan Rate * Micropower Monitoring: - Four-Channel Scanning: - Every 1ms 25mW - Every 10ms 5mW - < 1A of Power-Down Current - Programmable Interrupt Pin Controls Shutdown/Wakeup of the Microcontroller - Auto Power-Down Control - PWRCON Pin Allows Shutdown of External Op Amp * Wide Supply Range: - Analog Supply: 2.2V to 5.5V - Digital Supply: 1.65V to 5.5V * Small Footprint: 3mm x 3mm QFN The ADS7924 is a four-channel, 12-bit, analog-to-digital converter (ADC) with an I2CTM interface. With its low-power ADC core, support for low-supply operation, and a flexible measurement sequencer that essentially eliminates power consumption between conversions, the ADS7924 forms a complete monitoring system for power-critical applications such as battery-powered equipment and energy harvesting systems. 1 234 APPLICATIONS * * Portable and Battery-Powered Systems: - Medical, Communications, Remote Sensor Signal Monitoring, Power-Supply Monitoring Energy Harvesting MUX OUT ADCIN The ADS7924 features dedicated data registers and onboard programmable digital threshold comparators for each input. Alarm conditions can be programmed that generate an interrupt. The combination of data buffering, programmable threshold comparisons, and alarm interrupts minimize the host microcontroller time needed to supervise the ADS7924. The four-channel input multiplexer (MUX) is routed through external pins to allow a common signal conditioning circuit to be used between the MUX and ADC, thereby reducing overall component count. The low-power ADC uses the analog supply as its reference and can acquire and convert signals in only 10ms. An onboard oscillator eliminates the need to supply a master clock. The ADS7924 is offered in a small 3mm x 3mm QFN and is fully specified for operation over the industrial temperature range of -40C to +85C. AVDD DVDD SDA 2 IC Interface CH0 CH1 CH2 4-Channel MUX SAR ADC Data Buffers, Sequencer, and Alarms SCL A0 INT CH3 PWRCON RESET Oscillator AGND DGND 1 2 3 4 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. microPOWER is a trademark of Texas Instruments Incorporated. I2C is a trademark of NXP Semiconductors. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2010, Texas Instruments Incorporated ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the device product folder at ti.com. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range, unless otherwise noted. ADS7924 UNIT Supply voltage, AVDD to AGND -0.3 to +6 V Supply voltage, DVDD to DGND -0.3 to +6 V Supply voltage, DVDD to AVDD AVDD DVDD V -0.3 to +0.3 V AGND - 0.3 to AVDD + 0.3 V DGND - 0.3 to 6 V AGND to DGND Analog input voltage Digital input voltage with respect to DGND (SCL and SDA) Digital input voltage with respect to DGND (A0, RESET) Input current to all pins except supply pins Maximum operating temperature Storage temperature range (1) DGND - 0.3 to DVDD + 0.3 V -10 to +10 mA +125 C -60 to +150 C Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. THERMAL INFORMATION ADS7924 THERMAL METRIC (1) RTE UNITS 16 qJA Junction-to-ambient thermal resistance 48.1 qJC(top) Junction-to-case(top) thermal resistance 47.3 qJB Junction-to-board thermal resistance 60.8 yJT Junction-to-top characterization parameter 0.3 yJB Junction-to-board characterization parameter 14.1 qJC(bottom) Junction-to-case(bottom) thermal resistance 0.4 (1) 2 C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 ELECTRICAL CHARACTERISTICS Minimum/maximum specifications are at TA = -40C to +85C, 1.65V < DVDD < 5.5V, and 2.2V < AVDD < 5.5V. Typical specifications are at TA = +25C, AVDD = 5V, and DVDD = 5V, unless otherwise noted. ADS7924 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ANALOG INPUT Full-scale input span (CHX - AGND) 0 Input capacitance (1) 4 AVDD V 10 pF ADC sampling capacitance 15 MUX resistance 60 pF Input channel crosstalk 85 dB 12 Bits SYSTEM PERFORMANCE Resolution No missing codes 12 Bits Integral linearity -1.5 0.5 1.5 LSBs Differential linearity -1.0 0.6 1.5 LSBs Offset error -5 Offset error drift 5 0.01 Gain error -0.20 Gain error drift -0.01 0.20 0.6 Noise (rms) LSBs LSB/C % ppm/C 0.125 LSB SAMPLING DYNAMICS Monitoring time/channel (2) 10 s 20 % CLOCK Internal clock frequency variation DIGITAL INPUT/OUTPUT Logic family CMOS Logic level: VIH (SDA, SCL, A0, RESET) 0.8 DVDD DVDD + 0.3 VIL (SDA, SCL, A0, RESET) DGND - 0.3 0.4 V VI = DVDD or DGND -10 10 mA IOH = 100mA, INT pin 0.8 DVDD DVDD V IOH = 100A, PWRCON pin 0.8 AVDD AVDD V DGND 0.4 Input current II VOH (PWRCON, INT) VOL (PWRCON, INT, SDA) IOL = 100mA Low-level output current IOL SDA pin, VOL = 0.6V Load capacitance CB SDA pin V V 3 mA 400 pF 1.65 5.5 V 2.2 5.5 V 8 mA Data format Straight binary POWER-SUPPLY REQUIREMENTS Power-supply voltage: DVDD (3) AVDD IAVDD (4) tCYCLE = 2.5ms, AVDD = 2.2V 5 IPWRD, power-down current <1 mA TEMPERATURE RANGE Specified performance (1) (2) (3) (4) -40 +85 C CH0 to CH3 input pin capacitance. Rate at which channels can be scanned. This is the minimum acquisition time (6s) and conversion time (4s). DVDD cannot exceed AVDD. See Figure 3 and Figure 4 for more information. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 3 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com PIN CONFIGURATION DVDD AVDD ADCIN MUXOUT 15 14 13 8 4 AGND SDA (1) 7 3 Pad PWRCON SCLK Thermal 6 2 DGND INT 5 1 A0 RESET 16 RTE PACKAGE QFN-16 (TOP VIEW) 12 CH0 11 CH1 10 CH2 9 CH3 (1) Connect to AGND. TERMINAL FUNCTIONS 4 PIN NUMBER NAME 1 RESET Digital input 2 INT Digital output 3 SCLK Digital input Serial clock input 4 SDA Digital input/output Serial data 5 A0 Digital input I2C address selection 6 DGND Digital 7 PWRCON Digital output 8 AGND Analog Analog ground 9 CH3 Analog input Input channel 3 10 CH2 Analog input Input channel 2 11 CH1 Analog input Input channel 1 12 CH0 Analog input Input channel 0 13 MUXOUT Analog output 14 ADCIN Analog input 15 AVDD Analog Analog supply 16 DVDD Digital Digital supply FUNCTION DESCRIPTION External reset, active low Interrupt pin, active low; generated when input voltage is beyond programmed threshold Digital ground Power control pin to control shutdown/power-up of external op amp Multiplexer output ADC input Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 TIMING DIAGRAM tVDDAT tHIGH tVDACK tR tHDSTA tF tLOW SCL tSUDAT tHDSTA 9th Clock tSUSTO tSUSTA tSP tHDDAT SDA tBUF P S Sr P NOTE: S = Start, Sr = Repeated Start, and P = Stop. Figure 1. I2C Timing Diagram Table 1. I2C Timing Definitions ADS7924 PARAMETER MIN MAX UNIT 0.4 MHz SCL operating frequency fSCL 0 Bus free time between START and STOP condition tBUF 1.3 ms tHDSTA 600 ns Repeated START condition setup time tSUSTA 600 ns Stop condition setup time tSUSTO 600 ns Data hold time tHDDAT 0 ns Data setup time tSUDAT 100 ns SCL clock low period tLOW 1300 ns SCL clock high period tHIGH 600 Hold time after repeated START condition. After this period, the first clock is generated. Clock/data fall time Clock/data rise time ns tF 300 ns tR 300 ns Data valid time tVDDAT 0.9 ms Data valid acknowledge time tVDACK 0.9 ms 50 ns Pulse width of spike that must be suppressed by the input filter tSP 0 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 5 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS At TA = +25C, unless otherwise noted. CURRENT vs TEMPERATURE AVERAGE POWER DISSIPATION vs CYCLE TIME 1000 12 Auto-Single Mode tCYCLE = 2.5ms AVDD = DVDD = 5.0V 10 Fast I C Interface Mode AVDD = 2.2V tPU = 0V tACQ = 6ms 2 Power (mW) Current (mA) 14 8 6 Analog Current Auto-Scan Modes (4-Channel Measurements) 10 4 2 100 Auto-Single Modes (1-Channel Measurements) Digital Current 0 -40.0 -25.5 -11.0 3.5 18.0 32.5 47.0 61.5 76.0 1 0.01 90.5 105.0 1 0.1 Temperature (C) Figure 2. 1000 100 Figure 3. AVERAGE POWER DISSIPATION vs CYCLE TIME ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE 10 10000 AVDD = 5V tPU = 0V tACQ = 6ms 9 Analog Supply Current (mA) 1000 Power (mW) 10 tCYCLE (ms) Auto-Scan Modes (4-Channel Measurements) 100 Auto-Single Modes (1-Channel Measurements) 10 Auto-Single Mode tCYCLE = 2.5ms 8 7 6 5 4 3 2 1 1 0.01 0 1 0.1 10 100 2.0 1000 2.5 3.5 3.0 Figure 4. -2 -2 -3 -3 Gain Error (LSB) Gain Error (LSB) 5.5 6.0 AVDD = 2.2V -1 -4 -5 -6 -7 Mean + s Mean Mean - s -8 -9 -4 -5 -6 -7 -8 -9 -10 -10 2 3 4 5 6 -40.0 -25.5 -11.0 AVDD Supply Voltage (V) 3.5 18.0 32.5 47.0 61.5 76.0 90.5 105.0 Temperature (C) Figure 6. 6 5.0 GAIN ERROR DRIFT 0 30 Units Across Two Lots -1 4.5 Figure 5. TYPICAL GAIN ERROR vs AVDD VOLTAGE 0 4.0 AVDD Supply Voltage (V) tCYCLE (ms) Figure 7. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 TYPICAL CHARACTERISTICS (continued) At TA = +25C, unless otherwise noted. OFFSET ERROR DRIFT, TYPICAL TYPICAL OFFSET ERROR vs AVDD VOLTAGE 5.0 3 AVDD = 2.2V 2 4.0 Offset Error (LSB) Offset Error (LSB) 30 Units Across Two Lots 4.5 1 0 -1 Mean + s Mean Mean - s 3.5 3.0 2.5 2.0 1.5 1.0 -2 0.5 -3 0 18 -11 -40 47 76 105 2 AVDD Voltage (V) Figure 8. Figure 9. INTERNAL OSCILLATOR FREQUENCY vs VOLTAGE INTEGRAL NONLINEARITY 1.5 2.0 AVDD = 2.2V 1.5 1.3 Linearity Error (LSB) Frequency (% of Nominal) 1.4 1.2 1.1 1.0 0.9 0.8 0.7 1.0 0.5 0 -0.5 -1.0 -1.5 0.6 0.5 -2.0 2 5 4 3 6 0 512 1024 1536 AVDD Voltage (V) 2048 2560 3072 3584 4096 Code Figure 10. Figure 11. INTEGRAL NONLINEARITY INTEGRAL LINEARITY ERROR DRIFT 2.0 2.0 AVDD = 2.2V AVDD = 5.0V 1.5 1.5 1.0 1.0 0.5 0.5 INL (LSB) Linearity Error (LSB) 6 5 4 3 Temperature ( C) 0 -0.5 Maximum INL 0 -0.5 -1.0 -1.0 -1.5 -1.5 -2.0 -2.0 Minimum INL INL shown is worst result over transfer function. 0 512 1024 1536 2048 2560 3072 3584 4096 -40.0 -25.5 -11.0 3.5 18.0 32.5 47.0 61.5 76.0 90.5 105.0 Temperature (C) Code Figure 12. Figure 13. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 7 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25C, unless otherwise noted. DIFFERENTIAL NONLINEARITY DIFFERENTIAL NONLINEARITY 1.5 1.5 AVDD = 5V AVDD = 2.2V 1.0 Linearity Error (LSB) Linearity Error (LSB) 1.0 0.5 0 -0.5 -1.0 0.5 0 -0.5 -1.0 -1.5 -1.5 0 512 1024 1536 2048 3072 2560 4096 3584 0 512 1024 1536 Code 1.5 2048 2560 3072 3584 4096 Code Figure 14. Figure 15. DIFFERENTIAL NONLINEARITY vs TEMPERATURE NOISE HISTOGRAM (1) 9000 AVDD = 2.2V DC Input AVDD = 2.2V 8000 1.0 6000 Maximum DNL Count 0 Minimum DNL -0.5 5000 4000 3000 2000 -1.0 1000 DNL shown is worst result over transfer function. -1.5 2053 2052 Temperature (C) 2051 90.5 105.0 2050 76.0 2049 61.5 2048 47.0 2046 32.5 2045 18.0 2047 0 3.5 2043 -40.0 -25.5 -11.0 2044 DNL (LSB) 7000 0.5 Code Figure 16. Figure 17. NOISE HISTOGRAM(1) 9000 DC Input AVDD = 5V 8000 7000 Count 6000 5000 4000 3000 2000 1000 2053 2052 2051 2050 2049 2048 2047 2046 2045 2044 2043 0 Code Figure 18. (1) 8 At code center. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 OVERVIEW The ADS7924 is a miniature, four-channel, multiplexed, 12-bit, analog-to-digital converter (ADC) with an I2C serial interface. Figure 19 shows a block diagram. The four-channel input multiplexer is routed through external pins to allow a common signal conditioning block to be used for all four channels. The PWRCON digital output can be used to shut down active circuitry used in the signal conditioning; see the Application Information section for additional details. The successive-approximation-register (SAR) ADC performs a no-latency conversion on the selected input channel and stores the data in a dedicated register. A digital threshold comparator with programmable upper and lower limits can be enabled and used to create an alarm monitor. A dedicated interrupt output pin (INT) indicates when an alarm occurs. Two I2C addresses are available and are selected with the dedicated digital input pin A0. Both standard and fast mode formats for I2C are supported. MUX OUT ADCIN AVDD DVDD Registers RESET CH0 Upper Limit Control and Sequencer CH1 Upper Limit CH2 Upper Limit IC Interface CH3 Upper Limit CH0 CH1 CH2 SAR ADC SCL CH1 Data CH2 Data CH3 Data CH3 SDA A0 CH0 Data Input Multiplexer PWRCON 2 CH0 Lower Limit INT Comparator and Alarm Detect CH1 Lower Limit CH2 Lower Limit CH3 Lower Limit Clock Oscillator AGND AGND Figure 19. ADS7924 Block Diagram Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 9 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com MULTIPLEXER The ADS7924 has a four-channel, single-ended input multiplexer. As Figure 20 shows, ESD diodes protect the inputs. Make sure these diodes do not turn on by staying within the absolute input voltage range specification. The MUXOUT pin can be connected to AGND within the multiplexer; for example, to provide a test signal of 0V or as part of a calibration procedure. See the PWRCONFIG: Power Configuration register in the Register Map section for more details MUXOUT AVDD capacitor is connected to the ADCIN pin. While converting during the tCONV interval, the sampling capacitor is disconnected from the ADCIN pin, and the conversion process determines the voltage that was sampled. REFERENCE The analog supply voltage (AVDD) is used as the reference. Power to the ADS7924 should be clean and well bypassed. A 0.1mF ceramic capacitor should be placed as close as possible to the ADS7924 package. In addition, a 1mF to 10mF capacitor and a 5 to 10 series resistor may be used to low-pass filter a noisy supply. CLOCK CH0 The ADS7924 uses an internal clock. The clock speed determines the various timing settings such as conversion time, acquisition time, etc. AVDD AGND CH1 DATA FORMAT AVDD The ADS7924 provides 12 bits of data in unipolar format. The positive full-scale input produces an output code of FFFh and a zero input produces an output code of 0h. The output clips at these codes for signals that either exceed full-scale or go below '0'. Figure 21 shows code transitions versus input voltage. AGND CH2 AVDD AGND CH3 (1) AGND FFF AGND ADC INPUT 1/4 800 7FE 1/4 Figure 20. ADS7924 Multiplexer Output Code (Hex) FFE (1) See the PWRCONFIG: Power Configuration register in the Register Map section. 1LSB = AVDD/2 001 The ADCIN pin provides a single-ended input to the 12-bit successive approximation register (SAR) ADC. This pin is protected with ESD diodes in the same way as the multiplexer inputs. While acquiring the signal during the tACQ interval, the ADC sampling 12 000 0 0.5LSB 1/4 AVDD - 1.5LSB AVDD Input Voltage (VACDIN) (1) Excludes the effects of noise, INL, offset, and gain errors. Figure 21. ADS7924 Code Transition Diagram(1) 10 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 ADC CONVERSION TIMING Sleep Time The ADS7924 provides a flexible timing arrangement to support a wide variety of measurement needs. Three user-controlled timings include power up (tPU), acquisition (tACQ), and sleep (tSLEEP) plus a fixed conversion time (tCONV). The sleep time is allowed to elapse after conversions in the Auto-Single with Sleep, Auto-Scan with Sleep, and Auto-Burst Scan with Sleep modes. The nominal time programmed by the SLPTIME registers can be increased by a factor of eight using the SLPMULT8 bit or decreased by a factor of four using the SLPDIV4 bit. Power-Up Time The power-up time is allowed to elapse whenever the device has been shutdown in idle mode. Power-up time can allow external circuits, such as an op amp, between the MUXOUT and ADCIN pins to turn on. The nominal time programmed by the PUTIME[4:0] register bits is given by Equation 1: tPU = PWRUPTIME[4:0] x 2ms (1) For example, if PWRUPTIME is set to 25 ('011001') then 50ms is allowed to elapse before beginning the acquisition time. If a power-up time is not required, set the bits to '0' to effectively bypass. Acquisition Time The acquisition time is allowed to elapse before beginning a conversion. During this time, the ADC acquires the signal. The minimum acquisition time is 6s. The nominal time programmed by the ACQTIME[4:0] register bits is given by Equation 2: tACQ = (ACQTIME[4:0] x 2ms) + 6ms (2) For example, if ACQTIME is set to 30 ('011110') then 66ms is allowed to acquire the input signal. If an acquisition time greater than 6ms is not required, set the bits to '0'. Conversion Time The conversion time is always 4ms and cannot be programmed by the user. INTERRUPT OUTPUT (INT) The ADS7924 offers a dedicated output pin (INT) for signaling an interrupt condition. The INT pin can be configured to activate when the ADC is busy with a conversion, when data are ready for retrieval, or when an alarm condition occurs; see the Interrupt Configuration register in the Register Map section. To clear an interrupt from an alarm condition, read the INTCONFIG register (12h). To clear an interrupt from data ready, read the data registers. The interrupt clears when the lower four bits are retrieved. The INT pin can be configured to generate a static output (useful for a host controller monitoring for a level) or a pulse output (useful for a host controller monitoring for a edge transition). When a pulse output is selected, the nominal pulse width is 250ns. The Interrupt Control Register should be read to clear the interrupt. PWRCON The PWRCON pin allows the user to synchronize the shutdown/wakeup of an external op amp with the ADC conversion cycle. This feature provides further power reduction and can be useful in applications where the time difference between consecutive signal captures is large. The PWRCON pin can drive up to 3mA of current and its output voltage is the same as AVDD. This pin is controlled by the PWRCONFIG register. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 11 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com ALARM When an alarm occurs, the INT pin can be configured to generate an interrupt. The channel that generated the alarm can be read from the registers. A read of the Interrupt Control register clears the alarm register and also resets the alarm counter. The ADS7924 offers an independent alarm function for each input channel. An 8-bit window comparator can be enabled to test the ADC conversion result against an upper limit set by the ULR register and against a lower limit set by the LLR register. If the conversion result is less than or equal to the LLR threshold value or greater than or equal to the ULR threshold value, the comparator is tripped. There are separate upper and lower registers for each input channel. ADC OPERATING MODES The ADS7924 offers multiple operating modes to support a wide variety of monitoring needs. Conversions can either be started manually or set to automatically continue. The mode is set by writing to the MODE register, and changes take effect as soon as the write completes. Table 2 gives a brief description of each mode. A programmable counter determines how many comparator trips it takes to generate an alarm. A separate counter is used for each channel and is incremented whenever the comparator trips, either for the upper or lower thresholds. That is, an ADC conversion result on channel 1 that exceeds the ULR threshold or falls below the LLR threshold increments the counter for that channel. Figure 22 shows a conceptual diagram of the window comparator and alarm circuitry. Idle Mode Use this mode to save power when not converting. All circuits are shut down. Awake Mode All circuits are operating in this mode and the ADC is ready to convert. When switching between modes, be sure to first select the Awake mode and then switch to the desired mode. This procedure ensures the internal control logic is properly synchronized. Upper Limit Threshold ULRx[7:0] ADC ALMCNT[2:0] (2) CHX Data Window Comparator Counter X (2) X (1) Alarm for Channel X LLRx[7:0] Lower Limit Threshold (1) The same ALMCNT value is used for all four window comparators. (2) X = 0 to 3. Figure 22. Window Comparator/Alarm Conceptual Block Diagram Table 2. Mode Descriptions MODE Idle DESCRIPTION All circuits shutdown; lowest power setting Awake All circuits awake and ready to convert Manual-Single Select input channel is converted once Manual-Scan All input channels are converted once Auto-Single One input channel is continuously converted Auto-Scan All input channels are continuously converted Auto-Single with Sleep One input channel is continuously converted with programmable sleep time between conversions Auto-Scan with Sleep All input channels are continuously converted with programmable sleep time between conversions Auto-Burst Scan with Sleep All input channels are converted with minimal delay followed by a programmable sleep time 12 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 Manual-Single Mode After the conversion completes, the device waits for a new mode to be set. This mode can be set to Idle to save power. When tPU and tACQ are very short, the very short conversion time needed allows a read register operation to be issued on the I2C bus immediately after the write operation that initiates this mode. It is important to note that tPU only applies to the first manual-single command. This mode converts the selected channel once, as shown in Figure 23. After the ADC Mode Control register is written, the power-up time (tPU) and acquisition time (tACQ) are allowed to elapse. tPU can be set to '0' to effectively bypass if not needed. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. Sleep time (tSLEEP) is not used in this mode. Status Input Multiplexer Busy Data Ready PWRCON If multiple conversions are needed, the manual-single mode can be reissued without requiring the awake mode to be issued in between. Consecutive manual-single commands have no tPU period. Awake Acquire Selected Channel Convert Selected Channel tPU tACQ tCONV Awaiting Mode Selection Selected Channel (1) (1) (2) (3) (1) Busy and data ready are internal signals shown as active high that can be routed to the INT pin for external monitoring. (2) PWRCON is shown enabled and active high. (3) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register. Figure 23. Manual-Single Operation Example Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 13 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com Manual-Scan Mode This mode converts all of the channels once, starting with the selected channel, as illustrated in Figure 24. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse. This value can be set to '0' to effectively bypass if not needed. Before each conversion, an acquisition time (tACQ) is allowed to elapse. tACK time is programmable through the ACQCONFIG register, bits[4:0]. Sleep time (tSLEEP) is not used in this mode. The input multiplexer is automatically incremented as the conversions complete. If, for example, the initial selected channel is CH2, the conversion order is CH2, CH3, CH0, and CH1. Data from the conversions are always put into the data register that corresponds to a particular channel. For example, Status Input Multiplexer Busy Data Ready PWRCON CH2 data always goes in register DATA2_H and DATA2_L regardless of conversion order. After all four conversions complete, the device waits for a new mode to be set. This mode can be set to Idle afterwards to save power. The INT pin can be configured to indicate the completion of each individual conversion or it can wait until all four finish. In either case, the appropriate data register is updated after each conversion. These registers can be read at any time afterwards. If multiple scan are needed, the manual-scan mode can be reissued without requiring the Awake mode to be issued in between. Awake Acquire First Channel Convert First Channel Acquire Second Channel Convert Second Channel Acquire Third Channel Convert Third Channel Acquire Fourth Channel Convert Fourth Channel tPU tACQ tCONV tACQ tCONV tACQ tCONV tACQ tCONV Selected Channel Next Channel Next Channel Awaiting Mode Selection Next Channel (1) (2) (3) (4) (1) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring. (2) Data ready is an internal signal shown as active high and is enabled when all conversions are complete. It can be routed to the INT pin for external monitoring. (3) PWRCON is shown enabled and active high. (4) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register. Figure 24. Manual-Scan Operation Example 14 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 Auto-Single Mode This mode automatically converts the selected channel continuously, as shown in Figure 25. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse. This value can be set to '0' to effectively bypass if not needed. Before the conversion, an acquisition time (tACQ) is allowed to elapse. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. Sleep time (tSLEEP) is not used in this mode. After the conversion completes the cycle is repeated. Status This mode can be used with the onboard digital comparator to monitor the status of an input signal with little support needed from a host microcontroller. Note that the conversion time is less than the I2C data retrieval time. It is suggested to stop this mode by setting the mode to Idle or stopping the conversion by configuring the alarm to do so, before retrieving data. The alarm can also be configured to continue the conversion even after an interrupt is generated. Awake Acquire Selected Channel Convert Selected Channel Acquire Selected Channel Convert Selected Channel Acquire Selected Channel Convert Selected Channel tPU tACQ tCONV tACQ tCONV tACQ tCONV Input Multiplexer Selected Channel (1) (2) Busy PWRCON (3) (4) (1) Same channel is continuously converted. (2) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring. (3) PWRCON is shown enabled and active high. (4) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register. Figure 25. Example of Auto-Single Operation Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 15 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com Auto-Scan Mode This mode automatically converts all the channels continuously, starting with the selected channel, as illustrated in Figure 26. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse. This value can be set to '0' to effectively bypass if not needed. Before the conversion, an acquisition time (tACQ) is allowed to elapse. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. Sleep time (tSLEEP) is not used in this mode. The input multiplexer is automatically incremented as the conversions complete. If, for example, the initial selected channel is CH2, the conversion order is CH2, CH3, CH0, CH1, CH2, CH3, etc. until the mode Status Input Multiplexer Busy PWRCON is stopped. Data from the conversions are always put into the data register that corresponds to a particular channel. For example, CH2 data always go in register DATA2_H and DATA2_L regardless of conversion order. This mode can be used with the onboard digital comparator to monitor the status of the input signals with little support needed from a host microcontroller. It is suggested to interrupt this mode and stop the automatic conversions, either by setting the mode to Idle or configuring the alarm to do so, before retrieving data. Awake Acquire First Channel Convert First Channel Acquire Second Channel Convert Second Channel Acquire Third Channel Convert Third Channel Acquire Fourth Channel Convert Fourth Channel Acquire First Channel Convert First Channel tPU tACQ tCONV tACQ tCONV tACQ tCONV tACQ tCONV tACQ tCONV Selected Channel (First) Next Channel Next Channel Next Channel First Channel (1) (2) (3) (1) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring. (2) PWRCON is shown enabled and active high. (3) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register. Figure 26. Auto-Scan Operation Example 16 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 Auto-Single with Sleep Mode This mode automatically converts the selected channel repeatedly with a sleep interval between conversions, as shown in Figure 27. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse. This value can be set to '0' to effectively bypass if not needed. Before the conversion, an acquisition time (tACQ) is allowed to elapse. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. After the conversion, sleep time (tSLEEP) is allowed to elapse and then the cycle repeats. The length of the sleep time is controlled by register bits. During the sleep mode, power dissipation is minimal and the PWRCON output is always disabled. This mode can be used with the onboard digital comparator to periodically monitor the status of an input signal while saving power between conversions. Little support is needed from a host microcontroller. It is suggested to stop this mode by setting the mode to Idle or stopping the conversion by configuring the alarm to do so, before retrieving data. The length in time of the cycle (tCYCLE) sets the average power dissipation, as shown in Figure 3 or Figure 4. tCYCLE Status Awake tPU Acquire Selected Channel Convert Selected Channel Sleep tACQ tCONV tSLEEP Input Multiplexer Busy PWRCON Awake tPU Acquire Selected Channel Convert Selected Channel Sleep tACQ tCONV tSLEEP Selected Channel Awake tPU Acquire Selected Channel Convert Selected Channel tACQ tCONV (1) (2) (3) (4) (1) Same channel is continuously converted. (2) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring. (3) PWRCON is shown enabled and active high. (4) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register. Figure 27. Auto-Single with Sleep Operation Example Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 17 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com Auto-Scan with Sleep Mode This mode automatically converts all the channels repeatedly with a sleep interval between conversions, as illustrated in Figure 28. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse. This value can be set to '0' to effectively bypass if not needed. Before the first conversion of the selected input, an acquisition time (tACQ) is allowed to elapse. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. After the conversion, a sleep time (tSLEEP) is allowed to elapse and then the cycle repeats. The length of the sleep time is controlled by register bits. During the sleep mode, power dissipation is minimal and the PWRCON output is always disabled. The input multiplexer is automatically incremented as the conversions complete. If, for example, the initial selected channel is CH2, the conversion order is CH2, CH3, CH0, CH1, CH2, CH3, etc. until the mode is stopped. Data from the conversions are always put into the data register that corresponds to a particular channel. For example, CH2 data always goes in register DATA2_H and DATA2_L regardless of conversion order. This mode can be used with the onboard digital comparator to periodically monitor the status of the input signals while saving power between conversions. Little support is needed from a host microcontroller. It is suggested to stop this mode by setting the mode to Idle or stopping the conversion by configuring the alarm to do so, before retrieving data. The length in time of the cycle (tCYCLE) sets the average power dissipation, as shown in Figure 3 or Figure 4. tCYCLE Status Awake tPU Input Multiplexer Acquire First Channel Convert First Channel Sleep tACQ tCONV tSLEEP Awake Selected Channel tPU Acquire Second Channel Convert Second Channel Sleep tACQ tCONV tSLEEP Awake tPU Next Channel Acquire Third Channel Convert Third Channel Sleep tACQ tCONV tSLEEP Next Channel Awake tPU Acquire Fourth Channel Convert Fourth Channel tACQ tCONV Next Channel (1) Busy PWRCON (2) (3) (1) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring. (2) PWRCON is shown enabled and active high. (3) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register. Figure 28. Auto-Scan with Sleep Operation Example 18 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 Auto-Burst Scan with Sleep Mode This mode automatically converts all the channels without delay followed by a sleep interval before the cycle repeats, as shown in Figure 29. After the ADC Mode Control register is written, the power-up time (tPU) is allowed to elapse. This value can be set to '0' to effectively bypass if not needed. Before the first conversion of the selected input, an acquisition time (tACQ) is allowed to elapse. tACQ time is programmable through the ACQCONFIG register, bits[4:0]. Afterwards, all four inputs are measured without delay. The input multiplexer is automatically incremented as the conversions complete. If, for example, the initial selected channel is CH2, the conversion order is CH2, CH3, CH0, and CH1. After the four conversions, a sleep time (tSLEEP) is allowed to elapse and then the cycle repeats. The length of the sleep time is controlled by register bits. During the sleep mode, power dissipation is minimal and the PWRCON output is always disabled. Data from the conversions are always put into the data register that corresponds to a particular channel. For example, CH2 data always goes in register DATA2_H and DATA2_L regardless of conversion order. This mode can be used with the onboard digital comparator to periodically monitor the status of the input signals while saving power between conversions. Little support is needed from a host microcontroller. It is suggested to interrupt this mode and stop the automatic conversions, either by setting the mode to Idle or configuring the alarm to do so, before retrieving data. The length in time of the cycle (tCYCLE) sets the average power, as shown in Figure 3 or Figure 4. tCYCLE Awake Status tPU Input Multiplexer Busy PWRCON Aquire and Aquire and Convert Third Convert Fourth Channel Channel Aquire and Convert First Channel Aquire and Convert Second Channel tACQ + tCONV tACQ + tCONV tACQ + tCONV Next Channel Next Channel Selected Channel (First) tACQ + tCONV Sleep Awake tSLEEP tPU Next Channel Aquire and Convert First Channel Aquire and Convert Second Channel tACQ + tCONV tACQ + tCONV First Channel Next Channel (1) (2) (3) (1) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring. (2) PWRCON is shown enabled and active high. (3) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register. Figure 29. Auto-Burst Scan with Sleep Operation Example Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 19 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com REGISTER MAP The ADS7924 operation is controlled through a set of registers. Collectively, the registers contain all the information needed to configure the part. Table 3 shows the register map. Table 3. Register Map ADDRESS REGISTER RESET VALUE BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 00h MODECNTRL 00h MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 SEL/ID1 SEL/ID0 01h INTCNTRL X0h ALRM_ST3 ALRM_ST2 ALRM_ST1 ALRM_ST0 AEN/ST3 AEN/ST2 AEN/ST1 AEN/ST0 02h DATA0_U XXh DATA0[11] DATA0[10] DATA0[9] DATA0[8] DATA0[7] DATA0[6] DATA0[5] DATA0[4] 03h DATA0_L XXh DATA0[3] DATA0[2] DATA0[1] DATA0[0] 0 0 0 0 04h DATA1_U XXh DATA1[11] DATA1[10] DATA1[9] DATA1[8] DATA1[7] DATA1[6] DATA1[5] DATA1[4] 05h DATA1_L XXh DATA1[3] DATA1[2] DATA1[1] DATA1[0] 0 0 0 0 06h DATA2_U XXh DATA2[11] DATA2[10] DATA2[9] DATA2[8] DATA2[7] DATA2[6] DATA2[5] DATA2[4] 07h DATA2_L XXh DATA2[3] DATA2[2] DATA2[1] DATA2[0] 0 0 0 0 08h DATA3_U XXh DATA3[11] DATA3[10] DATA3[9] DATA3[8] DATA3[7] DATA3[6] DATA3[5] DATA3[4] 09h DATA3_L XXh DATA3[3] DATA3[2] DATA3[1] DATA3[0] 0 0 0 0 0Ah ULR0 XXh ULR0[7] ULR0[6] ULR0[5] ULR0[4] ULR0[3] ULR0[2] ULR0[1] ULR0[0] 0Bh LLR0 XXh LLR0[7] LLR0[6] LLR0[5] LLR0[4] LLR0[3] LLR0[2] LLR0[1] LLR0[0] 0Ch ULR1 XXh ULR1[7] ULR1[6] ULR1[5] ULR1[4] ULR1[3] ULR1[2] ULR1[1] ULR1[0] 0Dh LLR1 XXh LLR1[7] LLR1[6] LLR1[5] LLR1[4] LLR1[3] LLR1[2] LLR1[1] LLR1[0] 0Eh ULR2 XXh ULR2[7] ULR2[6] ULR2[5] ULR2[4] ULR2[3] ULR2[2] ULR2[1] ULR2[0] 0Fh LLR2 XXh LLR2[7] LLR2[6] LLR2[5] LLR2[4] LLR2[3] LLR2[2] LLR2[1] LLR2[0] 10h ULR3 XXh ULR3[7] ULR3[6] ULR3[5] ULR3[4] ULR3[3] ULR3[2] ULR3[1] ULR3[0] 11h LLR3 XXh LLR3[7] LLR3[6] LLR3[5] LLR3[4] LLR3[3] LLR3[2] LLR3[1] LLR3[0] 12h INTCONFIG E0h AIMCNT2 AIMCNT1 AIMCNT0 INTCNFG1 INTCNFG0 BUSY/INT INTPOL INTTRIG 13h SLPCONFIG 00h 0 CONVCTRL SLPDIV4 SLPMULT8 0 SLPTIME2 SLPTIME1 SLPTIME0 14h ACQCONFIG 00h 0 0 0 ACQTIME4 ACQTIME3 ACQTIME2 ACQTIME1 ACQTIME0 15h PWRCONFIG 00h CALCNTL PWRCONPOL PWRCONEN PWRUPTIME4 PWRUPTIME3 PWRUPTIME2 PWRUPTIME1 PWRUPTIME0 RESET 18h (A0 = 0) 19h (A0 = 1) RST/ID7 RST/ID6 RST/ID5 RST/ID4 RST/ID3 RST/ID2 RST/ID1 RST/ID0 16h 20 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 MODECNTRL: ADC Mode Control Register (Address = 00h) 7 6 5 4 3 2 1 0 MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 SEL/ID1 SEL/ID0 Bits[7:2] MODE[5:0]: Mode control 000000 100000 110000 110010 110001 110011 111001 111011 111111 Bits[1:0] = Idle mode (default) = Awake mode = Manual-Single mode = Manual-Scan mode = Auto-Single mode = Auto-Scan mode = Auto-Single with Sleep mode = Auto-Scan with Sleep mode = Auto-Burst Scan with Sleep mode SEL/ID[1:0]: Channel selection When read, these bits indicate the last channel converted. When writing to these bits, select which input appears on MUXOUT: 00 = Channel 0 is selected 01 = Channel 1 is selected 10 = Channel 2 is selected 11 = Channel 3 is selected (unless the CALCNTRL bit is set to '1') INTCNTRL: Interrupt Control Register (Address = 01h) 7 6 5 4 3 2 1 0 ALRM_ST3 ALRM_ST2 ALRM_ST1 ALRM_ST0 AEN/ST3 AEN/ST2 AEN/ST1 AEN/ST0 Bits[7:4] ALRM_ST[3:0]: Alarm status (read-only) Reading these bits indicates the alarm status for the channels. These bits are never masked--they always report the alarm status even when the alarm is not enabled by the corresponding AEN/ST bits. Bit 7 = Channel 3 alarm status, '1' indicates an alarm condition Bit 6 = Channel 2 alarm status, '1' indicates an alarm condition Bit 5 = Channel 1 alarm status, '1' indicates an alarm condition Bit 4 = Channel 0 alarm status, '1' indicates an alarm condition Bits[3:0] AEN/ST[3:0]: Alarm enable Writing to these bits enables the alarm for the corresponding channel. Reading these bits returns the status of the alarm for the corresponding channel when enabled. Reading returns a '0' when the alarm in not enabled. Bit 3 = Channel 3 alarm enable, 1 = enabled (default = 0) Bit 2 = Channel 2 alarm enable, 1 = enabled (default = 0) Bit 1 = Channel 1 alarm enable, 1 = enabled (default = 0) Bit 0 = Channel 0 alarm enable, 1 = enabled (default = 0) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 21 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 There are individual registers: the upper significant bits. The order of conversion. CH0. www.ti.com registers for each input channel to buffer the conversion data. The 12 bits are stored in two register stores the eight most significant bits; the lower register stores the lower four least data registers are always updated with the corresponding input channel regardless of the For example, DATA0_U and DATA0_L always contain the results of the latest conversion of DATA0_U: Conversion Data for Channel 0, Upper Bits Register (Address = 02h) 7 6 5 4 3 2 1 0 DATA0[11] (MSB) DATA0[10] DATA0[9] DATA0[8] DATA0[7] DATA0[6] DATA0[5] DATA0[4] DATA0_L: Conversion Data for Channel 0, Lower Bits Register (Address = 03h) 7 DATA0[3] 6 DATA0[2] 5 4 3 2 1 0 DATA0[1] DATA0[0] (LSB) 0 0 0 0 DATA1_U: Conversion Data for Channel 1, Upper Bits Register (Address = 04h) 7 6 5 4 3 2 1 0 DATA1[11] (MSB) DATA1[10] DATA1[9] DATA1[8] DATA1[7] DATA1[6] DATA1[5] DATA1[4] DATA1_L: Conversion Data for Channel 1, Lower Bits Register (Address = 05h) 7 DATA1[3] 6 DATA1[2] 5 4 3 2 1 0 DATA1[1] DATA1[0] (LSB) 0 0 0 0 DATA2_U: Conversion Data for Channel 2, Upper Bits Register (Address = 06h) 7 6 5 4 3 2 1 0 DATA2[11] (MSB) DATA2[10] DATA2[9] DATA2[8] DATA2[7] DATA2[6] DATA2[5] DATA2[4] DATA2_L: Conversion Data for Channel 2, Lower Bits Register (Address = 07h) 7 DATA2[3] 6 DATA2[2] 5 4 3 2 1 0 DATA2[1] DATA2[0] (LSB) 0 0 0 0 DATA3_U: Conversion Data for Channel 3, Upper Bits Register (Address = 08h) 7 6 5 4 3 2 1 0 DATA3[11] (MSB) DATA3[10] DATA3[9] DATA3[8] DATA3[7] DATA3[6] DATA3[5] DATA3[4] DATA3_L: Conversion Data for Channel 3, Lower Bits Register (Address = 09h) 7 DATA3[3] 22 6 DATA3[2] 5 4 3 2 1 0 DATA3[1] DATA3[0] (LSB) 0 0 0 0 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 There are individual upper and lower threshold registers for input channel. Each register is eight bits with the least significant bit weight equal to AVDD/256. The comparator is tripped when the input signal exceeds the value of the upper limit register or falls below the lower limit register. ULR0: Upper Limit Threshold for Channel 0 Comparator Register (Address = 0Ah) 7 6 5 4 3 2 1 0 ULR0[7] (MSB) ULR0[6] ULR0[5] ULR0[4] ULR0[3] ULR0[2] ULR0[1] ULR0[0] (LSB) LLR0: Lower Limit Threshold for Channel 0 Comparator Register (Address = 0Bh) 7 6 5 4 3 2 1 0 LLR0[7] (MSB) LLR0[6] LLR0[5] LLR0[4] LLR0[3] LLR0[2] LLR0[1] LLR0[0] (LSB) ULR1: Upper Limit Threshold for Channel 1 Comparator Register (Address = 0Ch) 7 6 5 4 3 2 1 0 ULR1[7] (MSB) ULR1[6] ULR1[5] ULR1[4] ULR1[3] ULR1[2] ULR1[1] ULR1[0] (LSB) LLR1: Lower Limit Threshold for Channel 1 Comparator Register (Address = 0Dh) 7 6 5 4 3 2 1 0 LLR1[7] (MSB) LLR1[6] LLR1[5] LLR1[4] LLR1[3] LLR1[2] LLR1[1] LLR0[0] (LSB) ULR2: Upper Limit Threshold for Channel 2 Comparator Register (Address = 0Eh) 7 6 5 4 3 2 1 0 ULR2[7] (MSB) ULR2[6] ULR2[5] ULR2[4] ULR2[3] ULR2[2] ULR2[1] ULR2[0] (LSB) LLR2: Lower Limit Threshold for Channel 2 Comparator Register (Address = 0Fh) 7 6 5 4 3 2 1 0 LLR2[7] (MSB) LLR2[6] LLR2[5] LLR2[4] LLR2[3] LLR2[2] LLR2[1] LLR2[0] (LSB) ULR3: Upper Limit Threshold for Channel 3 Comparator Register (Address = 10h) 7 6 5 4 3 2 1 0 ULR3[7] (MSB) ULR3[6] ULR3[5] ULR3[4] ULR3[3] ULR3[2] ULR3[1] ULR3[0] (LSB) LLR3: Lower Limit Threshold for Channel 3 Comparator Register (Address = 11h) 7 6 5 4 3 2 1 0 LLR3[7] (MSB) LLR3[6] LLR3[5] LLR3[4] LLR3[3] LLR3[2] LLR3[1] LLR3[0] (LSB) Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 23 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com INTCONFIG: Interrupt Configuration Register (Address = 12h) 7 6 5 4 3 2 1 0 ALMCNT2 ALMCNT1 ALMCNT0 INTCNFG2 INTCNFG1 INTCNFG0 INTPOL INTTRIG Bits[7:5] ALMCNT[2:0]: Alarm count These bits set the number of times the comparator threshold limit (either upper or lower) must be exceeded to generate an alarm. 000 = Every conversion generates an alarm 010 = Exceeding the threshold limit 1 time generates an alarm condition 100 = Exceeding the threshold limit 2 times generates an alarm condition 110 = Exceeding the threshold limit 3 times generates an alarm condition 111 = Exceeding the threshold limit 4 times generates an alarm condition 101 = Exceeding the threshold limit 5 times generates an alarm condition 110 = Exceeding the threshold limit 6 times generates an alarm condition 111 = Exceeding the threshold limit 7 times generates an alarm condition Bits[4:2] INTCNFG[2:0]: INT output pin configuration These bits determine which signal is output on INT. They also select the conversion control event; see the CONVCTRL bit in the SLPCONFIG register. The configuration of these bits is shown in Table 4. Table 4. INT Pin Configuration BIT SETTING INT PIN CONFIGURATION CONVERSION CONTROL EVENT 000 Alarm Alarm 001 Busy Alarm 010 Data ready: one conversion completed Data ready: one conversion complete 011 Busy Data ready: one conversion complete 100 Do not use -- 101 Do not use -- 110 Data ready: all four conversions complete Data ready: four conversions complete 111 Busy Data ready: four conversions complete Bit 1 INTPOL: INT pin polarity 0 = Active low (default) 1 = Active high Bit 0 INTTRIG: INT output pin signaling 0 = Static signal for use with level triggering (default) 1 = Pulse signal for use with edge triggering 24 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 SLPCONFIG: Sleep Configuration Register (Address = 13h) 7 6 5 4 3 2 1 0 0 CONVCTRL SLPDIV4 SLPMULT8 0 SLPTIME2 SLPTIME1 SLPTIME0 Bit 7 Always write '0' Bit 6 CONVCTRL: Conversion control This bit determines the conversion status after a conversion control event; see the INTCNFG bits in the INTCONFIG register. 0 = Conversions continue, independent of the control event status (default) 1 = Conversions are stopped as soon as a control event occurs; the event must be cleared to resume conversions Bit 5 SLPDIV4: Sleep time 4x divider This bit sets the speed of the sleep clock. 0 = Sleep time divider is '1' (default) 1 = Sleep time divider is '4' Bit 4 SLPMULT8: Sleep time 8x multiplier 0 = Sleep time multiplier is '1' (default) 1 = Sleep time multiplier is '8' Bit 3 Always write '0' Bits[2:0] SLPTIME[2:0]: Sleep time setting 000 = 2.5ms (default) 001 = 5ms 010 = 10ms 011 = 20ms 100 = 40ms 101 = 80ms 110 = 160ms 111 = 320ms Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 25 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com ACQCONFIG: Acquire Configuration Register (Address = 14h) 7 6 5 4 3 2 1 0 0 0 0 ACQTIME4 ACQTIME3 ACQTIME2 ACQTIME1 ACQTIME0 Bits[7:5] Always write '0' Bits[4:0] ACQTIME[4:0]: Signal acquire time These bits set the time to acquire the signal before a conversion (default = 0). tACQ = ACQTIME[4:0] x 2ms + 6s PWRCONFIG: Power-Up Configuration Register (Address = 15h) 7 6 5 4 3 2 1 0 CALCNTL PWRCONPOL PWRCONEN PWRUPTIME4 PWRUPTIME3 PWRUPTIME2 PWRUPTIME1 PWRUPTIME0 Bit 7 CALCNTL: Calibration control 0 = Setting CH3 in the Mode Control register selects the CH3 input to be routed to the MUXOUT pin. (default) 1 = Setting CH3 in the Mode Control register connects the MUXOUT pin to AGND. Bit 6 PWRCONPOL: PWRCON pin polarity 0 = Active low (default) 1 = Active high Bit 5 PWRCONEN: PWRCON enable 0 = The PWRCON pin is disabled (default) 1 = The PWRCON pin is always enabled Bits[4:0] PWRUPTIME[4:0]: Power-up time setting These bits set the power-up time (default = 0). tPWR = PWRUPTIME[4:0] x 2ms. RESET: Software Reset and Device ID Register (Address = 16h) 7 6 5 4 3 2 1 0 RST/ID7 RST/ID6 RST/ID5 RST/ID4 RST/ID3 RST/ID2 RST/ID1 RST/ID0 A read of this register returns the device ID when A0 determines the last bit of the device ID (0001100A0). A write to this register of 10101010 generates a software reset of the ADS7924. 26 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 I2C INTERFACE The ADS7924 communicates through an I2C interface. I2C is a two-wire, open-drain interface that supports multiple devices and masters on a single bus. Devices on the I2C bus only drive the bus lines low by connecting them to ground; they never drive the bus lines high. Instead, the bus wires are pulled high by pull-up resistors, so the bus wires are high when no device is driving them low. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention. Communication on the I2C bus always takes place between two devices, one acting as the master and the other as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I2C devices can act as masters or slaves, but the ADS7924 can only act as a slave device. An I2C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data are transmitted across the I2C bus in groups of eight bits. To send a bit on the I2C bus, the SDA line is driven to the appropriate level while SCL is low (a low on SDA indicates the bit is zero; a high indicates the bit is one). Once the SDA line settles, the SCL line is brought high, then low. This pulse on SCL clocks the SDA bit into the receiver shift register. If the I2C bus is held idle for more than 25ms, the bus times out. The I2C bus is bidirectional: the SDA line is used for both transmitting and receiving data. When the master reads from a slave, the slave drives the data line; when the master sends to a slave, the master drives the data line. The master always drives the clock line. The ADS7924 never drives SCL, because it cannot act as a master. On the ADS7924, SCL is an input only. Most of the time the bus is idle; no communication occurs, and both lines are high. When communication is taking place, the bus is active. Only master devices can start a communication and initiate a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is low. If the data line changes state while the clock line is high, it is either a START condition or a STOP condition. A START condition occurs when the clock line is high and the data line goes from high to low. A STOP condition occurs when the clock line is high and the data line goes from low to high. After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate with. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds. The master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device. Every byte transmitted on the I2C bus, whether it is address or data, is acknowledged with an acknowledge bit. When the master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA low. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when the master has finished reading a byte, it pulls SDA low to acknowledge this to the slave. It then sends a clock pulse to clock the bit. (The master always drives the clock line.) A not-acknowledge is performed by simply leaving SDA high during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is present at that address to pull the line low. When the master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. The master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition. See the Timing Diagrams section for a timing diagram showing the ADS7924 I2C transaction. I2C ADDRESS SELECTION The ADS7924 has one address pin, A0, that sets the I2C address. This pin can be connected to ground or VDD, allowing two addresses to be selected with one pin as shown in Table 5. The state of the address pin A0 is sampled continuously. Table 5. A0 Pin Connection and Corresponding Slave Address A0 PIN SLAVE ADDRESS Ground 1001000 DVDD 1001001 I2C SPEED MODES The ADS7924 supports the I2C standard and fast modes. Standard mode allows a clock frequency of up to 100kHz and fast mode permits a clock frequency of up to 400kHz. SLAVE MODE OPERATIONS The ADS7924 can act as either slave receivers or slave transmitters. As a slave device, the ADS7924 cannot drive the SCL line. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 27 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com Receive Mode: least significant byte is then sent by the slave and is followed by an acknowledgment from the master. The master may terminate transmission after any byte by not acknowledging or issuing a START or STOP condition. In slave receive mode the first byte transmitted from the master to the slave is the address with the R/W bit low. This byte allows the slave to be written to. The next byte transmitted by the master is the register pointer byte. The ADS7924 then acknowledges receipt of the register pointer byte. The next two bytes are written to the address given by the register pointer. The ADS7924 acknowledges each byte sent. Register bytes are sent with the most significant byte first, followed by the least significant byte. WRITING THE REGISTERS To access a write register from the ADS7924, the master must first write the appropriate value to the Pointer address. The Pointer address is written directly after the slave address byte, low R/W bit, and a successful slave acknowledgment. After the Pointer address is written, the slave acknowledges and the master issues a STOP or a repeated START condition. The MSB of the pointer address is the increment (INC) bit. When set to '1', the register address is automatically incremented after every register write which allows convenient writing of multiple registers. Set INC to '0' when writing a single register. Figure 30 and Figure 31 show timing examples. Transmit Mode: In slave transmit mode, the first byte transmitted by the master is the 7-bit slave address followed by the high R/W bit. This byte places the slave into transmit mode and indicates that the ADS7924 is being read from. The next byte transmitted by the slave is the most significant byte of the register that is indicated by the register pointer. This byte is followed by an acknowledgment from the master. The remaining 1 9 1 9 1/4 SCL SDA 1 0 0 1 0 0 A0(1) 0(2) R/W Start By Master 0 0 P4(3) P3 P2 P1 ACK By ADS7924 P0 1/4 ACK By ADS7924 Frame 2 Pointer Address Byte Frame 1 Slave Address Byte 1 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 ACK By ADS7924 Stop By Master Frame 3 Register Data Byte (1) The value of A0 is determined by the A0 pin. (2) When INC is set to '0', the address pointer remains unchanged after a read. (3) Bits P[4:0] point to the register to be written. Figure 30. Writing a Single Register Timing Diagram 28 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 1 9 9 1 SCL 1/4 1 SDA 0 0 1 0 0 A0(1) 1 R/W Start By Master (2) 0 0 P4 (3) P3 P2 P1 1/4 P0 ACK By ADS7924 ACK By ADS7924 Frame 2 Pointer Address Byte Frame 1 Slave Address Byte 1 9 1 9 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 ACK By ADS7924 Frame 3 Register Data Byte 1 D1 D0 ACK By ADS7924 Stop By Master Frame 4 Register Data Byte N (1) The value of A0 is determined by the A0 pin. (2) When INC is set to '1', the address pointer automatically increments for multiple register writes. (3) Bits P[4:0] point to the storing register to be written. Figure 31. Writing Multiple Registers Timing Diagram Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 29 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com READING THE REGISTERS The master may issue a START condition and send the slave address byte with the R/W bit high to begin the read. Note that if the previously selected register is to be read again there is no need to update the pointer address. Figure 32 to Figure 34 show examples of register reads. To read a specific register from the ADS7924, the master must first write the appropriate value to the pointer address. The pointer address is written directly after the slave address byte, low R/W bit, and a successful slave acknowledgment. The MSB of the pointer address is the INC bit. When set to '1', the register address is automatically incremented after every register read which allows convenient reading of multiple registers. Set INC to '0' when reading a single register. 1 9 1 9 1/4 SCL SDA 1 0 0 1 0 0 A0 (1) 0 R/W Start By Master (2) 0 0 P4 (3) P3 P2 P1 P0 ACK By ADS7924 ACK By ADS7924 Stop By Master Frame 2 Pointer Address Byte Frame 1 Slave Address Byte 1 9 1 9 SCL (Continued) SDA (Continued) 1 0 0 0 1 0 A0 (1) R/W Start By Master D7 D6 D5 D4 D3 D2 ACK By ADS7924 D1 D0 ACK By From ADS7924 Master (2) Frame 4 Data Byte Frame 3 Slave Address Byte (1) The value of A0 is determined by the A0 pin. (2) When INC is set to '0', the address pointer remains unchanged after a read. (3) Bits P[4:0] point to the register to be read. Figure 32. Reading a Single Register Timing Diagram 1 9 1 9 SCL SDA 1 0 0 1 0 0 A0 (1) Start By Master R/W D7 D6 D5 D4 D3 D2 D1 ACK By ADS7924 Frame 1 Slave Address Byte D0 ACK By ADS7924 Stop By Master Frame 2 Register Data Byte (1) The value of A0 is determined by the A0 pin. Figure 33. Reading a Previously Addressed Register Timing Diagram 30 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 1 9 1 9 1/4 SCL SDA 1 0 0 1 0 0 A0 (1) R/W Start By Master 1 (2) 0 0 P4 (3) P3 P2 P1 P0 ACK By Repeated Start ADS7924 By Master ACK By ADS7924 Frame 1 Slave Address Byte Frame 2 Pointer Address Byte 1 9 1 9 SCL (Continued) SDA (Continued) 1 0 0 0 1 0 A0 (1) D7 R/W Start By Master D6 D5 D4 D3 D2 D1 D0 From ADS7924 ACK By ADS7924 ACK By Master (2) Frame 4 Data Byte 1 Frame 3 Slave Address Byte 1 9 1 9 SCL (Continued) SDA (Continued) D7 Start By Master D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 Frame 5 Register Data Byte 2 D1 From ADS7924 ACK By Master From ADS7924 D2 D0 1 NACK By Master (2) Stop By Master Frame 6 Register Data Byte N (1) The value of A0 is determined by the A0 pin. (2) When INC is set to '1', the address pointer automatically increments for multiple register reads. (3) Bits P[4:0] point to the register to be read. Figure 34. Reading Multiple Registers Timing Diagram Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 31 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com APPLICATION INFORMATION AVERAGE POWER CONSUMPTION With its fast conversion time and programmable sleep time with near-zero power, the ADS7924 allows periodic monitoring of the inputs with a very low average power dissipation, especially as the monitoring interval increases. The average current required can be calculated as the weighed average of the currents consumed during the power-up, acquisition, converting, and sleep periods using Equation 3. IPUtPU + IACQtACQ + ICONVtCONV + ISLEEPtSLEEP IAVERAGE = tCYCLE (3) As * * * * * an example, calculate the average current in the following configuration: Mode programmed to Auto-Scan with Sleep Power-up time (tPU) programmed to '0' Acquisition time (tACQ) programmed to 6ms Sleep time (tSLEEP) programmed to 2.5ms AVDD = 2.2V Looking at Figure 28, the cycle time is seen to equal tCYCLE = 4tPU + 4tACQ + 4tCONV + 4tSLEEP = 4(0) + 4(6ms) + 4(4ms) + 4(2.5ms) = 10.04ms. Table 6 lists the supply current for different supply voltages and operating conditions. Using the data for 2.2V with the calculated cycle time in Equation 3 gives the following average current: 0 + (270mA)(4)(6ms) + (400mA)(4)(4ms) + (1.25mA)(4)(2.5ms) IAVERAGE = = 2.5mA 10.04ms (4) Table 6. Supply Current for Various Operating Conditions AVDD STATUS 5V 3.3V 2.7V 2.2V Idle 1A 1A 1A 1A Awake 45A 25A 20A 15A Acquiring 315A 285A 275A 270A Converting 730A 520A 450A 400A Sleeping 3A 2A 1.5A 1.25A Note the acquisition, conversion, and sleep times are multiplied by 4 because these are repeated four times in one cycle when in auto-scan with sleep mode. Average power dissipation for the above configuration where all four inputs are monitored every 10ms is (2.2V)(2.5mA) = 5.5mW. Figure 3 and Figure 4 plot Equation 3 to help illustrate the relationship between cycle time and average power dissipation. 32 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 BASIC CONNECTIONS The ADS7924 provides a break-out point in the signal path between the multiplexer output and the ADC input for external signal conditioning, if desired. Typical uses include adding an op amp, such as the TLV2780, along with an RC filter circuit. Using an Op Amp Adding an op amp provides a high input impedance to the sensor source and buffers the capacitive ADC input from high-impedance sensor circuits, as shown in Figure 35. Note that high-impedance input signals can be momentarily disrupted when coupled directly to a capacitive input like that of a sampling ADC. This disruption can create errors when sampling. The use of an op amp is recommended in these cases. SHDN TLV2780 AVDD 1mF 16 DVDD 14 15 AVDD 3kW 2 CH1 INT ADS7924 CH3 SDA MSP430 Microcontroller 4 5 8 3 A0 SCL DGND CH2 AGND 9 3kW 1 6 10 DVDD RESET PWRCON 11 CH0 7 12 ADCIN Sensor Signals MUXOUT 13 1mF Figure 35. Sensor Data Acquisition with TLV2780 Buffer Amplifier Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 33 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com Using an Op Amp and RC Filter Placing an RC low-pass filter in the signal path allows for filtering out noise. The RC component values should allow for sufficient settling time when changing from channel to channel. The time required for a full-scale input signal to settle to within 1LSB of a 12-bit ADC is given by Equation 5: Settling Time = R x C x ln(212) (5) RX and C form a low-pass filter for removing sensor and noise from other sources at the op amp input pin. The low-pass bandwidth is given by Equation 6: f-3dB = 1/(2pRC) (6) The f-3dB should be chosen such that the signals of interest are within half of the programmable sampling frequency. The noise bandwidth is given by Equation 7: fNB = 1/(4RC) (7) This term should be set to reduce noise bandwidth but still allow for enough settling time. Note that the ADS7924 has internal registers ACQCONFIG (address = 14h), PWRCONF (address = 15h), and SLPCONFIG (address = 13h) that can be programmed to slow down the channel-to-channel power up, acquisition, and sleep periods if needed to allow for a longer settling time requirement. In Figure 36, R is the sum of the sensor output impedance RSENSOR, the internal MUX resistance RMUX (approximately 60), and external resistor RX. The primary benefit of having the filter at the input of the op amp is that the amplifier does not have to drive the filter, which can cause instability with large capacitor values that may be needed in order to filter noise to low levels. SHDN TLV2780 AVDD RX C 16 DVDD 14 15 AVDD 3kW 3kW 2 CH1 INT ADS7924 CH3 SDA MSP430 Microcontroller 4 5 8 3 A0 SCL DGND CH2 AGND 9 DVDD 1 6 10 1mF RESET PWRCON 11 CH0 7 12 ADCIN Sensor Signals MUXOUT 13 1mF NOTE: f-3dB BW = 159kHz, R = 1k, and C = 1nF where R = RMUX + RSENSOR + RX. Figure 36. Sensor Data Acquisition with Filter and TLV2780 Buffer Amplifier 34 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 Op Amp Power-Up Time The TLV2780 typically powers up from a shutdown state in 800ns. This period is well within the ADS7924 minimum acquisition time of 6ms. Setting the PWRCONFIG register (address = 15h) allows for more time if another op amp with a shutdown feature is used. Using an RC Filter For applications where low output impedance signals are provided for the ADS7924 inputs, a simple RC filter may suffice, as shown in Figure 37. CX AVDD RX 16 DVDD 14 15 AVDD 3kW 2 CH1 INT ADS7924 CH3 SDA MSP430 Microcontroller 4 5 6 8 3 A0 SCL DGND CH2 AGND 9 3kW 1 RESET PWRCON 10 CH0 7 11 ADCIN 13 12 1mF 1mF MUXOUT Sensor Signals DVDD NOTE: f-3dB BW = 159kHz, R = 1k, and C = 1nF where R = RMUX + RSENSOR + RX, C = CX + CADCIN, RMUX is approximately 60, and CADCIN is approximately 15pF. Figure 37. Sensor Data Acquisition with Filter Only CX should be greater than 200pF, if possible. When coupled directly to the ADC input, using a capacitor with this value allows for faster settling when scanning between channels. Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 35 ADS7924 SBAS482A - JANUARY 2010 - REVISED MAY 2010 www.ti.com Op Amp with Filter and Gain Option Both filtering and gain are added in Figure 38. Gain is given by Equation 8: Gain = 1 + R1/R2 Where: R is the sum of the sensor output impedance RSENSOR, the internal MUX resistance RMUX (approximately 60), and the external resistor RX. (8) R2 R1 SHDN TLV2780 AVDD RX C 1mF 15 AVDD DVDD 14 INT ADS7924 CH2 SCL CH3 SDA 3 MSP430 Microcontroller A0 4 5 7 8 AGND 9 3kW 2 CH1 DGND 10 3kW 1 RESET 6 11 CH0 PWRCON 12 ADCIN 13 MUXOUT Sensor Signals DVDD 16 1m F NOTE: f-3dB BW = 159kHz, R = 1k, and C = 1nF where R = RMUX + RSENSOR + RX, and RMUX is approximately 60. Gain = 1 + R1/R2. Figure 38. Sensor Data Acquisition with Gain Set Resistors, Filter, and TLV2780 Buffer Amplifier 36 Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 ADS7924 www.ti.com SBAS482A - JANUARY 2010 - REVISED MAY 2010 Driving an RC Filter and the ADCIN Pin With An Op Amp A filter can be placed at the output of the op amp, as shown in Figure 39. Care must be taken to ensure that the op amp is capable of driving the RC filter circuit without the op amp becoming unstable. One of the benefits of this circuit is that the op amp noise is filtered along with sensor and other system noise right at the ADC input pin. SHDN C R TLV2780 AVDD 1mF 16 DVDD 14 15 AVDD 3kW RESET 2 CH1 INT ADS7924 CH3 SDA MSP430 Microcontroller 4 5 8 3 A0 SCL DGND CH2 AGND 9 3kW 1 6 10 CH0 PWRCON 11 7 12 ADCIN Sensor Signals MUXOUT 13 1mF DVDD NOTE: C = 200pF, R = 1k, and the capacitance at the ADCIN pin is approximately 15pF. Figure 39. Sensor Data Acquisition with an Op Amp Driving an RC Filter Submit Documentation Feedback Copyright (c) 2010, Texas Instruments Incorporated Product Folder Link(s): ADS7924 37 PACKAGE OPTION ADDENDUM www.ti.com 15-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty ADS7924IRTER ACTIVE WQFN RTE 16 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR ADS7924IRTET ACTIVE WQFN RTE 16 250 CU NIPDAU Level-2-260C-1 YEAR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS7924IRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS7924IRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7924IRTER WQFN RTE 16 3000 367.0 367.0 35.0 ADS7924IRTET WQFN RTE 16 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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