4-Channel
MUX
CH0
CH1
CH2
CH3
MUXOUT ADCIN AVDD DVDD
AGND DGND
SAR
ADC
DataBuffers,
Sequencer,and
Alarms
I C
Interface
2
SDA
SCL
A0
INT
PWRCON
RESET
Oscillator
ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
2.2V, 12-Bit, 4-Channel, microPOWER™
ANALOG-TO-DIGITAL CONVERTER WITH I
2
C INTERFACE
Check for Samples: ADS7924
1FEATURES DESCRIPTION
234• Intelligent Monitoring: The ADS7924 is a four-channel, 12-bit,
analog-to-digital converter (ADC) with an I2C™
– Auto-Sequencing of 4-Channel Multiplexer interface. With its low-power ADC core, support for
– Individual Alarm Thresholds for Each low-supply operation, and a flexible measurement
Channel sequencer that essentially eliminates power
– Programmable Scan Rate consumption between conversions, the ADS7924
forms a complete monitoring system for power-critical
• Micropower Monitoring: applications such as battery-powered equipment and
– Four-Channel Scanning: energy harvesting systems.
– Every 1ms →25mWThe ADS7924 features dedicated data registers and
– Every 10ms →5mWonboard programmable digital threshold comparators
– < 1µA of Power-Down Current for each input. Alarm conditions can be programmed
that generate an interrupt. The combination of data
– Programmable Interrupt Pin Controls buffering, programmable threshold comparisons, and
Shutdown/Wakeup of the Microcontroller alarm interrupts minimize the host microcontroller
– Auto Power-Down Control time needed to supervise the ADS7924.
– PWRCON Pin Allows Shutdown of External The four-channel input multiplexer (MUX) is routed
Op Amp through external pins to allow a common signal
• Wide Supply Range: conditioning circuit to be used between the MUX and
– Analog Supply: 2.2V to 5.5V ADC, thereby reducing overall component count. The
low-power ADC uses the analog supply as its
– Digital Supply: 1.65V to 5.5V reference and can acquire and convert signals in only
• Small Footprint: 3mm × 3mm QFN 10ms. An onboard oscillator eliminates the need to
supply a master clock.
APPLICATIONS The ADS7924 is offered in a small 3mm × 3mm QFN
• Portable and Battery-Powered Systems: and is fully specified for operation over the industrial
– Medical, Communications, Remote Sensor temperature range of –40°C to +85°C.
Signal Monitoring, Power-Supply
Monitoring
• Energy Harvesting
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2microPOWER is a trademark of Texas Instruments Incorporated.
3I2C is a trademark of NXP Semiconductors.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at ti.com.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted. ADS7924 UNIT
Supply voltage, AVDD to AGND –0.3 to +6 V
Supply voltage, DVDD to DGND –0.3 to +6 V
Supply voltage, DVDD to AVDD AVDD ≥DVDD V
AGND to DGND –0.3 to +0.3 V
Analog input voltage AGND – 0.3 to AVDD + 0.3 V
Digital input voltage with respect to DGND (SCL and SDA) DGND – 0.3 to 6 V
Digital input voltage with respect to DGND (A0, RESET) DGND – 0.3 to DVDD + 0.3 V
Input current to all pins except supply pins –10 to +10 mA
Maximum operating temperature +125 °C
Storage temperature range –60 to +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
THERMAL INFORMATION ADS7924
THERMAL METRIC(1) RTE UNITS
16
qJA Junction-to-ambient thermal resistance 48.1
qJC(top) Junction-to-case(top) thermal resistance 47.3
qJB Junction-to-board thermal resistance 60.8 °C/W
yJT Junction-to-top characterization parameter 0.3
yJB Junction-to-board characterization parameter 14.1
qJC(bottom) Junction-to-case(bottom) thermal resistance 0.4
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
ELECTRICAL CHARACTERISTICS
Minimum/maximum specifications are at TA= –40°C to +85°C, 1.65V < DVDD < 5.5V, and 2.2V < AVDD < 5.5V. Typical
specifications are at TA= +25°C, AVDD = 5V, and DVDD = 5V, unless otherwise noted. ADS7924
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input span (CHX – AGND) 0 AVDD V
Input capacitance(1) 4 10 pF
ADC sampling capacitance 15 pF
MUX resistance 60 Ω
Input channel crosstalk 85 dB
SYSTEM PERFORMANCE
Resolution 12 Bits
No missing codes 12 Bits
Integral linearity –1.5 ±0.5 1.5 LSBs
Differential linearity –1.0 ±0.6 1.5 LSBs
Offset error –5 5 LSBs
Offset error drift 0.01 LSB/°C
Gain error –0.20 –0.01 0.20 %
Gain error drift 0.6 ppm/°C
Noise (rms) 0.125 LSB
SAMPLING DYNAMICS
Monitoring time/channel(2) 10 µs
CLOCK
Internal clock frequency variation ±20 %
DIGITAL INPUT/OUTPUT
Logic family CMOS
Logic level:
VIH (SDA, SCL, A0, RESET) 0.8 DVDD DVDD + 0.3 V
VIL (SDA, SCL, A0, RESET) DGND – 0.3 0.4 V
Input current IIVI= DVDD or DGND –10 10 mA
IOH = 100mA, INT pin 0.8 DVDD DVDD V
VOH (PWRCON, INT) IOH = 100µA, PWRCON pin 0.8 AVDD AVDD V
VOL (PWRCON, INT, SDA) IOL = 100mA DGND 0.4 V
Low-level output current IOL SDA pin, VOL = 0.6V 3 mA
Load capacitance CBSDA pin 400 pF
Data format Straight binary
POWER-SUPPLY REQUIREMENTS
Power-supply voltage:
DVDD(3) 1.65 5.5 V
AVDD 2.2 5.5 V
IAVDD(4) tCYCLE = 2.5ms, AVDD = 2.2V 5 8 mA
IPWRD, power-down current <1 mA
TEMPERATURE RANGE
Specified performance –40 +85 °C
(1) CH0 to CH3 input pin capacitance.
(2) Rate at which channels can be scanned. This is the minimum acquisition time (6µs) and conversion time (4µs).
(3) DVDD cannot exceed AVDD.
(4) See Figure 3 and Figure 4 for more information.
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RESET
INT
SCLK
SDA
CH0
CH1
CH2
CH3
1
2
3
4
12
11
10
9
DVDD
16
A0 5
AVDD
15
DGND 6
ADCIN
14
PWRCON 7
MUXOUT
13
AGND 8
Thermal
Pad(1)
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
PIN CONFIGURATION
RTE PACKAGE
QFN-16
(TOP VIEW)
(1) Connect to AGND.
TERMINAL FUNCTIONS
PIN
NUMBER NAME FUNCTION DESCRIPTION
1 RESET Digital input External reset, active low
2 INT Digital output Interrupt pin, active low; generated when input voltage is beyond programmed threshold
3 SCLK Digital input Serial clock input
Digital
4 SDA Serial data
input/output
5 A0 Digital input I2C address selection
6 DGND Digital Digital ground
7 PWRCON Digital output Power control pin to control shutdown/power-up of external op amp
8 AGND Analog Analog ground
9 CH3 Analog input Input channel 3
10 CH2 Analog input Input channel 2
11 CH1 Analog input Input channel 1
12 CH0 Analog input Input channel 0
13 MUXOUT Analog output Multiplexer output
14 ADCIN Analog input ADC input
15 AVDD Analog Analog supply
16 DVDD Digital Digital supply
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SCL
SDA
tRtHDSTA
tHDSTA
tHDDAT
tBUF
tHIGH
tSUSTA tSUSTO
P S Sr P
tSP
tVDACK
tSUDAT 9thClock
tVDDAT
tF
tLOW
ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
TIMING DIAGRAM
NOTE: S = Start, Sr = Repeated Start, and P = Stop.
Figure 1. I2C Timing Diagram
Table 1. I2C Timing Definitions
ADS7924
PARAMETER MIN MAX UNIT
SCL operating frequency fSCL 0 0.4 MHz
Bus free time between START and STOP condition tBUF 1.3 ms
Hold time after repeated START condition. tHDSTA 600 ns
After this period, the first clock is generated.
Repeated START condition setup time tSUSTA 600 ns
Stop condition setup time tSUSTO 600 ns
Data hold time tHDDAT 0 ns
Data setup time tSUDAT 100 ns
SCL clock low period tLOW 1300 ns
SCL clock high period tHIGH 600 ns
Clock/data fall time tF300 ns
Clock/data rise time tR300 ns
Data valid time tVDDAT 0.9 ms
Data valid acknowledge time tVDACK 0.9 ms
Pulse width of spike that must be suppressed by the input filter tSP 0 50 ns
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14
12
10
8
6
4
2
0
Current( A)m
-40.0 105.0
Temperature( C)°
-25.5
Auto-SingleMode
t =2.5ms
A =5.0V
FastI CInterfaceMode
VDD=DVDD
CYCLE
2
AnalogCurrent
DigitalCurrent
-11.0 3.5 18.0 32.5 47.0 61.5 76.0 90.5
1000
100
10
1
Power( W)m
0.01 0.1 1000
t (ms)
CYCLE
1 10 100
AVDD=2.2V
t =0V
t =6 s
PU
ACQ m
Auto-ScanModes
(4-ChannelMeasurements)
Auto-SingleModes
(1-ChannelMeasurements)
10000
1000
100
10
1
Power( W)m
0.01 0.1 1000
t (ms)
CYCLE
1 10 100
AVDD=5V
t =0V
t =6 s
PU
ACQ m
Auto-SingleModes
(1-ChannelMeasurements)
Auto-ScanModes
(4-ChannelMeasurements)
10
9
8
7
6
5
4
3
2
1
0
AnalogSupplyCurrent( A)m
2.0 2.5 3.0 6.0
AVDDSupplyVoltage(V)
3.5 4.0 5.04.5 5.5
Auto-SingleMode
t =2.5ms
CYCLE
0
1
2
3
4
5
6
7
8
9
10
-
-
-
-
-
-
-
-
-
-
GainError(LSB)
2 3 6
AVDDSupplyVoltage(V)
4
30UnitsAcrossTwoLots
5
Mean+ s
Mean
Mean - s
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS
At TA= +25°C, unless otherwise noted.
CURRENT vs TEMPERATURE AVERAGE POWER DISSIPATION vs CYCLE TIME
Figure 2. Figure 3.
AVERAGE POWER DISSIPATION vs CYCLE TIME ANALOG SUPPLY CURRENT vs SUPPLY VOLTAGE
Figure 4. Figure 5.
TYPICAL GAIN ERROR vs AVDD VOLTAGE GAIN ERROR DRIFT
Figure 6. Figure 7.
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3
2
1
0
1
2
3
-
-
-
OffsetError(LSB)
-40 105
Temperature( C)°
-11
AVDD=2.2V
764718
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
OffsetError(LSB)
2 3 6
AVDDVoltage(V)
4
30UnitsAcrossTwoLots
5
Mean+ s
Mean
Mean - s
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
-
-
-
-
LinearityError(LSB)
0 512 4096
Code
1024 30721536
AVDD=2.2V
25602048 3584
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
Frequency(%ofNominal)
2 3 6
AVDDVoltage(V)
45
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
-
-
-
-
LinearityError(LSB)
0 512 4096
Code
1024 30721536
AVDD=5.0V
25602048 3584
2.0
1.5
1.0
0.5
0
0.5
1.0
1.5
2.0
-
-
-
-
INL(LSB)
Temperature( C)°
AVDD=2.2V
INLshownisworstresultovertransferfunction.
MaximumINL
MinimumINL
-40.0 105.0-25.5 -11.0 3.5 18.0 32.5 47.0 61.5 76.0 90.5
ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, unless otherwise noted.
OFFSET ERROR DRIFT, TYPICAL TYPICAL OFFSET ERROR vs AVDD VOLTAGE
Figure 8. Figure 9.
INTERNAL OSCILLATOR FREQUENCY vs VOLTAGE INTEGRAL NONLINEARITY
Figure 10. Figure 11.
INTEGRAL NONLINEARITY INTEGRAL LINEARITY ERROR DRIFT
Figure 12. Figure 13.
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1.5
1.0
0.5
0
0.5
1.0
1.5
-
-
-
LinearityError(LSB)
0 512 4096
Code
1024 30721536
AVDD=5V
25602048 3584
1.5
1.0
0.5
0
0.5
1.0
1.5
-
-
-
LinearityError(LSB)
0 512 4096
Code
1024 30721536
AVDD=2.2V
25602048 3584
1.5
1.0
0.5
0
0.5
1.0
1.5
-
-
-
DNL(LSB)
Temperature( C)°
AVDD=2.2V
DNLshownisworstresultovertransferfunction.
MaximumDNL
MinimumDNL
-40.0 105.0-25.5 -11.0 3.5 18.0 32.5 47.0 61.5 76.0 90.5
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
Count
Code
DCInput
AVDD=2.2V
2052
2050
2048
2044
2053
2051
2049
2047
2043
2046
2045
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
Count
Code
DCInput
AVDD=5V
2052
2050
2048
2046
2044
2053
2051
2049
2047
2045
2043
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
At TA= +25°C, unless otherwise noted.
DIFFERENTIAL NONLINEARITY DIFFERENTIAL NONLINEARITY
Figure 14. Figure 15.
DIFFERENTIAL NONLINEARITY vs TEMPERATURE NOISE HISTOGRAM(1)
Figure 16. Figure 17.
NOISE HISTOGRAM(1)
Figure 18.
(1) At code center.
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I C
2
Interface
MUXOUT
SAR
ADC
ADCIN
AGND AGND
AVDD DVDD
CH0Data
CH1Data
CH2Data
CH3Data
CH0UpperLimit
CH1UpperLimit
CH2UpperLimit
CH3UpperLimit
CH0LowerLimit
CH1LowerLimit
CH2LowerLimit
CH3LowerLimit
Comparatorand
AlarmDetect
Control
and
Sequencer
ClockOscillator
SDA
SCL
RESET
PWRCON
A0
INT
Input
Multiplexer
CH0
CH1
CH2
CH3
Registers
ADS7924
www.ti.com
SBAS482A –JANUARY 2010–REVISED MAY 2010
OVERVIEW
The ADS7924 is a miniature, four-channel, multiplexed, 12-bit, analog-to-digital converter (ADC) with an I2C
serial interface. Figure 19 shows a block diagram. The four-channel input multiplexer is routed through external
pins to allow a common signal conditioning block to be used for all four channels. The PWRCON digital output
can be used to shut down active circuitry used in the signal conditioning; see the Application Information section
for additional details.
The successive-approximation-register (SAR) ADC performs a no-latency conversion on the selected input
channel and stores the data in a dedicated register. A digital threshold comparator with programmable upper and
lower limits can be enabled and used to create an alarm monitor. A dedicated interrupt output pin (INT) indicates
when an alarm occurs. Two I2C addresses are available and are selected with the dedicated digital input pin A0.
Both standard and fast mode formats for I2C are supported.
Figure 19. ADS7924 Block Diagram
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AVDD
AGND
CH0
AVDD
AGND
CH1
AVDD
AGND
CH2
AVDD
AGND
CH3
MUXOUT
AGND
(1)
FFF
OutputCode(Hex)
0¼
InputVoltage(V )
ACDIN
FFE
800
¼
000
7FE
001
¼
AVDD
AVDD 1.5LSB-0.5LSB
1LSB=AVDD/212
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
MULTIPLEXER capacitor is connected to the ADCIN pin. While
converting during the tCONV interval, the sampling
The ADS7924 has a four-channel, single-ended input capacitor is disconnected from the ADCIN pin, and
multiplexer. As Figure 20 shows, ESD diodes protect the conversion process determines the voltage that
the inputs. Make sure these diodes do not turn on by was sampled.
staying within the absolute input voltage range
specification. The MUXOUT pin can be connected to REFERENCE
AGND within the multiplexer; for example, to provide
a test signal of 0V or as part of a calibration The analog supply voltage (AVDD) is used as the
procedure. See the PWRCONFIG: Power reference. Power to the ADS7924 should be clean
Configuration register in the Register Map section for and well bypassed. A 0.1mF ceramic capacitor should
more details be placed as close as possible to the ADS7924
package. In addition, a 1mF to 10mF capacitor and a
5Ωto 10Ωseries resistor may be used to low-pass
filter a noisy supply.
CLOCK
The ADS7924 uses an internal clock. The clock
speed determines the various timing settings such as
conversion time, acquisition time, etc.
DATA FORMAT
The ADS7924 provides 12 bits of data in unipolar
format. The positive full-scale input produces an
output code of FFFh and a zero input produces an
output code of 0h. The output clips at these codes for
signals that either exceed full-scale or go below '0'.
Figure 21 shows code transitions versus input
voltage.
(1) See the PWRCONFIG: Power Configuration register in the
Register Map section.
Figure 20. ADS7924 Multiplexer
ADC INPUT
The ADCIN pin provides a single-ended input to the
12-bit successive approximation register (SAR) ADC.
This pin is protected with ESD diodes in the same
way as the multiplexer inputs. While acquiring the
signal during the tACQ interval, the ADC sampling (1) Excludes the effects of noise, INL, offset, and gain errors.
Figure 21. ADS7924 Code Transition Diagram(1)
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SBAS482A –JANUARY 2010–REVISED MAY 2010
Sleep Time
ADC CONVERSION TIMING The sleep time is allowed to elapse after conversions
The ADS7924 provides a flexible timing arrangement in the Auto-Single with Sleep, Auto-Scan with Sleep,
to support a wide variety of measurement needs. and Auto-Burst Scan with Sleep modes. The nominal
Three user-controlled timings include power up (tPU), time programmed by the SLPTIME registers can be
acquisition (tACQ), and sleep (tSLEEP) plus a fixed increased by a factor of eight using the SLPMULT8
conversion time (tCONV). bit or decreased by a factor of four using the
SLPDIV4 bit.
Power-Up Time
The power-up time is allowed to elapse whenever the INTERRUPT OUTPUT (INT)
device has been shutdown in idle mode. Power-up
time can allow external circuits, such as an op amp, The ADS7924 offers a dedicated output pin (INT) for
between the MUXOUT and ADCIN pins to turn on. signaling an interrupt condition. The INT pin can be
The nominal time programmed by the PUTIME[4:0] configured to activate when the ADC is busy with a
register bits is given by Equation 1: conversion, when data are ready for retrieval, or
when an alarm condition occurs; see the Interrupt
tPU = PWRUPTIME[4:0] × 2ms (1) Configuration register in the Register Map section.
For example, if PWRUPTIME is set to 25 ('011001') To clear an interrupt from an alarm condition, read
then 50ms is allowed to elapse before beginning the the INTCONFIG register (12h). To clear an interrupt
acquisition time. If a power-up time is not required, from data ready, read the data registers. The interrupt
set the bits to '0' to effectively bypass. clears when the lower four bits are retrieved.
Acquisition Time The INT pin can be configured to generate a static
output (useful for a host controller monitoring for a
The acquisition time is allowed to elapse before level) or a pulse output (useful for a host controller
beginning a conversion. During this time, the ADC monitoring for a edge transition). When a pulse
acquires the signal. The minimum acquisition time is output is selected, the nominal pulse width is 250ns.
6µs. The nominal time programmed by the The Interrupt Control Register should be read to clear
ACQTIME[4:0] register bits is given by Equation 2:the interrupt.
tACQ = (ACQTIME[4:0] × 2ms) + 6ms (2)
For example, if ACQTIME is set to 30 ('011110') then PWRCON
66ms is allowed to acquire the input signal. If an The PWRCON pin allows the user to synchronize the
acquisition time greater than 6ms is not required, set shutdown/wakeup of an external op amp with the
the bits to '0'. ADC conversion cycle. This feature provides further
power reduction and can be useful in applications
Conversion Time where the time difference between consecutive signal
The conversion time is always 4ms and cannot be captures is large. The PWRCON pin can drive up to
programmed by the user. 3mA of current and its output voltage is the same as
AVDD. This pin is controlled by the PWRCONFIG
register.
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ADC
Window
Comparator
X(2)
ULRx[7:0](2)
CounterX
ALMCNT[2:0](1)
LLRx[7:0]
UpperLimitThreshold
LowerLimitThreshold
Alarmfor
ChannelX
CHXData
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
ALARM When an alarm occurs, the INT pin can be configured
to generate an interrupt. The channel that generated
The ADS7924 offers an independent alarm function the alarm can be read from the registers. A read of
for each input channel. An 8-bit window comparator the Interrupt Control register clears the alarm register
can be enabled to test the ADC conversion result and also resets the alarm counter.
against an upper limit set by the ULR register and
against a lower limit set by the LLR register. If the ADC OPERATING MODES
conversion result is less than or equal to the LLR
threshold value or greater than or equal to the ULR The ADS7924 offers multiple operating modes to
threshold value, the comparator is tripped. There are support a wide variety of monitoring needs.
separate upper and lower registers for each input Conversions can either be started manually or set to
channel. automatically continue. The mode is set by writing to
the MODE register, and changes take effect as soon
A programmable counter determines how many as the write completes. Table 2 gives a brief
comparator trips it takes to generate an alarm. A description of each mode.
separate counter is used for each channel and is
incremented whenever the comparator trips, either for Idle Mode
the upper or lower thresholds. That is, an ADC
conversion result on channel 1 that exceeds the ULR Use this mode to save power when not converting. All
threshold or falls below the LLR threshold increments circuits are shut down.
the counter for that channel. Figure 22 shows a
conceptual diagram of the window comparator and Awake Mode
alarm circuitry. All circuits are operating in this mode and the ADC is
ready to convert. When switching between modes, be
sure to first select the Awake mode and then switch
to the desired mode. This procedure ensures the
internal control logic is properly synchronized.
(1) The same ALMCNT value is used for all four window comparators.
(2) X = 0 to 3.
Figure 22. Window Comparator/Alarm Conceptual Block Diagram
Table 2. Mode Descriptions
MODE DESCRIPTION
Idle All circuits shutdown; lowest power setting
Awake All circuits awake and ready to convert
Manual-Single Select input channel is converted once
Manual-Scan All input channels are converted once
Auto-Single One input channel is continuously converted
Auto-Scan All input channels are continuously converted
Auto-Single with Sleep One input channel is continuously converted with programmable sleep time between conversions
Auto-Scan with Sleep All input channels are continuously converted with programmable sleep time between conversions
Auto-Burst Scan with All input channels are converted with minimal delay followed by a programmable sleep time
Sleep
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Status Awake
Awaiting
Mode
Selection
Busy(1)
DataReady(1)
P R NW CO (2)
Convert
Selected
Channel
I putn M lt p xeu e ri l Sele ect dCh nn la e
tPU tACQ tCONV
Acquire
Selected
Channel
(3)
ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
Manual-Single Mode After the conversion completes, the device waits for a
new mode to be set. This mode can be set to Idle to
This mode converts the selected channel once, as save power. When tPU and tACQ are very short, the
shown in Figure 23. After the ADC Mode Control very short conversion time needed allows a read
register is written, the power-up time (tPU) and register operation to be issued on the I2C bus
acquisition time (tACQ) are allowed to elapse. tPU can immediately after the write operation that initiates this
be set to '0' to effectively bypass if not needed. tACQ mode. It is important to note that tPU only applies to
time is programmable through the ACQCONFIG the first manual-single command.
register, bits[4:0]. Sleep time (tSLEEP) is not used in
this mode. If multiple conversions are needed, the manual-single
mode can be reissued without requiring the awake
mode to be issued in between. Consecutive
manual-single commands have no tPU period.
(1) Busy and data ready are internal signals shown as active high that can be routed to the INT pin for external monitoring.
(2) PWRCON is shown enabled and active high.
(3) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 23. Manual-Single Operation Example
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Status Awake
Awaiting
Mode
Selection
Busy(1)
DataReady(2)
P RCONW (3)
Convert
First
Channel
Convert
Second
Channel
Convert
Third
Channel
Convert
Fourth
Channel
In up t Mu ip el et l x r SelectedChan lne NextCh na nel NextCh na nel NextCh na nel
tPU tACQ tCONV tACQ tACQ tACQ
tCONV tCONV tCONV
Acquire
First
Channel
Acquire
Second
Channel
Acquire
Third
Channel
Acquire
Fourth
Channel
(4)
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
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Manual-Scan Mode CH2 data always goes in register DATA2_H and
DATA2_L regardless of conversion order. After all
This mode converts all of the channels once, starting four conversions complete, the device waits for a new
with the selected channel, as illustrated in Figure 24.mode to be set. This mode can be set to Idle
After the ADC Mode Control register is written, the afterwards to save power. The INT pin can be
power-up time (tPU) is allowed to elapse. This value configured to indicate the completion of each
can be set to '0' to effectively bypass if not needed. individual conversion or it can wait until all four finish.
Before each conversion, an acquisition time (tACQ) is In either case, the appropriate data register is
allowed to elapse. tACK time is programmable through updated after each conversion. These registers can
the ACQCONFIG register, bits[4:0]. Sleep time be read at any time afterwards. If multiple scan are
(tSLEEP) is not used in this mode. The input needed, the manual-scan mode can be reissued
multiplexer is automatically incremented as the without requiring the Awake mode to be issued in
conversions complete. If, for example, the initial between.
selected channel is CH2, the conversion order is
CH2, CH3, CH0, and CH1. Data from the
conversions are always put into the data register that
corresponds to a particular channel. For example,
(1) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(2) Data ready is an internal signal shown as active high and is enabled when all conversions are complete. It can be routed to the INT pin
for external monitoring.
(3) PWRCON is shown enabled and active high.
(4) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 24. Manual-Scan Operation Example
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Satust
Acquire
Selected
Channel
B syu (2)
PWRCON(3)
C nverto
Selected
Channel
In tpu Multiplexer Sele ect dCh nn la e (1)
tPU tACQ tCONV tACQ tACQ
tCONV tCONV
C nverto
Selected
Channel
C nverto
Selected
Channel
Awake
Acquire
Selected
Channel
Acquire
Selected
Channel
(4)
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SBAS482A –JANUARY 2010–REVISED MAY 2010
Auto-Single Mode This mode can be used with the onboard digital
comparator to monitor the status of an input signal
This mode automatically converts the selected with little support needed from a host microcontroller.
channel continuously, as shown in Figure 25. After Note that the conversion time is less than the I2C
the ADC Mode Control register is written, the data retrieval time. It is suggested to stop this mode
power-up time (tPU) is allowed to elapse. This value by setting the mode to Idle or stopping the conversion
can be set to '0' to effectively bypass if not needed. by configuring the alarm to do so, before retrieving
Before the conversion, an acquisition time (tACQ) is data. The alarm can also be configured to continue
allowed to elapse. tACQ time is programmable through the conversion even after an interrupt is generated.
the ACQCONFIG register, bits[4:0]. Sleep time
(tSLEEP) is not used in this mode. After the conversion
completes the cycle is repeated.
(1) Same channel is continuously converted.
(2) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(3) PWRCON is shown enabled and active high.
(4) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 25. Example of Auto-Single Operation
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Status Awake
Acquire
Second
Channel
Acquire
Third
Channel
Acquire
Fourth
Channel
Acquire
First
Channel
Busy(1)
Convert
Channel
First
PWRCON(2)
Convert
Channel
Second
Convert
Channel
Third
Convert
Channel
Fourth
InputMultiplexer SelectedChannel(First) NextChannel NextChannel NextChannel FirstChannel
tPU tACQ tCONV tACQ tACQ tACQ tACQ
tCONV tCONV tCONV tCONV
Convert
Channel
First
Acquire
First
Channel
(3)
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Auto-Scan Mode is stopped. Data from the conversions are always put
into the data register that corresponds to a particular
This mode automatically converts all the channels channel. For example, CH2 data always go in register
continuously, starting with the selected channel, as DATA2_H and DATA2_L regardless of conversion
illustrated in Figure 26. After the ADC Mode Control order.
register is written, the power-up time (tPU) is allowed
to elapse. This value can be set to '0' to effectively This mode can be used with the onboard digital
bypass if not needed. Before the conversion, an comparator to monitor the status of the input signals
acquisition time (tACQ) is allowed to elapse. tACQ time with little support needed from a host microcontroller.
is programmable through the ACQCONFIG register, It is suggested to interrupt this mode and stop the
bits[4:0]. Sleep time (tSLEEP) is not used in this mode. automatic conversions, either by setting the mode to
The input multiplexer is automatically incremented as Idle or configuring the alarm to do so, before
the conversions complete. If, for example, the initial retrieving data.
selected channel is CH2, the conversion order is
CH2, CH3, CH0, CH1, CH2, CH3, etc. until the mode
(1) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(2) PWRCON is shown enabled and active high.
(3) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 26. Auto-Scan Operation Example
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C nverto
Selected
Channel
SelectedChan eln (1)
Sleep Sleep
Satust
Busy(2)
P RCONW (3)
Input Multip exerl
tACQ tCONV tSLEEP tACQ tACQ
tCONV tCONV
tSLEEP
C nverto
Selected
Channel
C nverto
Selected
Channel
Acquire
Selected
Channel
Acquire
Selected
Channel
Acquire
Selected
Channel
tPU
Awake
tPU
Awake
tPU
Awake
tCYCLE
(4)
ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
Auto-Single with Sleep Mode This mode can be used with the onboard digital
comparator to periodically monitor the status of an
This mode automatically converts the selected input signal while saving power between conversions.
channel repeatedly with a sleep interval between Little support is needed from a host microcontroller. It
conversions, as shown in Figure 27. After the ADC is suggested to stop this mode by setting the mode to
Mode Control register is written, the power-up time Idle or stopping the conversion by configuring the
(tPU) is allowed to elapse. This value can be set to '0' alarm to do so, before retrieving data. The length in
to effectively bypass if not needed. Before the time of the cycle (tCYCLE) sets the average power
conversion, an acquisition time (tACQ) is allowed to dissipation, as shown in Figure 3 or Figure 4.
elapse. tACQ time is programmable through the
ACQCONFIG register, bits[4:0]. After the conversion,
sleep time (tSLEEP) is allowed to elapse and then the
cycle repeats. The length of the sleep time is
controlled by register bits. During the sleep mode,
power dissipation is minimal and the PWRCON
output is always disabled.
(1) Same channel is continuously converted.
(2) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(3) PWRCON is shown enabled and active high.
(4) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 27. Auto-Single with Sleep Operation Example
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Convert
Channel
First
SelectedChannel Ne Chanxt nel Ne Chanxt nel Ne Chanxt nel
Sleep
Satust
B syu (1)
Input Multiplexer
tACQ tCONV tSLEEP
Acquire
First
Channel
Convert
Channel
Se ndco Sleep
tSLEEP
tCONV
tACQ
tCYCLE
Convert
Channel
Th rdi Sleep
tSLEEP
tCONV
tACQ
Convert
Channel
Fourth
tCONV
tACQ
Acquire
Fourth
Channel
Acquire
Third
Channel
Acquire
Second
Channel
PWRCON(2)
tPU
Awake
tPU
Awake
tPU
Awake
tPU
Awake
(3)
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Auto-Scan with Sleep Mode is stopped. Data from the conversions are always put
into the data register that corresponds to a particular
This mode automatically converts all the channels channel. For example, CH2 data always goes in
repeatedly with a sleep interval between conversions, register DATA2_H and DATA2_L regardless of
as illustrated in Figure 28. After the ADC Mode conversion order.
Control register is written, the power-up time (tPU) is
allowed to elapse. This value can be set to '0' to This mode can be used with the onboard digital
effectively bypass if not needed. Before the first comparator to periodically monitor the status of the
conversion of the selected input, an acquisition time input signals while saving power between
(tACQ) is allowed to elapse. tACQ time is programmable conversions. Little support is needed from a host
through the ACQCONFIG register, bits[4:0]. After the microcontroller. It is suggested to stop this mode by
conversion, a sleep time (tSLEEP) is allowed to elapse setting the mode to Idle or stopping the conversion by
and then the cycle repeats. The length of the sleep configuring the alarm to do so, before retrieving data.
time is controlled by register bits. During the sleep The length in time of the cycle (tCYCLE) sets the
mode, power dissipation is minimal and the average power dissipation, as shown in Figure 3 or
PWRCON output is always disabled. The input Figure 4.
multiplexer is automatically incremented as the
conversions complete. If, for example, the initial
selected channel is CH2, the conversion order is
CH2, CH3, CH0, CH1, CH2, CH3, etc. until the mode
(1) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(2) PWRCON is shown enabled and active high.
(3) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 28. Auto-Scan with Sleep Operation Example
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Awake
Aquireand
Convert
Channel
First
Aquireand
Convert
Channel
Second
Aquireand
Convert
Channel
Third
Aquireand
Convert
Channel
Fourth
SelectedChannel(First) NextChannel NextChannel NextChannel NextChannel
Sleep
FirstChannel
Status
Busy(1)
PWRCON(2)
InputMultiplexer
Aquireand
Convert First
Channel
Aquireand
Convert Second
Channel
tACQ CONV
+t
tSLEEP tPU
tACQ CONV
+t
tACQ CONV
+t tACQ CONV
+t tACQ CONV
+t tACQ CONV
+t
Awake
tPU
tCYCLE
(3)
ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
Auto-Burst Scan with Sleep Mode PWRCON output is always disabled. Data from the
conversions are always put into the data register that
This mode automatically converts all the channels corresponds to a particular channel. For example,
without delay followed by a sleep interval before the CH2 data always goes in register DATA2_H and
cycle repeats, as shown in Figure 29. After the ADC DATA2_L regardless of conversion order.
Mode Control register is written, the power-up time
(tPU) is allowed to elapse. This value can be set to '0' This mode can be used with the onboard digital
to effectively bypass if not needed. Before the first comparator to periodically monitor the status of the
conversion of the selected input, an acquisition time input signals while saving power between
(tACQ) is allowed to elapse. tACQ time is programmable conversions. Little support is needed from a host
through the ACQCONFIG register, bits[4:0]. microcontroller. It is suggested to interrupt this mode
Afterwards, all four inputs are measured without and stop the automatic conversions, either by setting
delay. The input multiplexer is automatically the mode to Idle or configuring the alarm to do so,
incremented as the conversions complete. If, for before retrieving data. The length in time of the cycle
example, the initial selected channel is CH2, the (tCYCLE) sets the average power, as shown in Figure 3
conversion order is CH2, CH3, CH0, and CH1. After or Figure 4.
the four conversions, a sleep time (tSLEEP) is allowed
to elapse and then the cycle repeats. The length of
the sleep time is controlled by register bits. During the
sleep mode, power dissipation is minimal and the
(1) Busy is an internal signal shown as active high that can be routed to the INT pin for external monitoring.
(2) PWRCON is shown enabled and active high.
(3) The mode begins on the trailing edge of the I2C acknowledge after writing to the MODECNTL register.
Figure 29. Auto-Burst Scan with Sleep Operation Example
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REGISTER MAP
The ADS7924 operation is controlled through a set of registers. Collectively, the registers contain all the
information needed to configure the part. Table 3 shows the register map.
Table 3. Register Map
RESET
ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
VALUE
00h MODECNTRL 00h MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 SEL/ID1 SEL/ID0
01h INTCNTRL X0h ALRM_ST3 ALRM_ST2 ALRM_ST1 ALRM_ST0 AEN/ST3 AEN/ST2 AEN/ST1 AEN/ST0
02h DATA0_U XXh DATA0[11] DATA0[10] DATA0[9] DATA0[8] DATA0[7] DATA0[6] DATA0[5] DATA0[4]
03h DATA0_L XXh DATA0[3] DATA0[2] DATA0[1] DATA0[0] 0 0 0 0
04h DATA1_U XXh DATA1[11] DATA1[10] DATA1[9] DATA1[8] DATA1[7] DATA1[6] DATA1[5] DATA1[4]
05h DATA1_L XXh DATA1[3] DATA1[2] DATA1[1] DATA1[0] 0 0 0 0
06h DATA2_U XXh DATA2[11] DATA2[10] DATA2[9] DATA2[8] DATA2[7] DATA2[6] DATA2[5] DATA2[4]
07h DATA2_L XXh DATA2[3] DATA2[2] DATA2[1] DATA2[0] 0 0 0 0
08h DATA3_U XXh DATA3[11] DATA3[10] DATA3[9] DATA3[8] DATA3[7] DATA3[6] DATA3[5] DATA3[4]
09h DATA3_L XXh DATA3[3] DATA3[2] DATA3[1] DATA3[0] 0 0 0 0
0Ah ULR0 XXh ULR0[7] ULR0[6] ULR0[5] ULR0[4] ULR0[3] ULR0[2] ULR0[1] ULR0[0]
0Bh LLR0 XXh LLR0[7] LLR0[6] LLR0[5] LLR0[4] LLR0[3] LLR0[2] LLR0[1] LLR0[0]
0Ch ULR1 XXh ULR1[7] ULR1[6] ULR1[5] ULR1[4] ULR1[3] ULR1[2] ULR1[1] ULR1[0]
0Dh LLR1 XXh LLR1[7] LLR1[6] LLR1[5] LLR1[4] LLR1[3] LLR1[2] LLR1[1] LLR1[0]
0Eh ULR2 XXh ULR2[7] ULR2[6] ULR2[5] ULR2[4] ULR2[3] ULR2[2] ULR2[1] ULR2[0]
0Fh LLR2 XXh LLR2[7] LLR2[6] LLR2[5] LLR2[4] LLR2[3] LLR2[2] LLR2[1] LLR2[0]
10h ULR3 XXh ULR3[7] ULR3[6] ULR3[5] ULR3[4] ULR3[3] ULR3[2] ULR3[1] ULR3[0]
11h LLR3 XXh LLR3[7] LLR3[6] LLR3[5] LLR3[4] LLR3[3] LLR3[2] LLR3[1] LLR3[0]
12h INTCONFIG E0h AIMCNT2 AIMCNT1 AIMCNT0 INTCNFG1 INTCNFG0 BUSY/INT INTPOL INTTRIG
13h SLPCONFIG 00h 0 CONVCTRL SLPDIV4 SLPMULT8 0 SLPTIME2 SLPTIME1 SLPTIME0
14h ACQCONFIG 00h 0 0 0 ACQTIME4 ACQTIME3 ACQTIME2 ACQTIME1 ACQTIME0
15h PWRCONFIG 00h CALCNTL PWRCONPOL PWRCONEN PWRUPTIME4 PWRUPTIME3 PWRUPTIME2 PWRUPTIME1 PWRUPTIME0
18h
(A0 = 0)
16h RESET RST/ID7 RST/ID6 RST/ID5 RST/ID4 RST/ID3 RST/ID2 RST/ID1 RST/ID0
19h
(A0 = 1)
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MODECNTRL: ADC Mode Control Register (Address = 00h)
76543210
MODE5 MODE4 MODE3 MODE2 MODE1 MODE0 SEL/ID1 SEL/ID0
Bits[7:2] MODE[5:0]: Mode control
000000 = Idle mode (default)
100000 = Awake mode
110000 = Manual-Single mode
110010 = Manual-Scan mode
110001 = Auto-Single mode
110011 = Auto-Scan mode
111001 = Auto-Single with Sleep mode
111011 = Auto-Scan with Sleep mode
111111 = Auto-Burst Scan with Sleep mode
Bits[1:0] SEL/ID[1:0]: Channel selection
When read, these bits indicate the last channel converted.
When writing to these bits, select which input appears on MUXOUT:
00 = Channel 0 is selected
01 = Channel 1 is selected
10 = Channel 2 is selected
11 = Channel 3 is selected (unless the CALCNTRL bit is set to '1')
INTCNTRL: Interrupt Control Register (Address = 01h)
76543210
ALRM_ST3 ALRM_ST2 ALRM_ST1 ALRM_ST0 AEN/ST3 AEN/ST2 AEN/ST1 AEN/ST0
Bits[7:4] ALRM_ST[3:0]: Alarm status (read-only)
Reading these bits indicates the alarm status for the channels. These bits are never masked—they always report the alarm
status even when the alarm is not enabled by the corresponding AEN/ST bits.
Bit 7 = Channel 3 alarm status, '1' indicates an alarm condition
Bit 6 = Channel 2 alarm status, '1' indicates an alarm condition
Bit 5 = Channel 1 alarm status, '1' indicates an alarm condition
Bit 4 = Channel 0 alarm status, '1' indicates an alarm condition
Bits[3:0] AEN/ST[3:0]: Alarm enable
Writing to these bits enables the alarm for the corresponding channel.
Reading these bits returns the status of the alarm for the corresponding channel when enabled. Reading returns a '0' when
the alarm in not enabled.
Bit 3 = Channel 3 alarm enable, 1 = enabled (default = 0)
Bit 2 = Channel 2 alarm enable, 1 = enabled (default = 0)
Bit 1 = Channel 1 alarm enable, 1 = enabled (default = 0)
Bit 0 = Channel 0 alarm enable, 1 = enabled (default = 0)
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There are individual registers for each input channel to buffer the conversion data. The 12 bits are stored in two
registers: the upper register stores the eight most significant bits; the lower register stores the lower four least
significant bits. The data registers are always updated with the corresponding input channel regardless of the
order of conversion. For example, DATA0_U and DATA0_L always contain the results of the latest conversion of
CH0.
DATA0_U: Conversion Data for Channel 0, Upper Bits Register (Address = 02h)
76543210
DATA0[11] DATA0[10] DATA0[9] DATA0[8] DATA0[7] DATA0[6] DATA0[5] DATA0[4]
(MSB)
DATA0_L: Conversion Data for Channel 0, Lower Bits Register (Address = 03h)
76543210
DATA0[0]
DATA0[3] DATA0[2] DATA0[1] 0 0 0 0
(LSB)
DATA1_U: Conversion Data for Channel 1, Upper Bits Register (Address = 04h)
76543210
DATA1[11] DATA1[10] DATA1[9] DATA1[8] DATA1[7] DATA1[6] DATA1[5] DATA1[4]
(MSB)
DATA1_L: Conversion Data for Channel 1, Lower Bits Register (Address = 05h)
76543210
DATA1[0]
DATA1[3] DATA1[2] DATA1[1] 0 0 0 0
(LSB)
DATA2_U: Conversion Data for Channel 2, Upper Bits Register (Address = 06h)
76543210
DATA2[11] DATA2[10] DATA2[9] DATA2[8] DATA2[7] DATA2[6] DATA2[5] DATA2[4]
(MSB)
DATA2_L: Conversion Data for Channel 2, Lower Bits Register (Address = 07h)
76543210
DATA2[0]
DATA2[3] DATA2[2] DATA2[1] 0 0 0 0
(LSB)
DATA3_U: Conversion Data for Channel 3, Upper Bits Register (Address = 08h)
76543210
DATA3[11] DATA3[10] DATA3[9] DATA3[8] DATA3[7] DATA3[6] DATA3[5] DATA3[4]
(MSB)
DATA3_L: Conversion Data for Channel 3, Lower Bits Register (Address = 09h)
76543210
DATA3[0]
DATA3[3] DATA3[2] DATA3[1] 0 0 0 0
(LSB)
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There are individual upper and lower threshold registers for input channel. Each register is eight bits with the
least significant bit weight equal to AVDD/256. The comparator is tripped when the input signal exceeds the
value of the upper limit register or falls below the lower limit register.
ULR0: Upper Limit Threshold for Channel 0 Comparator Register (Address = 0Ah)
76543210
ULR0[7] (MSB) ULR0[6] ULR0[5] ULR0[4] ULR0[3] ULR0[2] ULR0[1] ULR0[0] (LSB)
LLR0: Lower Limit Threshold for Channel 0 Comparator Register (Address = 0Bh)
76543210
LLR0[7] (MSB) LLR0[6] LLR0[5] LLR0[4] LLR0[3] LLR0[2] LLR0[1] LLR0[0] (LSB)
ULR1: Upper Limit Threshold for Channel 1 Comparator Register (Address = 0Ch)
76543210
ULR1[7] (MSB) ULR1[6] ULR1[5] ULR1[4] ULR1[3] ULR1[2] ULR1[1] ULR1[0] (LSB)
LLR1: Lower Limit Threshold for Channel 1 Comparator Register (Address = 0Dh)
76543210
LLR1[7] (MSB) LLR1[6] LLR1[5] LLR1[4] LLR1[3] LLR1[2] LLR1[1] LLR0[0] (LSB)
ULR2: Upper Limit Threshold for Channel 2 Comparator Register (Address = 0Eh)
76543210
ULR2[7] (MSB) ULR2[6] ULR2[5] ULR2[4] ULR2[3] ULR2[2] ULR2[1] ULR2[0] (LSB)
LLR2: Lower Limit Threshold for Channel 2 Comparator Register (Address = 0Fh)
76543210
LLR2[7] (MSB) LLR2[6] LLR2[5] LLR2[4] LLR2[3] LLR2[2] LLR2[1] LLR2[0] (LSB)
ULR3: Upper Limit Threshold for Channel 3 Comparator Register (Address = 10h)
76543210
ULR3[7] (MSB) ULR3[6] ULR3[5] ULR3[4] ULR3[3] ULR3[2] ULR3[1] ULR3[0] (LSB)
LLR3: Lower Limit Threshold for Channel 3 Comparator Register (Address = 11h)
76543210
LLR3[7] (MSB) LLR3[6] LLR3[5] LLR3[4] LLR3[3] LLR3[2] LLR3[1] LLR3[0] (LSB)
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 23
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INTCONFIG: Interrupt Configuration Register (Address = 12h)
76543210
ALMCNT2 ALMCNT1 ALMCNT0 INTCNFG2 INTCNFG1 INTCNFG0 INTPOL INTTRIG
Bits[7:5] ALMCNT[2:0]: Alarm count
These bits set the number of times the comparator threshold limit (either upper or lower) must be exceeded to generate an
alarm.
000 = Every conversion generates an alarm
010 = Exceeding the threshold limit 1 time generates an alarm condition
100 = Exceeding the threshold limit 2 times generates an alarm condition
110 = Exceeding the threshold limit 3 times generates an alarm condition
111 = Exceeding the threshold limit 4 times generates an alarm condition
101 = Exceeding the threshold limit 5 times generates an alarm condition
110 = Exceeding the threshold limit 6 times generates an alarm condition
111 = Exceeding the threshold limit 7 times generates an alarm condition
Bits[4:2] INTCNFG[2:0]: INT output pin configuration
These bits determine which signal is output on INT. They also select the conversion control event; see the CONVCTRL bit
in the SLPCONFIG register. The configuration of these bits is shown in Table 4.
Table 4. INT Pin Configuration
BIT SETTING INT PIN CONFIGURATION CONVERSION CONTROL EVENT
000 Alarm Alarm
001 Busy Alarm
010 Data ready: one conversion completed Data ready: one conversion complete
011 Busy Data ready: one conversion complete
100 Do not use —
101 Do not use —
110 Data ready: all four conversions complete Data ready: four conversions complete
111 Busy Data ready: four conversions complete
Bit 1 INTPOL: INT pin polarity
0 = Active low (default)
1 = Active high
Bit 0 INTTRIG: INT output pin signaling
0 = Static signal for use with level triggering (default)
1 = Pulse signal for use with edge triggering
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SBAS482A –JANUARY 2010–REVISED MAY 2010
SLPCONFIG: Sleep Configuration Register (Address = 13h)
76543210
0 CONVCTRL SLPDIV4 SLPMULT8 0 SLPTIME2 SLPTIME1 SLPTIME0
Bit 7 Always write '0'
Bit 6 CONVCTRL: Conversion control
This bit determines the conversion status after a conversion control event; see the INTCNFG bits in the INTCONFIG
register.
0 = Conversions continue, independent of the control event status (default)
1 = Conversions are stopped as soon as a control event occurs; the event must be cleared to resume conversions
Bit 5 SLPDIV4: Sleep time 4x divider
This bit sets the speed of the sleep clock.
0 = Sleep time divider is '1' (default)
1 = Sleep time divider is '4'
Bit 4 SLPMULT8: Sleep time 8x multiplier
0 = Sleep time multiplier is '1' (default)
1 = Sleep time multiplier is '8'
Bit 3 Always write '0'
Bits[2:0] SLPTIME[2:0]: Sleep time setting
000 = 2.5ms (default)
001 = 5ms
010 = 10ms
011 = 20ms
100 = 40ms
101 = 80ms
110 = 160ms
111 = 320ms
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ACQCONFIG: Acquire Configuration Register (Address = 14h)
76543210
0 0 0 ACQTIME4 ACQTIME3 ACQTIME2 ACQTIME1 ACQTIME0
Bits[7:5] Always write '0'
Bits[4:0] ACQTIME[4:0]: Signal acquire time
These bits set the time to acquire the signal before a conversion (default = 0).
tACQ = ACQTIME[4:0] × 2ms + 6µs
PWRCONFIG: Power-Up Configuration Register (Address = 15h)
76543210
CALCNTL PWRCONPOL PWRCONEN PWRUPTIME4 PWRUPTIME3 PWRUPTIME2 PWRUPTIME1 PWRUPTIME0
Bit 7 CALCNTL: Calibration control
0 = Setting CH3 in the Mode Control register selects the CH3 input to be routed to the MUXOUT pin. (default)
1 = Setting CH3 in the Mode Control register connects the MUXOUT pin to AGND.
Bit 6 PWRCONPOL: PWRCON pin polarity
0 = Active low (default)
1 = Active high
Bit 5 PWRCONEN: PWRCON enable
0 = The PWRCON pin is disabled (default)
1 = The PWRCON pin is always enabled
Bits[4:0] PWRUPTIME[4:0]: Power-up time setting
These bits set the power-up time (default = 0).
tPWR = PWRUPTIME[4:0] × 2ms.
RESET: Software Reset and Device ID Register (Address = 16h)
76543210
RST/ID7 RST/ID6 RST/ID5 RST/ID4 RST/ID3 RST/ID2 RST/ID1 RST/ID0
A read of this register returns the device ID when A0 determines the last bit of the device ID (0001100A0).
A write to this register of 10101010 generates a software reset of the ADS7924.
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ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
I2C INTERFACE Every byte transmitted on the I2C bus, whether it is
address or data, is acknowledged with an
The ADS7924 communicates through an I2Cacknowledge bit. When the master has finished
interface. I2C is a two-wire, open-drain interface that sending a byte (eight data bits) to a slave, it stops
supports multiple devices and masters on a single driving SDA and waits for the slave to acknowledge
bus. Devices on the I2C bus only drive the bus lines the byte. The slave acknowledges the byte by pulling
low by connecting them to ground; they never drive SDA low. The master then sends a clock pulse to
the bus lines high. Instead, the bus wires are pulled clock the acknowledge bit. Similarly, when the master
high by pull-up resistors, so the bus wires are high has finished reading a byte, it pulls SDA low to
when no device is driving them low. This way, two acknowledge this to the slave. It then sends a clock
devices cannot conflict; if two devices drive the bus pulse to clock the bit. (The master always drives the
simultaneously, there is no driver contention. clock line.)
Communication on the I2C bus always takes place Anot-acknowledge is performed by simply leaving
between two devices, one acting as the master and SDA high during an acknowledge cycle. If a device is
the other as the slave. Both masters and slaves can not present on the bus, and the master attempts to
read and write, but slaves can only do so under the address it, it receives a not-acknowledge because no
direction of the master. Some I2C devices can act as device is present at that address to pull the line low.
masters or slaves, but the ADS7924 can only act as
a slave device. When the master has finished communicating with a
slave, it may issue a STOP condition. When a STOP
An I2C bus consists of two lines, SDA and SCL. SDA condition is issued, the bus becomes idle again. The
carries data; SCL provides the clock. All data are master may also issue another START condition.
transmitted across the I2C bus in groups of eight bits. When a START condition is issued while the bus is
To send a bit on the I2C bus, the SDA line is driven to active, it is called a repeated START condition.
the appropriate level while SCL is low (a low on SDA
indicates the bit is zero; a high indicates the bit is See the Timing Diagrams section for a timing
one). Once the SDA line settles, the SCL line is diagram showing the ADS7924 I2C transaction.
brought high, then low. This pulse on SCL clocks the
SDA bit into the receiver shift register. If the I2C bus I2C ADDRESS SELECTION
is held idle for more than 25ms, the bus times out. The ADS7924 has one address pin, A0, that sets the
The I2C bus is bidirectional: the SDA line is used for I2C address. This pin can be connected to ground or
both transmitting and receiving data. When the VDD, allowing two addresses to be selected with one
master reads from a slave, the slave drives the data pin as shown in Table 5. The state of the address pin
line; when the master sends to a slave, the master A0 is sampled continuously.
drives the data line. The master always drives the
clock line. The ADS7924 never drives SCL, because Table 5. A0 Pin Connection and Corresponding
it cannot act as a master. On the ADS7924, SCL is Slave Address
an input only. A0 PIN SLAVE ADDRESS
Most of the time the bus is idle; no communication Ground 1001000
occurs, and both lines are high. When communication DVDD 1001001
is taking place, the bus is active. Only master devices
can start a communication and initiate a START I2C SPEED MODES
condition on the bus. Normally, the data line is only
allowed to change state while the clock line is low. If The ADS7924 supports the I2C standard and fast
the data line changes state while the clock line is modes. Standard mode allows a clock frequency of
high, it is either a START condition or a STOP up to 100kHz and fast mode permits a clock
condition. A START condition occurs when the clock frequency of up to 400kHz.
line is high and the data line goes from high to low. A
STOP condition occurs when the clock line is high SLAVE MODE OPERATIONS
and the data line goes from low to high. The ADS7924 can act as either slave receivers or
After the master issues a START condition, it sends a slave transmitters. As a slave device, the ADS7924
byte that indicates which slave device it wants to cannot drive the SCL line.
communicate with. This byte is called the address
byte. Each device on an I2C bus has a unique 7-bit
address to which it responds. The master sends an
address in the address byte, together with a bit that
indicates whether it wishes to read from or write to
the slave device.
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Product Folder Link(s): ADS7924
Frame1SlaveAddressByte Frame2PointerAddressByte
1
StartBy
Master
ACKBy
ADS7924
ACKBy
ADS7924
1 9 1
Frame3RegisterDataByte
ACKBy
ADS7924
StopBy
Master
1
D7 D6 D5 D4 D3 D2 D1 D0
9
SDA
(Continued)
SCL
(Continued)
9
SDA
SCL
0 0 1 0 0 A0(1) R/W 0(2) 0 0 P4(3) P3 P2 P1 P0 ¼
¼
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
Receive Mode: least significant byte is then sent by the slave and is
followed by an acknowledgment from the master. The
In slave receive mode the first byte transmitted from master may terminate transmission after any byte by
the master to the slave is the address with the R/W not acknowledging or issuing a START or STOP
bit low. This byte allows the slave to be written to. condition.
The next byte transmitted by the master is the
register pointer byte. The ADS7924 then WRITING THE REGISTERS
acknowledges receipt of the register pointer byte. The
next two bytes are written to the address given by the To access a write register from the ADS7924, the
register pointer. The ADS7924 acknowledges each master must first write the appropriate value to the
byte sent. Register bytes are sent with the most Pointer address. The Pointer address is written
significant byte first, followed by the least significant directly after the slave address byte, low R/W bit, and
byte. a successful slave acknowledgment. After the Pointer
address is written, the slave acknowledges and the
Transmit Mode: master issues a STOP or a repeated START
condition. The MSB of the pointer address is the
In slave transmit mode, the first byte transmitted by increment (INC) bit. When set to '1', the register
the master is the 7-bit slave address followed by the address is automatically incremented after every
high R/W bit. This byte places the slave into transmit register write which allows convenient writing of
mode and indicates that the ADS7924 is being read multiple registers. Set INC to '0' when writing a single
from. The next byte transmitted by the slave is the register. Figure 30 and Figure 31 show timing
most significant byte of the register that is indicated examples.
by the register pointer. This byte is followed by an
acknowledgment from the master. The remaining
(1) The value of A0 is determined by the A0 pin.
(2) When INC is set to '0', the address pointer remains unchanged after a read.
(3) Bits P[4:0] point to the register to be written.
Figure 30. Writing a Single Register Timing Diagram
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Frame2PointerAddressByte
1
StartBy
Master
ACKBy
ADS7924
ACKBy
ADS7924
ACKBy
ADS7924
StopBy
Master
1 9 1
1
D7 D6 D5 D4 D3 D2 D1 D0
9
ACKBy
ADS7924
1
D7
SDA
(Continued)
SCL
(Continued)
D6 D5 D4 D3 D2 D1 D0
9
9
SDA
SCL
0 0 1 0 0A0(1) R/W 1(2) 0 0 P4(3) P3 P2 P1 P0 ¼
¼
Frame1SlaveAddressByte
Frame3RegisterDataByte1 Frame4RegisterDataByteN
ADS7924
www.ti.com
SBAS482A –JANUARY 2010–REVISED MAY 2010
(1) The value of A0 is determined by the A0 pin.
(2) When INC is set to '1', the address pointer automatically increments for multiple register writes.
(3) Bits P[4:0] point to the storing register to be written.
Figure 31. Writing Multiple Registers Timing Diagram
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): ADS7924
1
StartBy
Master
ACKBy
ADS7924
ACKBy
ADS7924
StartBy
Master
ACKBy
ADS7924
ACKBy
Master(2)
From
ADS7924
1 9 1 9
1 9 1 9
SDA
SCL
0 0 1 R/W 0(2) 0 0 P4(3) P3 P2 P1 P0
¼
SDA
(Continued)
SCL
(Continued)
1 0 0 1
0A0(1)
0A0(1) R/W D7 D6 D5 D4 D3 D2 D1 D0
StopBy
Master
0
0
Frame2PointerAddressByte
Frame3SlaveAddressByte Frame4DataByte
Frame1SlaveAddressByte
Frame1SlaveAddressByte Frame2RegisterDataByte
1
StartBy
Master
ACKBy
ADS7924
ACKBy
ADS7924
1 9 1 9
SDA
SCL
0 0 1 R/W D7 D6 D5
D4
D3 D2 D1 D0
0A0(1)
StopBy
Master
0
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
READING THE REGISTERS The master may issue a START condition and send
the slave address byte with the R/W bit high to begin
To read a specific register from the ADS7924, the the read. Note that if the previously selected register
master must first write the appropriate value to the is to be read again there is no need to update the
pointer address. The pointer address is written pointer address. Figure 32 to Figure 34 show
directly after the slave address byte, low R/W bit, and examples of register reads.
a successful slave acknowledgment. The MSB of the
pointer address is the INC bit. When set to '1', the
register address is automatically incremented after
every register read which allows convenient reading
of multiple registers. Set INC to '0' when reading a
single register.
(1) The value of A0 is determined by the A0 pin.
(2) When INC is set to '0', the address pointer remains unchanged after a read.
(3) Bits P[4:0] point to the register to be read.
Figure 32. Reading a Single Register Timing Diagram
(1) The value of A0 is determined by the A0 pin.
Figure 33. Reading a Previously Addressed Register Timing Diagram
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Product Folder Link(s): ADS7924
Frame1SlaveAddressByte Frame2PointerAddressByte
1
StartBy
Master
ACKBy
ADS7924
ACKBy
ADS7924
Frame5RegisterDataByte2 Frame6RegisterDataByteN
StartBy
Master
ACKBy
Master
NACKBy
Master(2)
From
ADS7924
1 9 1 9
1 9 1 9
SDA
SCL
0 0 1 R/W 1(2) 0 0 P4(3) P3 P2 P1 P0
¼
SDA
(Continued)
SCL
(Continued)
D7 D6 D5 D4
0A0(1)
D3 D7 D6 D5 D4 D3 D2 D1 D0
RepeatedStart
By Master
0
D2 D1 D0
StartBy
Master
ACKBy
ADS7924
ACKBy
Master(2)
From
ADS7924
1 9 1 9
SDA
(Continued)
SCL
(Continued)
1 0 0 1 0A0(1) R/W D7 D6 D5 D4 D3 D2 D1 D0
0
Frame3SlaveAddressByte Frame4DataByte1
From
ADS7924
1
Stop
By Master
ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
(1) The value of A0 is determined by the A0 pin.
(2) When INC is set to '1', the address pointer automatically increments for multiple register reads.
(3) Bits P[4:0] point to the register to be read.
Figure 34. Reading Multiple Registers Timing Diagram
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Product Folder Link(s): ADS7924
I t +I t +I t +I t
PU ACQ CONV SLEEPPU ACQ CONV SLEEP
tCYCLE
I =
AVERAGE
0+(270 A)(4)(6 s)+(400 A)(4)(4 s)+(1.25 A)(4)(2.5ms)mm m m m
10.04ms
I =
AVERAGE =2.5 Am
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
APPLICATION INFORMATION
AVERAGE POWER CONSUMPTION
With its fast conversion time and programmable sleep time with near-zero power, the ADS7924 allows periodic
monitoring of the inputs with a very low average power dissipation, especially as the monitoring interval
increases. The average current required can be calculated as the weighed average of the currents consumed
during the power-up, acquisition, converting, and sleep periods using Equation 3.
(3)
As an example, calculate the average current in the following configuration:
• Mode programmed to Auto-Scan with Sleep
• Power-up time (tPU) programmed to '0'
• Acquisition time (tACQ) programmed to 6ms
• Sleep time (tSLEEP) programmed to 2.5ms
• AVDD = 2.2V
Looking at Figure 28, the cycle time is seen to equal tCYCLE = 4tPU + 4tACQ + 4tCONV + 4tSLEEP = 4(0) + 4(6ms) +
4(4ms) + 4(2.5ms) = 10.04ms.
Table 6 lists the supply current for different supply voltages and operating conditions. Using the data for 2.2V
with the calculated cycle time in Equation 3 gives the following average current:
(4)
Table 6. Supply Current for Various Operating Conditions
AVDD
STATUS 5V 3.3V 2.7V 2.2V
Idle 1µA 1µA 1µA 1µA
Awake 45µA 25µA 20µA 15µA
Acquiring 315µA 285µA 275µA 270µA
Converting 730µA 520µA 450µA 400µA
Sleeping 3µA 2µA 1.5µA 1.25µA
Note the acquisition, conversion, and sleep times are multiplied by 4 because these are repeated four times in
one cycle when in auto-scan with sleep mode.
Average power dissipation for the above configuration where all four inputs are monitored every 10ms is
(2.2V)(2.5mA) = 5.5mW.
Figure 3 and Figure 4 plot Equation 3 to help illustrate the relationship between cycle time and average power
dissipation.
32 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7924
TLV2780
RESET
INT
SCL
SDA
CH0
CH1
CH2
CH3
1
2
3
4
12
11
10
9
DVDD 16
A0
5
AVDD 15
DGND
6
ADCIN 14
PWRCON
7
MUXOUT 13
AGND
8
ADS7924
SensorSignals
MSP430
Microcontroller
SHDN
DVDD
AVDD
1 Fm
1 Fm
3kW3kW
ADS7924
www.ti.com
SBAS482A –JANUARY 2010–REVISED MAY 2010
BASIC CONNECTIONS
The ADS7924 provides a break-out point in the signal path between the multiplexer output and the ADC input for
external signal conditioning, if desired. Typical uses include adding an op amp, such as the TLV2780, along with
an RC filter circuit.
Using an Op Amp
Adding an op amp provides a high input impedance to the sensor source and buffers the capacitive ADC input
from high-impedance sensor circuits, as shown in Figure 35. Note that high-impedance input signals can be
momentarily disrupted when coupled directly to a capacitive input like that of a sampling ADC. This disruption
can create errors when sampling. The use of an op amp is recommended in these cases.
Figure 35. Sensor Data Acquisition with TLV2780 Buffer Amplifier
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 33
Product Folder Link(s): ADS7924
RX
TLV2780
C
RESET
INT
SCL
SDA
CH0
CH1
CH2
CH3
1
2
3
4
12
11
10
9
DVDD 16
A0
5
AVDD 15
DGND
6
ADCIN 14
PWRCON
7
MUXOUT 13
AGND
8
ADS7924
SensorSignals
MSP430
Microcontroller
SHDN
DVDD
AVDD
1 Fm
1 Fm
3kW3kW
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
Using an Op Amp and RC Filter
Placing an RC low-pass filter in the signal path allows for filtering out noise. The RC component values should
allow for sufficient settling time when changing from channel to channel. The time required for a full-scale input
signal to settle to within 1LSB of a 12-bit ADC is given by Equation 5:
Settling Time = R × C × ln(212) (5)
RXand C form a low-pass filter for removing sensor and noise from other sources at the op amp input pin. The
low-pass bandwidth is given by Equation 6:
f–3dB = 1/(2pRC) (6)
The f–3dB should be chosen such that the signals of interest are within half of the programmable sampling
frequency. The noise bandwidth is given by Equation 7:
fNB = 1/(4RC) (7)
This term should be set to reduce noise bandwidth but still allow for enough settling time. Note that the ADS7924
has internal registers ACQCONFIG (address = 14h), PWRCONF (address = 15h), and SLPCONFIG (address =
13h) that can be programmed to slow down the channel-to-channel power up, acquisition, and sleep periods if
needed to allow for a longer settling time requirement.
In Figure 36,Ris the sum of the sensor output impedance RSENSOR, the internal MUX resistance RMUX
(approximately 60Ω), and external resistor RX. The primary benefit of having the filter at the input of the op amp
is that the amplifier does not have to drive the filter, which can cause instability with large capacitor values that
may be needed in order to filter noise to low levels.
NOTE: f–3dB BW = 159kHz, R = 1kΩ, and C = 1nF where R = RMUX + RSENSOR + RX.
Figure 36. Sensor Data Acquisition with Filter and TLV2780 Buffer Amplifier
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RX
CX
RESET
INT
SCL
SDA
CH0
CH1
CH2
CH3
1
2
3
4
12
11
10
9
DVDD 16
A0
5
AVDD 15
DGND
6
ADCIN 14
PWRCON
7
MUXOUT 13
AGND
8
ADS7924
SensorSignals
MSP430
Microcontroller
DVDD
AVDD
1 Fm
1 Fm
3kW3kW
ADS7924
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SBAS482A –JANUARY 2010–REVISED MAY 2010
Op Amp Power-Up Time
The TLV2780 typically powers up from a shutdown state in 800ns. This period is well within the ADS7924
minimum acquisition time of 6ms. Setting the PWRCONFIG register (address = 15h) allows for more time if
another op amp with a shutdown feature is used.
Using an RC Filter
For applications where low output impedance signals are provided for the ADS7924 inputs, a simple RC filter
may suffice, as shown in Figure 37.
NOTE: f–3dB BW = 159kHz, R = 1kΩ, and C = 1nF where R = RMUX + RSENSOR + RX, C = CX+ CADCIN, RMUX is approximately 60Ω, and
CADCIN is approximately 15pF.
Figure 37. Sensor Data Acquisition with Filter Only
CXshould be greater than 200pF, if possible. When coupled directly to the ADC input, using a capacitor with this
value allows for faster settling when scanning between channels.
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Link(s): ADS7924
RX
TLV2780
C
RESET
INT
SCL
SDA
CH0
CH1
CH2
CH3
1
2
3
4
12
11
10
9
DVDD
16
A0
5
AVDD
15
DGND
6
ADCIN
14
PWRCON
7
MUXOUT
13
AGND
8
R1
R2
ADS7924
SensorSignals
MSP430
Microcontroller
SHDN
DVDD
AVDD
1 Fm
1 Fm
3kW3kW
ADS7924
SBAS482A –JANUARY 2010–REVISED MAY 2010
www.ti.com
Op Amp with Filter and Gain Option
Both filtering and gain are added in Figure 38. Gain is given by Equation 8:
Gain = 1 + R1/R2
Where:
R is the sum of the sensor output impedance RSENSOR, the internal MUX resistance RMUX (approximately
60Ω), and the external resistor RX. (8)
NOTE: f–3dB BW = 159kHz, R = 1kΩ, and C = 1nF where R = RMUX + RSENSOR + RX, and RMUX is approximately 60Ω. Gain = 1 + R1/R2.
Figure 38. Sensor Data Acquisition with Gain Set Resistors, Filter, and TLV2780 Buffer Amplifier
36 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): ADS7924
TLV2780
RESET
INT
SCL
SDA
CH0
CH1
CH2
CH3
1
2
3
4
12
11
10
9
DVDD 16
A0
5
AVDD 15
DGND
6
ADCIN 14
PWRCON
7
MUXOUT 13
AGND
8
C
R
ADS7924
SensorSignals
MSP430
Microcontroller
SHDN
DVDD
AVDD
1 Fm
1 Fm
3kW3kW
ADS7924
www.ti.com
SBAS482A –JANUARY 2010–REVISED MAY 2010
Driving an RC Filter and the ADCIN Pin With An Op Amp
A filter can be placed at the output of the op amp, as shown in Figure 39. Care must be taken to ensure that the
op amp is capable of driving the RC filter circuit without the op amp becoming unstable. One of the benefits of
this circuit is that the op amp noise is filtered along with sensor and other system noise right at the ADC input
pin.
NOTE: C = 200pF, R = 1kΩ, and the capacitance at the ADCIN pin is approximately 15pF.
Figure 39. Sensor Data Acquisition with an Op Amp Driving an RC Filter
Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): ADS7924
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ADS7924IRTER ACTIVE WQFN RTE 16 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ADS7924IRTET ACTIVE WQFN RTE 16 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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PACKAGE OPTION ADDENDUM
www.ti.com 15-May-2010
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS7924IRTER WQFN RTE 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
ADS7924IRTET WQFN RTE 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS7924IRTER WQFN RTE 16 3000 367.0 367.0 35.0
ADS7924IRTET WQFN RTE 16 250 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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