DC1649A-A - Linear Technology

LTC6945

6945fa

For more information www.linear.com/LTC6945

Typical applicaTion

FeaTures DescripTion

Ultralow Noise and Spurious

0.35GHz to 6GHz Integer-N

Synthesizer

The LT C

6945 is a high performance, low noise, 6GHz phase-

locked loop (PLL), including a reference divider, phase-

frequency detector (PFD) with phase-lock indicator, charge

pump, integer feedback divider and VCO output divider.

The part features a buffered, programmable VCO output

divider with a range of 1 through 6. The differential, low

noise output buffer has user-programmable output power

ranging from –6dBm to 3dBm, and may be muted through

either a digital input pin or software.

The low noise reference buffer outputs a typical 0dBm

square wave directly into a 50Ω impedance from 10MHz

to 250MHz, or may be disabled through software.

The ultralow noise charge pump contains selectable high

and low voltage clamps useful for VCO monitoring, and

also may be set to provide a V+/2 bias.

All device settings are controlled through a SPI-compatible

serial port.

LTC6945 Data Converter Sample Clock

1GHz Sample Clock Phase Noise

applicaTions

n Low Noise Integer-N PLL

n 350MHz to 6GHz VCO Input Range

n –226dBc/Hz Normalized In-Band Phase Noise Floor

n –274dBc/Hz Normalized In-Band 1/f Noise

n –157dBc/Hz Wideband Output Phase Noise Floor

n Excellent Spurious Performance

n Output Divider (1 to 6, 50% Duty Cycle)

n Low Noise Reference Buffer

n Output Buffer Muting

n Charge Pump Supply from 3.15V to 5.25V

n Charge Pump Current from 250µA to 11.2mA

n Conﬁgurable Status Output

n SPI Compatible Serial Port Control

n PLLWizard™ Software Design Tool Support

n Wireless Base Stations (LTE, WiMAX, W-CDMA, PCS)

n Broadband Wireless Access

n Microwave Data Links

n Military and Secure Radio

n Test and Measurement

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

PLLWizard is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners.

OFFSET FREQUENCY (Hz)

–160

PHASE NOISE (dBc/Hz)

–150

–130

–110

–100

100 10k 100k 10M

40M

6945 TA01b

–170

1k 1M

–120

–140

–180

DSB INTEGRATION

(100Hz TO 1GHz)

RMS NOISE = 0.014°

RMS JITTER = 39fs

fPFD = 25MHz

BW = 2.3kHz

VVCO+

GND

VCO+

VCO–

VREFO+

REFO

STAT

SCLK

SDI

SDO

VD+

MUTE GND RF–

GND

LTC6945

fPFD = 25MHz

RF+VRF+BB

REF–REF+VREF+CP VCP+3.3V

3.3V

68nH

68nH SAMPLE CLOCK

1GHz, 7dBm

3.3V 5V

VTUNE

432Ω

570nF

47nF

100pF

16.5Ω

CRYSTEK

CVCSO-914-1000

LOOP

BANDWIDTH

~2.3kHz

0.01µF

100pF

6945 TA01b

0.1µF

SPI BUS

1µF

1.0µF

0.01µF

51.1Ω

100MHz

REF

1µF

100pF

GND

0.1µF

100pF

50Ω

ALT SAMPLE CLOCK

500MHz OR 1GHz

3.3V

LTC6945

6945fa

For more information www.linear.com/LTC6945

pin conFiguraTionabsoluTe MaxiMuM raTings

Supply Voltages

V+ (VREF+, VREFO+, VRF+, VVCO+, VD+) to GND ......3.6V

VCP+ to GND .........................................................5.5V

Voltage on CP Pin .................GND – 0.3V to VCP+ + 0.3V

Voltage on All Other Pins ..........GND – 0.3V to V+ + 0.3V

Operating Junction Temperature Range, TJ (Note 2)

LTC6945I ............................................... –40°C to 105°C

Junction Temperature, TJMAX ................................ 125°C

Storage Temperature Range .................. –65°C to 150°C

(Note 1)

9 10

TOP VIEW

GND

UFD PACKAGE

28-LEAD (4mm × 5mm) PLASTIC QFN

11 12 13

28 27 26 25 24

VREFO+

REFO

STAT

SCLK

SDI

SDO

VD+

VVCO+

GND

VCO+

VCO–

REF–

REF+

VREF+

VCP+

GND

MUTE

GND

RF–

RF+

VRF+

815

TJMAX = 125°C, θJCbottom = 3°C/W, θJCtop = 26°C/W

EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB

orDer inForMaTion

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION JUNCTION TEMPERATURE RANGE

LTC6945IUFD#PBF LTC6945IUFD#TRPBF 6945 28-Lead (4mm × 5mm) Plastic QFN –40°C to 105°C

Consult LT C Marketing for parts specified with wider operating temperature ranges.

Consult LT C Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Reference Inputs (REF+, REF–)

fREF Input Frequency l10 250 MHz

VREF Input Signal Level Single-Ended, 1µF AC-Coupling Capacitors l0.5 2 2.7 VP-P

Input Slew Rate l20 V/µs

Input Duty Cycle 50 %

Self-Bias Voltage l1.65 1.85 2.25 V

Input Resistance Differential l6.2 8.4 11.6 kΩ

Input Capacitance Differential 3 pF

Reference Output (REFO)

fREFO Output Frequency l10 250 MHz

PREFO Output Power fREFO = 10MHz, RLOAD = 50Ω l–0.2 3.2 dBm

Output Impedance, Disabled 800 Ω

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless

otherwise specified. All voltages are with respect to GND.

LTC6945

6945fa

For more information www.linear.com/LTC6945

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless

otherwise specified. All voltages are with respect to GND.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCO Input (VCO+, VCO–)

fVCO Input Frequency l350 6000 MHz

PVCOI Input Power Level RZ = 50Ω, Single-Ended l–8 0 6 dBm

Input Resistance Single-Ended, Each Input l97 121 145 Ω

RF Output (RF+, RF–)

fRF Output Frequency l350 6000 MHz

O Output Divider Range All Integers Included l1 6

Output Duty Cycle 50 %

Output Resistance Single-Ended, Each Output to VRF+l111 136 159 Ω

Output Common Mode Voltage l2.4 VRF+V

PRF(SE) Output Power, Single-Ended,

fRF = 900MHz

RFO[1:0] = 0, RZ = 50Ω, LC Match

RFO[1:0] = 1, RZ = 50Ω, LC Match

RFO[1:0] = 2, RZ = 50Ω, LC Match

RFO[1:0] = 3, RZ = 50Ω, LC Match

–9.7

–6.8

–3.9

–1.2

–6.0

–3.6

–0.4

2.3

dBm

Output Power, Muted RZ = 50Ω, Single-Ended, fRF = 900MHz, O = 2 to 6 l–60 dBm

Mute Enable Time l110 ns

Mute Disable Time l170 ns

Phase/Frequency Detector

fPFD Input Frequency l100 MHz

Lock Indicator, Available on the STAT Pin and via the SPI-Accessible Status Register

tLWW Lock Window Width LKWIN[1:0] = 0

LKWIN[1:0] = 1

LKWIN[1:0] = 2

LKWIN[1:0] = 3

3.0

10.0

30.0

90.0

tLWHYS Lock Window Hysteresis Increase in tLWW Moving from Locked State to

Unlocked State

22 %

Charge Pump

ICP Output Current Range 12 Settings (See Table 5) 0.25 11.2 mA

Output Current Source/Sink Accuracy VCP = VCP+/2, All Settings ±6 %

Output Current Source/Sink Matching ICP = 250µA to 1.4mA, VCP = VCP+/2

ICP = 2mA to 11.2mA, VCP = VCP+/2

±3.5

±2

Output Current vs Output Voltage

Sensitivity

(Note 3) l0.1 1.0 %/V

Output Current vs Temperature VCP = VCP+/2 l170 ppm/°C

Output Hi-Z Leakage Current ICP = 700µA, CPCLO = CPCHI = 0 (Note 3)

ICP = 11.2mA, CPCLO = CPCHI = 0 (Note 3)

0.5

VCLMP(LO) Low Clamp Voltage CPCLO = 1 0.84 V

VCLMP(HI) High Clamp Voltage CPCHI = 1, Referred to VCP+–0.96 V

VMID Mid-Supply Output Bias Ratio Referred to (VCP+ – GND) 0.48 V/V

Reference (R) Divider

R Divide Range All Integers Included l1 1023 Counts

LTC6945

6945fa

For more information www.linear.com/LTC6945

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless

otherwise specified. All voltages are with respect to GND.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCO (N) Divider

N Divide Range All Integers Included l32 65535 Counts

Digital Pin Specifications

VIH High Level Input Voltage MUTE, CS, SDI, SCLK l1.55 V

VIL Low Level Input Voltage MUTE, CS, SDI, SCLK l0.8 V

VIHYS Input Voltage Hysteresis MUTE, CS, SDI, SCLK 250 mV

Input Current MUTE, CS, SDI, SCLK l±1 µA

IOH High Level Output Current SDO and STAT, VOH = VD+ – 400mV l–2.3 –1.4 mA

IOL Low Level Output Current SDO and STAT, VOL = 400mV l1.8 3.4 mA

SDO Hi-Z Current l±1 µA

Digital Timing Specifications (See Figures 8 and 9)

tCKH SCLK High Time l25 ns

tCKL SCLK Low Time l25 ns

tCSS CS Setup Time l10 ns

tCSH CS High Time l10 ns

tCS SDI to SCLK Setup Time l6 ns

tCH SDI to SCLK Hold Time l6 ns

tDO SCLK to SDO Time To VIH/VIL/Hi-Z with 30pF Load l16 ns

Power Supply Voltages

VREF+ Supply Range l3.15 3.3 3.45 V

VREFO+ Supply Range l3.15 3.3 3.45 V

VD+ Supply Range l3.15 3.3 3.45 V

VRF+ Supply Range l3.15 3.3 3.45 V

VVCO+ Supply Range l3.15 3.3 3.45 V

VCP+ Supply Range l3.15 5.25 V

Power Supply Currents

IDD VD+ Supply Current Digital Inputs at Supply Levels l500 µA

ICC(CP) VCP+ Supply Current ICP = 11.2mA

ICP = 1.0mA

PDALL = 1

235

14.5

385

µA

ICC(REFO) VREFO+ Supply Currents REFO Enabled, RZ = ∞l7.8 9.0 mA

ICC Sum VREF+, VRF+, VVCO+ Supply

Currents

RF Muted, OD[2:0] = 1

RF Enabled, RFO[1:0] =0, OD[2:0] = 1

RF Enabled, RFO[1:0] = 3, OD[2:0] = 1

RF Enabled, RFO[1:0] =3, OD[2:0] = 2

RF Enabled, RFO[1:0] =3, OD[2:0] = 3

RF Enabled, RFO[1:0] =3, OD[2:0] = 4 to 6

PDALL = 1

105

111

116

202

117

124

128

396

µA

LTC6945

6945fa

For more information www.linear.com/LTC6945

elecTrical characTerisTics

The l denotes the specifications which apply over the full operating

junction temperature range, otherwise specifications are at TA = 25°C. VREF+ = VREF0+ = VD+ = VRF+ = VVCO+ = 3.3V, VCP+ = 5V unless

otherwise specified. All voltages are with respect to GND.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Phase Noise and Spurious

LM(MIN) Output Phase Noise Floor (Note 5) RFO[1:0] = 3, OD[2:0] = 1, fRF = 6GHz

RFO[1:0] = 3, OD[2:0] = 2, fRF = 3GHz

RFO[1:0] = 3, OD[2:0] = 3, fRF = 2GHz

RFO[1:0] = 3, OD[2:0] = 4, fRF = 1.5GHz

RFO[1:0] = 3, OD[2:0] = 5, fRF = 1.2GHz

RFO[1:0] = 3, OD[2:0] = 6, fRF = 1.0GHz

–155

–156

–157

–158

dBc/Hz

LM(NORM) Normalized In-Band Phase Noise Floor ICP = 11.2mA (Notes 6, 7, 8) –226 dBc/Hz

LM(NORM –1/f) Normalized In-Band 1/f Phase Noise ICP = 11.2mA (Notes 6, 9) –274 dBc/Hz

LM(IB) In-Band Phase Noise Floor (Notes 6, 7, 8, 10) –99 dBc/Hz

Integrated Phase Noise from 100Hz to

40MHz

(Notes 4, 7, 10) 0.13 °RMS

Spurious Reference Spur, PLL locked (Notes 4, 7, 10, 11) –102 dBc

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC6945I is guaranteed to meet specified performance limits

over the full operating junction temperature range of –40°C to 105°C.

Under maximum operating conditions, air flow or heat sinking may

be required to maintain a junction temperature of 105°C or lower. It is

strongly recommended that the exposed pad (Pin 29) be soldered directly

to the ground plane with an array of thermal vias as described in the

Applications Information section.

Note 3: For 0.9V ≤ VCP ≤ (VCP+ – 0.9V).

Note 4: VCO is Crystek CVCO55CL-0902-0928.

Note 5: fVCO = 6GHz, fOFFSET = 40MHz.

Note 6: Measured inside the loop bandwidth with the loop locked.

Note 7: Reference frequency supplied by Wenzel 501-04608A,

fREF = 10MHz, PREF = 13dBm.

Note 8: Output phase noise floor is calculated from normalized phase

noise floor by LM(OUT) = –226 + 10log10(fPFD) + 20log10(fRF/fPFD).

Note 9: Output 1/f phase noise is calculated from normalized 1/f phase

noise by LM(OUT –1/f) = –274 + 20log10 (fRF) – 10log10 (fOFFSET).

Note 10: ICP = 11.2mA, fPFD = 250kHz, fRF = 914MHz, FILT[1:0] = 3, Loop

BW = 7kHz.

Note 11: Measured using DC1649.

Typical perForMance characTerisTics

REF Input Sensitivity vs

Frequency REFO Output Power vs Frequency REFO Phase Noise

FREQUENCY (MHz)

SENSITIVITY (dBm)

–35

–30

–25

200 225

6945 G01

–40

–45

–55 50 100 150

250

75 125 175

–50

–15

–20

TJ = 105°C

TJ = 25°C

TJ = –40°C

BST = 1

FILT = 0

FREQUENCY (MHz)

POUT (dBm)

200 225

6945 G02

–1

–2

–4 50 100 150

25 250

75 125 175

–3

TJ = 105°C

TJ = 25°C

TJ = –40°C

OFFSET FREQUENCY (Hz)

–155

PHASE NOISE (dBc/Hz)

–150

–145

–140

100 10k 100k 1M 5M

6945 G03

–160

POUT = 1.45dBm

fREF = 10MHz

BST = 1

FILT = 3

NOTE 7

LTC6945

6945fa

For more information www.linear.com/LTC6945

Charge Pump Sink Current Error

vs Voltage, Output Current

Charge Pump Sink Current Error

vs Voltage, Temperature

Charge Pump Source Current

Error vs Voltage, Output Current

Typical perForMance characTerisTics

Charge Pump Source Current

Error vs Voltage, Temperature

RF Output Power vs Frequency

(Single-Ended On RF–)

RF Output HD2 vs Output Divide

(Single-Ended On RF–)

RF Output HD3 vs Output Divide

(Single-Ended On RF–)

MUTE Output Power

vs fVCO and Output Divide

(Single-Ended On RF–) Frequency Step Transient

OUTPUT VOLTAGE (V)

ERROR (%)

6945 G05

–1

–3

–2

–4

–5 10.5 21.5 3 3.5 4.5

2.5

TJ = 105°C

TJ = 25°C

TJ = –40°C

ICP = 11.2mA

OUTPUT VOLTAGE (V)

ERROR (%)

6945 G04

–1

–3

–2

–4

–5 10.5 21.5 3 3.5 4.5

2.5

250µA

1mA

11.2mA

OUTPUT VOLTAGE (V)

ERROR (%)

6945 G06

–1

–3

–2

–4

–5 10.5 21.5 3 3.5 4.5

2.5

250µA

1mA

11.2mA

OUTPUT VOLTAGE (V)

ERROR (%)

6945 G07

–1

–3

–2

–4

–5 10.5 21.5 3 3.5 4.5

2.5

TJ = 105°C

TJ = 25°C

TJ = –40°C

ICP = 11.2mA

FREQUENCY (GHz)

–3.5

OUT

(dBm)

–3.0

–2.0

–1.5

–1.0

3 3.5 4 54.5 5.5

1.0

6945 G08

–2.5

0.5 1 1.5 2 2.5 6

–0.5

0.5

TJ = 105°C

TJ = 25°C

TJ = –40°C

PVCO = 0dBm

LC = 180nH

CS = 270pF

TIME (µs)

1.85

FREQUENCY (GHz)

1.90

2.00

2.05

2.10

10 20 25 45

6945 G12

1.95

5 15 30 35 40

fPFD = 1MHz

BW = 40kHz

100MHz STEP

fVCO (GHz)

HD3 (dBc)

–15

–10

–5

6945 G10

–20

–25

–30 1235

0.5 4.5

1.5 2.5 3.5 5.5

fRF = fVCO/O

PVCO = 0dBm

LC = 180nH

CS = 270pF

O = 6

O = 3

O = 2

O = 1

fVCO (GHz)

–120

OUT

AT f

VCO

/O (dBm)

–110

–90

–80

–70

3 3.5 4 54.5 5.5

–30

6945 G11

–100

0.5 1 1.5 2 2.5 6

–60

–50

–40

fRF = fVCO/O

PVCO = 0dBm

LC = 180nH

CS = 270pF

O = 1

O = 2

O = 3

O = 4

O = 5

O = 6

fVCO (GHz)

–55

HD2 (dBc)

–50

–40

–35

–30

3 3.5 4 54.5 5.5

–20

6945 G09

–45

0.5 1 1.5 2 2.5 6

–25

fRF = fVCO/O

PVCO = 0dBm

LC = 180nH

CS = 270pF

O = 3

O = 5

O = 1

O = 6

O = 2

O = 4

LTC6945

6945fa

For more information www.linear.com/LTC6945

Typical perForMance characTerisTics

Spurious Response

fRF = 914MHz, fREF = 10MHz,

fPFD = 250kHz, Loop BW = 7kHz

Spurious Response

fRF = 2100MHz, fREF = 10MHz,

fPFD = 1MHz, Loop BW = 40kHz

VCO Input Sensitivity

vs Frequency, Temperature

Closed-Loop Phase Noise,

fRF = 914MHz

Closed-Loop Phase Noise,

fRF = 2100MHz

FREQUENCY (GHz)

SENSITIVITY (dBm)

–15

–10

6945 G13

–20

–25

–30

–35

1235

0.5 4.5

1.5 2.5 3.5 5.5

TJ = 105°C

TJ = 25°C

TJ = –40°C

Spurious Response

fRF = 5725MHz, fREF = 10MHz,

fPFD = 5MHz, Loop BW = 21kHz Supply Current vs Temperature

FREQUENCY OFFSET (MHz, IN 10kHz SEGMENTS)

–10 –3 –2 –1 0 21 3 10

–140

POUT (dBm)

–120

–80

–60

–113dBc –112dBc

–102dBc –102dBc

–40

6945 G17

–100

–20

RBW = 1Hz

VBW = 1Hz

NOTES 7, 11

FREQUENCY OFFSET (MHz, IN 10kHz SEGMENTS)

–20 –15 –10 –5 0 105 15 20

–140

POUT (dBm)

–120

–80

–60

–112dBc –112dBc

–100dBc –101dBc

–40

6945 G18

–100

–20

RBW = 1Hz

VBW = 1Hz

NOTES 7, 11

FREQUENCY OFFSET (MHz, IN 10kHz SEGMENTS)

–10 –0.75 –0.5 –0.25 0 0.50.25 0.75 10

–140

POUT (dBm)

–120

–80

–60

–113dBc –111dBc

–102dBc –102dBc

–40

6945 G16

–100

–20

RBW = 1Hz

VBW = 1Hz

NOTES 7, 10, 11

TEMPERATURE, TJ (°C)

–40

3.3V CURRENT (mA)

5V CURRENT (mA)

40 60 100

6945 G19

80 –20 0 20 80

33.0

33.5

34.0

32.5

32.0

31.5

34.5

35.0

35.5

PDREFO = 1

O = 1

RFO = 3

MUTE = 0

ICP = 11.2mA

OFFSET FREQUENCY (Hz)

–150

PHASE, NOISE (dBc/Hz)

–140

–120

–100

–90

100 10k 100k

6945 G14

–160

1k 1M 10M 40M

–110

–130

–170

RMS NOISE = 0.13°

fPFD = 250kHz

BW = 7kHz

NOTES 7, 10

VCO = CRYSTEK

CVCO55CL-0902-0928

OFFSET FREQUENCY (Hz)

–150

PHASE, NOISE (dBc/Hz)

–140

–120

–100

–90

100 10k 100k

6945 G15

–160

1k 1M 10M 40M

–110

–130

–170

RMS NOISE = 0.33°

fPFD = 1MHz

BW = 40kHz

NOTE 7

VCO = RFMD

UMX-586-D16-G

LTC6945

6945fa

For more information www.linear.com/LTC6945

VREFO+ (Pin 1): 3.15V to 3.45V Positive Supply Pin for

REFO Circuitry. This pin should be bypassed directly to

the ground plane using a 0.1µF ceramic capacitor as close

to the pin as possible.

REFO (Pin 2): Reference Frequency Output. This produces

a low noise square wave, buffered from the REF± differential

inputs. The output is self-biased and must be AC-coupled

with a 22nF capacitor.

STAT (Pin 3): Status Output. This signal is a configurable

logical OR combination of the UNLOCK, LOCK, THI and

TLO status bits, programmable via the STATUS register.

See the Operations section for more details.

CS (Pin 4): Serial Port Chip Select. This CMOS input initi-

ates a serial port communication burst when driven low,

ending the burst when driven back high. See the Operations

section for more details.

SCLK (Pin 5): Serial Port Clock. This CMOS input clocks

serial port input data on its rising edge. See the Operations

section for more details.

SDI (Pin 6): Serial Port Data Input. The serial port uses

this CMOS input for data. See the Operations section for

more details.

SDO (Pin 7): Serial Port Data Output. This CMOS three-

state output presents data from the serial port during a

read communication burst. Optionally attach a resistor

of >200k to GND to prevent a floating output. See the

Operations section for more details.

VD+ (Pin 8): 3.15V to 3.45V Positive Supply Pin for Serial

Port Circuitry. This pin should be bypassed directly to the

ground plane using a 0.1µF ceramic capacitor as close to

the pin as possible.

MUTE (Pin 9): RF Mute. The CMOS active-low input mutes

the RF± differential outputs while maintaining internal bias

levels for quick response to de-assertion.

GND (Pins 10, 17, 18, 19, 20, 21): Negative Power Supply

(Ground). These pins should be tied directly to the ground

plane with multiple vias for each pin.

RF–, RF+ (Pins 11, 12): RF Output Signals. The VCO

output divider is buffered and presented differentially on

these pins. The outputs are open collector, with 136Ω

(typical) pull-up resistors tied to VRF+ to aid impedance

matching. If used single-ended, the unused output should

be terminated to 50Ω. See the Applications Information

section for more details on impedance matching.

VRF+ (Pin 13): 3.15V to 3.45V Positive Supply Pin for

RF Circuitry. This pin should be bypassed directly to the

ground plane using a 0.01µF ceramic capacitor as close

to the pin as possible.

BB (Pin 14): RF Reference Bypass. This output must be

bypassed with a 1.0µF ceramic capacitor to GND. Do not

couple this pin to any other signal.

VCO–, VCO+ (Pins 15, 16): VCO Input Signals. The dif-

ferential signal placed on these pins is buffered with a low

noise amplifier and fed to the internal output and feedback

dividers. These self-biased inputs must be AC-coupled

and present a single-ended 121Ω (typical) resistance

to aid impedance matching. They may be used single-

ended by bypassing VCO– to GND with a capacitor. See

the Applications Information section for more details on

impedance matching.

VVCO+ (Pin 22): 3.15V to 3.45V Positive Supply Pin for

VCO Circuitry. This pin should be bypassed directly to the

ground plane using a 0.01µF ceramic capacitor as close

to the pin as possible.

GND (23): Negative Power Supply (Ground). This pin is

attached directly to the die attach paddle (DAP) and should

be tied directly to the ground plane.

VCP+ (Pin 24): 3.15V to 5.25V Positive Supply Pin for Charge

Pump Circuitry. This pin should be bypassed directly to

the ground plane using a 0.1µF ceramic capacitor as close

to the pin as possible.

CP (Pin 25): Charge Pump Output. This bi-directional cur-

rent output is normally connected to the external loop filter.

See the Applications Information section for more details.

pin FuncTions

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VREF+ (Pin 26): 3.15V to 3.45V Positive Supply Pin for

Reference Input Circuitry. This pin should be bypassed

directly to the ground plane using a 0.1µF ceramic capaci-

tor as close to the pin as possible.

REF+, REF– (Pins 27, 28): Reference Input Signals. This

differential input is buffered with a low noise amplifier,

which feeds the reference divider and reference buffer.

They are self-biased and must be AC-coupled with 1µF

capacitors. If used single-ended, bypass REF– to GND

with a 1µF capacitor. If the single-ended signal is greater

than 2.7VP-P, bypass REF– to GND with a 47pF capacitor.

GND (Exposed Pad Pin 29): Negative Power Supply

(Ground). The package exposed pad must be soldered

directly to the PCB land. The PCB land pattern should

have multiple thermal vias to the ground plane for both

low ground inductance and also low thermal resistance.

pin FuncTions

block DiagraM

RF–

GND

MUTE

RF+

VRF+

REF–

REFO

≤250MHz

≤100MHz

÷1 TO 1023

÷1 TO 6, 50%

÷32 TO 65535

350MHz

TO 6GHz

MUTE

1VREFO+

REF+

VREF+

R_DIV

LOCK

PFD

O_DIV

N_DIV

VVCO+

GND

VCO+

VCO–

250µA TO

11.2mA 25

VCP+

GND

6945 BD

350MHz TO 6GHz

SERIAL

PORT

STAT

7SDO

SDI

SCLK

8VD+

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Figure 1. Simplified REF Interface Schematic

Figure 2. Simplified REFO Interface Schematic

The LTC6945 is a high performance PLL, and, combined

with an external high performance VCO, can produce low

noise LO signals up to 6GHz. It is able to achieve superior

integrated phase noise performance due to its extremely

low in-band phase noise performance.

REFERENCE INPUT BUFFER

The PLL’s reference frequency is applied differentially on

pins REF+ and REF–. These high impedance inputs are

self-biased and must be AC-coupled with 1µF capacitors

(see Figure 1 for a simplified schematic). Alternatively, the

inputs may be used single-ended by applying the refer-

ence frequency at REF+ and bypassing REF– to GND with

a 1µF capacitor. If the single-ended signal is greater than

2.7VP-P, then use a 47pF capacitor for the GND bypass.

Table 1. FILT[1:0] Programming

FILT[1:0] fREF

3 <20MHz

2 NA

1 20MHz to 50MHz

0 >50MHz

Table 2. BST Programming

BST VREF

1 <2.0VP-P

0 ≥2.0VP-P

REFERENCE OUTPUT BUFFER

The reference output buffer produces a low noise square

wave with a noise floor of –155dBc/Hz (typical) at 10MHz.

Its output is low impedance, and produces 2dBm typical

output power into a 50Ω load at 10MHz. Larger output

swings will result if driving larger impedances. The out-

put is self-biased, and must be AC-coupled with a 22nF

capacitor (see Figure 2 for a simplified schematic). The

buffer may be powered down by using bit PDREFO found

in the serial port Power register h02.

4.2k

REF+

REF–

BST

FILT[1:0]

LOWPASS

4.2k

6945 F01

1.9V

BIAS VREF+VREF+

A high quality signal must be applied to the REF± inputs

as they provide the frequency reference to the entire PLL.

To achieve the part’s in-band phase noise performance,

apply a CW signal of at least 6dBm into 50Ω, or a square

wave of at least 0.5VP-P with slew rate of at least 40V/µs.

Additional options are available through serial port register

h08 to further refine the application. Bits FILT[1:0] control

the reference input buffer’s lowpass filter, and should be

set based upon fREF to limit the reference’s wideband

noise. The FILT[1:0] bits must be set correctly to reach

the LM(NORM) normalized in-band phase noise floor. See

Table 1 for recommended settings.

The BST bit should be set based upon the input signal level

to prevent the reference input buffer from saturating. See

Table 2 for recommended settings and the Applications

Information section for programming examples.

REFO

VREFO+

800Ω

6945 F02

REFERENCE (R) DIVIDER

A 10-bit divider, R_DIV, is used to reduce the frequency

seen at the PFD. Its divide ratio R may be set to any

integer from 1 to 1023, inclusive. Use the RD[9:0] bits

found in registers h03 and h04 to directly program the R

divide ratio. See the Applications Information section for

the relationship between R and the fREF

, fPFD, fVCO and

fRF frequencies.

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Figure 3. Simplified PFD Schematic

Figure 4. UNLOCK and LOCK Timing

PHASE/FREQUENCY DETECTOR (PFD)

The phase/frequency detector (PFD), in conjunction with

the charge pump, produces source and sink current pulses

proportional to the phase difference between the outputs

of the R and N dividers. This action provides the necessary

feedback to phase-lock the loop, forcing a phase align-

ment at the PFD’s inputs. The PFD may be disabled with

the CPRST bit which prevents UP and DOWN pulses from

being produced. See Figure 3 for a simplified schematic

of the PFD.

The user sets the phase difference lock window time,

tLWW

, for a valid LOCK condition with the LKWIN[1:0]

bits. See Table 3 for recommended settings for different

fPFD frequencies and the Applications Information section

for examples.

Table 3. LKWIN[1:0] Programming

LKWIN[1:0] tLWW fPFD

0 3ns >5MHz

1 10ns ≤5MHz

2 30ns ≤1.7MHz

3 90ns ≤550kHz

The PFD phase difference must be less than tLWW for the

COUNTS number of successive counts before the lock

indicator asserts the LOCK flag. The LKCT[1:0] bits found

in register h09 are used to set COUNTS depending upon

the application. See Table 4 for LKCT[1:0] programming

and the Applications Information section for examples.

Table 4. LKCT[1:0] Programming

LKCT[1:0] COUNTS

0 32

1 128

2 512

3 2048

When the PFD phase difference is greater than tLWW

, the

lock indicator immediately asserts the UNLOCK status

flag and clears the LOCK flag, indicating an out-of-lock

condition. The UNLOCK flag is immediately de-asserted

when the phase difference is less than tLWW

. See Figure 4

for more details.

D Q

RST

N DIV

D Q

RST

CPRST

DOWN

6945 F03

DELAY

R DIV

LOCK INDICATOR

The lock indicator uses internal signals from the PFD to

measure phase coincidence between the R and N divider

output signals. It is enabled by setting the LKEN bit in

the serial port register h07, and produces both LOCK and

UNLOCK status flags, available through both the STAT

output and serial port register h00.

+tLWW

–tLWW

UNLOCK FLAG

LOCK FLAG t = COUNTS/fPFD

6945 F04

PHASE

DIFFERENCE

AT PFD

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Figure 5. Simplified Charge Pump Schematic

CHARGE PUMP

The charge pump, controlled by the PFD, forces sink

(DOWN) or source (UP) current pulses onto the CP pin,

which should be connected to an appropriate loop filter.

See Figure 5 for a simplified schematic of the charge pump.

as for loops using negative-slope tuning oscillators, or

inverting op amps in conjunction with positive-slope tuning

oscillators. A passive loop filter as shown in Figure 15,

used in conjunction with a positive-slope VCO, requires

CPINV = 0.

CHARGE PUMP FUNCTIONS

The charge pump contains additional features to aid

in system start-up and monitoring. See Table 6 for a

summary.

Table 6. CP Function Bit Descriptions

BIT DESCRIPTION

CPCHI Enable High Voltage Output Clamp

CPCLO Enable Low Voltage Output Clamp

CPDN Force Sink Current

CPINV Invert PFD Phase

CPMID Enable Mid-Voltage Bias

CPRST Reset PFD

CPUP Force Source Current

CPWIDE Extend Current Pulse Width

THI High Voltage Clamp Flag

TLO Low Voltage Clamp Flag

The CPCHI and CPCLO bits found in register h0A enable

the high and low voltage clamps, respectively. When

CPCHI is enabled and the CP pin voltage exceeds ap-

proximately VCP+ – 0.9V, the THI status flag is set, and

the charge pump sourcing current is disabled. Alternately,

when CPCLO is enabled and the CP pin voltage is less

than approximately 0.9V, the TLO status flag is set, and

the charge pump sinking current is disabled. See Figure

5 for a simplified schematic.

The CPMID bit also found in register h0A enables a

resistive VCP+/2 output bias which may be used to pre-

bias troublesome loop filters into a valid voltage range

before attempting to lock the loop. When using CPMID,

it is recommended to also assert the CPRST bit, forcing

a PFD reset. Both CPMID and CPRST must be set to “0”

for normal operation.

The CPUP and CPDN bits force a constant ICP source or

sink current, respectively, on the CP pin. The CPRST bit

may also be used in conjunction with the CPUP and CPDN

–

THI

0.9V

VCP+

TLO

–

0.9V

6945 F05

–

VCP+/2

CPMID

CPUP

CPDN

DOWN

The output current magnitude ICP may be set from 250µA to

11.2mA using the CP[3:0] bits found in serial port register

h09. A larger ICP can result in lower in-band noise due to

the lower impedance of the loop filter components. See

Table 5 for programming specifics and the Applications

Information section for loop filter examples.

Table 5. CP[3:0] Programming

CP[3:0] ICP

0 250µA

1 350µA

2 500µA

3 700µA

4 1.0mA

5 1.4mA

6 2.0mA

7 2.8mA

8 4.0mA

9 5.6mA

10 8.0mA

11 11.2mA

12 to 15 Invalid

The CPINV bit found in register h0A should be set for ap-

plications requiring signal inversion from the PFD, such

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Figure 7. Simplified RF Interface Schematic

bits, allowing a pre-charge of the loop to a known state,

if required. CPUP, CPDN, and CPRST must be set to “0”

to allow the loop to lock.

The CPWIDE bit extends the charge pump output current

pulse width by increasing the PFD reset path’s delay value

(see Figure 3). CPWIDE is normally set to 0.

VCO INPUT BUFFER

The VCO frequency is applied differentially on pins VCO+ and

VCO–. The inputs are self-biased and must be AC-coupled.

Alternatively, the inputs may be used single-ended by ap-

plying the VCO frequency at VCO+ and bypassing VCO– to

GND with a capacitor. Each input provides a single-ended

OUTPUT (O) DIVIDER

The 3-bit O divider can reduce the frequency from the VCO

input buffer to the RF output buffer to extend the output

frequency range. Its divide ratio O may be set to any in-

teger from 1 to 6, inclusive, outputting a 50% duty cycle

even with odd divide values. Use the OD[2:0] bits found

in register h08 to directly program the 0 divide ratio. See

the Applications Information section for the relationship

between O and the fREF

, fPFD, fVCO and fRF frequencies.

RF OUTPUT BUFFER

The low noise, differential output buffer produces a dif-

ferential output power of –6dBm to 3dBm, settable with

bits RFO[1:0] according to Table 7. The outputs may be

combined externally, or used individually. Terminate any

unused output with a 50Ω resistor to VRF+.

Table 7. RFO[1:0] Programming

RFO[1:0} PRF (Differential) PRF (Single-Ended)

0 –6dBm –9dBm

1 –3dBm –6dBm

2 0dBm –3dBm

3 3dBm 0dBm

Each output is open collector with 136Ω pull-up resistors

to VRF+, easing impedance matching at high frequencies.

See Figure 7 for circuit details and the Applications Infor-

mation section for matching guidelines. The buffer may be

muted with either the OMUTE bit, found in register h02,

or by forcing the MUTE input low.

121Ω

VCO+

VC0–

121Ω

6945 F06

0.9V VVCO+

VVCO+

–

Figure 6. Simplified VCO Interface Schematic

121Ω resistance to aid in impedance matching at high

frequencies. See the Applications Information section for

matching guidelines.

VCO (N) DIVIDER

The 16-bit N divider provides the feedback from the VCO

input buffer to the PFD. Its divide ratio N may be set to any

integer from 32 to 65535, inclusive. Use the ND[15:0] bits

found in registers h05 and h06 to directly program the N

divide ratio. See the Applications Information section for

the relationship between N and the fREF

, fPFD, fVCO and

fRF frequencies.

6945 F07

VRF

RF+

136Ω136Ω

RF–

MUTE

OMUTE

RFO[1:0]

9MUTE

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SERIAL PORT

The SPI-compatible serial port provides control and moni-

toring functionality. A configurable status output, STAT,

gives additional instant monitoring.

Communication Sequence

The serial bus is comprised of CS, SCLK, SDI and SDO.

Data transfers to the part are accomplished by the se-

rial bus master device first taking CS low to enable the

LTC6945’s port. Input data applied on SDI is clocked on

the rising edge of SCLK, with all transfers MSB first. The

communication burst is terminated by the serial bus master

returning CS high. See Figure 8 for details.

Data is read from the part during a communication burst

using SDO. Readback may be multidrop (more than one

LTC6945 connected in parallel on the serial bus), as SDO

is three-stated (Hi-Z) when CS = 1, or when data is not

being read from the part. If the LTC6945 is not used in

a multidrop configuration, or if the serial port master is

not capable of setting the SDO line level between read

sequences, it is recommended to attach a high value

resistor of greater than 200k between SDO and GND to

ensure the line returns to a known level during Hi-Z states.

See Figure 9 for details.

Single Byte Transfers

The serial port is arranged as a simple memory map, with

status and control available in 12, byte-wide registers. All

data bursts are comprised of at least two bytes. The 7 most

significant bits of the first byte are the register address,

with an LSB of 1 indicating a read from the part, and LSB

of 0 indicating a write to the part. The subsequent byte,

or bytes, is data from/to the specified register address.

See Figure 10 for an example of a detailed write sequence,

and Figure 11 for a read sequence.

Figure 12 shows an example of two write communication

bursts. The first byte of the first burst sent from the serial

bus master on SDI contains the destination register address

(Addr0) and an LSB of “0” indicating a write. The next byte

is the data intended for the register at address Addr0. CS is

then taken high to terminate the transfer. The first byte of

the second burst contains the destination register address

(Addr1) and an LSB indicating a write. The next byte on

SDI is the data intended for the register at address Addr1.

CS is then taken high to terminate the transfer.

Figure 8. Serial Port Write Timing Diagram

Figure 9. Serial Port Read Timing Diagram

MASTER–CS

MASTER–SCLK

tCSS

tCS tCH

DATA DATA

6945 F07

tCKL tCKH

tCSS

tCSH

MASTER–SDI

MASTER–CS

MASTER–SCLK

LTC6945–SDO Hi-Z Hi-Z

6945 F09

8TH CLOCK

DATA DATA

tDO

tDO tDO

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Figure 10. Serial Port Write Sequence

Figure 11. Serial Port Read Sequence

Figure 12. Serial Port Single Byte Write

Multiple Byte Transfers

More efficient data transfer of multiple bytes is accom-

plished by using the LTC6945’s register address auto-

increment feature as shown in Figure 13. The serial port

master sends the destination register address in the first

byte and its data in the second byte as before, but continues

sending bytes destined for subsequent registers. Byte 1’s

address is Addr0+1, Byte 2’s address is Addr0+2, and so

on. If the resister address pointer attempts to increment

past 11 (h0B), it is automatically reset to 0.

An example of an auto-increment read from the part is

shown in Figure 14. The first byte of the burst sent from

the serial bus master on SDI contains the destination

read. Once the LTC6945 detects a read burst, it takes SDO

out of the Hi-Z condition and sends data bytes sequentially,

beginning with data from register Addr0. The part ignores

all other data on SDI until the end of the burst.

Multidrop Configuration

Several LTC6945s may share the serial bus. In this

multidrop configuration, SCLK, SDI and SDO are com-

mon between all parts. The serial bus master must use a

separate CS for each LTC6945 and ensure that only one

device has CS asserted at any time. It is recommended

to attach a high value resistor to SDO to ensure the line

returns to a known level during Hi-Z states.

A6 A5 A4 A3 A2

7-BIT REGISTER ADDRESS

Hi-Z

MASTER–CS

MASTER–SCLK

MASTER–SDI

LTC6945–SD0

A1 A0 0D7 D6 D5 D4 D3 D2 D1 D0

8 BITS OF DATA

0 = WRITE

6945 F10

16 CLOCKS

A6 A5 A4 A3 A2

7-BIT REGISTER ADDRESS

Hi-Z Hi-Z

A1 A0 1

D7X D6 D5 D4 D3 D2 D1 D0 DX

8 BITS OF DATA

1 = READ

6945 F11

MASTER–CS

MASTER–SCLK

MASTER–SDI

LTC6945–SDO

16 CLOCKS

Addr0 + Wr

Hi-Z

MASTER–CS

MASTER–SDI

LTC6945–SDO

Byte 0 Addr1 + Wr Byte 1

6945 F12

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Figure 13. Serial Port Auto-Increment Write

Figure 14. Serial Port Auto-Increment Read

Addr0 + Wr

Hi-Z

MASTER–CS

MASTER–SDI

LTC6945–SDO

Byte 0 Byte 1 Byte 2

6945 F12

Addr0 + Rd DON’T CARE

Hi-Z Hi-Z

MASTER–CS

MASTER–SDI

LTC6945–SDO

6945 F13

Byte 0 Byte 1 Byte 2

Serial Port Registers

The memory map of the LTC6945 may be found in Table 8,

with detailed bit descriptions found in Table 9. The register

address shown in hexadecimal format under the ADDR

column is used to specify each register. Each register is

denoted as either read-only (R) or read-write (R/W). The

is shown at the right.

The read-only register at address h00 is used to determine

different status flags. These flags may be instantly output

on the STAT pin by configuring register h01. See the STAT

Output section for more information.

The read-only register at address h0B is a ROM byte for

device identification.

STAT Output

The STAT output pin is configured with the x[5:0] bits

of register h01. These bits are used to bit-wise mask, or

enable, the corresponding status flags of status register

h00, according to Equation 1. The result of this bit-wise

Boolean operation is then output on the STAT pin:

STAT = OR (Reg00[5,2:0] AND Reg01[5,2:0]) (1)

or expanded:

STAT = (UNLOCK AND x[5]) OR

(LOCK AND x[2]) OR

(THI AND x[1]) OR

(TLO AND x[0])

For example, if the application requires STAT to go high

whenever the LOCK or THI flags are set, then x[2] and

x[1] should be set to “1”, giving a register value of h6.

Block Power-Down Control

The LTC6945’s power-down control bits are located in

device may be powered down independently. Care must

be taken with the LSB of the register, the POR (power-on

reset) bit. When written to a “1”, this bit forces a full reset

of the part’s digital circuitry to its power-up default state.

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Table 9. Serial Port Register Bit Field Summary

Table 8. Serial Port Register Contents

ADDR MSB [6] [5] [4] [3] [2] [1] LSB R/W DEFAULT

h00 * * UNLOCK * * LOCK THI TLO R

h01 * * x[5] * * x[2] x[1] x[0] R/W h04

h02 PDALL PDPLL * PDOUT PDREFO * OMUTE POR R/W h0E

h03 * * * * * * RD[9] RD[8] R/W h00

h04 RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] R/W h01

h05 ND[15] ND[14] ND[13] ND[12] ND[11] ND[10] ND[9] ND[8] R/W h00

h06 ND[7] ND[6] ND[5] ND[4] ND[3] ND[2] ND[1] ND[0] R/W hFA

h07 * * * * * * * LKEN R/W h01

h08 BST FILT[1] FILT[0] RFO[1] RFO[0] OD[2] OD[1] OD[0] R/W hF9

h09 LKWIN[1] LKWIN[0] LKCT[1] LKCT[0] CP[3] CP[2] CP[1] CP[0] R/W h9B

h0A CPCHI CPCLO CPMID CPINV CPWIDE CPRST CPUP CPDN R/W hE4

h0B REV[2] REV[1] REV[0] PART[4] PART[3] PART[2] PART[1] PART[0] R h40

*unused

BITS

DESCRIPTION DEFAULT

BST

REF Buffer Boost Current 1

CP[3:0]

CP Output Current hB

CPCHI

CP Enable Hi Voltage Output Clamp 1

CPCLO

CP Enable Low Voltage Output Clamp 1

CPDN

CP Pump Down Only 0

CPINV

CP Invert Phase 0

CPMID

CP Bias to Mid-Rail 1

CPRST

CP Three-State 1

CPUP

CP Pump Up Only 0

CPWIDE

CP Extend Pulse Width 0

FILT[1:0]

REF Input Buffer Filter h3

LKCT[1:0]

PLL Lock Cycle Count h1

LKEN

PLL Lock Indicator Enable 1

LKWIN[1:0]

PLL Lock Indicator Window h2

LOCK

PLL Lock Indicator Flag

ND[15:0]

N Divider Value (ND[15:0] > 31) h00FA

BITS

DESCRIPTION DEFAULT

OD[2:0]

Output Divider Value (0 < OD[2:0] < 7) h1

OMUTE

Mutes RF Output 1

PART[4:0]

Part Code h00

PDALL

Full Chip Power-Down 0

PDOUT

Powers Down O_DIV, RF Output Buffer 0

PDPLL

Powers Down REF, REFO, R_DIV, PFD,

CPUMP, N_DIV

PDREFO

Powers Down REFO 1

POR

Force Power-On Reset Register Initialization 0

RD[9:0]

R Divider Value (RD[9:0] > 0) h001

REV[2:0]

Rev Code

RFO[1:0]

RF Output Power h3

THI

CP Clamp High Flag

TLO

CP Clamp Low Flag

UNLOCK

PLL Unlock Flag

x[5,2:0]

STAT Output OR Mask h04

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INTRODUCTION

A PLL is a complex feedback system that may conceptually

be considered a frequency multiplier. The system multiplies

the frequency input at REF± and outputs a higher frequency

at RF±. The PFD, charge pump, N divider, and external

VCO and loop filter form a feedback loop to accurately

control the output frequency (see Figure 15). The R and

O dividers are used to set the output frequency resolution.

Using the above equations, the output frequency resolution

fSTEP produced by a unit change in N is given by Equation 5:

fSTEP =

REF

R•O

(5)

LOOP FILTER DESIGN

A stable PLL system requires care in selecting the external

loop filter values. The Linear Technology PLLWizard ap-

plication, available from www.linear.com, aids in design

and simulation of the complete system.

The loop design should use the following algorithm:

1. Determine the output frequency, fRF

, and frequency

step size, fSTEP

, based on application constraints. Using

Equations 2, 3, 4 and 5, change fREF

, N, R and O until

the application frequency constraints are met. Use the

minimum R value that still satisfies the constraints.

2. Select the loop bandwidth BW constrained by fPFD. A

stable loop requires that BW is less than fPFD by at least

a factor of 10.

3. Select loop filter component RZ and charge pump cur-

rent ICP based on BW and the VCO gain factor KVCO.

BW (in Hz) is approximated by the following equation:

BW ≅

•R

•K

VCO

2•π•N

or :

RZ=2•π•BW •N

•K

VCO

(6)

where KVCO is in Hz/V, ICP is in Amps, and RZ is in

Ohms. KVCO is the VCO’s frequency tuning sensitivity,

and may be determined from the VCO specifications. Use

ICP = 11.2mA to lower in-band noise unless component

values force a lower setting.

Figure 15. PLL Loop Diagram

R_DIV

N_DIV

÷R

÷N

÷O

fPFD

LTC6945

REF±

(fREF)

(fVCO)

KPFD

KVCO

RF±

(fRF)

LOOP FILTER

LF(s)

6945 F15

VCO±

ICP

O_DIV

OUTPUT FREQUENCY

When the loop is locked, the frequency fVCO (in Hz)

produced at the output of the VCO is determined by the

reference frequency fREF

, and the R and N divider values,

given by Equation 2:

fVCO =

REF

•N

(2)

Here, the PFD frequency fPFD produced is given by the

following equation:

fPFD =

REF

(3)

and fVCO may be alternatively expressed as:

fVCO = fPFD • N

The output frequency fRF produced at the output of the O

divider is given by Equation 4:

fRF =

VCO

(4)

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4. Select loop filter components CI and CP based on BW

and RZ

. A reliable loop can be achieved by using the

following equations for the loop capacitors (in Farads):

CI=

3.5

2•π•BW •RZ

(7)

CP=

7•π•BW •R

(8)

LOOP FILTERS USING AN OPAMP

Some VCO tune voltage ranges are greater than the

LTC6945’s charge pump voltage range. An active loop filter

using an op amp can increase the tuning voltage range.

To maintain the LTC6945’s high performance, care must

be given to picking an appropriate op amp.

The op amp input common mode voltage should be biased

within the LTC6945 charge pump’s voltage range, while

its output voltage should achieve the VCO tuning range.

See Figure 16 for an example op amp loop filter.

The op amp’s input bias current is supplied by the charge

pump; minimizing this current keeps spurs related to fPFD

low. The input bias current should be less than the charge

pump leakage (found in the Electrical Characteristics sec-

tion) to avoid increasing spurious products.

Op amp noise sources are highpass filtered by the PLL

loop filter and should be kept at a minimum, as their ef-

fect raises the total system phase noise beginning near

the loop bandwidth. Choose a low noise op amp whose

input-referred voltage noise is less than the thermal noise

of RZ. Additionally, the gain bandwidth of the op amp

should be at least 15 times the loop bandwidth to limit

phase margin degradation. The LT1678 is an op amp that

works very well in most applications.

An additional R-C lowpass filter (formed by RP2 and CP2

in Figure 16) connected at the input of the VCO will limit

the op amp noise sources. The bandwidth of this filter

should be placed approximately 15 to 20 times the PLL

loop bandwidth to limit loop phase margin degradation.

RP2 should be small (preferably much less than RZ) to

minimize its noise impact on the loop. However, picking

too small of a value can make the op amp unstable as it

has to drive the capacitor in this filter.

DESIGN AND PROGRAMMING EXAMPLE

This programming example uses the DC1649. Assume

the following parameters of interest :

fREF = 100MHz at 7dBm into 50Ω

fSTEP = 250kHz

fVCO = 902MHz to 928MHz

KVCO = 15MHz/V to 21.6MHz/V

fRF = 914MHz

Determining Divider Values

Following the Loop Filter Design algorithm, first determine

all the divider values. Using Equations 2, 3, 4 and 5, cal-

culate the following values:

O = 1

R = 100MHz/250kHz = 400

fPFD = 250kHz

N = 914MHz/250kHz = 3656

Figure 16. Op Amp Loop Filter

LOOP FILTER

LF(s)

CP2

KVCO

6945 F16

47µF

ICP

VCO±

(fVCO)

VCP+/2

VCP+

LTC6945

RP2

–

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The next step in the algorithm is to determine the open-

loop bandwidth. BW should be at least 10× smaller than

fPFD. Wider loop bandwidths could have lower integrated

phase noise, depending on the VCO phase noise signature,

while narrower bandwidths will likely have lower spurious

power. Use a factor of 25 for this design:

BW =

250kHz

=10kH

Loop Filter Component Selection

Now set loop filter resistor RZ and charge pump current

ICP

. Because the KVCO varies over the VCO’s frequency

range, using the KVCO geometric mean gives good results.

Using an ICP of 11.2mA, RZ is determined:

KVCO =106•15 •21.6 =18MHz /

RZ=2•π•10k •3656

11.2m •18M

=1.14k

Now calculate CI and CP from Equations 7 and 8:

CI=

3.5

2•π•10k •1.14k =48.9nF

CP=1

7•π•10k •1.14k

=3.99n

Status Output Programming

This example will use the STAT pin to monitor a phase

lock condition. Program x[2] = 1 to force the STAT pin

high whenever the LOCK bit asserts:

Reg01 = h04

Power Register Programming

For correct PLL operation all internal blocks should be

enabled, but PDREFO should be set if the REFO pin is

not being used. OMUTE may remain asserted (or the

MUTE pin held low) until programming is complete. For

PDREFO = 1 and OMUTE = 1:

Reg02 = h0A

Divider Programming

Program registers Reg03 to Reg06 with the previously

determined R and N divider values:

Reg03 = h01

Reg04 = h90

Reg05 = h0E

Reg06 = h48

Reference Input Settings and Output Divider

Programming

From Table 1, FILT = 0 for a 100MHz reference frequency.

Next, convert 7dBm into VP-P

. For a CW tone, use the

following equation with R = 50:

P-P

≅R•10

(dBm –21)/20

(9)

This gives VP-P = 1.41V, and, according to Table 2, set

BST = 1.

Now program Reg08, assuming maximum RF± output

power (RFO[1:0] = 3 according to Table 7) and OD[2:0] = 1:

Reg08 = h99

Lock Detect and Charge Pump Current Programming

Next determine the lock indicator window from fPFD. From

Table 3, LKWIN[1:0] = 3 for a tLWW of 90ns. The LTC6945

will consider the loop “locked” as long as the phase

coincidence at the PFD is within 8°, as calculated below:

phase = 360° • tLWW • fPFD = 360 • 90n • 250k ≅ 8°

LKWIN[1:0] may be set to a smaller value to be more

conservative. However, the inherent phase noise of the

loop could cause false “unlocks” for too small a value.

Choosing the correct COUNTS depends upon the ratio of

the bandwidth of the loop to the PFD frequency (BW/fPFD).

Smaller ratios dictate larger COUNTS values. A COUNTS

value of 128 will work for the ratio of 1/25. From Table 4,

LKCT[1:0] = 1 for 128 counts.

applicaTions inForMaTion

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Using Table 5 with the previously selected ICP of 11.2mA,

gives CP[3:0] = 11. This is enough information to program

Reg09:

Reg09 = hDB

To enable the lock indicator, write Reg07:

Reg07 = h01

Charge Pump Function Programming

The DC1649 includes an LT1678I op amp in the loop filter.

This allows the circuit to reach the voltage range speci-

fied for the VCO’s tuning input. However, it also adds an

inversion in the loop transfer function. Compensate for

this inversion by setting CPINV = 1.

This example does not use the additional voltage clamp

features to allow fault condition monitoring. The loop

feedback provided by the op amp will force the charge

pump output to be equal to the op amp positive input

pin’s voltage. Disable the charge pump voltage clamps

by setting CPCHI = 0 and CPCLO = 0. Disable all the other

charge pump functions (CPMID, CPRST, CPUP and CPDN)

to allow the loop to lock:

Reg0A = h10

The loop should now lock. Now unmute the output by

setting OMUTE = 0 (assumes the MUTE pin is high):

Reg02 = h08

REFERENCE SOURCE CONSIDERATIONS

A high quality signal must be applied to the REF± inputs as

they provide the frequency reference to the entire PLL. As

mentioned previously, to achieve the part’s in-band phase

noise performance, apply a CW signal of at least 6dBm

into 50Ω, or a square wave of at least 0.5VP-P with slew

rate of at least 40V/µs.

The LTC6945 may be driven single-ended to CMOS levels

(greater than 2.7VP-P). Apply the reference signal directly

without a DC-blocking capacitor at REF+, and bypass REF–

to GND with a 47pF capacitor. The BST bit must also be

set to “0”, according to guidelines given in Table 2.

The LTC6945 achieves an in-band normalized phase noise

floor of –226dBc/Hz (typical). To calculate its equivalent

input phase noise floor LM(IN), use Equation 10:

LM(IN) = –226 + 10 • log10(fREF) (10)

For example, using a 10MHz reference frequency gives

an input phase noise floor of –156dBc/Hz. The reference

frequency source’s phase noise must be approximately

3dB better than this to prevent limiting the overall system

performance.

IN-BAND OUTPUT PHASE NOISE

The in-band phase noise produced at fRF may be calculated

by using Equation 11.

M(OUT) =

–226

10 •log

PFD

( )

+20 •log10

fRF

fPFD

⎛

⎝

⎜⎞

⎠

⎟

LM(OUT) =–226 +10 •log10 fPFD

( )

+20 •log10

⎛

⎝

⎜⎞

⎠

⎟

(11)

As seen for a given PFD frequency fPFD, the output in-band

phase noise increases at a 20dB-per-decade rate with the

N divider count. So, for a given output frequency fRF, fPFD

should be as large as possible (or N should be as small as

possible) while still satisfying the application’s frequency

step size requirements.

OUTPUT PHASE NOISE DUE TO 1/f NOISE

In-band phase noise at very low offset frequencies may

be influenced by the LTC6945’s 1/f noise, depending upon

fPFD. Use the normalized in-band 1/f noise of –274dBc/Hz

with Equation 12 to approximate the output 1/f phase

noise at a given frequency offset fOFFSET:

LM(OUT –1/f) (fOFFSET) = –274 + 20 • log10(fRF) (12)

– 10 • log10(fOFFSET)

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applicaTions inForMaTion

Unlike the in-band noise floor LM(OUT), the 1/f noise

LM(OUT –1/f) does not change with fPFD and is not constant

over offset frequency. See Figure 17 for an example of

in-band phase noise for fPFD equal to 3MHz and 100MHz.

The total phase noise will be the summation of LM(OUT)

and LM(OUT –1/f).

VCO INPUT MATCHING

The VCO± inputs may be used differentially or single-ended.

Each input provides a single-ended 121Ω resistance to aid

in impedance matching at high frequencies. The inputs are

self-biased and must be AC-coupled using a 100pF capaci-

tors (or 270pF for VCO frequencies less than 500MHz).

The inputs may be used single-ended by applying the

AC-coupled VCO frequency at VCO+ and bypassing

VCO– to GND with a 100pF capacitor (270pF for frequen-

cies less than 500MHz). Measured VCO+ s-parameters

(with VCO– bypassed with 100pF to GND) are shown in

Table 10 to aid in the design of external impedance match-

ing networks.

RF OUTPUT MATCHING

The RF± outputs may be used in either single-ended or

differential configurations. Using both RF outputs differen-

tially will result in approximately 3dB more output power

than single-ended. Impedance matching to an external

load in both cases requires external chokes tied to VRF+.

Measured RF± s-parameters are shown below in Table 11

to aid in the design of impedance matching networks.

Figure 17. Theoretical In-Band Phase Noise, fRF = 2500MHz

OFFSET FREQUENCY (Hz)

–120

PHASE NOISE (dBc/Hz)

–90

10 100 10k 100k

6945 F17

–100

–110

–130

TOTAL NOISE

fPFD = 3MHz

TOTAL NOISE

fPFD = 100MHz

1/f NOISE

CONTRIBUTION

Table 10. Single-Ended VCO+ Input Impedance

FREQUENCY (MHz) IMPEDANCE (Ω) S11 (dB)

250 118 – j78 –5.06

500 83.6 – j68.3 –5.90

1000 52.8 – j56.1 –6.38

1500 35.2 – j41.7 –6.63

2000 25.7 – j30.2 –6.35

2500 19.7 – j20.6 –5.94

3000 17.6 – j11.2 –6.00

3500 17.8 – j3.92 –6.41

4000 19.8 + j4.74 –7.20

4500 21.5 + j15.0 –7.12

5000 21.1 + j19.4 –6.52

5500 27.1 + j22.9 –7.91

6000 38.3 + j33.7 –8.47

6500 36.7 + j42.2 –6.76

7000 46.2 + j40.9 –8.11

7500 76.5 + j36.8 –9.25

8000 84.1+ j52.2 –7.27

Table 11. Single-Ended RF Output Impedance

FREQUENCY (MHz) IMPEDANCE (Ω) S11 (dB)

500 102.8 – j49.7 –6.90

1000 70.2 – j60.1 –6.53

1500 52.4 – j56.2 –6.35

2000 43.6 – j49.2 –6.58

2500 37.9 – j39.6 –7.34

3000 32.7 – j28.2 –8.44

3500 27.9 – j17.8 –8.99

4000 24.3 – j9.4 –8.72

4500 22.2 – j3.3 –8.26

5000 21.6 + j1.9 –8.02

5500 21.8 + j6.6 –7.91

6000 23.1 + j11.4 –8.09

6500 25.7 + j16.9 –8.38

7000 29.3 + j23.0 –8.53

7500 33.5 + j28.4 –8.56

8000 37.9 + j32.6 –8.64

LTC6945

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For more information www.linear.com/LTC6945

applicaTions inForMaTion

Figure 19. Single-Ended Return LossFigure 18. Single-Ended Output Matching Schematic

For lower frequencies, transmission line (TL) baluns such as

the M/A-COM MABACT0065 and the TOKO #617DB-1673

provide good results. At higher frequencies, surface mount

(SMT) baluns such as those produced by TDK, Anaren,

and Johanson Technology, can be attractive alternatives.

See Table 13 for recommended balun part numbers versus

frequency range.

The listed SMT baluns contain internal chokes to bias RF±

and also provide input-to-output DC isolation. The pin

denoted as GND or DC FEED should be connected to the

VRF+ voltage. Figure 20 shows a surface mount balun’s

connections with a DC FEED pin.

RF+(–)

50Ω

TO 50Ω

LOAD

VRF+

RF–(+)

6945 F18

VRF+

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6

FREQUENCY (GHz)

S11 (dB)

–6

–4

–2

6945 F19

–10

–16

–8

–12

–14

68nH, 100pF

180nH, 270pF

Single-ended impedance matching is accomplished using

the circuit of Figure 18, with component values found in

Table 12. Using smaller inductances than recommended

can cause phase noise degradation, especially at lower

center frequencies.

Table 12. Suggested Single-Ended Matching Component Values

fRF (MHz) LC (nH) CS (pF)

350 to 1500 180nH 270pF

1000 to 5800 68nH 100pF

Return loss measured on the DC1649 using the above

component values is shown in Figure 19. A broadband

match is achieved using an (LC, CS) of either (68nH, 100pF)

or (180nH, 270pF). However, for maximum output power

and best phase noise performance, use the recommended

component values of Table 12. LC should be a wirewound

inductor selected for maximum Q factor and SRF, such

as the Coilcraft HP series of chip inductors.

The LTC6945’s differential RF± outputs may be combined

using an external balun to drive a single-ended load. The

advantages are approximately 3dB more output power than

each output individually and better 2nd-order harmonic

performance.

Figure 20. Example of a SMT Balun Connection

LTC6945

VRF+

RF–

RF+

TO 50Ω

LOAD

6945 F20

BALUN

23 1

54 6

BALUN PIN CONFIGURATION

UNBALANCED PORT

GND OR DC FEED

BALANCED PORT

GND

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applicaTions inForMaTion

Figure 22. Example Exposed Pad Land Pattern

Table 13. Suggested Baluns

fRF (MHz) PART NUMBER MANUFACTURER TYPE

350 to 900 #617DB-1673 TOKO TL

400 to 600 HHM1589B1 TDK SMT

600 to 1400 BD0810J50200 Anaren SMT

600 to 3000 MABACT0065 M/A-COM TL

1000 to 2000 HHM1518A3 TDK SMT

1400 to 2000 HHM1541E1 TDK SMT

1900 to 2300 2450BL15B100E Johanson SMT

2000 to 2700 HHM1526 TDK SMT

3700 to 5100 HHM1583B1 TDK SMT

4000 to 6000 HHM1570B1 TDK SMT

The listed TL baluns do not provide input-to-output DC

isolation and must be AC coupled at the output. Figure 21

displays RF± connections using these baluns.

Figure 21. Example of a TL Balun Connection

LTC6945

VRF+

RF–

RF+

TO 50Ω

LOAD

PRI

SEC

6945 F21

6945 F22

REFERENCE SIGNAL ROUTING AND SPURIOUS

The charge pump operates at the PFD’s update frequency

fPFD. The resultant output spurious energy is small and

is further reduced by the loop filter before it modulates

the VCO frequency.

However, improper PCB layout can degrade the LTC6945’s

inherent spurious performance. Care must be taken to

prevent the reference signal fREF from coupling onto the

VCO’s tune line, or into other loop filter signals. Example

suggestions are the following.

1. Do not share power supply decoupling capacitors

between same voltage power supply pins.

2. Use separate ground vias for each power supply decou-

pling capacitor, especially those connected to VREF+,

VCP+, and VVCO+.

3. Physically separate the reference frequency signal from

the loop filter and VCO.

SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES

Care must be taken when creating a PCB layout to mini-

mize power supply decoupling and ground inductances.

All power supply V+ pins should be bypassed directly to

the ground plane using a 0.1µF ceramic capacitor as close

to the pin as possible. Multiple vias to the ground plane

should be used for all ground connections, including to

the power supply decoupling capacitors.

The package’s exposed pad is a ground connection, and

must be soldered directly to the PCB land. The PCB land

pattern should have multiple thermal vias to the ground

plane for both low ground inductance and also low thermal

resistance (see Figure 22 for an example). See QFN Pack-

age Users Guide, page 8, on Linear Technology website’s

Packaging Information page for specific recommendations

concerning land patterns and land via solder masks. Links

are provided below.

http://www.linear.com/designtools/packaging

LTC6945

6945fa

For more information www.linear.com/LTC6945

LTC6945 Wideband Frequency Hopping Local Oscillator

Typical applicaTions

Frequency Hopping

LOOUT Frequency,

LO1 = 450MHz, LO2 = 700MHz

TIME (µs)

–0.6

OUT

FREQUENCY (MHz)MUTE VOLTAGES (V)

450

00.4

6945 TA02b

0–0.4 –0.2 0.2

550

650

750

0.6

MUTE1MUTE2

Frequency Hopping

LOOUT Power,

LO1 = 450MHz, LO2 = 700MHz

Frequency Hopping

LOOUT Spectrum,

LO1 = 450MHz Muted,

LO2 = 700MHz

FREQUENCY (MHz)

400

POWER (dBm)

–80

–20

–10

500 600 650

6945 TA02d

–100

–40

–60

–90

–30

–110

–50

–70

450 550 700 750

fPFD = 1MHz

OD = 2

–95dBc

VVCO+

GND

VCO+

VCO–

VREFO+

REFO

STAT

SCLK

SDI

SDO

VD+

MUTE GND RF–

GND

LTC6945

O_DIV = 2

RF+VRF+BB

REF–

3.3V

0.1µF

100MHz

REF

REF+VREF+CP VCP+GND

0.01µF

100pF

700MHz TO 1400MHz

1.0µF

22nF

LT1678IS8

274Ω

4.99k 4.99k

267nF

1µF

0.1µF

47µF

1µF

3.3V

SPI BUS

MUTE1

0.1µF

0.01µF

180nH180nH

3.3V

MUTE1

MUTE20V

3.3V

270pF

50Ω 270pF

13.3nF

12V RFMD

UMS-1400-A16-G

100pF

0.1µF

LOOP BANDWIDTH = ~7.6kHz

14V

3.3V 100Ω

VTUNE

–

VVCO+

GND

VCO+

VCO–

VREFO+

REFO

STAT

SCLK

SDI

SDO

VD+

MUTE GND RF–

GND

LTC6945

O_DIV = 2

RF+VRF+BB

REF–

3.3V

0.1µF

51.1Ω

REF+VREF+CP VCP+GND

0.01µF

100pF

700MHz TO 1400MHz

1.0µF

22nF

LT1678IS8

274Ω

4.99k 4.99k

267nF

1µF

0.1µF

47µF

1µF

3.3V

SPI BUS

MUTE2

0.1µF

0.01µF

180nH180nH

3.3V

POWER

COMBINER

3.3V

100ns 270pF

50Ω 270pF

S LO OUT

6945 TA02a

LO2 = 350MHz TO 700MHz

LO1 = 350MHz TO 700MHz

13.3nF

12V RFMD

UMS-1400-A16-G

100pF

0.1µF

LOOP BANDWIDTH = ~7.6kHz

14V

3.3V 100Ω

VTUNE

–

TIME (µs)

–0.6

LOOUT POWER (MHz)MUTE VOLTAGES (V)

–5.0

00.4

6945 TA02c

0–0.4 –0.2 0.2

–4.5

–4.0

–3.5

0.6

MUTE1MUTE2

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For more information www.linear.com/LTC6945

UFD Package

28-Lead Plastic QFN (4mm × 5mm)

(Reference LTC DWG # 05-08-1712 Rev B)

4.00 ± 0.10

(2 SIDES)

2.50 REF

5.00 ± 0.10

(2 SIDES)

NOTE:

1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1

TOP MARK

(NOTE 6)

0.40 ± 0.10

27 28

BOTTOM VIEW—EXPOSED PAD

3.50 REF

0.75 ± 0.05 R = 0.115

TYP

R = 0.05

TYP

PIN 1 NOTCH

R = 0.20 OR 0.35

× 45° CHAMFER

0.25 ± 0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UFD28) QFN 0506 REV B

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

0.25 ±0.05

0.50 BSC

2.50 REF

3.50 REF

4.10 ± 0.05

5.50 ± 0.05

2.65 ± 0.05

3.10 ± 0.05

4.50 ± 0.05

PACKAGE OUTLINE

2.65 ± 0.10

3.65 ± 0.10

3.65 ± 0.05

package DescripTion

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC6945

6945fa

For more information www.linear.com/LTC6945

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision hisTory

REV DATE DESCRIPTION PAGE NUMBER

A 3/15 Changed operating core temperature to operating junction temperature.

Updated power supply currents.

LTC6945

6945fa

For more information www.linear.com/LTC6945

 LINEAR TECHNOLOGY CORPORATION 2011

LT 0315 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC6945

relaTeD parTs

Typical applicaTion

LTC6945 Wideband Point-to-Point Radio Local Oscillator

VVCO+

GND

VCO+

VCO–

VREFO+

REFO

STAT

SCLK

SDI

SDO

VD+

MUTE GND RF–

GND

LTC6945

O_DIV = 2

RF+VRF+BB

REF–

3.3V

0.1µF

100MHz

REF

REF+VREF+CP VCP+GND

0.01µF

100pF

1.0µF

18.3nF

LT1678IS8

113Ω

4.99k

51.1Ω

4.99k

230nF

1µF 1µF

0.1µF

47µF

3.3V

SPI BUS

0.1µF

0.01µF

68nH68nH

3.3V

LO OUT

4900MHz TO 5900MHz

IN STEPS OF 5MHz

3.3V

100pF

50Ω 100pF

4.7nF

5V RFMD

UMZ-T2-227-O16-G

100pF

6945 TA03a

0.1µF

LOOP BANDWIDTH = ~21.4kHz

11V

3.3V 100Ω

VTUNE

–

Radio Local Oscillator

Phase Noise, fRF = 5725MHz

OFFSET FREQUENCY (Hz)

–140

PHASE, NOISE (dBc/Hz)

–130

–110

–90

–80

100 10k 100k 10M 40M

6945 TA03b

–150

1k 1M

–100

–120

–160

RMS NOISE = 0.47°

RMS JITTER = 230fs

fPFD = 5MHz

BW = 21kHz

PART NUMBER DESCRIPTION COMMENTS

LTC6946 Ultralow Noise and Spurious Integer-N Synthesizer with VCO 370MHz to 6.4GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor

LTC6947 Ultralow Noise and Spurious Fractional-N Synthesizer 350MHz to 6GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor

LTC6948 Ultralow Noise and Spurious Frac-N Synthesizer with VCO 370MHz to 6.4GHz, –226dBc/Hz Normalized In-Band Phase Noise Floor

LTC6950 Low Phase Noise and Spurious Integer-N PLL Core with Five

Output Clock Distribution and EZSync

1.4GHz Max VCO Frequency, Additive Jitter <20fsRMS, –226dBc/Hz

Normalized In-Band Phase Noise Floor

LTC6957 Low Phase Noise, Dual Output Buffer/Driver/Logic Converter Optimized Conversion of Sine Waves to Logic Levels, LVPECL/LVDS/

CMOS

LTC2000 16-/14-/11-Bit 2.5Gsps DAC Superior 80dBc SFDR at 70MHz Output, 40mA Nominal Drive and High

Linearity

LTC5569 Broadband Dual Mixer 300MHz to 4GHz, 26.8dBm IIP3, 2dB Gain, 11.7dB NF, 600mW Power

LTC5588-1 Ultrahigh OIP3 I/Q Modulator 200MHz to 6GHz, 31dBm OIP3, –160.6dBm/Hz Noise Floor

5575 Direct Conversion I/Q Demodulator 800MHz to 2.7GHz, 22.6dBm IIP3, 60dBm IIP2, 12.7dB NF