ICS950811 Integrated Circuit Systems, Inc. Frequency Generator with 200MHz Differential CPU Clocks Recommended Application: CK-408 clock for Brookdale-Mobile chipsets. Programmable for group to group skew. Pin Configuration Output Features: * 3 Differential CPU Clock Pairs (differential current mode) * 7 PCI (3.3V) @ 33.3MHz * 3 PCI_F (3.3V) @ 33.3MHz * 1 USB (3.3V) @ 48MHz * 1 DOT (3.3V) @ 48MHz * 1 REF (3.3V) @ 14.318MHz * 5 3V66 (3.3V) @ 66.6MHz * 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz Features: * Supports spread spectrum modulation, down spread 0 to -0.5%. * Efficient power management scheme through PD#, CPU_STOP# and PCI_STOP#. 56 pin SSOP/TSSOP Key Specifications: * CPU Output Jitter <150ps * 3V66 Output Jitter <250ps * 66MHz Output Jitter (Buffered Mode Only) <100ps * CPU Output Skew <100ps Block Diagram * These inputs have 150K internal pull-up resistor to VDD. Functionality FS2 FS1 FS0 0482E--08/09/07 CPU (MHz) HzOut(2:0) 3V66(1:0) 66M 3V66(4:2) (MHz) (MHz) PCI_F PCI (MHz) 66MHzIn 3V66(5) (MHz) 0 0 0 66.66 66.66 66.66 33.33 66.66 0 0 1 100.00 66.66 66.66 33.33 66.66 0 1 0 200.00 66.66 66.66 33.33 66.66 0 1 1 133.33 66.66 66.66 33.33 66.66 1 0 0 66.66 66.66 1 0 1 100.00 66.66 1 1 0 200.00 66.66 Buffered Mode Not Suppor ted See ICS950805 1 1 1 133.33 66.66 Mid 0 0 Tristate Tristate Tristate Tristate Tristate Mid 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/4 Mid 1 0 Reser v- Reser ved ed Reser ved Reser ved Reser ved Mid 1 1 Reser v- Reser ved ed Reser ved Reser ved Reser ved ICS950811 Pin Configuration PIN NUMBER PIN NAME TYPE 1, 8, 14, 19, 26, 32, 37, 46, 50 DESCRIPTION VDD PWR 2 X1 X2 Cr ystal Input 14.318MHz Cr ystal input 3 X2 X1 Cr ystal Output 14.318MHz Cr ystal output 7, 6, 5 PCICLK_F (2:0) OUT Free running PCI clock not affected by PCI_STOP# for power management. 4, 9, 15, 20, 27, 31, 36, 41, 47 GND PWR Ground pins for 3.3V supply 18, 17, 16, 13, 12,11, 10 PCICLK (6:0) OUT PCI clock outputs 24, 23, 22, 21 3V66 (5:2) OUT 66MHz reference clocks, from internal VCO 3.3V power supply 25 PD# IN 28 Vtt_PWRGD# IN Invokes power-down mode. Active Low. 29 SDATA I/O Data pin for I2C circuitry 5V tolerant 30 SCLK IN Clock pin of I2C circuitry 5V tolerant 33 3V66_0 OUT 66MHz reference clocks, from internal VCO Halts PCICLK clocks at logic 0 level, when input low except PCICLK_F which are free running 34 PCI_STOP# IN 35 3V66_1/VCH_CLK OUT 3.3V output selectable through I2C to be 66MHz from internal VCO or 48MHz (non-SSC) 38 48MHz_DOT OUT 48MHz output clock for DOT 48MHz output clock for USB 39 48MHz_USB OUT 40 FS2 IN 42 I REF OUT 43 MULTSEL0 IN 44, 48, 51 CPUCLKC (2:0) OUT "Complementor y" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. 45, 49, 52 CPUCLKT (2:0) OUT "True" clocks of differential pair CPU outputs. These are current outputs and external resistors are required for voltage bias. Special 3.3V input for Mode selection This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 3.3V LVTTL input for selecting the current multiplier for CPU outputs 53 CPU_STOP# IN Halts CPUCLK clocks at logic 0 level, when input low 55, 54 FS (1:0) IN Frequency select pins 56 REF OUT 14.318MHz reference clock. Power Groups (Analog) VDDA = PLL1 VDD48 = 48MHz, PLL VDDREF = VDD for Xtal, POR (Digital) VDDPCI VDD3V66 VDDCPU 0482E--08/09/07 2 ICS950811 Truth Table FS2 FS1 FS0 CPU (MHz) 3V66 (1:0) (MHz) 66Buff (2:0) 3V66 (4:2) (MHz) 66MHz_IN/ 3V66_5 PCI_F PCI (MHz) REF0 (MHz) USB/DOT (MHz) 0 0 0 66.66 66.66 66.66 66.66 33.33 14.318 48.00 0 0 1 100.00 66.66 66.66 66.66 33.33 14.318 48.00 0 1 0 200.00 66.66 66.66 66.66 33.33 14.318 48.00 66.66 66.66 33.33 14.318 48.00 0 1 1 133.33 66.66 1 0 0 66.66 66.66 1 0 1 100.00 66.66 1 1 0 200.00 66.66 1 1 1 133.33 66.66 Mid 0 0 Tristate Tristate TCLK/2 TCLK/4 Buffered Mode Not Suppor ted See ICS950805 Tristate Tristate Tristate Tristate Tristate Mid 0 1 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 Mid 1 0 Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Mid 1 1 Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Reser ved Maximum Allowed Current Condition Max 3.3V supply consumption Max discrete cap loads, Vdd = 3.465V All static inputs = Vdd or GND Powerdown Mode (PWRDWN# = 0) 40mA Full Active 360mA Host Swing Select Functions MULTISEL0 Board Target Trace/Term Z Output Current Voh @ Z Buffered Mode Not Suppor ted See ICS950805 0 1 Reference R, Iref = VDD/(3*Rr) 50 ohms Rr = 475 1%, Iref = 2.32mA 0482E--08/09/07 3 Ioh = 6* I REF 0.7V @ 50 ICS950811 General I2C serial interface information The information in this section assumes familiarity with I2C programming. How to Write: How to Read: * * * * * * * * * * * * * * * * Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 * ICS clock will acknowledge each byte one at a time. Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Byte 6 Byte 6 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 0482E--08/09/07 4 ICS950811 Byte 0: Control Register Bit Pin# Name PWD2 Type1 Bit 0 54 FS0 X R Bit 1 55 FS1 X R Bit 2 40 FS2 X R X R Bit 3 34 PCI_STOP#3 1 RW Bit 4 53 CPU_STOP# X R Bit 5 35 3V66_1/VCH 0 RW Bit 6 - CPU_T(2:0) 0 Bit 7 - Spread Enabled 0 RW Description Reflects the value of FS0 pin sampled on power up Reflects the value of FS1 pin sampled on power up Reflects the value of FS2 pin sampled on power up Hardware mode: Reflects the value of PCI_STOP# pin sampled on PWD Software mode: 0=PCICLK stopped 1=PCICLK not stopped Reflects the current value of the external CPU_STOP# pin VCH Select 66MHz/48MHz 0=66MHz, 1=48MHz In power down mode controls output level 0=stop high 1=stop low 0=Spread Off, 1=Spread On Byte 1: Control Register PWD2 Type1 1 RW 0=Disabled 1=Enabled4 1 RW 0=Disabled 1=Enabled4 45, 44 Name CPUCLKT0 CPUCLKC0 CPUCLKT1 CPUCLKC1 CPUCLKT2 CPUCLKC2 1 RW 0=Disabled 1=Enabled4 Bit 3 52, 51 CPUCLKT0 CPUCLKC0 0 RW Bit 4 49, 48 CPUCLKT1 CPUCLKC1 0 RW Bit 5 45, 44 CPUCLKT2 CPUCLKC2 0 RW B it 6 Bit 7 43 MULTSEL0 0 X R Bit Pin# Bit 0 52, 51 Bit 1 49, 48 Bit 2 Description Allow control of CPUCLKT0/C0 with asser tion of CPU_STOP# 0=Not free running 1=Free running Allow control of CPUCLKT1/C1 with asser tion of CPU_STOP# 0=Not free running 1=Free running Allow control of CPUCLKT2/C2 with asser tion of CPU_STOP# 0=Not free running 1=Free running (Reserved) Reflects the current value of MULTSEL0 Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP functionality via I2C Byte 0 Bit 3. In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix these modes. In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in PCI_STOP mode. Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)]. 4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high, CPUCLKC off, and external resistor termination will bring CPUCLKC low. 0482E--08/09/07 5 ICS950811 Byte 2: Control Register Bit Bit 0 Bit 1 Bit 2 B it 3 B it 4 Bit 5 B it 6 Bit 7 Pin# 10 11 12 13 16 17 18 - Name PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 - PWD 1 1 1 1 1 1 1 0 Type RW RW RW RW RW RW RW - Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled Allow control of PCICLK_F0 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F1 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running Allow control of PCICLK_F2 with asser tion of PCI_STOP#. 0=Free Running, 1=Not free running 0=Disabled 1=Enabled 0=Disabled 1=Enabled Byte 3: Control Register Bit Bit 0 Bit 1 Bit 2 Pin# 5 6 7 Name PCICLK_F0 PCICLK_F1 PCICLK_F2 PWD 1 1 1 Type RW RW RW Bit 3 5 PCICLK_F0 0 RW Bit 4 6 PCICLK_F1 0 RW Bit 5 7 PCICLK_F2 0 RW Bit 6 Bit 7 39 38 48MHz_USB 48MHz_DOT 1 1 RW RW Byte 4: Control Register Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# 21 22 23 24 35 33 - Name 3V66-2 3V66-3 3V66-4 3V66_5 3V66_1/VCH_CLK 3V66_0 - PWD 1 1 1 1 1 1 0 0 Type RW RW RW RW RW RW R R Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 0482E--08/09/07 6 Description 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled 0=Disabled 1=Enabled (Reserved) (Reserved) ICS950811 Byte 5: Programming Edge Rate (1 = enable, 0 = disable) Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# X X X X X X X X Name 48MHz_USB 48MHz_USB 48MHz_DOT 48MHz_DOT - PWD 0 0 0 0 0 0 0 0 Type RW RW RW RW - PWD 1 1 1 1 1 1 1 1 Type R R R R R R R R Description USB edge rate cntrol USB edge rate cntrol DOT edge rate control DOT edge rate control (Reserved) (Reserved) (Reserved) (Reserved) Byte 6: Vendor ID Register (1 = enable, 0 = disable) Bit Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Pin# X X X X X X X X Name Vendor ID Bit0 Vendor ID Bit1 Vendor ID Bit2 Vendor ID Bit3 Revision ID Bit0 Revision ID Bit1 Revision ID Bit2 Revision ID Bit3 Notes: 1. R= Read only RW= Read and Write 2. PWD = Power on Default 0482E--08/09/07 7 Description (Reserved) (Reserved) (Reserved) (Reserved) Revision ID values will be based on individual device's revision ICS950811 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD + 0.5 V Ambient Operating Temperature . . . . . . . . . . 0C to +85C Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL CONDITIONS VIH VIL IIH V IN = VDD IIL1 V IN = 0 V; Inputs with no pull-up resistors MIN 2 V SS - 0.3 -5 -5 TYP MAX VDD + 0.3 0.8 5 Input Low Current mA IIL2 Operating Supply Current IDD3.3OP IDD3.3OP Powerdown Current Input Frequency Pin Inductance 1 Input Capacitance 1 Transition time Settling time1 Clk Stabilization1 Time to first clock1 Delay1 UNITS V V mA mA I DD3.3PD Fi Lpin CIN COUT CINX Ttrans Ts TSTAB T1C tPZH,tPZL tPHZ,tPLZ V IN = 0 V; Inputs with pull-up resistors -200 CL = Full load; Select @ 100 MHz 229 230 360 CL =Full load; Select @ 133 MHz IREF=5 mA V DD = 3.3 V 220 233 360 38.1 14.318 45 Logic Inputs Output pin capacitance X1 & X2 pins To 1st crossing of target frequency From 1st crossing to 1% target frequency From VDD = 3.3 V to 1% target frequency Time to first clock Output enable delay (all outputs) Output disable delay (all outputs) 1 Guaranteed by design, not 100% tested in production. 0482E--08/09/07 8 27 36 1 1 1 mA mA 7 5 6 45 3 3 3 mA MHz nH pF pF pF ms ms ms 1.8 10 10 ms ns ns ICS950811 Electrical Characteristics - CPU TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Current Source Output Impedance SYMBOL Output High Voltage Output Low Voltage Rise Time Fall Time VOH3 VOL3 tr3 tf3 Duty Cycle dt3 Skew tsk3 Jitter, Cycle to cycle Zo1 tjcyc-cyc CONDITIONS VO = Vx IOH = -1 mA IOL = 1 mA VOL = 0.41V, VOH = 0.86V VOH = 0.86V VOL = 0.41V 1 measurement from differential wavefrom 0.35V to +035V VT = 50% VT = 50% MIN TYP MAX UNITS V 3000 2.4 175 175 240 242 0.4 700 700 45 51 55 % 50 100 ps 76 150 ps ps ps 1 Guaranteed by design, not 100% tested in production. IOWT can be varied and is selectable thru the MULTSEL pin. 2 Electrical Characteristics - PCICLK TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 tsk11 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter,cycle to cyc tjcyc-cyc 1 CONDITIONS MIN TYP 33.33 MAX UNITS MHz VO = VDD*(0.5) 12 33 55 IOH = -1 mA 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V -33 30 VOL = 0.4 V, VOH = 2.4 V 0.5 VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0482E--08/09/07 9 V 0.55 -33 38 V mA mA 1.32 0.5to 2 ns 0.5 1.39 0.5 to 2 ns 45 52 55 % 247 500 ps 111 500 ps ICS950811 Electrical Characteristics - 3V66 TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL Output Frequency FO1 RDSP11 VO = VDD*(0.5) Output Impedance Duty Cycle VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 Skew tsk11 Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Jitter CONDITIONS tjcyc-cyc IOH = -1 mA 1 MIN TYP 66.66 MAX UNITS MHz 12 33 55 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V -33 30 VOL = 0.4 V, VOH = 2.4 V 0.5 VOH = 2.4 V, V OL = 0.4 V VT = 1.5 V V 0.55 -33 38 V mA mA 1.38 2 ns 0.5 1.45 2 ns 45 54.4 55 % 243 500 ps 139 300 ps VT = 1.5 V VT = 1.5 V 3V66 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency Output Impedance SYMBOL FO1 CONDITIONS RDSP11 V O = V DD*(0.5) MIN TYP 48 20 48 Output High Voltage VOH1 IOH = -1 mA Output Low Voltage Output High Current Output Low Current 48DOT Rise Time VOL1 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V V OL @MIN = 1.95 V, VOL @MAX = 0.4 V -29 29 V OL = 0.4 V, V OH = 2.4 V 0.5 V OH = 2.4 V, VOL = 0.4 V 48DOT Fall Time VCH 48 USB Rise Time VCH 48 USB Fall Time 48 DOT Duty Cycle VCH 48 USB Duty Cycle 48 DOT Jitter VCH Jitter IOH1 IOL1 tr11 tf11 tr11 tf11 dt11 dt11 MAX UNITS MHz 60 2.4 V 0.4 -23 27 V mA mA 0.6 1 ns 0.5 0.8 1 ns V OL = 0.4 V, V OH = 2.4 V 1 1.2 2 ns V OH = 2.4 V, VOL = 0.4 V 1 1.3 2 ns V T = 1.5 V 45 52.8 55 % V T = 1.5 V 45 53.5 55 % 183 350 ps 223 350 ps 1 tjcyc-cyc V T = 1.5 V tjcyc-cyc 1 V T = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0482E--08/09/07 10 ICS950811 Electrical Characteristics - REF TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER Output Frequency SYMBOL FO1 Output Impedance RDSP11 Output High Voltage VOH1 VOL1 IOH1 IOL1 tr11 tf11 dt11 Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter tjcyc-cyc CONDITIONS VO = VDD*(0.5) 20 IOH = -1 mA 2.4 IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V 1 MIN TYP MAX UNITS 14.318 MHz 48 60 V -29 29 0.4 -23 27 V mA mA VOL = 0.4 V, VOH = 2.4 V 1 1.25 2 ns VOH = 2.4 V, V OL = 0.4 V 1 1.15 2 ns 45 53 55 % 723 1000 ps VT = 1.5 V VT = 1.5 V 1 Guaranteed by design, not 100% tested in production. 0482E--08/09/07 11 ICS950811 Un-Buffered Mode 3V66 & PCI Phase Relationship All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew described below as Tpci. 3V66 (1:0) 3V66 (4:2) 3V66_5 Tpci PCICLK_F (2:0) PCICLK (6:0) Group Skews at Common Transition Edges: (Un-Buffered Mode) GROUP 3V66 PCI 3V66 to PCI SYMBOL CONDITIONS 3V66 3V66 (5:0) pin to pin skew PCI S3V66-PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 3V66 (5:0) leads 33MHz PCI 1 Guaranteed by design, not 100% tested in production. 0482E--08/09/07 12 MIN 0 TYP 42 MAX UNITS 500 ps 0 130 500 ps 1.5 2.86 3.5 ns ICS950811 Normal operation transition to Suspend State S1 Entry sequence of events: 1. Power-Down (PD#) pin is taken from a high to low to start into S1 Suspend state with digital filtering of the transition in the clock circuit. 2. The first clocks to be forced to a Stop Low power down condition are the PCI buffer output clocks after a full clock cycle. If the PCI_Stop# is low, then the free-running PCI clocks (for PCI and APIC signals) are the remaining PCI buffer clocks stopped. 3. Immediately after the PCI clocks have been stopped the 66Buf_0:2 clocks are stopped low after the next high to low transition. It will always be a sequence of PCI stopping, THEN the 66Buf clocks. 4. Following the two buffer output clocks being stopped (PCI then 66.6Buffer outputs), the remaining clocks within a short delay will transition to a stopped power-down state. The first of these driven clocks that transition to a stopped state are all of the CPU PLL clocks: the CPU and the driven 3V66 clocks. 5. After the CPU PLL clocks are stopped, the 48 MHz clocks (USB, DOT clocks) will stop low, then the REF clock 14.318 MHz clock will stop low. 6. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to a low power stopped condition. 7. As a note to power management calculations, please be aware that the CPU design requires that in the Power-Down (S1 mode) the CPU outputs have a differential bias voltage driving the differential input stage of the CPU in this S1 state. For this PD condition of the clock generator, the IDD_PD is running around 30 to 45 mA from having the Iref running (5 mA), the output multiplier bias generator at a 2X condition and the output current source outputs are running at a 2xIref bias level (for approx 10 mA each CPU output). This results in a higher level of Clock generator IDD_PD than in prior generations of clocks due to the CPU output differential requirements. Suspend State S1 Exit transition to normal operation sequence of events: 1. Power-Down (PD#) pin is taken from Low to High with digital filtering of the transition in the clock circuit to return to normal running operation. 2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation. No clocks will operate until the Lock detect circuitry verifies the PLL has reached stable final frequency (the same as normal initial power-up). 3. The CPU PLL clocks (differential CPU outputs and the driven 3V66_(0:1) clocks are operating first as soon as the Lock detect releases the clocks. With the release of these clocks, the single 66Buf_1 buffer driven output (at pin 22) is also released from the PD stopped state (but NOT the other 66Buf0,2 and not the PCI outputs). This allows the GMCH chipset 66.6 MHz DLL stage to start operating and have an operating feedback path before the other buffer outputs are released. This change is why the requirement is made that pin 22 be the connection from the clock to the GMCH chipset. Note that along with the 66Buf_0,2 and the PCI clocks, the 48 MHz and REF (14.318 MHz) clocks are also NOT released at this point. 4. A delay is built into the clock generator that allows the CPU, driven 3V66_0,1 and the single buffer clock 66Buf_1 (at pin 22) to operate before other clocks are released. This delay is larger than 30 uS and shorter than 400 uS, and after this the other clocks are staged for a sequential release. 5. The initial clocks released after the delay are the 66Buf_0, 2 outputs. 6. After the 66Buf_0,2 clocks are released, then the PCI clocks are released. 7. It will always be the sequence of 66_1 (pin 22) released with the CPU clocks, then after the delay the remaining 66Buf_0,2 first, THEN the PCI clocks. 8. Following the 66Buf_0,2 clocks, the 48 MHz (DOT and USB clocks) and the REF (14.318MHz) clocks are released. 9. Note, the initial power-up time is the same as this PD release, the PLL will power-up and the outputs will be running within a 3 ms time point. 0482E--08/09/07 13 ICS950811 PCI_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge. Assertion of PCI_STOP# Waveforms PCI_STOP# PCI_F[2:0] 33MHz PCI[6:0] 33MHz tsu CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms CPU_STOP# CPUT CPUC CPU_STOP# Functionality CPU_STOP# CPUT CPUC 1 Normal Normal 0 iref * Mult Float 0482E--08/09/07 14 ICS950811 PD# - Assertion (transition from logic "1" to logic "0") When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description is applicable for all valid CPU frequencies 66, 100, 133, 200MHz. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete. Power Down Assertion of Waveforms - Buffered Mode 25ns 0ns 50ns PD# CPUT 100MHz CPUC 100MHz 3V66MHz 66MHz_IN 66MHz_OUT PCI 33MHz USB 48MHz REF 14.318MHz PD# Functionality CPU_STOP# CPUT CPUC 3V66 66MHz_OUT PCICLK_F PCICLK PCICLK USB/DOT 48MHz 1 Normal Normal 66MHz 66MHz_IN 66MHz_IN 66MHz_IN 48MHz 0 iref * Mult Float Low Low Low Low Low 0482E--08/09/07 15 ICS950811 c N L E1 INDEX AREA E 1 2 a D A A2 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -1.20 -.047 A1 0.05 0.15 .002 .006 A2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 D SEE VARIATIONS SEE VARIATIONS E 8.10 BASIC 0.319 BASIC E1 6.00 6.20 .236 .244 e 0.50 BASIC 0.020 BASIC L 0.45 0.75 .018 .030 N SEE VARIATIONS SEE VARIATIONS 0 8 0 8 aaa -0.10 -.004 A1 -Ce N SEATING PLANE b 56 aaa C VARIATIONS D mm. MIN MAX 13.90 14.10 Ref erence Doc.: JEDEC Publicat ion 95, M O-153 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) 10-0039 Ordering Information 950811yGLFT Example: XXXX y G - LF - T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type 0482E--08/09/07 16 D (inch) MIN .547 MAX .555 ICS950811 56-Lead, 300 mil Body, 25 mil, SSOP SYMBOL A A1 b c D E E1 e h L N In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8 VARIATIONS N 56 D mm. MIN 18.31 D (inch) MAX 18.55 Reference Doc.: JEDEC Publication 95, MO-118 10-0034 Ordering Information 950811yFLFT Example: XXXX y F - LF - T Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type 0482E--08/09/07 17 MIN .720 MAX .730 ICS950811 Revision History Rev. D E Issue Date Description 1. Removed SSOP Package Information. 12/21/06 2. Added LF Ordering Information. 08/09/07 Added SSOP Package Information. 0482E--08/09/07 18 Page # 16 17