tm TE CH T436432B SDRAM 512K x 32bit x 4Banks Synchronous DRAM FEATURES GRNERAL DESCRIPTION 2M x 32 SDRAM * * * * * 3.3V power supply Clock cycle time : 5 / 5.5 / 6 / 7 / 8 / 10 ns Internal four banks operation LVTTL compatible with multiplexed address All inputs are sampled at the positive going edge of system clock * Burst Read Single-bit Write operation * DQM for masking * Auto refresh and self refresh * 64ms refresh period (4K cycle) * MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length : 1 , 2 , 4 , 8 or full page for Sequential Burst 1 , 2 , 4 or 8 for Interleave Burst * Available package type : - 86 pin 400mil TSOP(II) and Lead free * Operating temperature : - 0 ~ +70 C The T436432B is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 524,288 words by 32 bits , fabricated with high performance CMOS technology . Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle . Range of operating frequencies , programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth , high performance memory system applications. PART NUMBER EXAMPLES CLOCK MAX CYCLE TIME FREQUENCY T436432B-5SG 5ns 200 MHz TSOP-II Lead free 0 ~ +70 C T436432B-5S 5ns 200 MHz TSOP-II T436432B-55SG 5.5ns 183 MHz TSOP-II Lead free 0 ~ +70 C 0 ~ +70 C T436432B-55S 5.5ns 183 MHz TSOP-II 0 ~ +70 C T436432B-6SG 6ns 166 MHz TSOP-II Lead free 0 ~ +70 C T436432B-6S 6ns 166 MHz TSOP-II 0 ~ +70 C T436432B-7SG 7ns 143 MHz TSOP-II Lead free 0 ~ +70 C T436432B-7S 7ns 143 MHz TSOP-II 0 ~ +70 C T436432B-8SG 8ns 125 MHz TSOP-II Lead free 0 ~ +70 C T436432B-8S 8ns 125 MHz TSOP-II 0 ~ +70 C T436432B-10SG 10ns 100 MHz TSOP-II Lead free 0 ~ +70 C T436432B-10S 10ns 100 MHz TSOP-II 0 ~ +70 C PART NO. PACKAGE TM Technology Inc. reserves the right P. 1 to change products or specifications without notice. OPERATING TEMPERATURE Publication Date: FEB. 2007 Revision: A tm TE CH T436432B PIN ARRANGEMENT (TSOP-II Top View) V D D D Q 0 V V ss 1 86 2 85 D Q 15 V D D Q 3 84 D Q 1 4 83 D Q 14 D Q 2 5 82 D Q 13 V SSQ 6 81 V D Q 3 7 80 D Q 12 D Q 4 8 79 D Q 11 9 78 V D Q 5 10 77 D Q 10 D Q 6 11 76 V SSQ 12 75 D Q 7 13 74 D Q 8 N .C 14 73 N .C D D 15 72 V ss D Q M 0 16 71 D Q M 1 W E 17 70 N .C C A S 18 69 N .C R A S 19 68 C LK C S 20 67 C K E V D D Q V 8 6 P IN T S O P (II) (4 0 0 m il) SSQ D D Q SSQ D Q 9 V D D Q N .C 21 66 A 9 B S 0 22 65 A 8 B S 1 23 64 A 7 A 1 0 /A P 24 63 A 6 A 0 25 62 A 5 A 1 26 61 A 4 A 2 27 60 A 3 D Q M 2 28 59 D Q M 3 V D D 29 58 V N .C 30 57 N .C D Q 16 31 56 D Q 31 SSQ 32 55 V D Q 17 33 54 D Q 30 D Q 18 34 53 D Q 29 V D D Q 35 52 V D Q 19 36 51 D Q 28 D Q 20 37 50 D Q 27 38 49 V D Q 21 39 48 D Q 26 D Q 22 40 47 D Q 25 V D D Q 41 46 D Q 23 42 45 D Q 24 43 44 V ss V V SSQ V D D TM Technology Inc. reserves the right P. 2 to change products or specifications without notice. V SS D D Q SSQ D D Q SSQ Publication Date: FEB. 2007 Revision: A tm TE CH T436432B BLOCK DIAGRAM D ata Input R egister Col. Buffer C olum n D ecoder 512K x 32 512K x 32 512K x 32 Output Buffer 512K x 32 Sense AM P Row Decoder Row Buffeer Refresh Counter Address Register A DD I/O Control Bank Select DQ Latency & Burst Length Program m ing R egister Tim ing Register C LK C KE CS R AS C AS TM Technology Inc. reserves the right P. 3 to change products or specifications without notice. WE D QM Publication Date: FEB. 2007 Revision: A tm TE CH T436432B PIN DESCRIPTION PIN NAME CLK System Clock CS Chip Select INPUT FUNCTION Active on the positive going edge to sample all input. Disables or enables device operation by masking or enabling all input except CLK,CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE Clock Enable CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. Row/column addresses are multiplexed on the same pins. A0 ~ A10/AP Address Row address : RA0 ~ RA10,column address : CA0 ~ CA7 Auot-precharge flag : A10/AP BS0~1 Bank Select Address Selects bank to be activated during row address latch time. Select bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK RAS Row Address Strobe with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK CAS Column Address Strobe with CAS low. Enables column access . WE DQM0~3 DQ0 ~ DQ31 VDD/VSS VDDQ/VSSQ N.C Write Enable Data Input/Output Mask Data Input/Output Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply/Ground Power and ground for the input buffers and the core logic. Data Output Isolated power supply and ground for the output buffers to provide Power/Ground improved noise immunity. No Connection No Connection. TM Technology Inc. reserves the right P. 4 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command State CKEn-1 CKEn DQM(6) BS0,1 A10 A9-0 CS# RAS# CAS# WE# BankActivate Idle(3) H X X V Row address L L H H BankPrecharge Any H X X V L X L L H L PrechargeAll Any H X X X H X L L H L Column address (A0 ~ A7) L H L L L H L L Column address (A0 ~ A7) L H L H L H L H L L L L Write Active(3) H X X V L Write and AutoPrecharge Active(3) H X X V H Read Active(3) H X X V L Read and Autoprecharge Active(3) H X X V H Mode Register Set Idle H X X No-Operation Any H X X X X X L H H H Active(4) H X X X X X L H H L Device Deselect Any H X X X X X H X X X AutoRefresh Idle H H X X X X L L L H SelfRefresh Entry Idle H L X X X X L L L H SelfRefresh Exit Idle L H X X X X H X X X L H H H Burst Stop OP code (SelfRefresh) Clock Suspend Mode Entry Active H L X X X X X X X X Power Down Mode Entry Any(5) H L X X X X H X X X L H H H Clock Suspend Mode Exit Power Down Mode Exit Active L H X X X X X X X X Any L H X X X X H X X X L H H H X X X X X X X (PowerDown) Data Write/Output Enable Active H X L Data Mask/Output Disable Note: X X X Active H X H X X X X 1. V = Valid, X = Don't care, L = Logic low, H = Logic high 2. CKEn signal is input level when commands are provided. CKEn-1 signal is input level one clock cycle before the commands are provided. 3. These are states of bank designated by BS signal. 4. Device state is 1, 2, 4, 8, and full page burst operation. 5. Power Down Mode can not enter in the burst operation. When this command is asserted in the burst cycle, device state is clock suspend mode. 6. DQM0-3 TM Technology Inc. reserves the right P. 5 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BS = Bank, A0-A10 = Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal. By latching the row address on A0 to A10 at the time of this command, the selected row access is initiated. The read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank activation. A subsequent BankActivate command to a different row in the same bank can only be issued after the previous active row has been precharged (refer to the following figure). The minimum time interval between successive BankActivate commands to the same bank is defined by tRC(min.). The SDRAM has four internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts the back-to-back activation of the four banks. tRRD(min.) specifies the minimum time required between activating different banks. After this command is used, the Write command and the Block Write command perform the no mask write operation. T0 T1 T2 T3 Tn+3 CLK Tn+4 Tn+5 Tn+6 .............. ADDRESS Bank A Row Addr. Bank A Col Addr. .............. Bank B Row Addr. R/W A with AutoPrecharge .............. Bank B Activate RAS# - RAS# delay time (tRRD) RAS# - CAS# delay (tRCD) COMM AND Bank A Activate NOP NOP Bank A Row Addr. NOP NOP Bank A Activate RAS# Cycle time (tRC) AutoPrecharge Begin : "H" or "L" BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3) 2 BankPrecharge command (RAS# = "L", CAS# = "H", WE# = "L", BS = Bank, A10 = "L", A0-A9 = Don't care) The BankPrecharge command precharges the bank disignated by BS0,1 signal. The precharged bank is switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated again. 3 PrechargeAll command (RAS# = "L", CAS# = "H", WE# = "L", BS = Don't care, A10 = "H", A0-A9 = Don't care) The PrechargeAll command precharges all the four banks simultaneously and can be issued even if all banks are not in the active state. All banks are then switched to the idle state. 4 Read command (RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "L", A0-A7 = Column Address) The Read command is used to read a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Read command is issued. During read bursts, the valid data-out element from the starting column address will be available following the CAS# latency after the issue of the Read command. Each subsequent data-out element will be valid by the next positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the mode register which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). TM Technology Inc. reserves the right P. 6 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B T0 T1 T2 T3 T4 T5 T6 T7 NOP NOP NOP NOP T8 CLK COMMAND READ A NOP NOP DOUT A0 CAS# latency=2 tCK2, DQ's DOUT A1 DOUT A0 CAS# latency=3 tCK3, DQ's DOUT A2 DOUT A1 NOP NOP DOUT A3 DOUT A2 DOUT A3 Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt coming from the Read command can occur on any clock cycle following a previous Read command (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 NOP NOP NOP NOP DOUT B2 DOUT B3 T7 T8 CLK COMMAND CAS# latency=2 tCK2, DQ's CAS# latency=3 tCK3, DQ's READ A READ B NOP DOUT A0 DOUT B0 DOUT A0 DOUT B1 DOUT B0 DOUT B1 DOUT B2 NOP NOP DOUT B3 Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance on the DQ pins must occur between the last read data and the Write command (refer to the following three figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be asserted (HIGH) at least one clock prior to the Write command to avoid internal bus contention. TM Technology Inc. reserves the right P. 7 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B T0 T1 T2 T3 NOP READ A NOP T4 T5 T6 T7 T8 NOP NOP CLK DQM COMMAND NOP NOP DQ's NOP DOUT A0 Must be Hi-Z before the Write Command WRITE B DINB 0 DINB1 DINB 2 : "H" or "L" Read to Write Interval (Burst Length * 4, CAS# Latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK 1 Clk Interval DQM COMMAND NOP NOP BANKA ACTIVATE NOP READ A CAS# latency=2 tCK2, DQ's WRITE A NOP DIN A0 DIN A1 NOP NOP DIN A2 DIN A3 : "H" or "L" Read to Write Interval (Burst Length 4, CAS# Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP NOP READ A NOP CAS# latency=2 tCK2, DQ's NOP WRITE B DIN B0 NOP DIN B1 NOP NOP DIN B2 DIN B3 : "H" or "L" Read to Write Interval (Burst Length 4, CAS# Latency = 2) A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll command is issued in different CAS# latency. TM Technology Inc. reserves the right P. 8 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Bank, Col A ADDRESS Bank, Row Bank(s) tRP COMMAND READ A NOP CAS# latency=2 tCK2, DQ's NOP DOUT A0 CAS# latency=3 tCK3, DQ's NOP Precharge NOP DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 NOP Activate NOP DOUT A3 Read to Precharge (CAS# Latency = 2, 3) 5 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge function is ignored. 6 Write command (RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address) The Write command is used to write a burst of data on consecutive clock cycles from an active row in an active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge (refer to the following figure). The DQs remain with high-impedance at the end of the burst unless another command is initiated. The burst length and burst sequence are determined by the mode register, which is already programmed. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue). T0 T1 T2 T3 T4 T5 T6 T7 T8 WRITE A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don't care CLK COM MAND DQ0 - DQ3 NOP The first data element and the write are registered on the same clock edge. Extra data is masked. Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3) A write burst without the AutoPrecharge function may be interrupted by a subsequent Write, BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from Write command can occur on any clock cycle following the previous Write command (refer to the following figure). TM Technology Inc. reserves the right P. 9 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP NOP NOP NOP NOP DIN B 1 DIN B2 DIN B3 CLK COM M AND NOP WRITE A WRITE B 1 Clk Interval DIN A0 DQ's DIN B0 Write Interrupted by a Write (Burst Length = 4, CAS# Latency = 1, 2, 3) The Read command that interrupts a write burst without auto precharge function should be issued one cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs (refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes will not be executed. T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP NOP CL K COM MA ND NOP WRITE A NOP READ B CAS# latency=2 tCK2 , DQ's DIN A 0 don't care CAS# latency=3 tCK3 , DQ's DIN A 0 don't care NOP NOP DOUT B 0 DOUT B 2 DOUT B 1 DOUT B 0 don't care DOUT B 3 DOUT B 1 DOUT B 2 DOUT B 3 Input data must be removed from the DQ's at least one clock cycle before the Read data appears on the outputs to avoid data contention. Input data for the write is masked. Write Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3) The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge function should be issued m cycles after the clock edge in which the last data-in element is registered, where m equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input data, starting with the clock edge following the last data-in element and ending with the clock edge on which the BankPrecharge/PrechargeAll command is entered (refer to the following figure). T0 T1 T2 T3 T4 T5 T6 CLK D QM tRP C OM M A ND WRITE ADDRESS BA NK COL n Precharge NOP NOP BANK (S) NOP Activate NOP ROW tWR DIN n DQ DI N n+ 1 : don't care Note: The DQMs can remain low in this example if the length of the write burst is 1 or 2. Write to Precharge TM Technology Inc. reserves the right P. 10 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm 7 TE CH T436432B Write and AutoPrecharge command (refer to the following figure) (RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically after the write operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the auto precharge function is ignored. T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND Bank A Activate NOP NOP Write A AutoPrecharge NOP NOP NOP NOP NOP tDAL CAS# latency=2 tCK2, DQ's DIN A0 DIN A1 * tDAL CAS# latency=3 tCK3, DQ's DIN A0 DIN A1 tDAL= tWR + tRP * * Begin AutoPrecharge Bank can be reactivated at completion of tDAL Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3) 8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A10-A0 = Register Data) The mode register stores the data for controlling the various operating modes of SDRAM. The Mode Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode register to make SDRAM useful for a variety of different applications. The default values of the Mode Register after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of pins BS0,1 and A10~A0 in the same cycle is the data written to the mode register. One clock cycle is required to complete the write in the mode register (refer to the following figure). The contents of the mode register can be changed using the same command and the clock cycle requirements during operation as long as all banks are in the idle state. TM Technology Inc. reserves the right P. 11 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 CLK tCK2 CKE Clock min. CS# RAS# CAS# WE# Address Key ADDR. DQM tRP DQ Hi-Z PrechargeAll Mode Register Set Command Any Command Mode Register Set Cycle (CAS# Latency = 2, 3) The mode register is divided into various fields depending on functionality. Address BS0,1 Function RFU* A10/AP A9 RFU* WBL A8 A7 A6 Test Mode A5 A4 CAS Latency A3 BT A2 A1 A0 Burst Length *Note: RFU (Reserved for future use) should stay "0" during MRS cycle. * Burst Length Field (A2~A0) This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2, 4, 8, or full page. A2 A1 A0 Burst Length 0 0 0 1 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Full Page TM Technology Inc. reserves the right P. 12 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B * Burst Type Field (A3) The Burst Type can be one of two modes, Interleave Mode or Sequential Mode. A3 Burst Type 0 Sequential 1 Interleave --- Addressing Sequence of Sequential Mode An internal column address is performed by increasing the address from the column address which is input to the device. The internal column address is varied by the Burst Length as shown in the following table. When the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are effective. Data n 0 1 2 3 4 5 6 7 - 255 256 257 - Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - N+255 n n+1 - 2 words: Burst Length 4 words: 8 words: Full Page: Column address is repeated until terminated. --- Addressing Sequence of Interleave Mode A column access is started in the input column address and is performed by inverting the address bits in the sequence shown in the following table. Data n Column Address Burst Length Data 0 A7 A6 A5 A4 A3 A2 A1 A0 Data 1 A7 A6 A5 A4 A3 A2 A1 A0# Data 2 A7 A6 A5 A4 A3 A2 A1# A0 Data 3 A7 A6 A5 A4 A3 A2 A1# A0# Data 4 A7 A6 A5 A4 A3 A2# A1 A0 Data 5 A7 A6 A5 A4 A3 A2# A1 A0# Data 6 A7 A6 A5 A4 A3 A2# A1# A0 Data 7 A7 A6 A5 A4 A3 A2# A1# A0# 4 words 8 words * CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC(min) CAS# Latency X tCK A6 A5 A4 CAS# Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 X X Reserved TM Technology Inc. reserves the right P. 13 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B * Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation. A8 A7 Test Mode 0 0 normal mode 0 1 Vendor Use Only 1 X Vendor Use Only * Write Burst Length (A9) This bit is used to select the burst write length. 9 A9 Write Burst Length 0 Burst 1 Single Bit No-Operation command (RAS# = "H", CAS# = "H", WE# = "H") The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low). This prevents unwanted commands from being registered during idle or wait states. 10 Burst Stop command (RAS# = "H", CAS# = "H", WE# = "L") The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the following figure. T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 T8 NOP NOP NOP NOP CLK READ A COMMAND NOP Burst Stop The burst ends after a delay equal to the CAS# latency. CAS# latency=2 tCK2, DQ's DOUT A0 CAS# latency=3 tCK3, DQ's DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 Termination of a Burst Read Operation (Burst Length * 4, CAS# Latency = 2, 3) T0 T1 T2 T3 T4 NOP NOP Burst Stop DIN A1 DIN A2 don't care T5 T6 T7 T8 NOP NOP NOP NOP CLK NOP COMMAND CAS# latency= 2, 3 DQ's WRITE A DIN A0 Input data for the Write is masked. Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3) TM Technology Inc. reserves the right P. 14 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No Operation command. 12 AutoRefresh command (RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BS0,1 = "Don`t care, A0-A10 = Don't care) The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 4096 times within 64ms. The time required to complete the auto refresh operation is specified by tRC(min.). To provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive auto refresh operations are performed. 13 SelfRefresh Entry command (RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A10 = Don't care) The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on CKE (SelfRefresh Exit command). 14 SelfRefresh Exit command (CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H") This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or Device Deselect commands must be issued for tRC(min.) because time is required for the completion of any bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation, a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the SelfRefresh mode. 15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L") When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period (64ms) since the command does not perform any refresh operations. 16 Clock Suspend Mode Exit / PowerDown Mode Exit command When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock cycle from the end of this command. 17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H") During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device selection, byte selection and bus control in a memory system. TM Technology Inc. reserves the right P. 15 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Absolute Maximum Rating Leaded Package Lead Free Package Symbol Item Unit Note VIN, VOUT Input, Output Voltage -1~4.6 V 1 VDD, VDDQ Power Supply Voltage - 1~4.6 V 1 TOPR Operating Temperature 0~70 C 1 TSTG Storage Temperature - 55~150 C 1 TSOLDER Soldering Temperature (10s) C 1 PD Power Dissipation 1 W 1 IOUT Short Circuit Output Current 50 mA 1 240 260 Recommended D.C. Operating Conditions (Ta = 0~70C) Symbol Parameter Min. Typ. Max. Unit Note VDD Power Supply Voltage 3.0 3.3 3.6 V 2 VDDQ Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2 VIH LVTTL Input High Voltage 2.0 - VDDQ + 0.3 V 2 VIL LVTTL Input Low Voltage - 0.3 - 0.8 V 2 Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25C) Symbol CI CI/O Parameter Min. Max. Unit Input Capacitance - 4.5 pF Input/Output Capacitance - 6.5 pF Note: These parameters are periodically sampled and are not 100% TM Technology Inc. reserves the right P. 16 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Recommended D.C. Operating Conditions (VDD = 3.3V 0.3V, Ta = 0~70C) Description/Test condition Operating Current 1 bank tRC tRC(min), Outputs Open, Input operation signal one transition per one cycle Precharge Standby Current in power down mode tCK = 15ns, CKE VIL(max) Precharge Standby Current in power down mode tCK = , CKE VIL(max) Precharge Standby Current in non-power down mode tCK = 15ns, CS# VIH(min), CKE VIH Input signals are changed once during 30ns. Precharge Standby Current in non-power down mode tCK = , CLK VIL(max), CKE VIH Active Standby Current in power down mode CKE VIL(max), tCK = 15ns Active Standby Current in power down mode CKE & CLK VIL(max), tCK = Active Standby Current in non-power down mode CKE VIH(min), CS# VIH(min), tCK = 15ns Active Standby Current in non-power down mode CKE VIH(min), CLK VIL(max), tCK = Operating Current (Burst mode) tCK =tCK(min), Outputs Open, Multi-bank interleave Refresh Current tRC TrC(min) Self Refresh Current CKE 0.2V Symbol - 5/5.5/6/7/8/10 Max. ICC1 200/190/180/155/135/120 3 ICC2P 3 3 ICC2PS 3 ICC2N 25 ICC2NS 15 ICC3P 5 ICC3PS 5 ICC3N 40 ICC3NS 30 ICC4 225/215//200/180/150/130 3, 4 ICC5 260/240/220/210/190/180 3 ICC6 2 Unit 3 mA 3 3 Parameter Description Min. Max. Unit IIL Input Leakage Current ( 0V*VIN*VDD, All other pins not under test = 0V ) - 1.5 1.5 uA VOH LVTTL Output "H" Level Voltage ( IOUT = -2mA ) 2.4 - V VOL LVTTL Output "L" Level Voltage ( IOUT = 2mA ) - 0.4 V TM Technology Inc. reserves the right P. 17 to change products or specifications without notice. Note Note Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Electrical Characteristics and Recommended A.C. Operating Conditions (VDD = 3.3V 0.3V, Ta = 0~70C) (Note: 5, 6, 7, 8) - 5/5.5/6/7/8/10 Symbol tRC tRRD tRCD tRP tRAS tCK2 A.C. Parameter Min. Row cycle time (same bank) Row activate to row activate delay (different banks) RAS# to CAS# delay (same bank) Precharge to refresh/row activate command (same bank) Row activate to precharge time (same bank) Clock cycle time CL* = 2 Unit Note 55/55/60/70/80/100 9 10/11/12/14/16/20 9 18/18/18/21/24/30 9 15/16.5/18/21/24/30 9 35/38.5/42/49/56/70 9 100,000 -/-/10/10/ - / - CL* = 3 tCK3 Max. ns 5/5.5/6/7/8/10 tAC2 Access time from CLK CL* = 2 -/-/6/6/-/- tAC3 (positive edge) CL* = 3 4.5/5/5.5/5.5/6/6 tOH Data output hold time tCH 9 2/2/2/2.5/2.5/2.5 9 Clock high time 2/2/2.5/3/3/3.5 10 tCL Clock low time 2/2/2.5/3/3/3.5 10 tIS Data/Address/Control Input set-up time 1.5/1.5/1.5/1.75/2/2.5 10 tIH Data/Address/Control Input hold time 1 10 tLZ Data output low impedance 1 9 tHZ2 Data output high impedance tHZ3 tWR Write recovery time tCCD CAS# to CAS# Delay time tMRS Mode Register Set cycle time CL* = 2 -/-/6/6/-/- CL* = 3 4.5/5/5.5/5.5/6/6 8 2 2/1/1/1/1/1 CLK 2 * CL is CAS# Latency. Note: 1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. 2. All voltages are referenced to VSS. VIL(Max) = VDDQ+1.0V for pulse width < 2ns. VIL(Min) = -1.0V for pulse width < 2.0ns 3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of tCK and tRC. Input signals are changed one time during tCK. 4. These parameters depend on the output loading. Specified values are obtained with the output open. 5. Power-up sequence is described in Note 11. TM Technology Inc. reserves the right P. 18 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B 6. A.C. Test Conditions LVTTL Interface Reference Level of Output Signals 1.4V / 1.4V Output Load Reference to the Under Output Load (B) Input Signal Levels 2.4V / 0.4V Transition Time (Rise and Fall) of Input Signals 1ns Reference Level of Input Signals 1.4V 1.4V 3.3V 50 1.2k Z0= 5 0 Output Output 30pF 30pF 870 LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B) 7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1 ns). 8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels. 9. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter. 10. Assumed input rise and fall time tT ( tR & tF ) = 1 ns If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be added to the parameter. 11. Power up Sequence Power up must be performed in the following sequence. 1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both CKE = "H" and DQM = "H." The CLK signals must be started at the same time. 2) After power-up, a pause of 200 seconds minimum is required. Then, it is recommended that DQM is held "HIGH" (VDD levels) to ensure DQ output is in high impedance. 3) All banks must be precharged. 4) Mode Register Set command must be asserted to initialize the Mode register. 5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device. TM Technology Inc. reserves the right P. 19 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Timing Waveforms Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCL tCH tCK2 t IS CKE t IS Begin AutoPrecharge Bank A Begin AutoPrecharge Bank B t IH t IS CS# RAS# CAS# WE# BS0,1 t IH t IS ADDR. CAx RBx RBx CBx RAy RAz CAy RBy DQM tRCD tDAL tRC t IS DQ Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Activate Write with Activate Write with Activate Command AutoPrecharge Command AutoPrecharge Command Bank A Command Bank B Command Bank A Bank A Bank B t WR tRP t IH Hi-Z Bx3 Ay0 Write Command Bank A TM Technology Inc. reserves the right P. 20 to change products or specifications without notice. Ay1 Ay2 tRRD Ay3 Precharge Activate Command Command Bank A Bank A Activate Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 CLK tCK2 tCH tCL CKE Begin AutoPrecharge Bank B t IS t IH tIH t IS CS# RAS# CAS# WE# BS0,1 t IH A10 RBx RAx RAy t IS A0-A11 RAx CAx CBx RBx RAy tRRD tRAS tRC DQM tAC2 t LZ tRCD Hi-Z DQ tAC2 Ax0 tRP t HZ Ax1 Bx0 tHZ t OH Activate Command Bank A Read Command Bank A Activate Command Bank B TM Technology Inc. reserves the right P. 21 to change products or specifications without notice. Bx1 Read with Auto Precharge Command Bank B Precharge Command Bank A Activate Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx DQM tRP tRC CAx tRC Ax0 Ax1 DQ PrechargeAll Command AutoRefresh Command AutoRefresh Command TM Technology Inc. reserves the right P. 22 to change products or specifications without notice. Activate Command Bank A Ax2 Ax3 Read Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 4. Power on Sequence and Auto Refresh (CBR) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High level is reauired Minimum of 2 Refresh Cycles are required CS# RAS# CAS# WE# BS0,1 A10 Address Key A0-A9 DQM tRP DQ tRC Hi-Z PrechargeALL Command Inputs must be stable for 200 s 1st AutoRefresh Command Mode Register Set Command 2nd Auto Refresh Command TM Technology Inc. reserves the right P. 23 to change products or specifications without notice. Any Command Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 5. Self Refresh Entry & Exit Cycle T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CLK *Note 2 *Note 4 *Note 1 tRC(min) tPDE *Note 3 CKE *Note 7 tSRX *Note 5 t IS *Note 6 CS# RAS# *Note 8 *Note 8 CAS# BS0,1 A0-A9 WE# DQM DQ Hi-Z Self Refresh Enter Hi-Z SelfRefresh Exit AutoRefresh Note: To Enter SelfRefresh Mode 1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in SelfRefresh mode as long as CKE stays "low". 4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh. 5. 6. 7. 8. 9. To Exit SelfRefresh Mode System clock restart and be stable before returning CKE high. Enable CKE and CKE should be set high for minimum time of tSRX. CS# starts from high. Minimum tRC is required after CKE going high to complete SelfRefresh exit. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the uses burst refresh. TM Technology Inc. reserves the right P. 24 to change products or specifications without notice. system Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T 7 T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM t HZ DQ Hi-Z Ax3 Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock TM Technology Inc. reserves the right P. 25 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RAx RAx CAx DQM t HZ DQHi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Clock Suspend 1 Cycle Ax2 Clock Suspend 2 Cycles Ax3 Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock TM Technology Inc. reserves the right P. 26 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T 1 T 2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 A0-A9 RAx RAx CAx DQM tHZ DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles Ax3 Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock TM Technology Inc. reserves the right P. 27 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = 1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM DQ Hi-Z DAx0 DAx1 Activate Clock Suspend Command 1 Cycle Bank A Write Command Bank A DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Note: CKE to CLK disable/enable = 1 clock TM Technology Inc. reserves the right P. 28 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9 RAx CAx DQM DQHi-Z DAx0 Activate Command Bank A DAx1 Clock Suspend Clock Suspend 1 Cycle 2 Cycles DAx2 DAx3 Clock Suspend 3 Cycles Write Command Bank A Note: CKE to CLK disable/enable = 1 clock TM Technology Inc. reserves the right P. 29 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM DQ Hi-Z DAx0 Activate Command Bank A DAx1 DAx2 Clock Suspend Clock Suspend 1 Cycle 2 Cycles DAx3 Clock Suspend 3 Cycles Write Command Bank A Note: CKE to CLK disable/enable = 1 clock TM Technology Inc. reserves the right P. 30 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 8. Power Down Mode and Clock Mask (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 tPDE t IS CKE Valid CS# RAS# CAS# WE# BS0,1 RAx A10 RAx A0~A9 CAx DQM tHZ Hi-Z Ax0 DQ ACTIVE STANDBY Activate Read Command Command Bank A Bank A Power Down Power Down Mode Entry Mode Exit Ax1 Clock Mask Start Ax2 Clock Mask End TM Technology Inc. reserves the right P. 31 to change products or specifications without notice. Ax3 Precharge Command Bank A Power Down Mode Entry PRECHARGE STANDBY Power Down Mode Exit Any Command Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BA0,1 A10 A0~A9 RAz RAw RAw CAw CAx CAy RAz CAz DQM DQHi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Aw3Ax0 Read Command Bank A Ax1 Read Command Bank A Ay0 Ay1Ay2 Ay3 Az0 Az1Az2 Az3 Precharge Read Command Command Bank A Bank A Activate Command Bank A TM Technology Inc. reserves the right P. 32 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BA0,1 A10 A0~A9 RAz RAw RAw CAw CAx RAz CAy CAz DQM DQHi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Read Command Bank A Aw3 Ax0 Ax1 Ay0 Ay1 Read Command Bank A TM Technology Inc. reserves the right P. 33 to change products or specifications without notice. Ay2 Az0 Ay3 Precharge Activate Command Command Bank A Bank A Az1 Az2 Az3 Read Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RAz RAw RAw CAw CAy CAx RAz CAz DQM DQHi-Z Aw0 Activate Command Bank A Read Command Bank A Aw1 Aw2 Read Command Bank A Aw3 Ax0 Ax1 Read Command Bank A TM Technology Inc. reserves the right P. 34 to change products or specifications without notice. Ay0 Az0 Ay1 Precharge Command Bank A Ay2 Ay3 Activate Command Bank A Read Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RBz RBw RBw CBw CBy CBx RBz CBz DQM Hi-Z DQ DBw0DBw1DBw2 Activate Command Bank A Write Command Bank B DBw3 DBx0 DBx1 DBy0 DBy1 Write Command Bank A Write Command Bank B DBy2 DBy3 Precharge Command Bank B Activate Command Bank B TM Technology Inc. reserves the right P. 35 to change products or specifications without notice. DBz0 DBz1 DBz2 DBz3 Write Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 RBz RBw A10 A0~A9 RBw CBw CBx CBy RBz CBz DQM DQ Hi-Z DBw0 Activate Command Bank A Write Command Bank B DBw1 DBw2 DBw3 DBx0 Write Command Bank B DBx1DBy0 DBy1 DBy2 DBy3 Write Command Bank B TM Technology Inc. reserves the right P. 36 to change products or specifications without notice. Precharge Activate Command Command Bank B Bank B DBz0 DBz1DBz2 DBz3 Write Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 RBz RBw A10 A0~A9 RBw CBw CBx CBy RBz CBz DQM DQ Hi-Z DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Activate Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B TM Technology Inc. reserves the right P. 37 to change products or specifications without notice. DBz0 DBz1 DBz2 Precharge Command Bank B Activate Command Bank B Write Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BS0,1 RBx A10 RAx RAx RBx CBx A0~A9 RBy RBy CAx CBy tRCD tRP tAC1 DQM DQHi-Z Bx0 Activate Command Bank B Read Command Bank B Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Activate Command Bank A Precharge Command Bank B Activate Read Command Command Bank B Bank A TM Technology Inc. reserves the right P. 38 to change products or specifications without notice. Ax4 Ax5 Ax6 Ax7 By0 Read Command Bank B By1 By2 Precharge Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RBx A0~A9 RBx RAx RAx CBx tRCD RBy RBy CAx tAC2 tRP DQM Hi-Z DQ Activate Command Bank B Bx0 Read Command Bank B CBy Bx1 Bx2 Bx3 Bx4 Activate Command Bank A Bx5 Bx6 Bx7 Ax0 Precharge Command Bank B Read Command Bank A TM Technology Inc. reserves the right P. 39 to change products or specifications without notice. Ax1 Activate Command Bank B Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 By1 Read Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 High CKE CS# RAS# CAS# WE# BS0,1 A10 RBx RAx RBx A0~A9 RAx CBx tRCD RBy RBy CAx tAC3 tRP DQM Hi-Z DQ Activate Command Bank B Bx0 Read Command Bank B CBy Bx1 Bx2 Bx3 Activate Command Bank A Bx4 Bx5 Bx6 Read Command Bank A TM Technology Inc. reserves the right P. 40 to change products or specifications without notice. Ax7 Bx7 Precharge Command Bank B Ax0 Ax1 Ax2 Ax3 Activate Command Bank B Ax4 By0 Ax5 Ax6 Read Command Bank B Precharge Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx RBx RAy RBx CBx RAy tRCD tRP CAy tWR DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Write Command Bank A DAx4 DAx5DAx6 DAx7 DBx0 DBx1 DBx2 DBx3DBx4 DBx5 DBx6 DBx7 Activate Command Bank B Write Command Bank B TM Technology Inc. reserves the right P. 41 to change products or specifications without notice. Precharge Command Bank A Activate Command Bank A DAy0 DAy1 DAy2 DAy3 Precharge Command Bank B Write Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RAy RBx CAx RBx RAy CBx tRCD tWR* tRP CAy tWR* DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DAx4DAx5 Activate Write Command Command Bank A Bank A DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4DBx5 DBx6 DBx7 DAy0 DAy1DAy2 Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A DAy3 DAy4 Write Command Bank A Precharge Command Bank B * tWR > tWR(min.) TM Technology Inc. reserves the right P. 42 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBx CAx RAy CBx RBx tRCD RAy tWR* CAy tRP tWR* DQM Hi-Z DQ Activate Command Bank A DAx0DAx1 DAx2 DAx3DAx4 DAx5 Write Command Bank A DAx6 DAx7 DBx0 DBx1DBx2 Activate Command Bank B Write Command Bank B DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 Precharge Command Bank A Activate Command Bank A Write Command Bank A DAy1 DAy2 DAy3 Precharge Command Bank B * tWR > tWR(min.) TM Technology Inc. reserves the right P. 43 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RAx RAx CAx CAy CAz DQM DQ Hi-Z Ax0 Ax1 Activate Command Bank A Read Command Bank A Ax2 Ax3 DAy0DAy1 DAy3 Az0 Read The Write Data Write Command is Masked with a Command Bank A Zero Clock Bank A Latency TM Technology Inc. reserves the right P. 44 to change products or specifications without notice. Az3 Az1 The Read Data is Masked with a Two Clock Latency Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx CAz CAy DQM DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency TM Technology Inc. reserves the right P. 45 to change products or specifications without notice. Az0 Read Command Bank A Az1 Az3 The Read Data is Masked with a Two Clock Latency Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAy CAx CAz DQM DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Write The Write Data Command is Masked with a Bank A Zero Clock Latency TM Technology Inc. reserves the right P. 46 to change products or specifications without notice. Az0 Read Command Bank A Az1 Az3 The Read Data is Masked with a Two Clock Latency Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx RAx A0~A9 RBw CBw CBx Ax3 Bw0 Bw1 CBy CAy CBz tRCD tAC1 DQM DQ RBw Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Activate Command Bank B Read Command Bank B Bx0 Bx1 Read Command Bank B By0 Read Command Bank B By1 Ay0 Read Command Bank A TM Technology Inc. reserves the right P. 47 to change products or specifications without notice. Ay1 Bz0 Read Command Bank B Bz1 Bz2 Bz3 Precharge Command Bank A Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAy tRCD DQM DQ RAx Hi-Z RAx Read Command Bank A CBx CBy CAy CBz By0 By1 Ay0 tAC2 Ax0 Activate Command Bank A CBw Ax1 Ax2 Activate Command Bank B Ax3 Bw0 Read Read Command Command Bank B Bank B Bw1 Bx0 Bx1 Read Command Bank B TM Technology Inc. reserves the right P. 48 to change products or specifications without notice. Read Command Bank A Ay1 Read Command Bank B Precharge Command Bank A Bz0 Bz1 Bz2 Bz3 Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBx CAx tRCD DQM RBx CBx CBz CAy tAC3 DQHi-Z Ax0 Activate Command Bank A CBy Read Command Bank A Activate Command Bank B Ax1 Ax2 Read Command Bank B Ax3 Bx0 Read Command Bank B Bx1 By0 By1 Read Command Bank B TM Technology Inc. reserves the right P. 49 to change products or specifications without notice. Bz0 Bz1 Ay0 Read Prechaerge CommandCommand Bank A Bank B Ay1 Ay2 Ay3 Precharge Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw A0~A9 RAx CAx RBw CBw CBx CBy CBz CAy tRP tWR tRP tRCD DQM tRRD DQ Hi-Z DAx0 Activate Command Bank A DAx1 DAx2 DAx3 DBw0DBw1 DBx0 DBx1 DBy0 Activate Command Bank B Write Command Bank B Write Command Bank B DBy1 DAy0 Write Command Bank B DAy1 Write Command Bank A Write Command Bank A TM Technology Inc. reserves the right P. 50 to change products or specifications without notice. DBz0 DBz1 Write Command Bank B Precharge Command Bank A DBz2 DBz3 Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBw CAx RBw CBw CBx CBy CAy tRCD DQM CBz tRP tWR tRP tRRD DQ Hi-Z DAx0DAx1 DAx2 Activate Command Bank A Write Command Bank A Activate Command Bank B DAx3DBw0 DBw1 DBx0 Write Command Bank B Write Command Bank B DBx1DBy0 DBy1DAy0 DAy1 DBz0 DBz1 DBz2 Write Command Bank B TM Technology Inc. reserves the right P. 51 to change products or specifications without notice. Write Command Bank A Write Command Bank B Precharge Command Bank A DBz3 Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw A0~A9 RAx CAx RBw CBw CBx CBy CAy tRCD DQM CBz tWR tRP tWR(min) tRRD > tRRD(min) DQ Hi-Z DAx0 DAx1 DAx2 DAx3DBw0 Activate Command Bank A Activate Command Bank B Write Command Bank A DBw1DBx0 DBx1 DBy0 DBy1 DAy0 DAy1 DBz0 DBz1 DBz2 DBz3 Write Command Bank B Write Command Bank B Write Command Bank B TM Technology Inc. reserves the right P. 52 to change products or specifications without notice. Write Command Bank A Write Command Bank B Precharge Command Bank A Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBy RBx CAx RBx CBx CAy RBz RBy CBy RBz CBz DQM DQ Hi-Z Ax0 Activate Command Bank A Read Command Bank A Ax1 Ax2 Ax3 Bx0 Activate Command Bank B Read with Auto Precharge Command Bank B Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 Activate Command Bank B Read with Auto Precharge Command Bank A TM Technology Inc. reserves the right P. 53 to change products or specifications without notice. By0 Read with Auto Precharge Command Bank B By1 By2 By3 Bz0 Bz1 Bz2 Bz3 Activate Command Bank B Read with Auto Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBx CAx RAz RBy RBx CBx RAy RBy CBy RAz CAz DQM DQ Hi-Z Activate Command Bank A Ax0 Read Command Bank A Ax1 Ax2 Ax3 Read with Activate Command Auto Precharge Command Bank B Bank B Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 By0 By1 By2 By3 Az0 Az1 Az2 Read with Activate Read with Activate Read with Auto Precharge Command Auto Precharge Command Auto Precharge Command Bank B Command Bank A Command Bank A Bank B Bank A TM Technology Inc. reserves the right P. 54 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx RBx A0~A9 RAx CAx RBx RBy CBx CAy CBy RBy DQM DQ Hi-Z Activate Command Bank A Ax0 Activate Command Bank B Read Command Bank A Ax1 Ax2 Read with Auto Precharge Command Bank B Ax3 Bx0 Bx1 Bx2 Read with Auto Precharge Command Bank A TM Technology Inc. reserves the right P. 55 to change products or specifications without notice. Bx3 Ay0 Activate Command Bank B Ay1 Ay2 Ay3 By0 By1 By2 By3 Read with Auto Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RAx RBx RAx CAx RBx RBy CBx CAy RBy RAz RAz CBy CAz DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2DBx3 DAy0 DAy1DAy2 DAy3 DBy0 Activate Command Bank A Write Command Bank A Activate Write with Command Auto Precharge Bank B Command Bank B Write with Auto Precharge Command Bank A DBy1 DBy2 DBy3 Activate Write with Command Auto Precharge Bank B Command Bank B TM Technology Inc. reserves the right P. 56 to change products or specifications without notice. DAz0 DAz0 DAz0DAz0 Activate Command Bank A Write with Auto Precharge Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RAx RAx RBy RBx CAx RBx CBx CAy RBy RAz CAz CBy RAz DBy0 DBy1 DBy2 DBy3DAz0 DAz1 DAz2 DAz3 DQM DQ Hi-Z DAx0 DAx1 DAx2 DAx3 DBx0 DBx1DBx2 DBx3 DAy0 DAy1DAy2 DAy3 Activate Write Command Command Bank A Bank A Activate Write with Command Auto Precharge Bank B Command Bank B Write with Auto Precharge Command Bank A TM Technology Inc. reserves the right P. 57 to change products or specifications without notice. Activate Write with Write with Activate Command Auto Precharge Command Auto Precharge Bank B Command Command Bank A Bank B Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A9 RAx RBx A0~A9 RAx CAx RBx RBy CBx CAy RBy CBy DQM DQHi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 Activate Command Bank B Write Command Bank A Write with Auto Precharge Command Bank B Write with Auto Precharge Command Bank A TM Technology Inc. reserves the right P. 58 to change products or specifications without notice. DAy2 DAy3 Activate Command Bank B DBy0 DBy1 DBy2DBy3 Write with Auto Precharge Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BS0,1 RAx A10 A0~A9 RAx RBx CAx RBy RBx RBy CBx tRP tRRD DQM DQHi-Z Ax Activate Command Bank A Ax+1 Ax+2 Ax-2 Ax-1 Activate Command Bank B The burst counter wraps from the highest order Read page address back to zero Command during this time interval Bank A Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Read Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. TM Technology Inc. reserves the right P. 59 to change products or specifications without notice. Bx+6 Bx+7 Precharge Command Bank B Activate Burst Stop Command Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 RBx RAx A10 RAx A0~A9 CAx RBy CBx RBx RBy tRP DQM DQHi-Z Activate Command Bank A Ax Read Command Bank A Ax+1 Ax+2Ax-2 Ax-1 Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4Bx+5 Bx+6 Activate Read Precharge Full Page burst operation does not Command Command Command Bank B Bank Bterminate when the burst length is satisfied; Bank B The burst counter wraps the burst counter increments and continues from the highest order bursting beginning with the starting address. page address back to zero Burst Stop during this time interval Command TM Technology Inc. reserves the right P. 60 to change products or specifications without notice. Activate Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBx CAx RBy RBy CBx RBx tRP DQM DQ Hi-Z Activate Command Bank A Ax Read Command Bank A Activate Command Bank B Ax+1 Ax+2 Ax-2 Ax-1 Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval Ax Ax+1 Bx Bx+1 Bx+2 Bx+3 Bx+4 Bx+5 Precharge Full Page burst operation does not Command terminate when the burst length is Bank B satisfied; the burst counter increments and continues bursting beginning with the Burst Stop starting address. Command TM Technology Inc. reserves the right P. 61 to change products or specifications without notice. Activate Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBx CAx RBx RBy RBy CBx DQM DQ Hi-Z DBx DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 Activate Command Bank B The burst counter wraps from the highest order Write page address back to zero Command during this time interval Bank A Activate Command Bank A DBx+ 1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+ 6 DBx+ 7 Write Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. TM Technology Inc. reserves the right P. 62 to change products or specifications without notice. Data is ignored Precharge Command Bank B Burst Stop Activate Command Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RAx RAx RBx CAx RBx RBy RBy CBx DQM DQ Hi-Z Activate Command Bank A DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx DAx+ 1 DBx Write Command Bank A DBx+ 1DBx+ 2 DBx+ 3 Activate Write Command Command Bank B Bank B The burst counter wraps Full Page burst operation does not terminate when the burst from the highest order page address back to zero length is satisfied; the burst counter increments and continues bursting during this time interval beginning with the starting address. TM Technology Inc. reserves the right P. 63 to change products or specifications without notice. DBx+ 4 DBx+ 5 DBx+ 6 Data is ignored Precharge Command Bank B Burst Stop Command Activate Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBx CAx RBy RBx RBy CBx DQM Data is ignored DQ Hi-Z Activate Command Bank A DAx DAx+ 1 DAx+ 2 DAx+ 3 DAx- 1 DAx Write Command Bank A DAx+ 1 DBx DBx+ 1 DBx+ 2 DBx+ 3 Activate Write Command Command Bank B Bank B The burst counter wraps Full Page burst operation does from the highest order page address back to zero not terminate when the burst length is satisfied; the burst counter during this time interval increments and continues bursting beginning with the starting address. TM Technology Inc. reserves the right P. 64 to change products or specifications without notice. DBx+ 4 DBx+ 5 Precharge Command Bank B Burst Stop Command Activate Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RAx RAx CAy CAx CAz LDQM UDQM DQ0 - DQ7 Ax0 Ax1 Ax1 DQ8 - DQ15 Activate Command Bank A ReadUpper 3 Bytes are masked Command Bank A DAy1DAy2 Ax2 Ax2 Lower Byte is masked Ax3 DAy0 DAy1 DAy3 Write Upper 3 Bytes Read Command are masked Command Bank A Bank A TM Technology Inc. reserves the right P. 65 to change products or specifications without notice. Az0 Az1 Az2 Az1 Az2 Lower Byte is masked Az3 Lower Byte is masked Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 21. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE High Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A Begin Auto Precharge Bank B Begin Auto Precharge Bank A CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RAu RBu CBu RBu RAu CAu RBv RAv RBv CBv RAv tRP DQM DQ Bu0 Activate Command Bank B Read Bank B with Auto Precharge Au1 Activate Command Bank B Read Bank A with Auto Precharge CAv tRP Bu1 Au0 Activate Command Bank A RBw Activate Command Bank A Read Bank B with Auto Precharge RBw tRP Bv0 Bv1 CBw Activate Command Bank A Read Bank B with Auto Precharge CBx RAx CAx tRP Av1 Bw0 Bw1 Activate Command Bank B RAx RAw CAw RBx tRP Av0 Read Bank A with Auto Precharge RBx RAw tRP Aw0 Activate Command Bank B Read Bank A with Auto Precharge TM Technology Inc. reserves the right P. 66 to change products or specifications without notice. Aw1Bx0 Read Bank B with Auto Precharge RAy RBy CBy RAy CAy RBz tRP Bx1 Activate Command Bank A RBz RBy tRP Read Bank A with Auto Precharge tRP By1 Ay0 Ay1 Activate Command Bank A Read Bank B with Auto Precharge CBz RAz tRP Ax0 Ax1 By0 Activate Command Bank B RAz Activate Command Bank B Read Bank A with Auto Precharge Bz0 Activate Command Bank A Read Bank B with Auto Precharge Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RBx RBx RBw CAx CBx CAy CBy CAz CBz RBw tRP DQM tRRD tRCD DQ Ax0 Activate Command Bank A Activate Command Bank B Bx0 Ay0 Ay1 Read Read Command Command Bank B Read Bank B Command Read Bank A Command Bank A By0 By1 Read Command Bank A TM Technology Inc. reserves the right P. 67 to change products or specifications without notice. Az0 Az1 Read Command Bank B Az2 Bz0 Bz1 Bz2 Precharge Command Bank B (Precharge Temination) Activate Command Bank B Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE CS# RAS# CAS# WE# BS0,1 A10 A0~A9 RAx RBx RAx RBw RBx CAx CBx CAy CAz CBy CBz RBw tWR tRP DQM tRRD tRCD DQ DAx0DBx0DAy0 Activate Command Bank A DAy1 DBy0 DBy1 Write Command Bank B Write Write Command Command Bank A Bank A Activate Command Bank B Write Command Bank B DAz0 DAz1 DAz2 DBz0 DBz1 Write Command Bank A TM Technology Inc. reserves the right P. 68 to change products or specifications without notice. Write Command Bank B DBz2 Precharge Command Bank B (Precharge Temination) Activate Write Data Command Bank B is masked Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAy RAz CAy A0~A9 RAx CAx RAy RAz CAz tRP tWR tRP Precharge Termination of a Read Burst. DQM DQ DAz6 DAz7 DAx0 DAx1 DAx2 DAx3 DAx4 Ay0 Read Activate Precharge Termination Precharge Command Command Command of a Write Burst. Bank A Bank A Write data is masked. Bank A Write Activate Command Command Bank A Bank A TM Technology Inc. reserves the right P. 69 to change products or specifications without notice. DAz0 Ay1 Ay2 Precharge Command Bank A DAz1 DAz2 DAz3 DAz4 DAz5 Write Command Bank A Activate Command Bank A Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 24.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency=2) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK2 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RAz RAy RAy CAx RAz CAy tWR tRP CAz tRP tRP DQM DQ DAx0 DAx1 DAx2 DAx3 Activate Command Bank A Write Precharge Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked. Ay0 Ay1 Activate Command Bank A Read Command Bank A TM Technology Inc. reserves the right P. 70 to change products or specifications without notice. Ay2 Precharge Command Bank A Az0 Activate Command Bank A Az1 Az2 Precharge Read Command Command Bank A Bank A Precharge Termination of a Read Burst Publication Date: FEB. 2007 Revision: A tm TE CH T436432B Figure 24.3. Precharge Termination of a Burst (Burst Length=4, 8 or Full Page, CAS# Latency=3) T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK tCK3 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx RAz RAy RAy CAx tWR CAy RAz tRP tRP DQM DQ Ay0 DAx0 DAx1 Activate Command Bank A Write Command Bank A Write Data is masked Precharge Command Bank A Activate Command Bank A Read Command Bank A Precharge Command Bank A Ay1 Ay2 Activate Precharge Termination Command of a Read Burst Bank A Precharge Termination of a Write Burst TM Technology Inc. reserves the right P. 71 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A tm TE CH T436432B 86 Pin TSOP II Package Outline Drawing Information 86 0.254 HE E 44 L L1 43 A1 A2 A D e Symbol A A1 A2 B C D E e HE L L1 S y L L1 y B S C 1 Min 0.002 0.037 0.007 0.87 0.395 - Dimension in inch Normal 0.004 0.039 0.008 0.005 0.875 0.400 0.0197 Max 0.047 0.006 0.041 0.009 0.88 0.405 - Min 0.05 0.95 0.17 22.09 10.03 - 0.455 0.016 0 0.463 0.020 0.0315 0.024 - 0.471 0.024 0.004 8 11.56 0.40 0 Dimension in mm Normal Max 1.20 0.10 0.15 1 1.05 0.2 0.23 0.127 22.22 22.35 10.16 10.29 0.50 11.76 0.50 0.80 0.61 - 11.96 0.60 0.10 8 Notes : 1. Dimension D&E do not include interlead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension : mm TM Technology Inc. reserves the right P. 72 to change products or specifications without notice. Publication Date: FEB. 2007 Revision: A