TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 1 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
SDRAM
2M x 32 SDRAM
512K x 32bit x 4Banks Synchronous DRAM
FEATURES
• 3.3V power supply
• Clock cycle time : 5 / 5.5 / 6 / 7 / 8 / 10 ns
• Internal four banks operation
• LVTTL compatible with multiplexed address
• All inputs are sampled at the positive going
edge of system clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto refresh and self refresh
• 64ms refresh period (4K cycle)
• MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length :
1 , 2 , 4 , 8 or full page for Sequential Burst
1 , 2 , 4 or 8 for Interleave Burst
• Available package type :
- 86 pin 400mil TSOP(II) and Lead free
• Operating temperature :
- 0 ~ +70 °C
PART NUMBER EXAMPLES
GRNERAL DESCRIPTION
The T436432B is 67,108,864 bits synchronous
high data rate Dynamic RAM organized as
4 x 524,288 words by 32 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
PART NO. CLOCK
CYCLE TIME MAX
FREQUENCY PACKAGE OPERATING
TEMPERATURE
T436432B-5SG 5ns 200 MHz TSOP-II Lead free 0 ~ +70 °C
T436432B-5S 5ns 200 MHz TSOP-II 0 ~ +70 °C
T436432B-55SG 5.5ns 183 MHz TSOP-II Lead free 0 ~ +70 °C
T436432B-55S 5.5ns 183 MHz TSOP-II 0 ~ +70 °C
T436432B-6SG 6ns 166 MHz TSOP-II Lead free 0 ~ +70 °C
T436432B-6S 6ns 166 MHz TSOP-II 0 ~ +70 °C
T436432B-7SG 7ns 143 MHz TSOP-II Lead free 0 ~ +70 °C
T436432B-7S 7ns 143 MHz TSOP-II 0 ~ +70 °C
T436432B-8SG 8ns 125 MHz TSOP-II Lead free 0 ~ +70 °C
T436432B-8S 8ns 125 MHz TSOP-II 0 ~ +70 °C
T436432B-10SG 10ns 100 MHz TSOP-II Lead free 0 ~ +70 °C
T436432B-10S 10ns 100 MHz TSOP-II 0 ~ +70 °C
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 2 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
PIN ARRANGEMENT
(TSOP-II Top View)
VDDQ
VDD
82
81
80
79
77
78
76
72
71
70
69
68
67
66
65
1
2
3
4
6
5
7
8
9
11
15
16
17
18
19
20
VDDQ
DQ11
DQ10
A8
A7
A9
10
21
22
83
84
85
86
DQ1
DQ2
N.C
BS0
DQ15
DQ14
VSSQ
Vss
23
24
25
64
63
62
VSSQ
DQ0
DQ3
DQ4
VDDQ
DQ5
DQ6
RAS
CS
BS1
A 10/A P
A0
VSSQ
DQ13
DQ12
DQ9
N.C
DQM1
N.C
A6
A5
A4
12
13
14
75
74
73
VSSQ
DQ7
N.C
DQ8
N.C
W E
CAS
86 PINTSO P(II)
(400m il)
DQM2
A1 26
27
28
29
31
30
32
33
34
36
40
41
42
43
35
VSSQ
N.C
DQ16
A2
VSSQ
DQ17
DQ18
VDDQ
DQ19
37
38
39
DQ20
VSSQ
DQ21
57
56
55
54
52
53
51
47
46
45
44
VDDQ
DQ30
DQ29
58
59
60
61
A3
DQM3
VSSQ
Vss
VSS
N.C
DQ31
DQ28
DQ25
CKE
DQ24
50
49
48
DQ27
VDDQ
DQ26
VDD
DQM0
VDD
DQ22
VDDQ
DQ23
VDD Vss
VDDQ
CLK
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tm
T436432B
TM Technology Inc. reserves the right P. 3 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
BLOCK DIAGRAM
Data Input Register
I/O Control Output Buffer
512K x 32
512K x 32
Sense AMP
Column Decoder
Latency & Burst Length
Programming Register
Bank Select
Row Buffeer
Refresh Counter
Row Decoder
Address Register
Col. Buffer
Timing Register
DQ
DQMRASCSCKECLK
ADD
CAS WE
512K x 32
512K x 32
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tm
T436432B
TM Technology Inc. reserves the right P. 4 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
PIN DESCRIPTION
PIN NAME INPUT FUNCTION
CLK System Clock
Active on the positive going edge to sample all input.
CS Chip Select Disables or enables device operation by masking or enabling all input
except CLK,CKE and DQM
CKE Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
Auot-precharge flag : A10/AP
BS0~1 Bank Select Address Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
RAS Row Address Strobe
Latches row addresses on the positive going edge of the CLK
with RAS low.
Enables row access & precharge.
CAS Column Address Strobe
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access .
WE Write Enable Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
DQM0~3 Data Input/Output
Mask
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ DQ31 Data Input/Output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power Supply/Ground
Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output
Power/Ground
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
N.C No Connection
No Connection.
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CH
tm
T436432B
TM Technology Inc. reserves the right P. 5 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows
the truth table for the operation commands.
Table 2. Trut h Table (Note (1), (2) )
Command State CKEn-1 CKEn DQM(6) BS0,1 A
10 A
9-0 CS# RAS# CAS# WE#
BankActivate Idle(3) H X X V Row address L L H H
BankPrecharge Any H X X V L X L L H L
PrechargeAll Any H X X X H X L L H L
Write Active(3) H X X V L L H L L
Write and AutoPrecharge Active(3) H X X V H
Column
address (A0
~ A7) L H L L
Read Active(3) H X X V L L H L H
Read and Autoprecharge Active(3) H X X V H
Column
address (A0
~ A7) L H L H
Mode Register Set Idle H X X OP code L L L L
No-Operation Any H X X X X X L H H H
Burst Stop Active(4) H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
AutoRefresh Idle H H X X X X L L L H
SelfRefresh Entry Idle H L X X X X L L L H
SelfRefresh Exit Idle L H X X X X H X X X
(SelfRefresh) L H H H
Clock Suspend Mode Entry Active H L X X X X X X X X
Power Down Mode Entry Any(5) H L X X X X H X X X
L H H H
Clock Suspend Mode Exit Active L H X X X X X X X X
Power Down Mode Exit Any L H X X X X H X X X
(PowerDown) L H H H
Data Write/Output Enable Active H X L X X X X X X X
Data Mask/Output Disable Active H X H X X X X X X X
Note: 1. V = Valid, X = Don't care, L = Logic low, H = Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
6. DQM0-3
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tm
T436432B
TM Technology Inc. reserves the right P. 6 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Commands
1 BankActivate
(RAS# = "L", CAS# = "H", WE# = "H", BS = Bank, A0-A10 = Row Address)
The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal. By
latching the row address on A0 to A10 at the time of this command, the selected row access is initiated. The
read or write operation in the same bank can occur after a time delay of tRCD(min.) from the time of bank
activation. A subsequent BankActivate command to a different row in the same bank can only be issued after
the previous active row has been precharged (refer to the following figure). The minimum time interval
between successive BankActivate commands to the same bank is defined by tRC(min.). The SDRAM has four
internal banks on the same chip and shares part of the internal circuitry to reduce chip area; therefore it restricts
the back-to-back activation of the four banks. tRRD(min.) specifies the minimum time required between
activating different banks. After this command is used, the Write command and the Block Write command
perform the no mask write operation.
CLK
ADDRESS
T0 T 1 T2 T3 Tn+3 Tn+4 Tn+5 Tn+6
..............
COMMAND
..............
..............
NOP NOP NOP NOP
RAS# - CAS# delay (tRCD)RAS# - RAS# delay time (tRRD)
RAS# Cycle time (tRC)
Bank A
Row Addr. Bank A
Col Addr. Bank B
Row Addr. Bank A
Row Addr.
Bank A
Activate R/W A with
AutoPrecharge Bank B
Activate Bank A
Activate
AutoPrecharge
Begin
: "H" or "L"
BankActivate Command Cycle (Burst Length = n, CAS# Latency = 3)
2 BankPrecharge command
(RAS# = "L", CAS# = "H", WE# = "L", BS = Bank, A10 = "L", A0-A9 = Don't care)
The BankPrecharge command precharges the bank disignated by BS0,1 signal. The precharged bank is
switched from the active state to the idle state. This command can be asserted anytime after tRAS(min.) is
satisfied from the BankActivate command in the desired bank. The maximum time any bank can be active is
specified by tRAS(max.). Therefore, the precharge function must be performed in any active bank within
tRAS(max.). At the end of precharge, the precharged bank is still in the idle state and is ready to be activated
again.
3 PrechargeAll command
(RAS# = "L", CAS# = "H", WE# = "L", BS = Don’t care, A10 = "H", A0-A9 = Don't care)
The PrechargeAll command precharges all the four banks simultaneously and can be issued even if all
banks are not in the active state. All banks are then switched to the idle state.
4 Read command
(RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "L", A0-A7 = Column Address)
The Read command is used to read a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least tRCD(min.) before the Read command is issued. During read
bursts, the valid data-out element from the starting column address will be available following the CAS#
latency after the issue of the Read command. Each subsequent data-out element will be valid by the next
positive clock edge (refer to the following figure). The DQs go into high-impedance at the end of the burst
unless other command is initiated. The burst length, burst sequence, and CAS# latency are determined by the
mode register which is already programmed. A full-page burst will continue until terminated (at the end of the
page it will wrap to column 0 and continue).
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CH
tm
T436432B
TM Technology Inc. reserves the right P. 7 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
CLK
COMMAND
C AS# latenc y=2
tCK2, DQ's
C AS# latenc y=3
tCK3, DQ's
T0T 1 T2T3 T4T5 T6T7 T8
READ A NOP NOP NOP NOP NOP NOP NOP NOP
DOUT A0DOUT A1DOUT A2DOUT A3
DOUT A0DOUT A1DOUT A2DOUT A3
Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3)
The read data appears on the DQs subject to the values on the DQM inputs two clocks earlier (i.e. DQM
latency is two clocks for output buffers). A read burst without the auto precharge function may be interrupted
by a subsequent Read or Write command to the same bank or the other active bank before the end of the burst
length. It may be interrupted by a BankPrecharge/ PrechargeAll command to the same bank too. The interrupt
coming from the Read command can occur on any clock cycle following a previous Read command (refer to
the following figure).
CLK
COMMAND
C AS# latenc y=2
tCK2, DQ's
C AS# latenc y=3
tCK3, DQ's
T0T 1 T2T3 T4T5 T6T7 T8
READ A READ B NOP NOP NOP NOP NOP NOP NOP
DOUT A0DOUT B0DOUT B1DOUT B2DOUT B3
DOUT A0DOUT B0DOUT B1DOUT B2DOUT B3
Read Interrupted by a Read (Burst Length = 4, CAS# Latency = 2, 3)
The DQM inputs are used to avoid I/O contention on the DQ pins when the interrupt comes from a Write
command. The DQMs must be asserted (HIGH) at least two clocks prior to the Write command to suppress
data-out on the DQ pins. To guarantee the DQ pins against I/O contention, a single cycle with high-impedance
on the DQ pins must occur between the last read data and the Write command (refer to the following three
figures). If the data output of the burst read occurs at the second clock of the burst write, the DQMs must be
asserted (HIGH) at least one clock prior to the Write command to avoid internal bus contention.
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 8 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
READ A NOP NOP NOP NOP WRITE B NOP NOP
CLK
DQM
COMMAND
DQ's
T0T 1 T2T3 T4T5 T6T7 T8
NOP
DOUT A0DINB0DINB1DINB2
Must be Hi-Z before
the Write Command
: "H" or "L" Read to Write Interval (Burst Length • 4, CAS# Latency = 3)
CLK
DQM
COMMAND
T0T 1 T2T3 T4T5 T6T7 T8
NOP NOP NOP NOP NOP NOP
BANKA
ACTIVATE
DIN A0DIN A1DIN A2DIN A3
1 Cl k In terv al
C AS# latenc y=2
tCK2, DQ's
READ A WR IT E A
: "H" or "L"
Read to Write Interval (Burst Length ≥
≥≥
≥ 4, CAS# Latency = 2)
CLK
DQM
COMMAND
T0T 1 T2T3 T4T5 T6T7 T8
NOP READ A NOP WR ITE B NOP NOP NOP
DIN B0DIN B1DIN B2DIN B3
C AS# latenc y=2
tCK2, DQ's
NOP NOP
: "H" or "L"
Read to Write Interval (Burst Length ≥
≥≥
≥ 4, CAS# Latency = 2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/ PrechargeAll
command to the same bank. The following figure shows the optimum time that BankPrecharge/ PrechargeAll
command is issued in different CAS# latency.
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 9 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
CLK
COMMAND
CAS# latency=2
tCK2, DQ's
T0T 1T2T3T4T5T6T7T8
READ A NOP NOP NOP NOP Activate NOP
NOP Precharge
CAS# latency=3
tCK3, DQ's
DOUT A0DOUT A1DOUT A2DOUT A3
DOUT A0DOUT A1DOUT A2DOUT A3
ADDRESS
tRP
Bank,
Col A Bank(s) Bank,
Row
Read to Precharge (CAS# Latency = 2, 3)
5 Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the read
operation. Once this command is given, any subsequent command cannot occur within a time delay of {tRP(min.)
+ burst length}. At full-page burst, only the read operation is performed in this command and the auto precharge
function is ignored.
6 Write command
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "L", A0-A7 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row in an
active bank. The bank must be active for at least tRCD(min.) before the Write command is issued. During write
bursts, the first valid data-in element will be registered coincident with the Write command. Subsequent data
elements will be registered on each successive positive clock edge (refer to the following figure). The DQs
remain with high-impedance at the end of the burst unless another command is initiated. The burst length and
burst sequence are determined by the mode register, which is already programmed. A full-page burst will
continue until terminated (at the end of the page it will wrap to column 0 and continue).
CLK
COMMAND
T0T 1T2T3T4T5T6T7T8
DIN A3
NOP WRITE A NOP NOP NOP NOP NOP
NOP NOP
DIN A0DIN A1DIN A2
DQ0 - DQ3
The first data element and the write
are registered on the same clock edge. Extra data is masked.
don't care
Burst Write Operation (Burst Length = 4, CAS# Latency = 1, 2, 3)
A write burst without the AutoPrecharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt coming from
Write command can occur on any clock cycle following the previous Write command (refer to the following
figure).
TE
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tm
T436432B
TM Technology Inc. reserves the right P. 10 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
CLK
COMMAND
T0T 1 T2T3 T4T5 T6T7 T8
DIN B2
NOP WRITE A NOP NOP NOP NOP NOP
WRIT E B N O P
DIN A0DIN B0DIN B1
DQ's DIN B3
1 Clk Interval
Write Interrupted by a Write (Burst Length = 4, CAS# La tency = 1, 2, 3)
The Read command that interrupts a write burst without auto precharge function should be issued one
cycle after the clock edge in which the last data-in element is registered. In order to avoid data contention, input
data must be removed from the DQs at least one clock cycle before the first read data appears on the outputs
(refer to the following figure). Once the Read command is registered, the data inputs will be ignored and writes
will not be executed.
CLK
COMMAND
T0T 1 T2T3 T4T5 T6T7 T8
NOP WRITE A NOP NOP NOP NOP NOP
READ B NOP
DIN A0don't care DOUT B2
DOUT B0DOUT B1DOUT B3
DIN A0don't care don't care DOUT B2
DOUT B0DOUT B1DOUT B3
Input data for the write is masked.
Inp ut data must be removed from the DQ's at l e as t o ne clock
cycle before the Read data appears on the outputs to avoid
d at a co nte nti on.
CAS# latency=2
tCK2, DQ's
CAS# latency=3
tCK3, DQ's
Write Interrupted by a Read (Burst Leng th = 4, CAS# Latency = 2, 3)
The BankPrecharge/PrechargeAll command that interrupts a write burst without the auto precharge
function should be issued m cycles after the clock edge in which the last data-in element is registered, where m
equals tWR/tCK rounded up to the next whole number. In addition, the DQM signals must be used to mask input
data, starting with the clock edge following the last data-in element and ending with the clock edge on which
the BankPrecharge/PrechargeAll command is entered (refer to the following figure).
CLK
T0T 1T2T3T4T5T6
WRITE
COMMAND
BANK (S) ROW
NOP NOPPrecharge NOP NOP Activate
BANK
COL n
DIN
nDIN
n + 1
DQM
ADDRESS
DQ
tWR
tRP
: don't care
Note:
The DQMs can remain low in this example if the length of the write burst is 1 or 2.
Write to Precharge
TE
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tm
T436432B
TM Technology Inc. reserves the right P. 11 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
7 Write and AutoPrecharge command (refer to the following figure)
(RAS# = "H", CAS# = "L", WE# = "L", BS = Bank, A10 = "H", A0-A7 = Column Address)
The Write and AutoPrecharge command performs the precharge operation automatically after the write
operation. Once this command is given, any subsequent command can not occur within a time delay of {(burst
length -1) + tWR + tRP(min.)}. At full-page burst, only the write operation is performed in this command and the
auto precharge function is ignored.
CLK
COMMAND
T0T 1 T2T3 T4T5 T6T7 T8
NOP NOP NOP NOP NOP
NOP NOP
CAS # latency=2
tCK2, DQ's
CAS # latency=3
tCK3, DQ's
DIN A0DIN A1
DIN A0DIN A1
*
*
tDAL= tWR + tRP *Begin AutoPrecharge
Bank can be reactivated at completion of tDAL
Bank A
Activate Writ e A
AutoPrecharge
tDAL
tDAL
Burst Write with Auto-Precharge (Burst Length = 2, CAS# Latency = 2, 3)
8 Mode Register Set command
(RAS# = "L", CAS# = "L", WE# = "L", BS0,1 and A10-A0 = Register Data)
The mode register stores the data for controlling the various operating modes of SDRAM. The Mode
Register Set command programs the values of CAS# latency, Addressing Mode and Burst Length in the Mode
register to make SDRAM useful for a variety of different applications. The default values of the Mode Register
after power-up are undefined; therefore this command must be issued at the power-up sequence. The state of
pins BS0,1 and A10~A0 in the same cycle is the data written to the mode register. One clock cycle is required
to complete the write in the mode register (refer to the following figure). The contents of the mode register can
be changed using the same command and the clock cycle requirements during operation as long as all banks are
in the idle state.
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tm
T436432B
TM Technology Inc. reserves the right P. 12 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
RAS#
T0 T 1 T2T3T4T5 T6T7 T8T9 T10
CLK
CKE
CS#
CAS#
WE#
ADDR.
DQM
DQ
tCK2
Cl oc k mi n.
Addr es s Key
tRP
Hi-Z
PrechargeAll Mode Register
Set Command Any
Command
Mode Register Set Cycle (CAS# Latency = 2, 3)
The mode register is divided into various fields depending on functionality.
Address BS0,1 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Function RFU* RFU* WBL Test Mode CAS Latency BT Burst Length
*Note: RFU (Reserved for future use) should stay “0” during MRS cycle.
• Burst Length Field (A2~A0)
This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be 2,
4, 8, or full page.
A2 A1 A0 Burst Length
0 0 0 1
0 0 1 2
0 1 0 4
0 1 1 8
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1 1 1 Full Page
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T436432B
TM Technology Inc. reserves the right P. 13 Publication Date: FEB. 2007
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• Burst Type Field (A3)
The Burst Type can be one of two modes, Interleave Mode or Sequential Mode.
A3 Burst Type
0 Sequential
1 Interleave
--- Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column address which is input to
the device. The internal column address is varied by the Burst Length as shown in the following table. When
the value of column address, (n + m), in the table is larger than 255, only the least significant 8 bits are
effective.
Data n 0 1 2 3 4 5 6 7 - 255 256 257 -
Column Address n n+1 n+2 n+3 n+4 n+5 n+6 n+7 - N+255 n n+1 -
2 words:
Burst Length 4 words:
8 words:
Full Page: Column address is repeated until terminated.
--- Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bits in the
sequence shown in the following table.
Data n Column Address Burst Length
Data 0 A7 A6 A5 A4 A3 A2 A1 A0
Data 1 A7 A6 A5 A4 A3 A2 A1 A0# 4 words
Data 2 A7 A6 A5 A4 A3 A2 A1# A0
Data 3 A7 A6 A5 A4 A3 A2 A1# A0# 8 words
Data 4 A7 A6 A5 A4 A3 A2# A1 A0
Data 5 A7 A6 A5 A4 A3 A2# A1 A0#
Data 6 A7 A6 A5 A4 A3 A2# A1# A0
Data 7 A7 A6 A5 A4 A3 A2# A1# A0#
• CAS# Latency Field (A6~A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first read data.
The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum whole value
satisfying the following formula must be programmed into this field.
tCAC(min) ≤ CAS# Latency X tCK
A6 A5 A4 CAS# Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2 clocks
0 1 1 3 clocks
1 X X Reserved
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T436432B
TM Technology Inc. reserves the right P. 14 Publication Date: FEB. 2007
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• Test Mode field (A8~A7)
These two bits are used to enter the test mode and must be programmed to "00" in normal operation.
A8 A7 Test Mode
0 0 normal mode
0 1 Vendor Use Only
1 X Vendor Use Only
• Write Burst Length (A9)
This bit is used to select the burst write length.
A9 Write Burst Length
0 Burst
1 Single Bit
9 No-Operation command
(RAS# = "H", CAS# = "H", WE# = "H")
The No-Operation command is used to perform a NOP to the SDRAM which is selected (CS# is Low).
This prevents unwanted commands from being registered during idle or wait states.
10 Burst Stop command
(RAS# = "H", CAS# = "H", WE# = "L")
The Burst Stop command is used to terminate either fixed-length or full-page bursts. This command is
only effective in a read/write burst without the auto precharge function. The terminated read burst ends after a
delay equal to the CAS# latency (refer to the following figure). The termination of a write burst is shown in the
following figure.
CLK
COMMAND
T0T 1T2T3 T4T5 T6T7 T8
READ A NOP NOP NOP NOP NOP NOP
NOP Bu rs t Stop
C AS# laten c y= 2
tCK2, DQ's
C AS# laten c y= 3
tCK3, DQ's
DOUT A0DOUT A1DOUT A2DOUT A3
DOUT A0DOUT A1DOUT A2DOUT A3
The burst ends after a delay equal to the CAS# latency.
Termination of a Burst Read Operation (Burst Length • 4, CAS# Latency = 2, 3)
CLK
COMMAND
T0T 1T2T3 T4T5 T6T7 T8
NOP WRITE A NOP NOP NOP NOP NOP
NOP Bu rs t St op
C AS# lat e ncy= 2 , 3
DQ's DIN A0DIN A1DIN A2do n't care
Input data for the Write is masked.
Termination of a Burst Write Operation (Burst Length = X, CAS# Latency = 1, 2, 3)
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TM Technology Inc. reserves the right P. 15 Publication Date: FEB. 2007
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11 Device Deselect command (CS# = "H")
The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and
Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the No
Operation command.
12 AutoRefresh command
(RAS# = "L", CAS# = "L", WE# = "H",CKE = "H", BS0,1 = “Don‘t care, A0-A10 = Don't care)
The AutoRefresh command is used during normal operation of the SDRAM and is analogous to CAS#-
before-RAS# (CBR) Refresh in conventional DRAMs. This command is non-persistent, so it must be issued
each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the
address bits a "don't care" during an AutoRefresh command. The internal refresh counter increments
automatically on every auto refresh cycle to all of the rows. The refresh operation must be performed 4096
times within 64ms. The time required to complete the auto refresh operation is specified by tRC(min.). To
provide the AutoRefresh command, all banks need to be in the idle state and the device must not be in power
down mode (CKE is high in the previous cycle). This command must be followed by NOPs until the auto
refresh operation is completed. The precharge time requirement, tRP(min), must be met before successive auto
refresh operations are performed.
13 SelfRefresh Entry command
(RAS# = "L", CAS# = "L", WE# = "H", CKE = "L", A0-A10 = Don't care)
The SelfRefresh is another refresh mode available in the SDRAM. It is the preferred refresh mode for data
retention and low power operation. Once the SelfRefresh command is registered, all the inputs to the SDRAM
become "don't care" with the exception of CKE, which must remain LOW. The refresh addressing and timing is
internally generated to reduce power consumption. The SDRAM may remain in SelfRefresh mode for an
indefinite period. The SelfRefresh mode is exited by restarting the external clock and then asserting HIGH on
CKE (SelfRefresh Exit command).
14 SelfRefresh Exit command
(CKE = "H", CS# = "H" or CKE = "H", RAS# = "H", CAS# = "H", WE# = "H")
This command is used to exit from the SelfRefresh mode. Once this command is registered, NOP or
Device Deselect commands must be issued for tRC(min.) because time is required for the completion of any
bank currently being internally refreshed. If auto refresh cycles in bursts are performed during normal operation,
a burst of 4096 auto refresh cycles should be completed just prior to entering and just after exiting the
SelfRefresh mode.
15 Clock Suspend Mode Entry / PowerDown Mode Entry command (CKE = "L")
When the SDRAM is operating the burst cycle, the internal CLK is suspended(masked) from the
subsequent cycle by issuing this command (asserting CKE "LOW"). The device operation is held intact while
CLK is suspended. On the other hand, when all banks are in the idle state, this command performs entry into
the PowerDown mode. All input and output buffers (except the CKE buffer) are turned off in the PowerDown
mode. The device may not remain in the Clock Suspend or PowerDown state longer than the refresh period
(64ms) since the command does not perform any refresh operations.
16 Clock Suspend Mode Exit / PowerDown Mode Exit command
When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the
subsequent cycle by providing this command (asserting CKE "HIGH"). When the device is in the PowerDown
mode, the device exits this mode and all disabled buffers are turned on to the active state. tPDE(min.) is required
when the device exits from the PowerDown mode. Any subsequent commands can be issued after one clock
cycle from the end of this command.
17 Data Write / Output Enable, Data Mask / Output Disable command (DQM = "L", "H")
During a write cycle, the DQM signal functions as a Data Mask and can control every word of the input
data. During a read cycle, the DQM functions as the controller of output buffers. DQM is also used for device
selection, byte selection and bus control in a memory system.
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T436432B
TM Technology Inc. reserves the right P. 16 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Absolute Maximum Rating
Symbol Item
Leaded Package Lead Free Package Unit Note
VIN, VOUT Input, Output Voltage -1~4.6 V 1
VDD, VDDQ Power Supply Voltage - 1~4.6 V 1
TOPR Operating Temperature 0~70 °C 1
TSTG Storage Temperature - 55~150 °C 1
TSOLDER Soldering Temperature (10s) 240 260 °C 1
PD Power Dissipation 1 W 1
IOUT Short Circuit Output Current 50 mA 1
Recommended D.C. Operating Conditions (Ta = 0~70°C)
Symbol Parameter Min. Typ. Max. Unit Note
VDD Power Supply Voltage 3.0 3.3 3.6 V 2
VDDQ Power Supply Voltage(for I/O Buffer) 3.0 3.3 3.6 V 2
VIH LVTTL Input High Voltage 2.0 - VDDQ + 0.3 V 2
VIL LVTTL Input Low Voltage - 0.3 - 0.8 V 2
Capacitance (VDD = 3.3V, f = 1MHz, Ta = 25°C)
Symbol Parameter Min. Max. Unit
CI Input Capacitance - 4.5 pF
CI/O Input/Output Capacitance - 6.5 pF
Note: These parameters are periodically sampled and are not 100%
TE
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T436432B
TM Technology Inc. reserves the right P. 17 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Recommended D.C. Operating Conditions (VDD = 3.3V ±
±±
± 0.3V, Ta = 0~70°C)
- 5/5.5/6/7/8/10
Description/Test condition Symbol Max. Unit Note
Operating Current
tRC ≥ tRC(min), Outputs Open, Input
signal one transition per one cycle
1 bank
operation
ICC1 200/190/180/155/135/120 3
Precharge Standby Current in power down mode
tCK = 15ns, CKE ≤ VIL(max) ICC2P 3 3
Precharge Standby Current in power down mode
tCK = ∞, CKE ≤ VIL(max) ICC2PS 3
Precharge Standby Current in non-power down mode
tCK = 15ns, CS# ≥ VIH(min), CKE ≥ VIH
Input signals are changed once during 30ns.
ICC2N 25
3
Precharge Standby Current in non-power down mode
tCK = ∞, CLK ≤ VIL(max), CKE ≥ VIH ICC2NS 15
Active Standby Current in power down mode
CKE ≤ VIL(max), tCK = 15ns ICC3P 5 mA 3
Active Standby Current in power down mode
CKE & CLK ≤ VIL(max), tCK = ∞ ICC3PS 5 3
Active Standby Current in non-power down mode
CKE ≥ VIH(min), CS# ≥ VIH(min), tCK = 15ns ICC3N 40
Active Standby Current in non-power down mode
CKE ≥ VIH(min), CLK ≤ VIL(max), tCK = ∞ ICC3NS 30
Operating Current (Burst mode)
tCK =tCK(min), Outputs Open, Multi-bank interleave ICC4 225/215//200/180/150/130
3, 4
Refresh Current
tRC ≥ TrC(min) ICC5 260/240/220/210/190/180
3
Self Refresh Current
CKE ≤ 0.2V ICC6 2
Parameter Description Min. Max. Unit Note
IIL Input Leakage Current
( 0V•VIN•VDD, All other pins not under test = 0V ) - 1.5 1.5 uA
VOH LVTTL Output "H" Level Voltage
( IOUT = -2mA ) 2.4 - V
VOL LVTTL Output "L" Level Voltage
( IOUT = 2mA ) - 0.4 V
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T436432B
TM Technology Inc. reserves the right P. 18 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V ±
±±
± 0.3V, Ta = 0~70°C) (Note: 5, 6, 7, 8)
- 5/5.5/6/7/8/10
Symbol A.C. Parameter Min. Max. Unit Note
tRC Row cycle time
(same bank) 55/55/60/70/80/100
9
tRRD Row activate to row activate delay
(different banks) 10/11/12/14/16/20
9
tRCD RAS# to CAS# delay
(same bank) 18/18/18/21/24/30
9
tRP Precharge to refresh/row activate command (same
bank) 15/16.5/18/21/24/30 9
tRAS Row activate to precharge time
(same bank) 35/38.5/42/49/56/70 100,000
9
tCK2 Clock cycle time CL* = 2 -/-/10/10/ - / -
tCK3 CL* = 3 5/5.5/6/7/8/10
ns
tAC2 Access time from CLK CL* = 2 -/-/6/6/-/-
9
tAC3 (positive edge) CL* = 3 4.5/5/5.5/5.5/6/6
tOH Data output hold time 2/2/2/2.5/2.5/2.5
9
tCH Clock high time 2/2/2.5/3/3/3.5
10
tCL Clock low time 2/2/2.5/3/3/3.5
10
tIS Data/Address/Control Input set-up time 1.5/1.5/1.5/1.75/2/2.5 10
tIH Data/Address/Control Input hold time 1
10
tLZ Data output low impedance 1
9
tHZ2 Data output high impedance CL* = 2 -/-/6/6/-/-
tHZ3 CL* = 3 4.5/5/5.5/5.5/6/6 8
tWR Write recovery time 2
tCCD CAS# to CAS# Delay time 2/1/1/1/1/1 CLK
tMRS Mode Register Set cycle time 2
* CL is CAS# Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
2. All voltages are referenced to VSS. VIL(Max) = VDDQ+1.0V for pulse width < 2ns. VIL(Min) = -1.0V for pulse
width < 2.0ns
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value
of tCK and tRC. Input signals are changed one time during tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
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TM Technology Inc. reserves the right P. 19 Publication Date: FEB. 2007
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6. A.C. Test Conditions
LVTTL Interface
Reference Level of Output Signals 1.4V / 1.4V
Output Load Reference to the Under Output Load (B)
Input Signal Levels 2.4V / 0.4V
Transition Time (Rise and Fall) of Input Signals 1ns
Reference Level of Input Signals 1.4V
3.3V
1.2kΩ
870Ω
30pF
Output
1.4V
50Ω
Output
30pF
50Ω
Z0=
LVTTL D.C. Test Load (A) LVTTL A.C. Test Load (B )
7. Transition times are measured between VIH and VIL. Transition(rise and fall) of input signals are in a fixed slope (1
ns).
8. tHZ defines the time in which the outputs achieve the open circuit condition and are not at reference levels.
9. If clock rising time is longer than 1 ns, ( tR / 2 -0.5) ns should be added to the parameter.
10. Assumed input rise and fall time tT ( tR & tF ) = 1 ns
If tR or tF is longer than 1 ns, transient time compensation should be considered, i.e., [(tr + tf)/2 - 1] ns should be
added to the parameter.
11. Power up Sequence
Power up must be performed in the following sequence.
1) Power must be applied to VDD and VDDQ(simultaneously) when all input signals are held "NOP" state and both
CKE = "H" and DQM = "H." The CLK signals must be started at the same time.
2) After power-up, a pause of 200seconds minimum is required. Then, it is recommended that DQM is held
"HIGH" (VDD levels) to ensure DQ output is in high impedance.
3) All banks must be precharged.
4) Mode Register Set command must be asserted to initialize the Mode register.
5) A minimum of 2 Auto-Refresh dummy cycles must be required to stabilize the internal circuitry of the device.
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TM Technology Inc. reserves the right P. 20 Publication Date: FEB. 2007
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Timing Waveforms
Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency=2)
BS0,1
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
tCH tCL tCK2
tIS
tIS tIH
Begin AutoPrecharge
Bank A Begin AutoPrecharge
Bank B tIS
tIH
tIS
RBx CAx RBx CBx RAy CAy RAz RBy
tRCD tDAL
tRC tIS tIH tWR tRP tRRD
Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3
Activate
Command
Bank A
Write with
AutoPrecharge
Command
Bank A
Activate
Command
Bank B
Write with
AutoPrecharge
Command
Bank B
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
Activate
Command
Bank B
CLK
CKE
CS#
RAS#
CAS#
WE#
ADDR.
DQM
DQ Hi-Z
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T436432B
TM Technology Inc. reserves the right P. 21 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency=2)
T0T 1T2T3T4T5T6T7 T8T9T10T 11T12T13
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A11
DQM
DQ
tCH tCL tCK2
tIS
tIS
tIH
Begin AutoPrecharge
Bank B tIH
tIH
tIS
RAx
RAx CAx RBx
RBx
CBx
RAy
RAy
tRRD tRAS tRC
tRCD tAC2
tLZ
tOH
tHZ
Ax0 Ax1 Bx0 Bx1
tRP
Activate
Command
Bank A
Read
Command
Bank A
Activate
Command
Bank B
Read with
Auto Precharge
Command
Bank B
Precharge
Command
Bank A
Activate
Command
Bank A
Hi-Z tAC2
tHZ
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TM Technology Inc. reserves the right P. 22 Publication Date: FEB. 2007
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Figure 3. Auto Refresh (CBR) (Burst Length=4 , CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
tCK2
RAx
RAx CAx
tRP tRC
Ax0 Ax1 Ax2 Ax3
PrechargeAll
Command AutoRefresh
Command AutoRefresh
Command Activate
Command
Bank A
Read
Command
Bank A
tRC
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TM Technology Inc. reserves the right P. 23 Publication Date: FEB. 2007
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Figure 4. Power on Sequence and Auto Refresh (CBR)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T13 T 14 T15 T 16 T17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
tCK2
High level
is reauired Minimum of 2 Refresh Cycles are required
Hi-Z tRP tRC
Add ress Key
Inputs must be
stable for 200
µ
s
PrechargeALL
Command 1st AutoRef resh
Command 2nd Auto Refresh
Command
Mode Register
Set Command
Any
Command
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T436432B
TM Technology Inc. reserves the right P. 24 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 5. Self Refresh Entry & Exit Cycle
CLK
CKE
CS#
RAS#
CAS#
BS0,1
A0-A9
WE#
DQM
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19
DQ
*Note 1
*Note 2
tIS
*Note 3
*Note 4 tRC(min) *Note 7
*Note 5
*Note 6
*Note 8
*Note 8
Hi-Z Hi-Z
Self Refresh Enter SelfRefresh Exit AutoRefresh
tSRX
tPDE
Note: To Enter SelfRefresh Mode
1. CS#, RAS# & CAS# with CKE should be low at the same clock cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in SelfRefresh mode as long as CKE stays "low".
4. Once the device enters SelfRefresh mode, minimum tRAS is required before exit from SelfRefresh.
To Exit SelfRefresh Mode
5. System clock restart and be stable before returning CKE high.
6. Enable CKE and CKE should be set high for minimum time of tSRX.
7. CS# starts from high.
8. Minimum tRC is required after CKE going high to complete SelfRefresh exit.
9. 4096 cycles of burst AutoRefresh is required before SelfRefresh entry and after SelfRefresh exit if the system
uses burst refresh.
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T436432B
TM Technology Inc. reserves the right P. 25 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 6.1. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=1)
T0T 1T2T3T4T5T6T
7T8 T9 T10 T 11 T1 T13 T14 T15 T16 T17 T1 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
tCK1
RAx
RAx CAx
Hi-Z Ax0 Ax1 Ax2 Ax3
Activate
Command
Bank A Read
Command
Bank A
Cl oc k Su sp en d
1 Cyc le Cl oc k Su spen d
2 Cycles Cl oc k Su sp en d
3 Cycles
tHZ
Note: CKE to CLK disable/enable = 1 clock
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T436432B
TM Technology Inc. reserves the right P. 26 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 6.2. Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
tCK2
RAx
RAx CAx
Hi-Z Ax0 Ax1 Ax2 Ax3
Activate
Command
Bank A
Read
Command
Bank A
Cl ock Su sp en d
1 Cycle
Cl ock Su sp en d
2 Cycl es Cl oc k Su sp en d
3 Cycl es
tHZ
Note: CKE to CLK disable/enable = 1 clock
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T436432B
TM Technology Inc. reserves the right P. 27 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 6.3 . Clock Suspension During Burst Read (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
tCK3
RAx
RAx CAx
Hi-Z Ax0 Ax1 Ax2 Ax3
Activate
Command
Bank A
Read
Command
Bank A
Cl ock Su sp en d
1 Cycle Cl ock Su sp en d
2 Cycl es Cl oc k Susp en d
3 Cycl es
tHZ
T 2
Note: CKE to CLK disable/enable = 1 clock
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T436432B
TM Technology Inc. reserves the right P. 28 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 7.1 . Clock Suspension During Burst Write (Using CKE)
(Burst Length = 4, CAS# Latency = 1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
tCK1
RAx
RAx CAx
Hi-Z DAx0
Activate
Command
Bank A
Write
Command
Bank A
Cl oc k Su sp en d
2 Cycles Cl ock Susp en d
3 Cycles
DAx1 DAx2 DAx3
Cl oc k Su sp en d
1 Cycle
Note: CKE to CLK disable/enable = 1 clock
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T436432B
TM Technology Inc. reserves the right P. 29 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 7.2 . Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BA0,1
A10
A0-A9
DQM
DQ
tCK2
RAx
RAx CAx
Hi-Z DAx0
Activate
Command
Bank A Write
Command
Bank A
Cl ock Su sp end
2 Cycl es Cl oc k Su sp en d
3 Cycl es
DAx1 DAx2 DAx3
Cl ock Susp en d
1 Cyc le
Note: CKE to CLK disable/enable = 1 clock
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T436432B
TM Technology Inc. reserves the right P. 30 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 7.3 . Clock Suspension During Burst Write (Using CKE)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ DAx0 DAx1 DAx2 DAx3
tCK3
RAx
RAx CAx
Hi-Z
Activate
Command
Bank A Write
Command
Bank A
Cl oc k Su sp en d
2 Cycles Clock Susp en d
3 Cycles
Cl oc k Su sp en d
1 Cyc le
Note: CKE to CLK disable/enable = 1 clock
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T436432B
TM Technology Inc. reserves the right P. 31 Publication Date: FEB. 2007
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Figure 8. Power Down Mode and Clock Mask (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0~A9
DQM
DQ
tCK2 tIS tPDE
RAx
RAx CAx
tHZ
Ax3
Ax2
Ax1
Ax0
Activate
Command
Bank A
Power Down
Mode Entry Power Down
Mode Exit
Read
Command
Bank A
Clock Mask
Start Clock Mask
End Precharge
Command
Bank A
Power Down
Mode Entr
y
PRECHARGE
STANDBY
Any
Command
Power Down
Mode Exit
Hi-Z
Valid
ACTIVE
STANDBY
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T436432B
TM Technology Inc. reserves the right P. 32 Publication Date: FEB. 2007
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Figure 9.1. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BA0,1
tCK1
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Aw0 Aw1 Aw2 Aw3Ax0 Ax1 Ay0 Ay1Ay2 Ay3
RAw
RAw CAw CAx CAy
Read
Command
Bank A
Hi-Z
CAz
Az0 Az1Az2 Az3
Read
Command
Bank A
Activate
Command
Bank A
RAz
RAz
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Figure 9.2. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BA0,1
tCK2
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
RAw
RAw CAw CAx CAy
Read
Command
Bank A
Hi-Z
CAz
Az0 Az1 Az2 Az3
Read
Command
Bank A
Activate
Command
Bank A
RAz
RAz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 34 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 9.3. Random Column Read (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank A
Read
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3
RAw
RAw CAw CAx CAy
Read
Command
Bank A
Hi-Z
CAz
Read
Command
Bank A
Activate
Command
Bank A
RAz
RAz
Az0
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 35 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 10.1. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
Activate
Command
Bank A
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command
Bank B
DBw0DBw1DBw2 DBw3 DBx0 DBx1DBy0DBy1 DBy2 DBy3
RBw
RBw CBw CBx CBy
Write
Command
Bank B
Hi-Z
CBz
DBz0DBz1 DBz2 DBz3
Write
Command
Bank B
Activate
Command
Bank B
RBz
RBz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 36 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 10.2. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Activate
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
DBw0 DBw1DBw2 DBw3 DBx0 DBx1
DBy0 DBy1 DBy2 DBy3
RBw
RBw CBw CBx CBy
Write
Command
Bank B
Hi-Z
CBz
DBz0 DBz1
DBz2 DBz3
Write
Command
Bank B
Activate
Command
Bank B
RBz
RBz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 37 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 10.3. Random Column Write (Page within same Bank)
(Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank A
Write
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
DBw0 DBw1DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3
RBw
RBw CBw CBx CBy
Write
Command
Bank B
Hi-Z
CBz
DBz0 DBz1
Write
Command
Bank B
Activate
Command
Bank B
RBz
RBz
DBz2
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 38 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 11.1. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
Activate
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank B
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1
RBx
RBx RBy
Read
Command
Bank B
Hi-Z
CBy
Read
Command
Bank B
Precharge
Command
Bank A
High
RAx
Read
Command
Bank A
Activate
Command
Bank B
By0 By1 By2
Ax2 Ax3 Ax4 Ax5 Ax6 Ax7
CBx CAx
RAx
RBy
tRCD tAC1 tRP
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 39 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 11.2. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Activate
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank B
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1
RBx
RBx RBy
Read
Command
Bank B
Hi-Z
CBy
Read
Command
Bank B
High
RAx
Read
Command
Bank A
Activate
Command
Bank B
By0 By1
Ax2Ax3 Ax4 Ax5 Ax6 Ax7
CBx CAx
RAx
RBy
tRCD tAC2 tRP
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 40 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 11.3. Random Row Read (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank B
Activate
Command
Bank A
Precharge
Command
Bank B
Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1
RBx
RBx RBy
Read
Command
Bank B
Hi-Z
CBy
Read
Command
Bank B
High
RAx
Read
Command
Bank A
Activate
Command
Bank B
Ax7 By0
Ax2 Ax3 Ax4 Ax5Ax6
CBx CAx
RAx
RBy
tRCD tAC3 tRP
Precharge
Command
Bank A
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 41 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 12.1. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
DAx0 DAx1 DAx2DAx3 DAx4 DAx5DAx6 DAx7 DBx0 DBx1
RAx
RAx RAy
Write
Command
Bank A
Hi-Z
CAy
High
RBx
Precharge
Command
Bank B
DBx7 DAy3
DBx2 DBx3DBx4 DBx5 DBx6
CAx CBx
RBx
RAy
tRCD
DAy0DAy1 DAy2
Write
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank A
tRP tWR
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 42 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 12.2. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Activate
Command
Bank A
Activate
Command
Bank B Precharge
Command
Bank A
DAx0 DAx1DAx2 DAx3DAx4DAx5 DAx6 DAx7 DBx0 DBx1
RAx
RAx RAy
Write
Command
Bank A
Hi-Z
CAy
High
RBx
Precharge
Command
Bank B
DBx7
DBx2 DBx3 DBx4DBx5 DBx6
CAx CBx
RBx
RAy
tRCD
Write
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank A
DAy3
DAy0 DAy1DAy2 DAy4
tWR* tRP tWR*
*
tWR > tWR(min.)
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 43 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 12.3. Random Row Write (Interleaving Banks)
(Burst Length=8, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank A
Activate
Command
Bank B
Precharge
Command
Bank A
DAx0DAx1 DAx2 DAx3DAx4 DAx5 DAx6 DAx7 DBx0 DBx1
RAx
RAx RAy
Write
Command
Bank A
Hi-Z
CAy
High
RBx
Precharge
Command
Bank B
DBx7
DBx2 DBx3 DBx4 DBx5 DBx6
CAx CBx
RBx
RAy
tRCD
Write
Command
Bank A
Write
Command
Bank B
Activate
Command
Bank A
DAy3
DAy0 DAy1 DAy2
tWR* tRP tWR*
* tWR > tWR(min.)
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 44 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
Activate
Command
Bank A
The Write Data
is Masked with a
Zero Clock
Latency
Read
Command
Bank A
Ax0 Ax1 Ax2 Ax3 DAy0DAy1
Hi-Z
Precharge
Command
Bank B
Az3
DAy3 Az0 Az1
Read
Command
Bank A
Write
Command
Bank A
The Read Data
is Masked with a
Two Clock
Latency
RAx
RAx CAx CAy CAz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 45 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Activate
Command
Bank A
The Write Data
is Masked with a
Zero Clock
Latenc
y
Read
Command
Bank A
Ax0 Ax1 Ax2 Ax3 DAy0 DAy1
Hi-Z Az3
DAy3 Az0 Az1
Read
Command
Bank A
Write
Command
Bank A
The Read Data
is Masked with a
Two Clock
Latenc
y
RAx
RAx CAx CAy CAz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 46 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank A
The Write Data
is Masked with a
Zero Clock
Latenc
y
Read
Command
Bank A
Ax0 Ax1 Ax2 Ax3 DAy0 DAy1
Hi-Z Az3
DAy3 Az0 Az1
Read
Command
Bank A
Write
Command
Bank A
The Read Data
is Masked with a
Two Clock
Latenc
y
RAx
RAx CAx CAy CAz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 47 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
Activate
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank A
Bw0 Bw1 Bx0 Bx1 By1 Ay0
Hi-Z Bz0
Read
Command
Bank A
Read
Command
Bank A
RAx
RAx
Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1 Bz2 Bz3
Activate
Command
Bank B Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
tRCD tAC1
RAx RBw
RBw
CBw CBx CBy CAy CBz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 48 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency=2)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21
T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Activate
Command
Bank A
Read
Command
Bank B
Precharge
Command
Bank A
Bw0 Bw1 Bx0 Bx1 By1 Ay0
Hi-Z Bz0
Read
Command
Bank A
Read
Command
Bank A
RAx
RAx
Ax0 Ax1 Ax2 Ax3 By0 Ay1 Bz1 Bz2 Bz3
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank B
tRCD tAC2
CAy RAx
RAx
CBw CBx CBy CAy CBz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 49 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank A
Prechaerge
Command
Bank B
Bx0 Bx1 By0 By1 Bz1 Ay0
Hi-Z Ay2
Read
Command
Bank A
Read
Command
Bank A
RAx
RAx
Ax0 Ax1 Ax2 Ax3 Bz0 Ay1 Ay3
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Precharge
Command
Bank A
tRCD tAC3
CAx RBx
RBx
CBx CBy CBz CAy
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 50 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
Activate
Command
Bank A
Write
Command
Bank B
DBw0DBw1 DBx0 DBx1 DBy1 DAy0
Hi-Z
Write
Command
Bank A
Precharge
Command
Bank A
RAx
RAx
DAx0 DAx1 DAx2 DAx3 DBy0 DAy1 DBz0
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Precharge
Command
Bank B
tRCD
CAx RBw
RBw
CBw CBx CBy CAy
DBz1 DBz2 DBz3
Write
Command
Bank B
tRRD
tRP tWR tRP
CBz
T6
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 51 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Activate
Command
Bank A
Write
Command
Bank B
DBw0 DBw1 DBx0 DBx1 DBy1DAy0
Hi-Z
Write
Command
Bank A Precharge
Command
Bank A
RAx
RAx
DAx0
DAx1 DAx2 DAx3 DBy0 DAy1 DBz0
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Precharge
Command
Bank B
tRCD
CAx RBw
RBw
CBw CBx CBy CAy
DBz1 DBz2 DBz3
Write
Command
Bank B
tRRD
tRP tWR tRP
CBz
WE#
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 52 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank A
Write
Command
Bank B
DBw0 DBw1DBx0 DBx1 DBy1 DAy0
Hi-Z
Write
Command
Bank A
Precharge
Command
Bank A
RAx
RAx
DAx0DAx1 DAx2 DAx3 DBy0 DAy1 DBz0
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Precharge
Command
Bank B
tRCD
CAx RBw
RBw
CBw CBx CBy CAy
DBz1 DBz2 DBz3
Write
Command
Bank B
tRRD > tRRD(min)
tRP
tWR tWR(min)
CBz
WE#
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 53 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
Activate
Command
Bank A
Activate
Command
Bank B
Bx0 Bx1 Bx2 Bx3 Ay1 Ay2
Hi-Z
Read
Command
Bank A
RAx
RAx
RBx
Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0
Activate
Command
Bank B
Activate
Command
Bank B
RBx CBx CAy RBy CBy
By1 By2 By3
RBz
High
Bz0 Bz1 Bz2 Bz3
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Read with
Auto Precharge
Command
Bank B Read with
Auto Precharge
Command
Bank B
CAx
RBy RBz
CBz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 54 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Activate
Command
Bank A
Activate
Command
Bank A
Bx0 Bx1 Bx2 Bx3 Ay1 Ay2
Hi-Z
Read
Command
Bank A
RAx
RAx
RBx
Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0
Activate
Command
Bank B
Activate
Command
Bank B
RBx CBx RBy
RAy CBy
By1 By2 By3
High
Az0 Az1 Az2
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
Read with
Auto Precharge
Command
Bank B
Read with
Auto Precharge
Command
Bank A
CAx
RBy RAz
CAz
RAz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 55 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank A
Bx0 Bx1 Bx2 Bx3 Ay1 Ay2
Hi-Z
Read
Command
Bank A
RAx
RAx
RBx
Ax0 Ax1 Ax2 Ax3 Ay0 Ay3 By0
Activate
Command
Bank B
Activate
Command
Bank B
RBx CBx
By1 By2 By3
High
Read with
Auto Precharge
Command
Bank B Read with
Auto Precharge
Command
Bank A
Read with
Auto Precharge
Command
Bank B
CAx
RBy
CBy
RBy
CAy
WE#
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 56 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 12 T 13 T 14 T 15 T 16 T 17 T18 T19 T20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
Activate
Command
Bank A
DBx0 DBx1 DBx2DBx3 DAy1DAy2
Hi-Z
Write
Command
Bank A
RAx
RAx
RBx
DAx0 DAx1 DAx2 DAx3 DAy0 DAy3 DBy0
Activate
Command
Bank B
Activate
Command
Bank B
CBx CAy
DBy1 DBy2 DBy3
High
Write with
Auto Precharge
Command
Bank B Write with
Auto Precharge
Command
Bank A
Write with
Auto Precharge
Command
Bank B
RBy
CAz
CBy
RBy
DAz0 DAz0
Activate
Command
Bank A
Write with
Auto Precharge
Command
Bank A
DAz0DAz0
CAx RBx
RAz
RAz
T 11
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 57 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Activate
Command
Bank A
DBx0 DBx1DBx2 DBx3 DAy1DAy2
Hi-Z
Write
Command
Bank A
RAx
RAx
RBx
DAx0 DAx1 DAx2 DAx3 DAy0 DAy3 DBy0
Activate
Command
Bank B
Activate
Command
Bank B
CBx CAy
DBy1 DBy2 DBy3
High
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
Write with
Auto Precharge
Command
Bank B
RBy
CBy
RBy
DAz0 DAz1
Activate
Command
Bank A
Write with
Auto Precharge
Command
Bank A
DAz2 DAz3
CAx RBx CAz
RAz
RAz
WE#
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 58 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A9
A0~A9
DQM
DQ
BS0,1
tCK3
Activate
Command
Bank A
DBx0 DBx1 DBx2 DBx3 DAy1 DAy2
Hi-Z
Write
Command
Bank A
RAx
RAx
RBx
DAx0 DAx1 DAx2 DAx3 DAy0 DAy3 DBy0
Activate
Command
Bank B
Activate
Command
Bank B
CBx
DBy1 DBy2DBy3
High
Write with
Auto Precharge
Command
Bank B
Write with
Auto Precharge
Command
Bank A
Write with
Auto Precharge
Command
Bank B
CAyCAx RBx CBy
RBy
RBy
`
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 59 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
Activate
Command
Bank A
Ax Ax+1 Bx Bx+1 Bx+3 Bx+4
Hi-Z
Read
Command
Bank A
RAx
RAx
RBx
Ax+1 Ax+2 Ax-2 Ax-1 Bx+2 Bx+5
Activate
Command
Bank B Burst Stop
Command
CBx
High
Read
Command
Bank B
Precharge
Command
Bank B
CAx RBx RBy
RBy
Ax Bx+6 Bx+7
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
burstin
g
be
g
innin
g
with the startin
g
address.
Activate
Command
Bank B
tCK1
tRRD tRP
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 60 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
Activate
Command
Bank A
Ax Ax+1 Bx Bx+1 Bx+3 Bx+4
Hi-Z
Read
Command
Bank A
RAx
RAx
Ax+1 Ax+2Ax-2 Ax-1 Bx+2 Bx+5
Activate
Command
Bank B
Burst Stop
Command
CBx
High
Read
Command
Bank B
Precharge
Command
Bank B
RBxCAx RBy
RBy
Ax Bx+6
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Activate
Command
Bank B
tCK2
tRP
RBx
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 61 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
Activate
Command
Bank A
Ax Ax+1 Bx Bx+1 Bx+3 Bx+4
Hi-Z
Read
Command
Bank A
RAx
RAx
Ax+1 Ax+2 Ax-2 Ax-1 Bx+2 Bx+5
Activate
Command
Bank B
Burst Stop
Command
CBx
High
Read
Command
Bank B
Precharge
Command
Bank B
RBxCAx RBy
RBy
Ax
The burst counter wraps
from the highest order
page address back to zero
durin
g
this time interval
Full Page burst operation does not
terminate when the burst length is
satisfied; the burst counter
increments and continues
bursting beginning with the
starting address.
Activate
Command
Bank B
tCK3
tRP
RBx
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 62 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
DAx+1
DAx
Activate
Command
Bank A
Hi-Z
Activate
Command
Bank B
RAx
RAx
Burst Stop
Command
CBx
High
Write
Command
Bank B
Precharge
Command
Bank B
RBxCAx RBy
RBy
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
be
g
innin
g
with the startin
g
address.
Activate
Command
Bank B
tCK1
DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 DBx+7
Write
Command
Bank A
Da ta is ignor ed
RBx
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 63 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
DAx+1
DAx
Activate
Command
Bank A
Hi-Z
Activate
Command
Bank B
RAx
RAx
Burst Stop
Command
CBx
High
Write
Command
Bank B
Precharge
Command
Bank B
RBx
CAx RBy
RBy
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
be
g
innin
g
with the startin
g
address.
Activate
Command
Bank B
tCK2
DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1DBx+2DBx+3 DBx+4 DBx+5 DBx+6
Write
Command
Bank A
Data is ig nor ed
RBx
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 64 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
DAx+1
DAx
Activate
Command
Bank A
Hi-Z
Activate
Command
Bank B
RAx
RAx
Burst Stop
Command
CBx
High
RBxCAx
Write
Command
Bank B
Precharge
Command
Bank B
RBy
RBy
The burst counter wraps
from the highest order
page address back to zero
during this time interval
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
be
g
innin
g
with the startin
g
address.
Activate
Command
Bank B
tCK3
RBx
DAx+2 DAx+3 DAx-1 DAx DAx+1 DBx DBx+1DBx+2DBx+3 DBx+4 DBx+5
Write
Command
Bank A
Da ta is ignor ed
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 65 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency=2)
T0T 1T2T3T4T5T6T7T8T9T10T 11T12T13T14T15T16T17T18T19T20T21T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
LDQM
UDQM
BS0,1
RAx
RAx CAy
High
CAx
tCK2
CAz
Activate
Command
Bank A
Read
Command
Bank A
Upper 3 Bytes
are masked Write
Command
Bank A
Upper 3 Bytes
are masked Read
Command
Bank A
Lower Byte
is mask ed Lower Byte
is mask ed Lower Byte
is mask ed
Ax0 Ax1 Ax2
Ax1 Ax2 Ax3
DAy1
DAy2
DAy0 DAy1 DAy3
Az1 Az2
Az1 Az2
Az0 Az3
DQ0 - DQ7
DQ8 - DQ15
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 66 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 21. Random Row Read (Interleaving Banks)
(Burst Length=2, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
High
tCK1
Bu0 Bu1Au0 Au1 Bv0 Bv1 Av0 Av1 Bw0 Bw1 Aw0 Aw1Bx0 Bx1 Ax0 Ax1 By0 By1 Ay0 Ay1 Bz0
Activate
Command
Bank B
Read
Bank B
with Auto
Prechar
g
e
Activate
Command
Bank A
Read
Bank A
with Auto
Prechar
g
e
Activate
Command
Bank B
Read
Bank B
with Auto
Prechar
g
e
Activate
Command
Bank A
Read
Bank A
with Auto
Prechar
g
e
Activate
Command
Bank B
Read
Bank B
with Auto
Prechar
g
e
Activate
Command
Bank A
Read
Bank A
with Auto
Prechar
g
e
Activate
Command
Bank B
Read
Bank B
with Auto
Prechar
g
e
Activate
Command
Bank A
Read
Bank A
with Auto
Prechar
g
e
Activate
Command
Bank B
Read
Bank B
with Auto
Prechar
g
e
Activate
Command
Bank A
Read
Bank A
with Auto
Prechar
g
e
Activate
Command
Bank B
Read
Bank B
with Auto
Prechar
g
e
Activate
Command
Bank A
RBu
RBu CBu
RAu
RAu CAu
RBv
RBv CBv
RAv
RAv CAv
RBw
RBw CBw
RAw
RAw CAw
RBx
RBx CBx
RAx
RAx CAx
RBy
RBy CBy
RAy
RAy CAy
RBz
RBz CBz
RAz
RAz
tRP tRP tRP tRP tRP tRP tRP tRP tRP tRP
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
Begin Auto
Precharge
Bank B
Begin Auto
Precharge
Bank A
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 67 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
Ax0 Bx0 Ay0Ay1 By0 By1 Az0Az1 Az2 Bz0 Bz1 Bz2
Activate
Command
Bank A Read
Command
Bank A
Activate
Command
Bank B
Read
Command
Bank B
Read
Command
Bank B
Read
Command
Bank A
Read
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
tRP
Read
Command
Bank A Activate
Command
Bank B
tRRD tRCD
RAx
RAx
RBx
RBx CAx CBx CAy CBy CAz CBz
RBw
RBw
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 68 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
DAx0DBx0DAy0 DAy1 DBy0 DBy1 DAz0 DAz1DAz2 DBz0DBz1 DBz2
Activate
Command
Bank A Write
Command
Bank A
Activate
Command
Bank B
Write
Command
Bank B
Write
Command
Bank B
Write
Command
Bank A
Write
Command
Bank B
Precharge
Command Bank B
(Precharge Temination)
tRP
Write
Command
Bank A Activate
Command
Bank B
tRRD tRCD
RAx
RAx
RBx
RBx CAx CBx CAy CBy CAz CBz
RBw
RBw
tWR
Write Data
is mask ed
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 69 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency=1)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T 19 T 20 T 21 T 22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK1
DAx0 DAx1DAx2 DAx3 DAx4 Ay0 Ay1 Ay2 DAz3DAz2DAz0
Activate
Command
Bank AWrite
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Write
Command
Bank A
RAx
RAx
RAy
CAx RAyCAy RAz
DAz1 DAz4 DAz5DAz6 DAz7
Precharge Termination
of a Write Burst.
Write data is masked. Activate
Command
Bank A
Activate
Command
Bank A
tWR tRP tRP Precharge
Termination of
a Read Burst.
RAz
CAz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 70 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 24.2. Precharge Termination of a Burst
(Burst Length=8 or Full Page, CAS# Latency=2)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 1 1 T 12 T 13 T 14 T 15 T 16 T 17 T 18 T19 T20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK2
DAx0 DAx1DAx2 DAx3 Ay2Ay0 Ay1
Activate
Command
Bank A
Write
Command
Bank A
Precharge
Command
Bank A
Read
Command
Bank A
Precharge
Command
Bank A
Activate
Command
Bank A
RAx
RAx
RAy
CAx RAy CAy
Az0 Az1 Az2
Precharge Termination
of a Write Burst.
Write data is masked.
Activate
Command
Bank A
tWR tRP tRP
RAz
CAz
High
Read
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Read Burst
tRP
RAz
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 71 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
Figure 24.3. Precharge Termination of a Burst
(Burst Length=4, 8 or Full Page, CAS# Latency=3)
T0 T 1 T2 T3 T4 T5 T6 T7 T8 T9 T 10 T 11 T 12 T 13 T 14 T 15 T 16 T17 T18 T 19 T 20 T21 T22
CLK
CKE
CS#
RAS#
CAS#
WE#
A10
A0~A9
DQM
DQ
BS0,1
tCK3
DAx0 Ay0 Ay1 Ay2
Activate
Command
Bank A
Write
Command
Bank A
Precharge Termination
of a Write Burst
Read
Command
Bank A
Precharge
Command
Bank A
RAx
RAx
RAy
CAx RAy CAy
Write Data
is masked
Activate
Command
Bank A
tWR tRP tRP
RAz
RAz
High
Activate
Command
Bank A
Precharge
Command
Bank A
Precharge Termination
of a Read Burst
DAx1
TE
CH
tm
T436432B
TM Technology Inc. reserves the right P. 72 Publication Date: FEB. 2007
to change products or specifications without notice. Revision: A
86 Pin TSOP II Package Outline Drawing Information
y
86
1D
E
HE
0.254
θ°
L
L1
A
A1A2
SB
eLL1
C
43
44
Symbol Dimension in inch Dimension in mm
Min Normal Max Min Normal Max
A - - 0.047 - - 1.20
A1 0.002 0.004 0.006 0.05 0.10 0.15
A2 0.037 0.039 0.041 0.95 1 1.05
B 0.007 0.008 0.009 0.17 0.2 0.23
C - 0.005 - - 0.127 -
D 0.87 0.875 0.88 22.09 22.22 22.35
E 0.395 0.400 0.405 10.03 10.16 10.29
e - 0.0197 - - 0.50 -
HE 0.455 0.463 0.471 11.56 11.76 11.96
L 0.016 0.020 0.024 0.40 0.50 0.60
L1 - 0.0315 - - 0.80 -
S - 0.024 - - 0.61 -
y - - 0.004 - - 0.10
θ
θθ
θ 0° - 8° 0
° - 8°
Notes :
1. Dimension D&E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Dimension S includes end flash.
4. Controlling dimension : mm
