SAMA5D27 SOM1 1Gbit (128MB) DDR2 SDRAM, 10/100 Ethernet PHY, 64Mbit (8MB) Flash, 1Kbit EEPROM, Power Management IC, SAMA5D27 MPU Introduction The Microchip SAMA5D27 SOM1 is a small single-sided System-On-Module (SOM) based on the highperformance System-in-Package 32-bit Arm(R) Cortex(R)-A5 processor-based MPU SAMA5D27 and 1Gb DDR2 SDRAM running up to 500 MHz. The SAMA5D27 SOM1 is built on a common set of proven Microchip components to reduce time to market by simplifying hardware design and software development. The SOM also limits design rules of the main application board, reducing overall PCB complexity and cost. The SAMA5D27 SOM1 is delivered with a free Linux distribution and bare metal C examples. Figure 1. SAMA5D27 SOM1 Features * * System-In-Package (SAMA5D27C-D1G-CU) including: - Arm Cortex-A5 processor-based SAMA5D2 MPU - 1Gbit DDR2 SDRAM On-Board Power Management Unit (MIC2800-G1JJYML) (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 1 SAMA5D27 SOM1 * * * * * * * * 1Kb Serial EEPROM with EUI-48TM Node Identity (24AA02E48T-I/OT) 64Mb Serial Quad I/O Flash Memory (SST26VF064BT-104I/MF) 10Base-T/100Base-TX Ethernet PHY (KSZ8081RNAIA) 40 x 38 mm Module, Pitch 0.8mm, solderable by hand 103 I/Os Up to 7 Tampers One USB Device, one USB Host and one HSIC Interface Shutdown and Reset Control Pins * * * Support for up to 6 PTC Lines Up to 24-bit LCD Interface Independent Power Supplies Available for Camera Sensor, for SD Card and for Backup depending on Voltage Domains Operational Specifications: - Main operating voltage: 3.3V 5% - Temperature range: -40C to 85C - Integrated crystals, internal voltage regulators - Multiple interfaces and I/Os for easy application development * Applications * * * * Healthcare/Patient Monitoring IoT Secure Gateways Human Machine Interface, Control Panel Home and Building Automation, Thermostat, Industrial Gateways (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 2 Table of Contents Introduction......................................................................................................................1 Features.......................................................................................................................... 1 Applications..................................................................................................................... 2 1. Description.................................................................................................................5 2. Reference Documents...............................................................................................6 3. Block Diagram........................................................................................................... 7 4. Pinout........................................................................................................................ 8 4.1. 4.2. Pinout Overview........................................................................................................................... 8 Pin List .........................................................................................................................................9 5. Functional Description............................................................................................. 16 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. SAMA5D27 System-In-Package................................................................................................ 16 Power Supplies.......................................................................................................................... 17 System Control...........................................................................................................................18 Ethernet PHY............................................................................................................................. 19 QSPI Memory.............................................................................................................................20 EEPROM Memory......................................................................................................................21 6. Power Supply Connections and Timing Sequences................................................23 6.1. 6.2. 6.3. 6.4. Power Supply Configuration #1..................................................................................................23 Power Supply Configuration #2..................................................................................................24 Power Supply Configuration #3..................................................................................................26 Power Supply Configuration #4..................................................................................................27 7. Booting Guidelines.................................................................................................. 30 7.1. 7.2. 7.3. 7.4. Boot Process.............................................................................................................................. 30 Boot Configuration......................................................................................................................30 NVM Programming.....................................................................................................................31 Boot From External Memory...................................................................................................... 31 8. Debug Considerations............................................................................................. 33 9. Electrical Characteristics......................................................................................... 34 9.1. 9.2. 9.3. Absolute Maximum Ratings........................................................................................................34 Operational Characteristics........................................................................................................ 34 DC Electrical Characteristics......................................................................................................35 10. Mechanical Characteristics......................................................................................37 10.1. Module Dimensions....................................................................................................................37 (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 3 SAMA5D27 SOM1 10.2. Module Land Pattern.................................................................................................................. 38 11. Production Settings................................................................................................. 40 11.1. Bake Information........................................................................................................................ 40 11.2. Reflow Profile............................................................................................................................. 40 12. Ordering Information................................................................................................42 13. Revision History.......................................................................................................43 The Microchip Web Site................................................................................................ 44 Customer Change Notification Service..........................................................................44 Customer Support......................................................................................................... 44 Product Identification System........................................................................................ 45 Microchip Devices Code Protection Feature................................................................. 45 Legal Notice...................................................................................................................45 Trademarks................................................................................................................... 46 Quality Management System Certified by DNV.............................................................46 Worldwide Sales and Service........................................................................................48 (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 4 SAMA5D27 SOM1 Description 1. Description The SAMA5D27 SOM1 is a high-performance System-On-Module based on the 32-bit ARM Cortex-A5 RISC SAMA5D2 processor. The SAMA5D27 SOM1 is certified for industrial operating conditions over a -40 to 85C temperature range. The system of the SAMA5D27 SOM1 operates at a maximum CPU operating frequency of 500 MHz and a maximum bus speed of 166 MHz. It features up to: * 1 Gbit of DDR2 SDRAM memory (SAMA5D27C-D1G-CU) * 1 Kb of EEPROM memory (24AA02E48T-I/OT) with EUI-48 * 64 Mb of QSPI Flash (SST26VF064BT-104I/MF) memory The SAMA5D27 SOM1 is a 176-pin, 0.8mm pad pitch module with a 40mm x 38mm size. The SAMA5D27 SOM1 offers an extensive peripheral set, including High-speed USB Host and Device, HSIC Interface, 10Base-T/100Base-TX Ethernet Interface, system control and up to 103 I/Os featuring: * * * * * * * * * * * * Up to 4 UARTS Up to 4 Flexcoms Up to 6 Capactive Touch lines for up to 9 touch buttons Up to 4 ADC Inputs Up to 2 CAN Up to 7 Tamper Pins Serial Interfaces such as SPI, TWI, QSPI, SSC and IS SD/MMC, eMMC, SDIO Interfaces Up to 24-bit LCD RGB Interface CMOS Camera Interface Mono PDMIC and Full-Bridge Class-D Stereo Up to 6 Capacitive Touch Lines Tip: Each I/O of the SAMA5D27 SOM1 is configurable, as either a general-purpose I/O line only, or as an I/O line multiplexed with up to six peripheral I/Os. As the multiplexing is hardwaredefined, the hardware designer and programmer must carefully determine the configuration of the PIO Controllers required by their application. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 5 SAMA5D27 SOM1 Reference Documents 2. Reference Documents The SAMA5D27 SOM1 is equipped with various Microchip silicon devices. The relevant documentation is listed in the table below. Type Document Title Available Ref. No./Product Datasheet SAMA5D2 www.microchip.com/ SAMA5D2 DS60001476 Datasheet SAMA5D2 System-In-Package (SIP) www.microchip.com/ SAMA5D2 SIP DS60001484 Datasheet Serial EEPROMs with EUI-48 Node Identity www.microchip.com/ 24AA02E48 24AA02E48T-I/OT Datasheet 10BASE-T/100BASE-TX Ethernet PHY www.microchip.com/ksz8081 KSZ8081RNAIA Datasheet Serial Quad I/O (SQI) Flash Memory www.microchip.com/ sst26vf064b SST26VF064BT-104I/MF Datasheet Digital Power Management IC www.microchip.com/mic2800 MIC2800-G1JJYML (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 6 SAMA5D27 SOM1 Block Diagram Block Diagram Figure 3-1. SAMA5D27 SOM1 Block Diagram VDDSDHC VDDISC JTAG & DBGU Interfaces VDDBU TWI Interface Power Management Unit MIC2800-G1JJYML MAIN 3.3V 1K Serial EEPROM with EUI-48 Node Identity 24AA02E48T-I/OT DEBUG 7 * PIOBU BACKUP RXD WAKEUP RESET MPU + DDR2 1Gb SAMA5D27C-D1G-CU LFBGA289 SYSTEM SHUTDOWN Disable Boot CLK_AUDIO 10BASE-T / 100BASE-TX PHY With RMII Support KSZ8081RNAIA Physical Receiver Transceiver Interface 64Mbit Serial QUAD I/O Flash Memory SST26VF064BT-104I/MF External QSPI Connection MISC COMPP / COMPN USB Device Connector USB Dev. USB Host Connector USB Host HSIC Device HSIC (c) 2018 Microchip Technology Inc. Datasheet CLASS-D Stereo Mono PDMIC Interface Camera Interface LCD Interface up to 24-bit SD-CARD Interface SDIO Interface eMMC Interface IS Interface SSC Interface QSPI Interface TWI Interface 2 * SPI Interfaces Up to 2 * CAN Up to 4 * ADC Inputs Up to 6 * PTC Lines Up to 4 * FLEXCOM 103 I/O Available Up to 4 * UART 3. DS60001521B-page 7 SAMA5D27 SOM1 Pinout 4. Pinout 4.1 Pinout Overview The categories of pins are listed below: * * * * Red: Power Supplies Black: Ground Blue: Signals Orange: Reserved for future use 176 GND_24 175 PC11/ISI_D2/TCLK4/CANRX0/A0/NBS0 PC16/ISI_D7/RK0/A5 PC25/ISI_FIELD/A14 PC18/ISI_D9/FLEXCOM3_IO2/A7 GND_23 170 PC23/ISI_HSYNC/A12 PB26/LCDDAT15/URXD0 PB24/LCDDAT13/RK0/TCLK2/FLEXCOM3_IO3 PB28/LCDDAT17/FLEXCOM0_IO0/TIOA5 GND_22 165 PB30/LCDDAT19/FLEXCOM0_IO2/TCLK5 PB21/LCDDAT10/TF0/TCLK3/FLEXCOM3_IO2 PB27/LCDDAT16/UTXD0 PB15/LCDDAT4/TF1/I2SCK1 PB22/LCDDAT11/TD0/TIOA2/FLEXCOM3_IO1 160 PB23/LCDDAT12/RD0/TIOB2/FLEXCOM3_IO0 PB25/LCDDAT14/RF0/FLEXCOM3_IO4 PB19/LCDDAT8/RF1/TIOA3 PB17/LCDDAT6/RD1/I2SDI1 PB20/LCDDAT9/TK0/TIOB3/PCK1 155 PB13/LCDDAT2/PCK1 PB16/LCDDAT5/TD1/I2SWS1 RFU2 PB18/LCDDAT7/RK1/I2SDO1 PB12/LCDDAT1/UTXD3/PDMCLK0 150 PB14/LCDDAT3/TK1/I2SMCK1 GND_21 PB11/LCDDAT0/URXD3/PDMDAT0 RFU1 PC02/LCDDAT23/CANRX0/SPI1_MOSI/I2SMCK0 145 PC00/LCDDAT21/FLEXCOM0_IO4 PB29/LCDDAT18/FLEXCOM0_IO1/TIOB5 PB31/LCDDAT20/FLEXCOM0_IO3 PC03/LCDPWM/TIOA1/SPI1_MISO/I2SWS0 PC01/LCDDAT22/CANTX0/SPI1_SPCK/I2SCK0 140 PC06/LCDHSYNC/TWD1/SPI1_NPCS2 PC07/LCDPCK/TWCK1/SPI1_NPCS3/URXD1 PC08/LCDDEN/FIQ/PCK0/UTXD1 PC05/LCDVSYNC/TCLK1/SPI1_NPCS1/I2SDO0 PC04/LCDDISP/TIOB1/SPI1_NPCS0/I2SDI0 135 PB10/TIOB3/PWMEXTRG1/QSPI1_IO3 PB05/TCLK2/PWMH2/QSPI1_SCK PB07/TIOB2/PWMH3/QSPI1_IO0 PB09/TIOA3/PWMFI1/QSPI1_IO2 131 GND_20 Figure 4-1. SAMA5D27 SOM1 Pinout Overview 1 130 5 125 10 120 15 115 20 110 25 105 30 100 35 95 40 90 89 88 85 80 75 70 65 60 55 50 GND_19 RFU0 PB08/TCLK3/PWML3/QSPI1_IO1 PB06/TIOA2/PWML2/QSPI1_CS DIS_BOOT PB04/UTXD4/FIQ/CLASSD_R3 PB02/PWMFI0/CLASSD_R1 PB03/URXD4/IRQ/PWMEXTRG0/CLASSD_R2 PB01/SPI0_SPCK/PWML1/CLASSD_R0 PD00/FLEXCOM4_IO4/UTXD3/A23 PC30/FLEXCOM4_IO2/A19 PB00/SPI0_MOSI/PWMH1 PC29/FLEXCOM4_IO1/A18 PC28/FLEXCOM4_IO0/PCK2/A17 PC31/FLEXCOM4_IO3/URXD3/A20 PC26/CANTX1/A15 PC27/PCK1/CANRX1/A16 PD01/A24 PA16/SPI0_MISO/TD1/QSPI0_IO0/I2SWS1/FLEXCOM3_IO3/D11 PA14/SPI0_SPCK/TK1/QSPI0_SCK/I2SMCK1/FLEXCOM3_IO2/D9 PD25/AD6 PA15/SPI0_MOSI/TF1/QSPI0_CS/I2SCK1/FLEXCOM3_IO0/D10 PA17/SPI0_NPCS0/RD1/QSPI0_IO1/I2SDI1/FLEXCOM3_IO4/D12 GND_18 PA22/FLEXCOM1_IO2/SPI1_SPCK/SDMMC1_CK/QSPI0_SCK PA18/SPI0_NPCS1/RK1/QSPI0_IO2/I2SDO1/SDMMC1_DAT0/D13 PA20/SPI0_NPCS3/TIOB0/SDMMC1_DAT2/D15 PA21/PCK2/IRQ/TCLK0/SDMMC1_DAT3/NANDRDY PA23/FLEXCOM1_IO1/SPI1_MOSI/QSPI0_CS PA19/SPI0_NPCS2/RF1/QSPI0_IO3/TIOA0/SDMMC1_DAT1/D14 PA26/FLEXCOM1_IO4/SPI1_NPCS1/QSPI0_IO2 PA24/FLEXCOM1_IO0/SPI1_MISO/QSPI0_IO0 GND_17 PA25/FLEXCOM1_IO3/SPI1_NPCS0/QSPI0_IO1 PA29/TCLK1/SPI0_NPCS1/SDMMC1_WP/CLASSD_L1 PA28/TIOB1/SPI0_NPCS3/SPI1_NPCS3/SDMMC1_CMD/CLASSD_L0 PA30/SPI0_NPCS0/PWMH0/SDMMC1_CD/CLASSD_L2 PA31/SPI0_MISO/PWML0/CLASSD_L3 PA12/SDMMC0_WP/IRQ/NRD/NANDOE PA13/SDMMC0_CD/FLEXCOM3_IO1/D8 PA27/TIOA1/SPI0_NPCS2/SPI1_NPCS2/SDMMC1_RSTN/QSPI0_IO3 GND_16 GND_07 PIOBU2 PIOBU7 PIOBU5 PIOBU4 PIOBU3 WKUP GND_08 PD28/JTAG_TDI PD29/JTAG_TDO PD27/JTAG_TCK PD30/JTAG_TMS VDDBU GND_09 PD20/TIOA2/TWCK1/AD1 PD19/PCK0/TWD1/AD0 PIOBU6 nRST CLK_AUDIO GND_10 COMPP COMPN VDDSDHC GND_11 USBA_M USBA_P GND_12 USBB_M USBB_P GND_13 STROBE DATA GND_14 PA01/SDMMC0_CMD/QSPI0_CS/D1 PA09/SDMMC0_DAT7/TIOA4/FLEXCOM2_IO3/NCS3 PA08/SDMMC0_DAT6/TCLK5/FLEXCOM2_IO2/NWE/NANDWE PA07/SDMMC0_DAT5/TIOB5/FLEXCOM2_IO1/D7 PA00/SDMMC0_CK/QSPIO0_SLK/D0 PA03/SDMMC0_DAT1/QSPI0_IO1/D3 PA10/SDMMC0_RSTN/TIOB4/FLEXCOM2_IO4/A21/NANDALE PA02/SDMMC0_DAT0/QSPI0_IO0/D2 PA04/SDMMC0_DAT2/QSPI0_IO2/D4 PA05/SDMMC0_DAT3/QSPI0_IO3/D5 PA06/SDMMC0_DAT4/TIOA5/FLEXCOM2_IO0/D6 PA11/SDMMC0_VDDSEL/TCLK4/A22/NANDCLE GND_15 45 42 43 GND_00 PC09/FIQ/ISI_D0/TIOA4 PC12/ISI_D3/URXD3/TK0/A1 PC13/ISI_D4/UTXD3/TF0/A2 PC17/ISI_D8/RF0/A6 PC19/ISI_D10/FLEXCOM3_IO1/A8 PC21/ISI_PCK/FLEXCOM3_IO3/A10 PC14/ISI_D5/TD0/A3 PC10/ISI_D1/TIOB4/CANTX0 GND_01 PC22/ISI_VSYNC/FLEXCOM3_IO4/A11 PC15/ISI_D6/RD0/A4 PC24/ISI_MCK/A13 PC20/ISI_D11/FLEXCOM3_IO0/A9 VDDISC VDDIN_3V3 VDDIN_3V3 GND_02 PD21/EEPROM_TWD_PD21 PD22/EEPROM_TWCK_PD22 PD05/TWCK1/NCS1/PTCROW2 PD06/PCK1/NCS2/PTCROW3 PD02/URXD1/A25 PD03/UTXD1/FIQ/NWAIT/PTCROW0 PD07/NWR1/NBS1/PTCROW4 GND_03 PD04/TWD1/NCS0/PTCROW1 PD08/NANDRDY/PTCROW5 PD24/UTXD2/AD5 PD23/URXD2/AD4 GND_04 RXD PIOBU1 PD26/AD7 SHDN ETH_LED0 ETH_RXM ETH_RXP GND_05 ETH_TXM ETH_TXP GND_06 (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 8 SAMA5D27 SOM1 Pinout 4.2 Pin List The pin list of the SAMA5D27 SOM1 is provided in the following tables. Table 4-1. System-On-Module Pin Description: PIOA Pin Number PIO Power Rail Other Features Type 80 PA00 VDDSDHC SDMMC0_CK/QSPIO0_SLK/D0 I/O 76 PA01 VDDSDHC SDMMC0_CMD/QSPI0_CS/D1 I/O 83 PA02 VDDSDHC SDMMC0_DAT0/QSPI0_IO0/D2 I/O 81 PA03 VDDSDHC SDMMC0_DAT1/QSPI0_IO1/D3 I/O 84 PA04 VDDSDHC SDMMC0_DAT2/QSPI0_IO2/D4 I/O 85 PA05 VDDSDHC SDMMC0_DAT3/QSPI0_IO3/D5 I/O 86 PA06 VDDSDHC SDMMC0_DAT4/TIOA5/ FLEXCOM2_IO0/D6 I/O 79 PA07 VDDSDHC SDMMC0_DAT5/TIOB5/ FLEXCOM2_IO1/D7 I/O 78 PA08 VDDSDHC SDMMC0_DAT6/TCLK5/ FLEXCOM2_IO2/NWE/NANDWE I/O 77 PA09 VDDSDHC SDMMC0_DAT7/TIOA4/ FLEXCOM2_IO3/NCS3 I/O 82 PA10 VDDSDHC SDMMC0_RSTN/TIOB4/ FLEXCOM2_IO4/A21/NANDALE I/O 87 PA11 VDDIN_3V3 SDMMC0_VDDSEL/TCLK4/A22/ NANDCLE I/O 92 PA12 VDDIN_3V3 SDMMC0_WP/IRQ/NRD/NANDOE I/O 91 PA13 VDDIN_3V3 SDMMC0_CD/FLEXCOM3_IO1/D8 I/O 111 PA14 VDDIN_3V3 SPI0_SPCK/TK1/QSPI0_SCK/ I2SMCK1/FLEXCOM3_IO2/D9 I/O 109 PA15 VDDIN_3V3 SPI0_MOSI/TF1/QSPI0_CS/I2SCK1/ I/O FLEXCOM3_IO0/D10 112 PA16 VDDIN_3V3 SPI0_MISO/TD1/QSPI0_IO0/ I2SWS1/FLEXCOM3_IO3/D11 I/O 108 PA17 VDDIN_3V3 SPI0_NPCS0/RD1/QSPI0_IO1/ I2SDI1/FLEXCOM3_IO4/D12 I/O 105 PA18 VDDIN_3V3 SPI0_NPCS1/RK1/QSPI0_IO2/ I2SDO1/SDMMC1_DAT0/D13 I/O 101 PA19 VDDIN_3V3 SPI0_NPCS2/RF1/QSPI0_IO3/ TIOA0/SDMMC1_DAT1/D14 I/O (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 9 SAMA5D27 SOM1 Pinout Pin Number PIO Power Rail Other Features Type 104 PA20 VDDIN_3V3 SPI0_NPCS3/TIOB0/ SDMMC1_DAT2/D15 I/O 103 PA21 VDDIN_3V3 PCK2/IRQ/TCLK0/SDMMC1_DAT3/ NANDRDY I/O 106 PA22 VDDIN_3V3 FLEXCOM1_IO2/SPI1_SPCK/ SDMMC1_CK/QSPI0_SCK I/O 102 PA23 VDDIN_3V3 FLEXCOM1_IO1/SPI1_MOSI/ QSPI0_CS I/O 99 PA24 VDDIN_3V3 FLEXCOM1_IO0/SPI1_MISO/ QSPI0_IO0 I/O 97 PA25 VDDIN_3V3 FLEXCOM1_IO3/SPI1_NPCS0/ QSPI0_IO1 I/O 100 PA26 VDDIN_3V3 FLEXCOM1_IO4/SPI1_NPCS1/ QSPI0_IO2 I/O 90 PA27 VDDIN_3V3 TIOA1/SPI0_NPCS2/SPI1_NPCS2/ SDMMC1_RSTN/QSPI0_IO3 I/O 95 PA28 VDDIN_3V3 TIOB1/SPI0_NPCS3/SPI1_NPCS3/ SDMMC1_CMD/CLASSD_L0 I/O 96 PA29 VDDIN_3V3 TCLK1/SPI0_NPCS1/SDMMC1_WP/ I/O CLASSD_L1 94 PA30 VDDIN_3V3 SPI0_NPCS0/PWMH0/ SDMMC1_CD/CLASSD_L2 I/O 93 PA31 VDDIN_3V3 SPI0_MISO/PWML0/CLASSD_L3 I/O Table 4-2. System-On-Module Pin Description: PIOB Pin Number PIO Power Rail Other Features Type 119 PB00 VDDIN_3V3 SPI0_MOSI/PWMH1 I/O 122 PB01 VDDIN_3V3 SPI0_SPCK/PWML1/CLASSD_R0 I/O 124 PB02 VDDIN_3V3 PWMFI0/CLASSD_R1 I/O 123 PB03 VDDIN_3V3 URXD4/IRQ/PWMEXTRG0/ CLASSD_R2 I/O 125 PB04 VDDIN_3V3 UTXD4/FIQ/CLASSD_R3 I/O 134 PB05 VDDIN_3V3 TCLK2/PWMH2/QSPI1_SCK I/O 127 PB06 VDDIN_3V3 TIOA2/PWML2/QSPI1_CS I/O 133 PB07 VDDIN_3V3 TIOB2/PWMH3/QSPI1_IO0 I/O 128 PB08 VDDIN_3V3 TCLK3/PWML3/QSPI1_IO1 I/O (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 10 SAMA5D27 SOM1 Pinout Pin Number PIO Power Rail Other Features Type 132 PB09 VDDIN_3V3 TIOA3/PWMFI1/QSPI1_IO2 I/O 135 PB10 VDDIN_3V3 TIOB3/PWMEXTRG1/QSPI1_IO3 I/O 148 PB11 VDDIN_3V3 LCDDAT0/URXD3/PDMDAT0 I/O 151 PB12 VDDIN_3V3 LCDDAT1/UTXD3/PDMCLK0 I/O 155 PB13 VDDIN_3V3 LCDDAT2/PCK1 I/O 150 PB14 VDDIN_3V3 LCDDAT3/TK1/I2SMCK1 I/O 162 PB15 VDDIN_3V3 LCDDAT4/TF1/I2SCK1 I/O 154 PB16 VDDIN_3V3 LCDDAT5/TD1/I2SWS1 I/O 157 PB17 VDDIN_3V3 LCDDAT6/RD1/I2SDI1 I/O 152 PB18 VDDIN_3V3 LCDDAT7/RK1/I2SDO1 I/O 158 PB19 VDDIN_3V3 LCDDAT8/RF1/TIOA3 I/O 156 PB20 VDDIN_3V3 LCDDAT9/TK0/TIOB3/PCK1 I/O 164 PB21 VDDIN_3V3 LCDDAT10/TF0/TCLK3/ FLEXCOM3_IO2 I/O 161 PB22 VDDIN_3V3 LCDDAT11/TD0/TIOA2/ FLEXCOM3_IO1 I/O 160 PB23 VDDIN_3V3 LCDDAT12/RD0/TIOB2/ FLEXCOM3_IO0 I/O 168 PB24 VDDIN_3V3 LCDDAT13/RK0/TCLK2/ FLEXCOM3_IO3 I/O 159 PB25 VDDIN_3V3 LCDDAT14/RF0/FLEXCOM3_IO4 I/O 169 PB26 VDDIN_3V3 LCDDAT15/URXD0 I/O 163 PB27 VDDIN_3V3 LCDDAT16/UTXD0 I/O 167 PB28 VDDIN_3V3 LCDDAT17/FLEXCOM0_IO0/TIOA5 I/O 144 PB29 VDDIN_3V3 LCDDAT18/FLEXCOM0_IO1/TIOB5 I/O 165 PB30 VDDIN_3V3 LCDDAT19/FLEXCOM0_IO2/TCLK5 I/O 143 PB31 VDDIN_3V3 LCDDAT20/FLEXCOM0_IO3 I/O Table 4-3. System On Module Pin Table : PIOC Pin Number PIO Power Rail Other Features Type 145 PC00 VDDIN_3V3 LCDDAT21/FLEXCOM0_IO4 I/O 141 PC01 VDDIN_3V3 LCDDAT22/CANTX0/SPI1_SPCK/ I2SCK0 I/O (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 11 SAMA5D27 SOM1 Pinout Pin Number PIO Power Rail Other Features Type 146 PC02 VDDIN_3V3 LCDDAT23/CANRX0/SPI1_MOSI/ I2SMCK0 I/O 142 PC03 VDDIN_3V3 LCDPWM/TIOA1/SPI1_MISO/ I2SWS0 I/O 136 PC04 VDDIN_3V3 LCDDISP/TIOB1/SPI1_NPCS0/ I2SDI0 I/O 137 PC05 VDDIN_3V3 LCDVSYNC/TCLK1/SPI1_NPCS1/ I2SDO0 I/O 140 PC06 VDDIN_3V3 LCDHSYNC/TWD1/SPI1_NPCS2 I/O 139 PC07 VDDIN_3V3 LCDPCK/TWCK1/SPI1_NPCS3/ URXD1 I/O 138 PC08 VDDIN_3V3 LCDDEN/FIQ/PCK0/UTXD1 I/O 2 PC09 VDDISC FIQ/ISI_D0/TIOA4 I/O 9 PC10 VDDISC ISI_D1/TIOB4/CANTX0 I/O 175 PC11 VDDISC ISI_D2/TCLK4/CANRX0/A0/NBS0 I/O 3 PC12 VDDISC ISI_D3/URXD3/TK0/A1 I/O 4 PC13 VDDISC ISI_D4/UTXD3/TF0/A2 I/O 8 PC14 VDDISC ISI_D5/TD0/A3 I/O 12 PC15 VDDISC ISI_D6/RD0/A4 I/O 174 PC16 VDDISC ISI_D7/RK0/A5 I/O 5 PC17 VDDISC ISI_D8/RF0/A6 I/O 172 PC18 VDDISC ISI_D9/FLEXCOM3_IO2/A7 I/O 6 PC19 VDDISC ISI_D10/FLEXCOM3_IO1/A8 I/O 14 PC20 VDDISC ISI_D11/FLEXCOM3_IO0/A9 I/O 7 PC21 VDDISC ISI_PCK/FLEXCOM3_IO3/A10 I/O 11 PC22 VDDISC ISI_VSYNC/FLEXCOM3_IO4/A11 I/O 170 PC23 VDDISC ISI_HSYNC/A12 I/O 13 PC24 VDDISC ISI_MCK/A13 I/O 173 PC25 VDDISC ISI_FIELD/A14 I/O 115 PC26 VDDIN_3V3 CANTX1/A15 I/O 114 PC27 VDDIN_3V3 PCK1/CANRX1/A16 I/O 117 PC28 VDDIN_3V3 FLEXCOM4_IO0/PCK2/A17 I/O 118 PC29 VDDIN_3V3 FLEXCOM4_IO1/A18 I/O (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 12 SAMA5D27 SOM1 Pinout Pin Number PIO Power Rail Other Features Type 120 PC30 VDDIN_3V3 FLEXCOM4_IO2/A19 I/O 116 PC31 VDDIN_3V3 FLEXCOM4_IO3/URXD3/A20 I/O Table 4-4. System-On-Module Pin Description: PIOD Pin Number PIO Power Rail Other Features Type 121 PD00 VDDIN_3V3 FLEXCOM4_IO4/UTXD3/A23 I/O 113 PD01 VDDIN_3V3 A24 I/O 23 PD02 VDDIN_3V3 URXD1/A25 I/O 24 PD03 VDDIN_3V3 UTXD1/FIQ/NWAIT/PTCROW0 I/O 27 PD04 VDDIN_3V3 TWD1/NCS0/PTCROW1 I/O 21 PD05 VDDIN_3V3 TWCK1/NCS1/PTCROW2 I/O 22 PD06 VDDIN_3V3 PCK1/NCS2/PTCROW3 I/O 25 PD07 VDDIN_3V3 NWR1/NBS1/PTCROW4 I/O 28 PD08 VDDIN_3V3 NANDRDY/PTCROW5 I/O 58 PD19 VDDIN_3V3 PCK0/TWD1/AD0 I/O 57 PD20 VDDIN_3V3 TIOA2/TWCK1/AD1 I/O 19 PD21 VDDIN_3V3 EEPROM_TWD_PD21 I/O 20 PD22 VDDIN_3V3 EEPROM_TWCK_PD22 I/O 30 PD23 VDDIN_3V3 URXD2/AD4 I/O 29 PD24 VDDIN_3V3 UTXD2/AD5 I/O 110 PD25 VDDIN_3V3 AD6 I/O 34 PD26 VDDIN_3V3 AD7 I/O 53 PD27 VDDIN_3V3 JTAG_TCK I/O 51 PD28 VDDIN_3V3 JTAG_TDI I/O 52 PD29 VDDIN_3V3 JTAG_TDO I/O 54 PD30 VDDIN_3V3 JTAG_TMS I/O Table 4-5. System-On-Module Pin Description: System Pin Number PIO Power Rail Designation Type 61 CLK_AUDIO VDDIN_3V3 Audio clock Output 64 COMPN VDDBU External analog comparator input Input 63 COMPP VDDBU External analog comparator input Input 126 DIS_BOOT VDDIN_3V3 QSPI Interface Disable pin Input (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 13 SAMA5D27 SOM1 Pinout Pin Number PIO Power Rail Designation Type 67 USBA_M VDDIN_3V3 USB Device High Speed Data - - 68 USBA_P VDDIN_3V3 USB Device High Speed Data + - 70 USBB_M VDDIN_3V3 USB Host Port B High Speed Data - - 71 USBB_P VDDIN_3V3 USB Host Port B High Speed Data + - 74 DATA VDDHSIC USB High-Speed Inter-Chip Data - 73 STROBE VDDHSIC USB High-Speed Inter-Chip Strobe - 60 NRST VDDIN_3V3 Microprocessor reset Input / Active Low 33 PIOBU1 VDDBU Tamper or Wakeup input Input 44 PIOBU2 VDDBU Tamper or Wakeup input Input 48 PIOBU3 VDDBU Tamper or Wakeup input Input 47 PIOBU4 VDDBU Tamper or Wakeup input Input 46 PIOBU5 VDDBU Tamper or Wakeup input Input 59 PIOBU6 VDDBU Tamper or Wakeup input Input 45 PIOBU7 VDDBU Tamper or Wakeup input Input 32 RXD VDDBU Low Power Asynchronous Receiver Input 35 SHDN VDDBU Shutdown Control Output 49 WKUP VDDBU Wakeup Input 36 ETH_LED0 VDDIN_3V3 Status LED control for Ethernet ports Output 37 ETH_RXM 2.5V Physical receive or transmit signal (- differential) I/O 38 ETH_RXP 2.5V Physical receive or transmit signal (+ differential) I/O 40 ETH_TXM 2.5V Physical receive or transmit signal (- differential) I/O 41 ETH_TXP 2.5V Physical receive or transmit signal (+ differential) I/O Table 4-6. System-On-Module Pin Description: Power Pin Number PIO Description 16,17 VDDIN_3V3 Main 3.3V Supply inputs. Used for - Peripheral I/O lines and MIC2800G1JJYML supplies. 55 VDDBU Input supply for Slow Clock Oscillator, internal 32 kHz RC (c) 2018 Microchip Technology Inc. Comments Datasheet - DS60001521B-page 14 SAMA5D27 SOM1 Pinout Pin Number PIO Description Comments Oscillator and a part of the System Controller 65 VDDSDHC SDMMC I/O lines supply input - 15 VDDISC Image Sensor I/O lines supply input For decoupling guidelines, refer to the section "Design Guidelines". 1, 10, 18, 26, 31, 39, 42, 43, 50, 56, 62, 66, 69, 72, 75, 88, 89, 98, 107, 130, 131, 149, 166, 171, 176 GND Ground connections Must be connected together 129 RFU0 Reserved for future use Must be left floating 147 RFU1 Reserved for future use Must be left floating 153 RFU2 Reserved for future use Must be left floating (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 15 SAMA5D27 SOM1 Functional Description 5. Functional Description 5.1 SAMA5D27 System-In-Package The SAMA5D2 System-In-Package (SIP) (SAMA5D27C-D1G-CU) integrates the ARM Cortex-A5 processor-based SAMA5D2 MPU with 1 Gbit DDR2-SDRAM in a single package. By combining the high-performance, ultra-low-power SAMA5D2 with DDR2-SDRAM in a single package, PCB routing complexity, area and number of layers is reduced. This makes board design easier and lowers the overall cost of bill of materials. Board design is more robust by facilitating design for EMI, ESD and signal integrity. For more information about the SIP, see "Reference Documents". This section lists the sole reference documents for product information on the SAMA5D2 and the DDR2-SDRAM memory. The SAMA5D27C-D1G-CU is available in a 289-ball TFBGA package. Connections of the supplies and the system pins of the SAMA5D27C-D1G-CU are described in the following schematics. Figure 5-1. SAMA5D27C-D1G-CU Supplies Distribution Schematic BLM03AX100SZ1 1 VDDIN_3V3 2 VDDIOP2 1 2 VDDIOP1 BLM03AX100SZ1 2 1 0R 100nF 2 1 4.7F 100nF VDDOSC MLZ1608N100L 2 VDDUTMII 100nF 2.2R 100nF 100nF VDDIOP0 100nF 1 100nF 10F BLM03AX100SZ1 BLM03AX100SZ1 1 2 BLM03AX100SZ1 (c) 2018 Microchip Technology Inc. Datasheet VDDAUDIOPLL 100nF MLZ1608N100L 0R GNDUTMII 2 VDDANA 100nF 1 4.7F 2.2R DS60001521B-page 16 SAMA5D27 SOM1 Functional Description Figure 5-2. SAMA5D27C-D1G-CU Supplies Decoupling Schematic VDDCORE (1V25) D7 E9 H2 L12 P7 U3 100nF 100nF 100nF 100nF 100nF 100nF 1nF 1nF 1nF 1nF 1nF 1nF 10F VDDCORE VDDIODDR (1V8) 100nF 100nF 100nF 100nF 100nF 100nF 100nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 10F VDDIODDR E8 E11 G12 H10 J8 L10 L14 U5 VDDBU (3V3) J5 K4 VDDIOP0 (3V3) D4 F3 VDDIOP1 (3V3) N12 P12 VDDIOP2 (3V3) D9 (1V25) R7 VDDANA 1 VDDCORE 2 VDDHSIC BLM03AX100SZ1 VDDFUSE VDDAUDIOPLL BLM03AX100SZ1 1 2 VDDCORE VDDUTMIC VDDUTMII (2V5) N13 (3V3) M4 (1V25) M7 (3V3) P6 N8 VDDSDHC VDDCORE 2.2R VDDOSC 1 2 MLZ1608N100L VDDPLLA (1V25) R5 (3V3) N6 H3 VDDISC U2G VDDCORE_1 VDDCORE_2 VDDCORE_3 VDDCORE_4 VDDCORE_5 VDDCORE_6 GNDCORE_1 GNDCORE_2 GNDCORE_3 GNDCORE_4 GNDCORE_5 GNDCORE_6 VDDIODDR_1 VDDIODDR_2 VDDIODDR_3 VDDIODDR_4 VDDIODDR_5 VDDIODDR_6 VDDIODDR_7 GNDIODDR_1 GNDIODDR_2 GNDIODDR_3 GNDIODDR_4 GNDIODDR_5 GNDIODDR_6 GNDIODDR_7 GNDBU VDDBU VDDANA_1 VDDANA_2 GNDANA_1 GNDANA_2 VDDIOP0_1 VDDIOP0_2 GNDIOP0_1 GNDIOP0_2 VDDIOP1_1 VDDIOP1_2 GNDIOP1_1 GNDIOP1_2 VDDIOP2_1 GNDIOP2_1 E12 F12 J11 K6 K7 K11 E10 F8 G10 H12 J9 K10 M14 U4 M1 J6 E3 F2 M12 P11 D6 VDDHSIC VDDFUSE GNDDPLL VDDAUDIOPLL GNDAUDIOPLL VDDUTMIC GNDUTMIC VDDUTMII GNDUTMII VDDSDMMC GNDSDMMC VDDPLLA GNDPLLA VDDOSC GNDOSC VDDISC GNDISC T3 T4 R6 M6 GNDUTMII R8 T5 P5 H5 100nF 100nF 100nF 100nF 100nF 100nF 4.7F 100nF 100nF 4.7F 100nF SAMA5D27C-D1G-CU Figure 5-3. SAMA5D27C-D1G-CU System Schematic U2 U1 3 1 GND1 1 GND2 NX2016SA_24MHz 4 3 nRST WKUP 2 100R 10K Y1 12pF 50V 100R 12pF 50V SHDN RXD CLK_AUDIO T7 R3 R2 R4 T2 TST SHDN N2 T8 RXD CLK_AUDIO ADVREFP HHSDPB HHSDMB HHSDPDATC HHSDMSTRC VBG COMPP COMPN PIOBU0 PIOBU1 PIOBU2 PIOBU3 PIOBU4 PIOBU5 PIOBU6 PIOBU7 U10 T10 USBA_P USBA_M U11 T11 USBB_P USBB_M T12 U12 DATA STROBE T6 U6 U7 P3 M3 P2 P4 N4 M5 N5 N3 100R 100R COMPP COMPN LOWQ# PIOBU1 PIOBU2 PIOBU3 PIOBU4 PIOBU5 PIOBU6 PIOBU7 10pF 25V GNDUTMII R &C as close as possible 2 1 5.2 NRST JTAGSEL WKUP HHSDPA HHSDMA SAMA5D27C-D1G-CU NX2012SA_32-768KHz 8pF 50V XIN32 XOUT32 100R L9 VDDANA XIN XOUT 5.62K U9 U8 Y2 8pF 50V Power Supplies The SAMA5D27 SOM1 is supplied by an external 3.3V and generates its own internal supplies by interfacing with the Microchip MIC2800-G1JJYML power management unit. The MIC2800 is a high-performance power management IC, providing three output voltages with maximum efficiency and is optimized to respect the MPU power up and down cycles. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 17 SAMA5D27 SOM1 Functional Description Integrating a 2 MHz DC/DC converter with an LDO post regulator, the MIC2800 gives two high-efficiency outputs with a second, 300mA LDO for maximum flexibility. The DC-to-DC converter uses small values of L and C to reduce board space while still retaining efficiency over 90% at load currents up to 600mA. The three outputs supply the following internal nodes: * DCDC set @ 1.8V supplies SAMA5D27C-D1G-CU DDR2 pads and device. * LDO1 set @ 1.25V supplies SAMA5D27C-D1G-CU Core. * LDO2 set @ 2.5V supplies SAMA5D27C-D1G-CU VDDFUSE pad. The MIC2800 is a Cap design, operating with very small ceramic output capacitors and inductors for stability. It is available in fixed output voltages in the 16-pin 3mm x 3mm MLF(R) lead-less package. For more information, refer to the product web page. Figure 5-4. Power Management Unit Schematic VDDFUSE VDDIN_3V3 VDDIN_3V3 10uF 56K VDDIODDR 16 15 100K 1 LOWQ# 14 2 13 EN2 SW FB EN1 MIC2800-G1JJYML LDO LDO1 LOWQ CBYP CBIAS CSET 5.3 8 2 1 2.2uH 5 9 10 11 10uF VDDIODDR VDDCORE 2.2uF POR 12 10uF 10nF 17 100nF LDO2 4 100nF VIN1 VIN2 TPAD 6 7 PGND VDDBU SGND 4.7uF 3 100nF nRST System Control The SAMA5D27 SOM1 provides global system Reset (NRST) and Shutdown (SHDN) pins to the application board. * * The NRST pin is an output pin generated by the internal Power Management Unit (MIC2800G1JJYML) in respect with power sequence timing. It can be forced externally in case of a system crash and must be connected as described in the example schematic below. The SHDN pin is an output pin and is managed by the software application. It switches the Main 3.3V Supply ON or OFF. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 18 SAMA5D27 SOM1 Functional Description Figure 5-5. Internal System Control Schematic VDDIN_3V3 VDDBU 10K 100K nRST G2 3 D2 Q1 5 S2 4 D1 2 DMN26D0UDJ-7 G1 SHDN 6 S1 1 From SAMA5D27 5.4 Ethernet PHY The Microchip SAMA5D27 SOM1 embeds a single-supply 10BASE-T/100BASE-TX Ethernet physicallayer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ8081RNAIA is a highly-integrated PHY solution. The KSZ8081RNAIA offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant MACs in Ethernet processors. The KSZ8081RNAIA is available in 24-pin, lead-free QFN packages. For more information, refer to the product web page. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 19 SAMA5D27 SOM1 Functional Description Figure 5-6. Ethernet PHY Schematic VDDIN_3V3 1K U6 6 5 ETH_RXP ETH_RXM 4 3 1 22 25 100nF 6.49K 9 ETH_XI 8 TXP TXM RXP RXM VDD_1V2 GND PADDLE REXT REF_CLK TXD1 TXD0 TXEN RXD1 RXD0 RXER CRS_DV/PHYAD[1_0] MDC MDIO INTRP VDDA_3V3 XI GTXCK_PD09 GTX1_PD16 GTX0_PD15 GTXEN_PD10 GRX1_PD14 GRX0_PD13 GRXER_PD12 GRXDV_PD11 GMDC_PD17 GMDIO_PD18 ETH_INT_IRQ_PD31 2 4 1 7 2 VDDIO XO LED0/ANEN_SPEED RST# 3 3 GND1 ETH_XO NX2016SA_25MHz 1 GND2 2 1 22pF 50V Y3 1K 16 21 20 19 12 13 17 15 11 10 18 10uF 100nF 10uF 100nF VDDIN_3V3 10K BLM18PG181SN1D VDDIN_3V3 VDDIN_3V3 2.2uF ETH_TXP ETH_TXM 14 10K 23 ETH_LED0 24 nRST 0R KSZ8081RNAIA 22pF 50V 5.5 QSPI Memory The SAMA5D27 SOM1 embeds the SST26VF064BT-104I/MF, a 64Mb Serial Quad I/O Flash memory. The SST26VF064BT-104I/MF SQI features a six-wire, 4-bit I/O interface that allows for low-power, highperformance operation in a low pin-count package. The SST26VF064BT-104I/MF is available in 8-lead WDFN package with 6mm x 5mm dimensions. For more information, refer to the product web page. Figure 5-7. QSPI Memory Schematic VDDIN_3V3 VDDIN_3V3 VDDIN_3V3 VDDIN_3V3 100nF 10K DNP 10K DNP 10K DNP 10K DNP 10K DNP 100nF 22R 22R 22R 22R 22R QSPI_IO0_PB07 QSPI_IO1_PB08 QSPI_IO2_PB09 QSPI_IO3_PB10 QSPI_SCK_PB05 5 2 3 7 6 SI/SIO0 VDD SO/SIO1 VSS WP#/SIO2 CE# HOLD/SIO3 SCK TPAD 10K 10K 8 4 1 9 SST26VF064BT-104I/MF 22R 22R 22R 22R 22R (c) 2018 Microchip Technology Inc. 5 QSPI_CS# 4 VCC OE OUT IN GND 1 DIS_BOOT 2 3 10K DNP 22R QSPI_CS_PB06 NL17SZ126DFT2G PB07/TIOB2/PWMH3/QSPI1_IO0 PB08/TCLK3/PWML3/QSPI1_IO1 PB06/TIOA2/PWML2/QSPI1_CS 22R PB09/TIOA3/PWMFI1/QSPI1_IO2 PB10/TIOB3/PWMEXTRG1/QSPI1_IO3 PB05/TCLK2/PWMH2/QSPI1_SCK Datasheet DS60001521B-page 20 SAMA5D27 SOM1 Functional Description Tip: In case of non-use at application level of the QSPI embedded in SAMA5D27 SOM1, it is possible to reassign the signals dedicated to QSPI memory to another PIO function as defined in the table below. To do so, the DIS_BOOT pin (SAMA5D27 SOM1 pad 126) must be forced to ground. Table 5-1. Other GPIO Possibilities for QSPI Interface in Case of Non-use Pin Number Power Rail 134 VDDIN_3V3 127 133 128 132 135 VDDIN_3V3 VDDIN_3V3 VDDIN_3V3 VDDIN_3V3 VDDIN_3V3 Primary PIO Peripheral Signal Dir Func Signal Dir IOset PB05 I/O A TCLK2 I 1 C PWMH2 O 1 D QSPI1_SCK O 2 A TIOA2 I/O 1 C PWML2 O 1 D QSPI1_CS O 2 A TIOB2 I/O 1 C PWMH3 O 1 D QSPI1_IO0 I/O 2 A TCLK3 I 1 C PWML3 O 1 D QSPI1_IO1 I/O 2 A TIOA3 I/O 1 C PWMFI1 I 1 D QSPI1_IO2 I/O 2 A TIOB3 I/O 1 C PWMEXTRG1 I 1 D QSPI1_IO3 I/O 2 PB06 PB07 PB08 PB09 PB10 I/O I/O I/O I/O I/O Reset State PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST PIO, I, PU, ST Tip: The QSPI interface can be shared with another external device. To do so, the QSPI_CS# node must stay at "High" level. That means that the DIS_BOOT pin (SAMA5D27 SOM1 pad 126) must be forced to ground. 5.6 EEPROM Memory The SAMA5D27 SOM1 embeds the 24AA02E48T-I/OT, a 1Kb Serial EEPROM with pre-programmed EUI-48 MAC address. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 21 SAMA5D27 SOM1 Functional Description The device is organized as one block of 128 x 8-bit memory with a 2-wire serial interface. The second block is reserved for MAC Address storage. The 24AA02E48T-I/OT also has a page write capability for up to 8 bytes of data. The 24AA02E48T-I/OT is available in the standard 5-lead SOT-23 package. For more information, see the product web page. Figure 5-8. EEPROM Memory Schematic VDDIN_3V3 VDDIN_3V3 100nF 5 2 NC VSS VCC SCL SDA 24AA02E48T-I/OT 4 2.2K 2.2K 1 3 EEPROM_TWCK_PD22 22R EEPROM_TWD_PD21 22R PD22/EEPROM_TWCK_PD22 22R PD21/EEPROM_TWD_PD21 22R Tip: The 2-Wire serial interface can be externally shared with another device. 2-Wire Data Signal (SAMA5D27 SOM1Pad 19) and 2-Wire Clock Signal (SAMA5D27 SOM1Pad 20) are used. Important: If the 2-Wire serial interface is used externally, the device connected must have a different IC address than the embedded EEPROM. For more details, refer to the device datasheet. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 22 SAMA5D27 SOM1 Power Supply Connections and Timing ... 6. Power Supply Connections and Timing Sequences The SAMA5D27 SOM1 can be supplied in different ways depending on application needs. Four power domains must be supplied and can be connected differently. The four different power connections are described below: * Power Configuration #1: All supplies are connected to the Main 3.3V Supply. * Power Configuration #2: Backup domain is connected to a coin-cell and the rest to the Main 3.3V Supply. * Power Configuration #3: Backup domain is connected to a coin-cell. Camera sensor is connected to a separate power supply and the rest to the Main 3.3V Supply. * Power Configuration #4: All supply domains are connected to separate power supplies. For each power configuration, a Power-On and Power-Off timing sequences to respect are described below. Power Supply Configuration #1 The SAMA5D27 SOM1 is supplied by only one main supply. In this configuration mode, all supplies are connected together and supplied by the main 3.3V supply. All PIOs have VDDIN_3V3 Power Rail as voltage reference. Figure 6-1. Power Configuration #1 3.3V VDDIN_3V3 VDDBU SAMA5D27-SOM1 6.1 VDDISC VDDSDHC SHDN SHDN nRST nRST In this configuration mode, the two following timing sequences are applied. Figure 6-2. Power-On Sequence Timing Diagram SYSTEM IS OFF VDDIN_3V3 SYSTEM IS POWERED-UP RESET IS RELEASED MAIN 3.3V IS PRESENT a Tmain VDDBU VDDIN_3V3 LEVEL VDDISC c VDDSDHC d INT_VDD Tstart VDDIN_3V3 LEVEL VDDIN_3V3 LEVEL Tpor SHDN nRST (c) 2018 Microchip Technology Inc. INTERNAL SUPPLIES GENERATION e VDDIN_3V3 LEVEL f Datasheet DS60001521B-page 23 SAMA5D27 SOM1 Power Supply Connections and Timing ... Figure 6-3. Power-Off Sequence Timing Diagram SYSTEM IS ON POWER-OFF PROCEDURE VDDIN_3V3 VDDBU VDDIN_3V3 LEVEL VDDISC VDDIN_3V3 LEVEL VDDSDHC VDDIN_3V3 LEVEL INT_VDD SOFTWARE SYSTEM IS POWER-DOWN MAIN 3.3V IS PRESENT Tstop Tmain_off INTERNAL SUPPLIES SWITCH-OFF SOFTWARE IS RUNNING SHDN a SYSTEM IS OFF c d SOFTWARE SHUTDOWN SOFTWARE REQUEST Tsoft b nRST Table 6-1. Timing Values Symbol Description Min. Typ. Max. Unit tmain(1) Main 3.3V Startup Time - - 1 ms tstart Internal Delay before starting System Core Supplies 1 - 3 ms tpor Power-On Reset Delay - 10 11 ms tsoft Software Shutdown Time Depending on system off time ms tmain_off Main 3.3V Power-off Time - - 1 ms tstop Internal Delay before switching off System Core Supplies 1 - 3 ms Note: 1. The three supplies VDDIN_3V3, VDDISC and VDDSDHC must be applied at the same time. If a delay is implemented, it must be lower than 800s. VDDBU must be applied at the same time as VDDIN_3V3 or just before. It is forbidden to apply VDDBU after VDDIN_3V3. 6.2 Power Supply Configuration #2 The SAMA5D27 SOM1 is supplied by different power supplies. * * Backup domain is connected to a coin-cell. The rest of the power inputs are connected to the main 3.3V supply. In this configuration, the following PIOs have VDDBU Power Rail as reference. All other PIO have VDDIN_3V3 Power Rail as reference. * COMPP and COMPN * PIOBU1 to PIOBU7 * RXD, SHDN and WKUP (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 24 SAMA5D27 SOM1 Power Supply Connections and Timing ... Figure 6-4. Power Configuration #2 3.3V VDDIN_3V3 SAMA5D27-SOM1 VDDBU VDDISC VDDSDHC SHDN SHDN nRST nRST In this configuration, the two following timing sequences are applied. Figure 6-5. Power-On Sequence Timing Diagram SYSTEM IN BACKUP SYSTEM IS POWERED-UP VDDIN_3V3 RESET IS RELEASED MAIN 3.3V IS PRESENT b VDDBU VDDBU ALWAYS PRESENT VDDISC c VDDSDHC d Tstart VDDIN_3V3 LEVEL VDDIN_3V3 LEVEL Tmain INT_VDD SHDN INTERNAL SUPPLIES GENERATION e Tpor a VDDBU LEVEL / SOFTWARE RELEASE nRST f Figure 6-6. Power-Off Sequence Timing Diagram SYSTEM IS ON POWER-OFF PROCEDURE VDDIN_3V3 MAIN 3.3V IS PRESENT VDDBU SYSTEM IN BACKUP c VDDBU ALWAYS PRESENT VDDISC VDDIN_3V3 LEVEL VDDSDHC VDDIN_3V3 LEVEL INT_VDD SOFTWARE SYSTEM IS POWER-DOWN Tstop Tmain_off INTERNAL SUPPLIES SWITCH-OFF SOFTWARE IS RUNNING SHDN a d SOFTWARE SHUTDOWN SOFTWARE REQUEST Tsoft b nRST Table 6-2. Timing Values Symbol Description Min. Typ. Max. Unit tmain(1) Main 3.3V Startup Time - - 1 ms tstart Internal Delay before starting System Core Supplies 1 - 3 ms tpor Power-On Reset Delay - 10 11 ms tsoft Software Shutdown Time Depending on system off time ms tmain_off Main 3.3V Power-off Time - - 1 ms tstop Internal Delay before switching-off System Core Supplies 1 - 3 ms Note: (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 25 SAMA5D27 SOM1 Power Supply Connections and Timing ... 1. Power Supply Configuration #3 Some power inputs of the SAMA5D27 SOM1 are grouped and others are supplied by a separated power supplies. * * * Backup domain is connected to a coin cell. Camera sensor power input (VDDISC) is connected to a separate power supply set at one of the following voltage levels (1.8V/2.5V/2.8V/3.0V or 3.3V) depending on the camera sensor technology used in the application. The remaining power inputs are connected to the main 3.3V supply. In this configuration, the following PIOs have: * VDDBU Power Rail as reference - COMPP and COMPN - PIOBU1 to PIOBU7 - RXD, SHDN and WKUP * VDDISC Power Rail as reference - PC09 to PC25 * All other PIOs have VDDIN_3V3 Power Rail as reference. Figure 6-7. Power Configuration #3 3.3V VDDIN_3V3 VDDBU SAMA5D27-SOM1 6.3 The three supplies VDDIN_3V3, VDDISC and VDDSDHC must be applied at the same time. If a delay is implemented, it must be lower than tstart. VDDISC VDDSDHC SHDN SHDN nRST nRST In this configuration mode, the two following timing sequences are applied. Figure 6-8. Power-On Sequence Timing Diagram SYSTEM IN BACKUP WAKE UP VDDIN_3V3 SYSTEM IS POWERED-UP Ton1 VDDBU VDDISC VDDBU ALWAYS PRESENT d VDDSDHC Tstart EXTERNAL VDDISC LEVEL (1.8V/2.5V/2.8V/3.0V/3.3V) VDDIN_3V3 LEVEL c Tmain INT_VDD SHDN RESET IS RELEASED MAIN 3.3V IS PRESENT b Tpor a nRST (c) 2018 Microchip Technology Inc. INTERNAL SUPPLIES GENERATION e VDDBU LEVEL / SOFTWARE RELEASE f Datasheet DS60001521B-page 26 SAMA5D27 SOM1 Power Supply Connections and Timing ... Figure 6-9. Power-Off Sequence Timing Diagram SYSTEM IS ON POWER-OFF PROCEDURE VDDIN_3V3 VDDBU Toff1 EXTERNAL VDDISC LEVEL (1.8V/2.5V/2.8V/3.0V/3.3V) VDDSDHC d Tstop Tmain_off VDDIN_3V3 LEVEL INT_VDD INTERNAL SUPPLIES SWITCH-OFF SOFTWARE IS RUNNING SHDN a SYSTEM IN BACKUP c VDDBU ALWAYS PRESENT VDDISC SOFTWARE SYSTEM IS POWER-DOWN MAIN 3.3V IS PRESENT e SOFTWARE SHUTDOWN SOFTWARE REQUEST Tsoft b nRST Table 6-3. Timing Values Symbol Description Min. Typ. Max. Unit tmain(1) Main 3.3V Startup Time (From regulator available on the motherboard) - - 1 ms ton1 VDDISC Regulator Startup Time (From regulator - available on the motherboard) - 800 s tstart Internal Delay before starting System Core Supplies 1 - 3 ms tpor Power-On Reset Delay - 10 11 ms tsoft Software Shutdown Time Depending on system off time ms tmain_off Main 3.3V Power-off Time (From regulator available on the motherboard) - - 1 ms toff1 VDDISC Regulator Power-off Time (From regulator available on the motherboard) - - 1 ms tstop Internal Delay before switching off System Core Supplies 1 - 3 ms Note: 1. The supplies VDDIN_3V3 and VDDSDHC must be applied at the same time. If a delay is implemented, it must be lower than tstart. 6.4 Power Supply Configuration #4 Each power input of the SAMA5D27 SOM1 is supplied by separate power supplies. * * * * Backup domain is connected to a coin cell. Camera sensor power input (VDDISC) is connected to a separate power supply set at one of the following voltage levels (1.8V/2.5V/2.8V/3.0V or 3.3V) depending on the camera sensor technology used in the application. SD Card power input (VDDSDHC) is connected to a separate power supply set at one of the following voltage levels (1.8V or 3.3V) depending on the SD Card Technology/Speed used in the application. VDDIN_3V3 power input is connected to the main 3.3V supply. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 27 SAMA5D27 SOM1 Power Supply Connections and Timing ... In this configuration, the following PIOs have: * VDDBU Power Rail as reference - COMPP and COMPN - PIOBU1 to PIOBU7 - RXD, SHDN and WKUP * VDDISC Power Rail as reference - PC09 to PC25 * VDDSDHC Power Rail as reference - PA00 to PA10 * All other PIOs have VDDIN_3V3 Power Rail as reference. Figure 6-10. Power Configuration #4 3.3V VDDIN_3V3 VDDBU SAMA5D27-SOM1 SDMMC0_VDDSEL VDDISC VDDSDHC SHDN SHDN nRST nRST In this configuration mode, the two following timing sequences are applied. Figure 6-11. Power-On Sequence Timing Diagram SYSTEM IN BACKUP WAKE UP VDDIN_3V3 SYSTEM IS POWERED-UP RESET IS RELEASED MAIN 3.3V IS PRESENT b Ton1 Ton2 VDDBU VDDBU ALWAYS PRESENT VDDISC EXTERNAL VDDISC LEVEL (1.8V/2.5V/2.8V/3.0V/3.3V) d Tstart Tmain VDDSDHC DYNAMIC VDDSDHC LEVEL (3.3V) c DYNAMIC VDDSDHC LEVEL (1.8V) SDMMC0_VDDSEL g INT_VDD INTERNAL SUPPLIES GENERATION e SHDN Tsys Tpor a nRST VDDBU LEVEL / SOFTWARE RELEASE f Figure 6-12. Power-Off Sequence Timing Diagram SYSTEM IS ON VDDIN_3V3 POWER-OFF PROCEDURE Toff1 VDDBU ALWAYS PRESENT VDDISC EXTERNAL VDDISC LEVEL (1.8V/2.5V/2.8V/3.0V/3.3V) VDDSDHC LEVEL (1.8V) d VDDSDHC LEVEL (3.3V) Toff2 Tstop e Tmain_off SDMMC0_VDDSEL INT_VDD SOFTWARE SYSTEM IN BACKUP c VDDBU VDDSDHC SYSTEM IS POWER-DOWN MAIN 3.3V IS PRESENT INTERNAL SUPPLIES SWITCH-OFF SOFTWARE IS RUNNING SHDN a SOFTWARE REQUEST f SOFTWARE SHUTDOWN Tsoft b nRST (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 28 SAMA5D27 SOM1 Power Supply Connections and Timing ... Table 6-4. Timing Values Symbol Description Min. Typ. Max. Unit tmain Main 3.3V Startup Time (From regulator available on the mother board) - - 1 ms ton1 VDDISC Regulator Startup Time (From regulator - available on the mother board) - 800 s ton2 VDDSDHC Regulator Startup Time (From regulator available on the mother board) - - 800 s tstart Internal Delay before starting System Core Supplies 1 - 3 ms tpor Power-On Reset Delay - 10 11 ms tsys Low Speed to High Speed card timing(1) Depending on system on time ms tsoft Software Shutdown Time Depending on system off time ms tmain_off Main 3.3V Power-off Time (From regulator available on the motherboard) - - 1 ms toff1 VDDISC Regulator Power-off Time (From regulator available on the motherboard) - - 1 ms toff2 VDDSDHC Regulator Power-off Time (From regulator available on the motherboard) - - 1 ms tstop Internal Delay before switching off System Core Supplies 1 - 3 ms Note: 1. Timing depends on the system boot time. No particular recommendations to apply. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 29 SAMA5D27 SOM1 Booting Guidelines 7. Booting Guidelines This section provides an overview of how to program a Non Volatile Memory (NVM) and boot from it. The SAMA5D27 SOM1 embeds a Quad I/O Flash Memory as a source for boot. Another type of NVM may be located on the motherboard. This section explains how to program, select and boot from an NVM. 7.1 Boot Process The system always boots from the ROM memory at address 0x0. The ROM code is a boot program contained in the embedded ROM. It is also called "First level bootloader". The SAMA5D2 can be configured to run a Standard Boot mode or a Secure Boot mode. More information on how the Secure Boot mode can be enabled, and how the chip operates in this mode, is provided in the document "SAMA5D2x Secure Boot Strategy", document no. 44040. To obtain this application note and additional information about the secure boot and related tools, contact a Microchip sales representative. By default, the chip starts in Standard Boot Mode. The ROM code standard sequence is executed as follows: * Basic chip initialization: crystal or external clock frequency detection. * * Attempt to retrieve a valid code from external non-volatile memories (NVM). Execution of a monitor called SAM-BA Monitor, in case no valid application has been found on any NVM (1). Note: 1. This may be the case during the first start-up or after an NVM erase or when a "boot disable jumper" is used on the memory Chip Select, in order to force an update. 7.2 Boot Configuration The boot sequence is controlled using a Boot Configuration Word in the Fuse area. The Boot Configuration Word allows several customizations of the Boot Sequence: * To configure the IO Set where the external memories used to boot are connected (see Section 16.4.8 "Hardware and Software Constraints" for a description of the IO sets) * To disable the boot on selected memories * To configure the UART port used as a terminal console * To configure the JTAG pins used for debug. Refer to Debug Considerations. See the section "Boot Configuration Word" of the SAMA5D2 datasheet, document no. DS60001476, for a detailed description of all the bitfields in this word. By default, the value of this word is 0x0. During prototyping phases, the value of this fuse word can be overridden by the content of a backup register. The conditions to enable this feature are as follows: * The fuse bit DISABLE_BSCR must not be set (default value). * The Boot Sequence Controller Configuration Register (BSC_CR) must have the BUREG_VALID bit set and indicate in BUREG_INDEX which register has to be used. Using BUREG allows the user to test several boot configuration options, including Secure Boot Mode, without burning fuses. Note: VDDBU must be connected in order to benefit from this feature. However, in production, it is highly recommended to disable this feature and to write the boot configuration in fuses. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 30 SAMA5D27 SOM1 Booting Guidelines 7.3 NVM Programming The SAMA5D27 SOM1 is delivered with SAM-BA(R) In-System Programmer, a comprehensive tool to program boot memories. In case the boot code does not find a valid program in NVM, the SAM-BA monitor is launched in order to program the considered NVM. The SAM-BA monitor principle is to: * Initialize DBGU and USB. * Check if USB Device enumeration occurred. * Check if characters are received on the DBGU. Once the communication interface is identified, the application runs in an infinite loop waiting for different commands. The firmware can be sent and programmed in the NVM. For more information, refer to the following link. http://www.at91.com/linux4sam/bin/view/Linux4SAM/ Sama5d2XplainedMainPage#Using_SAM_BA_to_flash_components 7.4 Boot From External Memory Several types of external memories such as NAND Flash, SDCard, SPI Flash, QSPI Flash, etc. can be connected to the SAMA5D27 SOM1 and placed on the motherboard. For details of the Boot sequence, refer to the "NVM Bootloader Program Description for MRL C Parts" diagram of the SAMA5D2 datasheet, document no. DS60001476. The table below provides the list of external memory types and interfaces that may be used to boot the SAMA5D27 SOM1: Table 7-1. External Memory Connections Memory Type Interface PIO Comments SD-MMC0 PA0 to PA13 If external SDMMC0 interface is not used, bit SDMMC_0 in Boot Configuration Word must be set to 1. SD-MMC1 PA18 to PA22, PA27 to PA30 If external SDMMC1 Interface is not used, bit SDMMC_1 in Boot Configuration Word must be set to 1. If external SDMMC0 Interface is not used, bit SDMMC_0 in Boot Configuration Word must be set to 1. SDCard eMMC SD-MMC0 PA0 to PA10, PA13 NAND Flash NFC Field NFC in Boot Configuration Word must PA0 to PA21, PC11 to be set to "01". IOSET2 is selected. (See PC31, PD0 to PD8 Notes below) QSPI Flash QSPI0 PA0 to PA5 (c) 2018 Microchip Technology Inc. Field QSPI_0 in Boot Configuration Word must be set to "00". IOSET1 is selected. (See Notes below) Datasheet DS60001521B-page 31 SAMA5D27 SOM1 Booting Guidelines Memory Type Interface QSPI1 PIO Comments PA14 to PA19 Field QSPI_0 in Boot Configuration Word must be set to "01". IOSET2 is selected. (See Notes below) PA22 to PA27 Field QSPI_0 in Boot Configuration Word must be set to "10". IOSET3 is selected. (See Notes below) PB5 to PB10 Need to tie DIS-BOOT pin to GND. Bits QSPI_1 in Boot Configuration Word must be set to "01". IOSET2 is selected. (See Notes below) PA14 to PA17 Bits SPI_0 in Boot Configuration Word must be set to "00". IOSET1 is selected. (See Notes below) PA30, PA31, PB0, PB1 Bits SPI_0 in Boot Configuration Word must be set to "01". IOSET2 is selected. (See Notes below) PA22 to PA25 Bits SPI_1 in Boot Configuration Word must be set to "01". IOSET2 is selected. (See Notes below) PC1 to PC4 Bits SPI_1 in Boot Configuration Word must be set to "00". IOSET1 is selected. (See Notes below) SPI0 SPI Flash SPI1 Note: For these external memory configurations, set the EXT_MEM_BOOT_ENABLE bit to "1" in Boot Configuration Word. Note: The Boot Configuration Word allows several customizations of the boot sequence. For details, refer to the section "Boot Configuration" in the SAMA5D2 datasheet, document no. DS60001476. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 32 SAMA5D27 SOM1 Debug Considerations 8. Debug Considerations The SAMA5D27 SOM1 JTAG access is disabled during the execution of the ROM code sequence. It is re-enabled when jumping into SRAM when a valid code has been found on an external NVM, at the same time the ROM memory and fuses are hidden. If no valid boot is found on an external NVM, the ROM code * enables the USB connection and one UART serial port * starts the standard SAM-BA monitor * locks access to the ROM memory * re-enables the JTAG connection The SAMA5D27 SOM1 has multiple debug and JTAG settings. For more information, refer to the SAMA5D2 datasheet, document no. DS60001476, "SECUMOD JTAG Protection Control Register", "Customer Fuse Matrix" and "Special Function Bits". The JTAG I/O set can be configured. For correct operations, the I/O set to be used is JTAG_IOSET_3, i.e., the field JTAG_IO_SET in the Boot Configuration Word must be written with value '2'.(1) Note: Due to IO conflict on line PA22, JTAG_IOSET_4 must not be implemented when SDMMC1 is used as an NVM boot media. See the SAMA5D2 datasheet, document no. DS60001476, "Boot Configuration Word". (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 33 SAMA5D27 SOM1 Electrical Characteristics 9. Electrical Characteristics This section provides an overview of the electrical characteristics of the SAMA5D27 SOM1 module. Absolute maximum ratings for the SAMA5D27 SOM1 module are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the module at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. 9.1 Absolute Maximum Ratings Table 9-1. Absolute Maximum Ratings Parameter Conditions Min. Max. Storage Temperature - -60C +150C Maximum Operating Temperature - -40C +85C Voltage on Inputs Pins With respect to ground -0.3V +4.0V On VDDIN_3V3 Pads - +4.0V On VDDBU Pad - +4.0V On VDDSDHC Pad - +4.0V On VDDISC Pad - +4.0V Maximum Voltage Important: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 9.2 Operational Characteristics The following characteristics are applicable to the operating temperature range TA = -40C to +85C, unless otherwise specified. Table 9-2. Table 7. Power Supplies Operating Conditions Pad Parameters Conditions Min. Typ. Max. DC Supply - 3.0V 3.3V 3.6V VDDIN_3V3 Maximum Input Current - - - 450mA VDDBU DC Supply Must be established first or at the same time as VDDIN_3V3. 1.65V 3.3V 3.6V (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 34 SAMA5D27 SOM1 Electrical Characteristics Pad VDDSDHC VDDISC Parameters Conditions Maximum Input Current - DC Supply SDHC I/Os Lines Maximum Input Current - DC Supply ISC I/Os Lines Maximum Input Current - Min. Typ. Max. - - 0.1 mA 1.65V 3.3V 3.6V - - 30mA 1.65V 3.3V 3.6V - - 30mA 9.3 DC Electrical Characteristics 9.3.1 Standard Interfaces The following characteristics are applicable to the operating temperature range TA = -40C to +85C, unless otherwise specified. Table 9-3. DC Electrical Characteristicsfor GPIO Inputs Pad Parameters Conditions Min. Typ. Max. VIL Low-level Input Voltage All GPIO @ 3.3V -0.3V - 0.4V VIH High-level Input Voltage All GPIO @ 3.3V 2.3V - 3.6V VOL Low-level Output Voltage IO Max. - - 0.41V VOH High-level Output Voltage IO Max. 2.9V - -- IIL Low-level Input Current All GPIO @ 3.3V -1A - 1A IIH High-level Input Current All GPIO @ 3.3V -1A - 1A IOL Low-level Output Current All GPIO @ 3.3V / Low -2mA - -- All GPIO @ 3.3V / High -32mA - -- IOH High-level Output Current All GPIO @ 3.3V / Low - - 2mA All GPIO @ 3.3V / High - - 32mA Pull-up Resistors All GPIO @ 3.3V and PDxx in AD mode. 280k 380k 480k All IOs in GPIO mode @3.3V. 40k 66k 130k RPULLUP (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 35 SAMA5D27 SOM1 Electrical Characteristics Pad Parameters RPULLDOWN Pull-down Resistors Conditions Min. Typ. Max. All GPIO @ 3.3V and PDxx in AD mode 280 k 380k 480k All IOs in GPIO mode @3.3V. 40k 77k 160k Note: This table applies to all the following pads: PA0-PA31, PB0-PB31, PC0-PC31, PD0-PD8, PD19PD30. 9.3.2 Other PIOs The following characteristics are applicable to the operating temperature range TA = -40C to +85C, unless otherwise specified. Table 9-4. Table 7. DC Electrical Characteristics for System Inputs Pad Parameters Conditions Min. Typ. Max. VIL Low-level Input Voltage DIS_BOOT - - 1.0V VIH High-level Input Voltage DIS_BOOT 2.3V - - (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 36 SAMA5D27 SOM1 Mechanical Characteristics 10. Mechanical Characteristics 10.1 Module Dimensions The SAMA5D27 SOM1 has dimensions of 40mm x 38mm with the specific following mechanical characteristics. Figure 10-1. System-On-Module Dimensions E1 PIN 1 CORNER S 131 132 133 140 134 137 135 136 143 141 142 144 138 139 146 145 152 149 147 148 150 151 158 153 154 161 159 160 155 162 156 157 164 163 171 170 167 165 166 172 174 173 168 169 175 176 E2 1 130 2 129 3 128 4 127 5 126 6 7 124 8 123 9 10 122 121 11 120 125 12 119 118 117 15 116 16 115 17 114 18 113 19 112 20 111 21 110 22 109 23 108 24 25 106 26 105 27 28 104 103 29 102 aaa P1t 107 30 101 31 100 99 32 33 98 34 97 35 96 86 P2 184 180 (TP8) (TP4) 91 (TP7) 186 e (TP10) 31 182 27 26 25 (TP6) 185 (TP9) aaa 179 P1b (TP3) D BOTTOM VIEW 82 70 59 54 51 47 48 183 A1 P2Eb E 41 nx ff 88 87 84 83 82 85 81 80 79 78 75 77 76 74 72 69 71 70 68 73 66 67 65 63 64 62 60 57 59 58 56 55 61 54 89 53 90 42 52 91 41 51 40 50 92 45 93 39 48 49 38 47 94 46 95 37 44 36 43 D1 14 D2 TOP VIEW 13 177 9 8 181 (TP1) 178 (TP2) 4 P2 155 173 170 (TP5) jjj x m jjj P2Ea f fxn ff B SAMA5D27-SOM1 DIMENSIONS 176 40 x 38 x 2.80 0.8 mm Pads : Body : Pads Pitch : Units: Drawn by : R C R SAMA5D27-SOM1_POD A11 02/05/2017 Table 10-1. System-On-Module Dimensions Common Dimensions Symbol Min. Typ. Max. Comments X E -- 40.000 40.100 - Y D -- 38.000 38.100 - Pad Pitch e -- 0.800 -- - PCB Thickness S 1.150 1.200 1.250 - Total Thickness A1 -- 2.750 2.800 - PCB Angle Hole Diameter(1) B Body Size (c) 2018 Microchip Technology Inc. - Datasheet 0.200 - - DS60001521B-page 37 SAMA5D27 SOM1 Mechanical Characteristics Common Dimensions Symbol Pad Length(1) Min. Typ. Comments Max. Bottom Side P1b - 1.500 - - Top Side P1t - 0.800 - - - Solder Mask defined 0.550 - - - 0.400 typic minus metallization - - Pad Width(1) P2 Pad Space(1) aaa Opening Drilling Diameter - 0.600 - 0.200 - fff Pad Count n Edge Center to Center Pad Axis to Edge(1) 0.400 - 176 X E1 37.550 37.630 37.700 - Y D1 34.400 34.480 34.550 - X E2 35.550 35.630 35.700 - Y D2 32.400 32.480 32.550 - X P2Ea - 2.000 - - Y P2Eb - 2.600 - - Note: 1. Tolerances are defined upon: - IPC A600 - Class2 - IPC 2615 WARNING 10.2 Test points placed on the bottom side are used for factory test only. It is not possible to connect external devices on these test points. Module Land Pattern The SAMA5D27 SOM1 Module has the following recommended Land Pattern characteristics. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 38 SAMA5D27 SOM1 Mechanical Characteristics Figure 10-2. System-On-Module Land Pattern LAND PATTERN RECOMMENDATIONS PIN 1 CORNER S1 k S2 W L Pads : Body : Pads Pitch : Units: WARNING SAMA5D27-SOM1 DIMENSIONS 176 40 x 38 x 2.80 0.8 mm Drawn by : R C R SAMA5D27-SOM1_POD A11 02/05/2017 Do not place vias, copper or signals in the S1-S2 area on the top PCB layer of the motherboard. Copper and low-speed signals may be used on inner and opposite layers. Table 10-2. System-On-Module Land Pattern Dimensions Symbol Common Dimensions Min. Typ. Max. Comments Land Pattern Pad Width W - 0.600 - Solder Mask Defined 0.550 Land Pattern Pad Length L - 2.000 - - Land Pattern Pad X Space S1 - 37.000 - - Land Pattern Pad Y Space S2 - 35.000 - - k - 0.200 - - Land Pattern Pad Space (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 39 SAMA5D27 SOM1 Production Settings 11. Production Settings 11.1 Bake Information The SAMA5D27-SOM1 module is rated MSL 3, indicating that storage and assembly processes must be compliant with IPC/JEDEC J-STD-033C. The SAMA5D27-SOM1 module has a total thickness of 2.750 mm (PCB and SMD mounted) and is comparable to a die package. Thus baking instructions must comply with Table 4-1 of J-STD-033-C as a package body comprised between 2.0mm and 4.5mm. Refer to the highlighted information in the table below. IPC/JEDEC J-STD-033C February 2012 Table 4-1 Reference Conditions for Drying Mounted or Unmounted SMD Packages (User Bake: Floor life begins counting at time = 0 after bake) Bake @ 125 C +10/-0 C Package Body Thickness 1.4 mm Thickness >1.4 mm 2.0 mm Thickness >2.0 mm 4.5 mm BGA package >17 mm x 17 mm or any stacked die package Level Exceeding Floor Life by >72 h Exceeding Floor Life by 72 h Bake @ 90 C +8/-0 C 5% RH Exceeding Floor Life by >72 h Exceeding Floor Life by 72 h Bake @ 40 C +5/-0 C 5% RH Exceeding Floor Life by >72 h Exceeding Floor Life by 72 h 2 5 hours 3 hours 17 hours 11 hours 8 days 5 days 2a 7 hours 5 hours 23 hours 13 hours 9 days 7 days 3 9 hours 7 hours 33 hours 23 hours 13 days 9 days 4 11 hours 7 hours 37 hours 23 hours 15 days 9 days 5 12 hours 7 hours 41 hours 24 hours 17 days 10 days 5a 16 hours 10 hours 54 hours 24 hours 22 days 10 days 2 18 hours 15 hours 63 hours 2 days 25days 20 days 2a 21 hours 16 hours 3 days 2 days 29 days 22 days 3 27 hours 17 hours 4 days 2 days 37 days 23 days 4 34 hours 20 hours 5 days 3 days 47 days 28 days 5 40 hours 25 hours 6 days 4 days 57 days 35 days 5a 48 hours 40 hours 8 days 6 days 79 days 56 days 2 48 hours 48 hours 10 days 7 days 79 days 67 days 2a 48 hours 48 hours 10 days 7 days 79 days 67 days 3 48 hours 48 hours 10 days 8 days 79 days 67 days 4 48 hours 48 hours 10 days 10 days 79 days 67 days 5 48 hours 48 hours 10 days 10 days 79 days 67 days 5a 48 hours 48 hours 10 days 10 days 79 days 67 days 2-5a 96 hours (See Note 2) As above per package thickness and moisture level Not applicable As above per package thickness and moisture level Not applicable As above per package thickness and moisture level Note 1: Table 4-1 is based on worst-case molded lead frame SMD packages. Users may reduce the actual bake time if technically justified (e.g., absorption/ desorption data, etc.). In most cases it is applicable to other nonhermetic surface mount SMD packages. If parts have been exposed to >60% RH it may be necessary to increase the bake time by tracking desorption data to ensure parts are dry. Note 2: For BGA packages >17 mm x 17 mm, that do not have internal planes that block the moisture diffusion path in the substrate, may use bake times based on the thickness/moisture level portion of the table. Note 3: If baking of packages >4.5 mm thick is required see appendix B. 11.2 Reflow Profile The SAMA5D27 SOM1 was assembled using standard lead-free reflow profile IPC/JEDEC J-STD-020E. We recommend a maximum of two soldering processes. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 40 SAMA5D27 SOM1 Production Settings The SAMA5D27 SOM1can be soldered to the host PCB by using the standard and lead-free solder reflow profile. To avoid damage to the module, follow the JEDEC recommendations as well as those listed below: * Do not exceed the peak temperature (Tp) of 245C. * Refer to the solder paste datasheet for specific reflow profile recommendations. * Use no-clean flux solder paste. * Use only one flow. If the PCB requires multiple flows, mount the module at the time of the final flow. Figure 11-1. Reflow Profile Example used for Soldering SAMA5D27 SOM1 Module on SAMA5D27SOM1-EK1 Board - Supplier Tp > Tc - User Tp < Tc Tc Supplier tp Tc -5C User tp Te m p e r a t u r e Tp tp Max. Ramp Up Rate = 3C/s Max. Ramp Down Rate = 6C/s TL Tsmax Tc -5C tL Preheat Area Tsmin ts 25 Time 25C to Peak Time IPC-020e-5-1 Profile Feature J-STD-020E Profile Temperature Min Tsmin 150C Temperature Max Tsmax 200C Temperature Rise ts (from Tsmin to Tsmax) 60 to 120 seconds Ramp-up Rate TL to Tp 3C/sec.max Liquidous Temperature Time maintained above 217C TL 60 to 150 seconds Peak Temperature Tp 245C Time (tp) within 5C of the specified classification temperature (Tc) 30 seconds Ramp-down rate 6C/second max Tp to TL Time 25C to peak temperature (c) 2018 Microchip Technology Inc. 8 minutes max Datasheet DS60001521B-page 41 SAMA5D27 SOM1 Ordering Information 12. Ordering Information Table 12-1. Ordering Information Ordering Code Version Package Carrier Type Operating Temperature Range ATSAMA5D27-SOM1 1 176-pin 38x40mm Tray -40C to +85C (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 42 SAMA5D27 SOM1 Revision History 13. Revision History Table 13-1. SAMA5D27 SOM1 Datasheet, Rev. DS60001521B, Feb-2018 Changes Features: added PTC support and LCD interface. Applications: updated list. Description: added PTC support. Reference Documents: corrected datasheet cross-reference. Pinout Overview: updated figure with correct color key. SAMA5D27C-D1G-CU Supplies Decoupling Schematic: updated all occurrences of 1V2 to 1V25. SAMA5D27 System-In-Package: removed table "SAMA5D27C-D1G-CU External Crystal". Power Supplies: LDO1 output changed to 1.25V Ethernet PHY: removed table "KSZ8081RNAIA External Crystal". QSPI Memory Schematic: updated QSPI memory reference. EEPROM Memory: updated Important Note. Module Land Pattern: added Warning. Added Production Settings. Updated Reflow Profile. Updated Ordering Information. Table 13-2. SAMA5D27 SOM1 Datasheet, Rev. DS60001521A, Oct-2017 Changes First issue. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 43 SAMA5D27 SOM1 The Microchip Web Site Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: * * * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Customer Change Notification Service Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at http://www.microchip.com/. Under "Support", click on "Customer Change Notification" and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 44 SAMA5D27 SOM1 Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. ATSAMA5 D27 - SOM1 Architecture Product Group System on Module Version Architecture: SAMA5 Product Group: D27 System on Module: SOM Version: 1 Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: * * * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 45 SAMA5D27 SOM1 Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-2664-6 AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11, Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali, Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK, ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, Vision, Versatile are trademarks or registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California (R) (R) and India. The Company's quality system processes and procedures are for its PIC MCUs and dsPIC (c) 2018 Microchip Technology Inc. Datasheet DS60001521B-page 46 SAMA5D27 SOM1 (R) DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2018 Microchip Technology Inc. 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