Synchronous DRAM
Rev. 1.2 February 2008
1 of 15
K4S280832K
K4S281632K
K4S280432K
128Mb K-die SDRAM Specification
* Samsung Electronics reserves the right to change products or specification without notice.
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure couldresult in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
54 TSOP-II with Pb-Free & Halogen-Free
(RoHS compliant)
Synchronous DRAM
Rev. 1.2 February 2008
2 of 15
K4S280832K
K4S281632K
K4S280432K
Table of Contents
1.0 FEATURES .................................................................................................................................... 4
2.0 GENERAL DESCRIPTION ............................................................................................................ 4
3.0 Ordering Information ................................................................................................................... 4
4.0 Package Physical Dimension ..................................................................................................... 5
5.0 FUNCTIONAL BLOCK DIAGRAM ................................................................................................ 6
6.0 PIN CONFIGURATION (Top view) .............................................................................................7
7.0 PIN FUNCTION DESCRIPTION .................................................................................................... 7
8.0 ABSOLUTE MAXIMUM RATINGS ............................................................................................... 8
9.0 DC OPERATING CONDITIONS ....................................................................................................8
10.0 CAPACITANCE ........................................................................................................................... 8
11.0 DC CHARACTERISTICS (x4, x8) ...............................................................................................9
12.0 DC CHARACTERISTICS (x16) ................................................................................................. 10
13.0 AC OPERATING TEST CONDITIONS ...................................................................................... 11
14.0 OPERATING AC PARAMETER ................................................................................................ 11
15.0 AC CHARACTERISTICS .......................................................................................................... 12
16.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS ............................................................... 12
17.0 IBIS SPECIFICATION ............................................................................................................... 13
18.0 SIMPLIFIED TRUTH TABLE ..................................................................................................... 15
Synchronous DRAM
Rev. 1.2 February 2008
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K4S281632K
K4S280432K
Revision History
Revision Month Year History
1.0 February 2007 - Release revision 1.0 SPEC
1.1 November 2007 - Revised typo of package dimension
- Added the comment of Halogen-free supporting
1.2 February 2008 - Added -50 bin(200MHz) DRAM
Synchronous DRAM
Rev. 1.2 February 2008
4 of 15
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K4S281632K
K4S280432K
Part No. Orgainization Max Freq. Interface Package
K4S280432K-U*1C/L75 32Mb x 4 133MHz (CL=3)
LVTTL
54pin TSOP(II)
Pb-free & Halogen-free*1
K4S280832K-UC/L75 16Mb x 8 133MHz (CL=3)
K4S281632K-UC/L50 8Mb x 16 200MHz(CL=3)
K4S281632K-UC/L60 8Mb x 16 166MHz (CL=3)
K4S281632K-UC/L75 8Mb x 16 133MHz (CL=3)
The K4S280432K / K4S280832K / K4S281632K is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
2,097,152 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
• 54pin TSOP II Pb-Free and Halogen-Free package
• RoHS compliant
8M x 4Bit x 4 / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
Row & Column address configuration
Organization Row Address Column Address
16Mx8 A0~A11 A0-A9
8Mx16 A0~A11 A0-A8
1.0 FEATURES
2.0 GENERAL DESCRIPTION
3.0 Ordering Information
Note 1 : 128Mb K-die SDR DRAMs support Pb-free & Halogen-free package with Pb-free package code(-U).
Synchronous DRAM
Rev. 1.2 February 2008
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4.0 Package Physical Dimension
54Pin TSOP(II) Package Dimension
#1
(1.50)
(1.50)
#54 #28
#27
10.16 ± 0.10
(R 0.15)
22.22 ± 0.10
0.210 ± 0.05
0.665 ± 0.05
(R 0.15)
(0.71) [0.80 ± 0.08]
0.80TYP
0.35 +0.10
- 0.05
(10°)
1.00 ± 0.10
0.05 MIN
(10°)
1.20 MAX
0.10 MAX
0.075 MAX
[
[
(10.76)
0.125 +0.075
- 0.035
(10°)
(10°)
11.76 ± 0.20
(0.80)(0.80)
(0.50)
(4°)
0.45 ~ 0.75
(0° ∼ 8°)
0.25TYP
(R 0.25)
(R 0.25)
(0.50)
Unit : mm
NOTE
1. ( ) IS REFERENCE
2. [ ] IS ASS’Y OUT QUALITY
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Bank Select
Data Input Register
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
5.0 FUNCTIONAL BLOCK DIAGRAM
Synchronous DRAM
Rev. 1.2 February 2008
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Pin Name Input Function
CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A11 Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA11,
Column address : (x4 : CA0 ~ CA9,CA11), (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)
BA0 ~ BA1Bank select address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
DQ0 ~ NData input/output Data inputs/outputs are multiplexed on the same pins.
(x4 : DQ0 ~ 3), (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU No connection
/reserved for future use This pin is recommended to be left No Connection on the device.
54Pin TSOP
(400mil x 875mil)
(0.8 mm Pin pitch)
VDD
N.C
VDDQ
N.C
DQ0
VSSQ
N.C
N.C
VDDQ
N.C
DQ1
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
N.C
VSSQ
N.C
DQ3
VDDQ
N.C
N.C
VSSQ
N.C
DQ2
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
N.C
DQ1
VSSQ
N.C
DQ2
VDDQ
N.C
DQ3
VSSQ
N.C
VDD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ7
VSSQ
N.C
DQ6
VDDQ
N.C
DQ5
VSSQ
N.C
DQ4
VDDQ
N.C
VSS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
N.C/RFU
UDQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
VSS
x16 x8 x4 x16
x8x4
6.0 PIN CONFIGURATION (Top view)
7.0 PIN FUNCTION DESCRIPTION
Synchronous DRAM
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K4S280432K
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1W
Short circuit current IOS 50 mA
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDD+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL --0.4VIOL = 2mA
Input leakage current ILI -10 - 10 uA 3
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
Notes :
(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin Symbol Min Max Unit
Clock CCLK 2.5 3.5 pF
RAS, CAS, WE, CS, CKE, DQM CIN 2.5 3.8 pF
Address CADD 2.5 3.8 pF
(x4 : DQ0 ~ DQ3), (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15) COUT 4.0 6.0 pF
8.0 ABSOLUTE MAXIMUM RATINGS
9.0 DC OPERATING CONDITIONS
10.0 CAPACITANCE
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(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
75
Operating current
(One bank active) ICC1
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
90 mA 1
Precharge standby current in
power-down mode
ICC2P CKE ≤ VIL(max), tCC = 10ns 2 mA
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞2
Precharge standby current in
non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 20
mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 10
Active standby current in
power-down mode
ICC3P CKE ≤ VIL(max), tCC = 10ns 5 mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞5
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 30 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 25 mA
Operating current
(Burst mode) ICC4 IO = 0 mA
Page burst 110 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 200 mA 2
Self refresh current ICC6 CKE ≤ 0.2V C2mA3
L 800 uA 4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S280832K-UC
4. K4S280832K-UL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Notes :
11.0 DC CHARACTERISTICS (x4, x8)
Synchronous DRAM
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(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition Version Unit Note
50 60 75
Operating current
(One bank active) ICC1
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
140 130 100 mA 1
Precharge standby current in
power-down mode
ICC2P CKE ≤ VIL(max), tCC = 10ns 2 mA
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞2
Precharge standby current in
non power-down mode
ICC2NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 20
mA
ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable 10
Active standby current in
power-down mode
ICC3P CKE ≤ VIL(max), tCC = 10ns 5 mA
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞5
Active standby current in
non power-down mode
(One bank active)
ICC3NCKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns 30 mA
ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
25 mA
Operating current
(Burst mode) ICC4
IO = 0 mA
Page burst 4Banks Activated
tCCD = 2CLKs
160 150 140 mA 1
Refresh current ICC5 tRC ≥ tRC(min) 230 220 200 mA 2
Self refresh current ICC6 CKE ≤ 0.2V C2mA3
L800uA4
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S281632K-UC
4. K4S281632K-UL
5. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ)
Notes :
12.0 DC CHARACTERISTICS (x16)
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(VDD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter Value Unit
Input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
3.3V
1200Ω
870Ω
Output
50pF
VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt = 1.4V
50Ω
Output
50pF
Z0 = 50Ω
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
Notes :
(AC operating conditions unless otherwise noted)
Parameter Symbol Version Unit
50 (x16 only) 60 (x16 only) 75
Row active to row active delay tRRD(min) 10 12 15 ns
RAS to CAS delay tRCD(min) 15 18 20 ns
Row precharge time tRP(min) 15 18 20 ns
Row active time tRAS(min) 40 42 45 ns
tRAS(max) 100 us
Row cycle time tRC(min) 55 60 65 ns
Last data in to row precharge tRDL(min) 2 CLK
Last data in to Active delay tDAL(min) 2 CLK + tRP -
Last data in to new col. address delay tCDL(min) 1 CLK
Last data in to burst stop tBDL(min) 1 CLK
Col. address to col. address delay tCCD(min) 1 CLK
Number of valid output data CAS latency=3 2 ea
CAS latency=2 - 1
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the
next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
6. tRC =tRFC, tRDL = tWR.
13.0 AC OPERATING TEST CONDITIONS
14.0 OPERATING AC PARAMETER
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Parameter Symbol Condition Min Typ Max Unit Notes
Output rise time trh Measure in linear
region : 1.2V ~ 1.8V 1.37 4.37 Volts/ns 3
Output fall time tfh Measure in linear
region : 1.2V ~ 1.8V 1.30 3.8 Volts/ns 3
Output rise time trh Measure in linear
region : 1.2V ~ 1.8V 2.8 3.9 5.6 Volts/ns 1,2
Output fall time tfh Measure in linear
region : 1.2V ~ 1.8V 2.0 2.9 5.0 Volts/ns 1,2
1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to VSS.
Notes :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
4. tSS applies for address setup time, clock enable setup time, commend setup time and data setup time
tSH applies for address holde time, clock enable hold time, commend hold time and data hold time
Notes :
(AC operating conditions unless otherwise noted)
Parameter Symbol 50 (x16 only) 60 (x16 only) 75
Min Max Min Max Min Max
CLK cycle time CAS latency=3 tCC
51000 61000 7.5 1000
CAS latency=2 - - 10
CLK to valid
output delay
CAS latency=3 tSAC
-4.555.4
CAS latency=2 - - - 6
Output data
hold time
CAS latency=3 tOH
2-2.5 3
CAS latency=2 - - - 3
CLK high pulse width tCH 2-2.5 2.5
CLK low pulse width tCL 2-2.5 2.5
Input setup time tSS 1.5 - 1.5 1.5
Input hold time tSH 1-1 0.8
CLK to output in Low-Z tSLZ 1-1 1
CLK to output
in Hi-Z
CAS latency=3 tSHZ
-4.555.4
CAS latency=2 - - - 6
15.0 AC CHARACTERISTICS
16.0 DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
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IOH Characteristics (Pull-up)
Voltage
200MHz
166MHz
133MHz
Min
200MHz
166MHz
133MHz
Max
(V) I (mA) I (mA)
3.45 -2.4
3.3 -27.3
3.0 0.0 -74.1
2.6 -21.1 -129.2
2.4 -34.1 -153.3
2.0 -58.7 -197.0
1.8 -67.3 -226.2
1.65 -73.0 -248.0
1.5 -77.9 -269.7
1.4 -80.8 -284.3
1.0 -88.6 -344.5
0.0 -93.0 -502.4
IOL Characteristics (Pull-down)
Voltage
200MHz
166MHz
133MHz
Min
200MHz
166MHz
133MHz
Max
(V) I (mA) I (mA)
0.0 0.0 0.0
0.4 27.5 70.2
0.65 41.8 107.5
0.85 51.6 133.8
1.0 58.0 151.2
1.4 70.7 187.7
1.5 72.9 194.4
1.65 75.4 202.5
1.8 77.0 208.6
1.95 77.6 212.0
3.0 80.3 219.6
3.45 81.4 222.6
0
-100
-200
-300
-400
-500
-600
030.5 1 1.5 2 2.5 3.5
Voltage
mA
250
200
150
100
50
0
030.5 1 1.5 2 2.5 3.5
Voltage
mA
200MHz/166MHz /133MHz Pull-up
200MHz/166MHz /133MHz Pull-down
IOH Min (200MHz/166MHz/133MHz)
IOH Max (200MHz/166MHz/133MHz)
IOH Min (200MHz/166MHz/133MHz)
IOH Max (200MHz/166MHz/133MHz)
17.0 IBIS SPECIFICATION
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VDD Clamp @ CLK, CKE, CS, DQM & DQ
VDD (V) I (mA)
0.0 0.0
0.2 0.0
0.4 0.0
0.6 0.0
0.7 0.0
0.8 0.0
0.9 0.0
1.0 0.23
1.2 1.34
1.4 3.02
1.6 5.06
1.8 7.35
2.0 9.83
2.2 12.48
2.4 15.30
2.6 18.31
VSS Clamp @ CLK, CKE, CS, DQM & DQ
VSS (V) I (mA)
-2.6 -57.23
-2.4 -45.77
-2.2 -38.26
-2.0 -31.22
-1.8 -24.58
-1.6 -18.37
-1.4 -12.56
-1.2 -7.57
-1.0 -3.37
-0.9 -1.75
-0.8 -0.58
-0.7 -0.05
-0.6 0.0
-0.4 0.0
-0.2 0.0
0.0 0.0
20
15
10
5
0
0312
Voltage
mA
I (mA)
mA
I (mA)
Minimum VDD clamp current
(Referenced to VDD)
Minimum VSS clamp current
0
-10
-20
-30
-40
-3 0-2 -1
-50
-60
Voltage
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(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A0 ~ A9,
A11, Note
Register Mode register set H X L L L L X OP code 1,2
Refresh
Auto refresh HHLL LHX X 3
Self
refresh
Entry L 3
Exit L H LH HHXX
3
HX XX 3
Bank active & row addr. H X L L H H X V Row address
Read &
column address
Auto precharge disable HXLHLHXV
LColumn
address
4
Auto precharge enable H 4,5
Write &
column address
Auto precharge disable H X LHLLX V LColumn
address
4
Auto precharge enable H 4,5
Burst stop H X L H H L X X 6
Precharge Bank selection HXLLHLX
VL X
All banks XH
Clock suspend or
active power down
Entry H L HX X X XXLV VV
Exit L H X X X X X
Precharge power down mode
Entry H L HX X X X
X
LH HH
Exit L H HX X X X
LV VV
DQM H X V X 7
No operation command H X HX XX XX
LH HH
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Notes :
18.0 SIMPLIFIED TRUTH TABLE
