NXP Semiconductors
Data Sheet: Technical Data
NXP reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
Document Number: IMX28CEC
Rev. 4, 10/2018
i.MX28
Package Information
Plastic package
Case MAPBGA-289, 14 x 14 mm, 0.8 mm pitch
Ordering Information
See Table on page 3 for ordering information.
1 Introduction
The i.MX28 is a low-power, high-performance
applications processor optimized for the general
embedded industrial and consumer markets. The core of
the i.MX28 is NXP's fast, power-efficient
implementation of the ARM926EJ-S™ core, with
speeds of up to 454 MHz.
The device is suitable for a wide range of applications,
including the following:
• Human-machine interface (HMI) panels:
industrial, home
• Industrial drive, PLC, I/O control display, factory
robotics display, graphical remote controls
• Handheld scanners and printers
• Patient-monitoring, portable medical devices
• Smart energy meters, energy gateways
• Media phones, media gateways
The integrated power management unit (PMU) on the
i.MX28 is composed of a triple output DC-DC switching
converter and multiple linear regulators. These provide
i.MX28 Applications
Processors for Consumer
Products
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Ordering Information and Functional
Part Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Special Signal Considerations. . . . . . . . . . . . . . . . 11
3 Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 i.MX28 Device-Level Conditions . . . . . . . . . . . . . . 11
3.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . 18
3.3 I/O DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 I/O AC Timing and Parameters . . . . . . . . . . . . . . . 22
3.5 Module Timing and Electrical Parameters. . . . . . . 27
4 Package Information and Contact Assignments . . . . . . . 59
4.1 Case MAPBGA-289, 14 x 14 mm, 0.8 mm Pitch. . 59
4.2 Ground, Power, Sense, and Reference Contact
Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3 Signal Contact Assignments . . . . . . . . . . . . . . . . . 61
4.4 i.MX280 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 63
4.5 i.MX283 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 65
4.6 i.MX286 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.7 i.MX287 Ball Map . . . . . . . . . . . . . . . . . . . . . . . . . 69
5 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Introduction
i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018
NXP Semiconductors2
power sequencing for the device and its I/O peripherals such as memories and SD cards, as well as provide
battery charging capability for Li-Ion batteries.
The i.MX28 processor includes an additional 128-Kbyte on-chip SRAM to make the device ideal for
eliminating external RAM in applications with small footprint RTOS.
The i.MX28 supports connections to various types of external memories, such as mobile DDR, DDR2 and
LV-DDR2, SLC and MLC NAND Flash.
The i.MX28 can be connected to a variety of external devices such as high-speed USB2.0 OTG, CAN,
10/100 Ethernet, and SD/SDIO/MMC.
1.1 Device Features
The following lists the features of the i.MX28:
• ARM926EJ-S CPU running at 454 MHz:
— 16-Kbyte instruction cache and 32-Kbyte data cache
— Arm embedded trace macrocell (CoreSight™ ETM9™)
— Parallel JTAG interface
• 128 KBytes of integrated low-power on-chip SRAM
• 128 KBytes of integrated mask-programmable on-chip ROM
• 1280 bits of on-chip one-time-programmable (OCOTP) ROM
• 16-bit mobile DDR (mDDR) (1.8 V), DDR2 (1.8 V) and LV-DDR2 (1.5 V), up to 205 MHz DDR
clock frequency with voltage overdrive
• Support for up to eight NAND Flash memory devices with up to 20-bit BCH ECC
• Four synchronous serial ports (SSP) for SDIO/MMC/MS/SPI: SSP0, SSP1, SSP2, and SSP3. SSP0
and SSP1 can support three modes,1-bit, 4-bit, and 8-bit, whereas SSP2 and SSP3 can support only
1-bit and 4-bit modes.
• 10/100-Mbps Ethernet MAC compatible with IEEE Std 802.3™:
— Single 10/100 Ethernet with GMII/RMII or Dual 10/100 Ethernet with RMII interface
— Supporting IEEE Std 1588™-compatible hardware timestamp
— Supporting 50-MHz/25-MHz clock output for external Ethernet PHY
• Two 2.0B protocol-compatible Controller Area Network (CAN) interfaces
• One USB2.0 OTG device/host controller and PHY
• One USB2.0 host controller and PHY
• LCD controller, up to 24-bit RGB (DOTCK) modes and 24-bit system-mode
• Pixel-processing pipeline (PXP) supports full path from color-space conversion, scaling,
alpha-blending to rotation without intermediate memory access.
• SPDIF transmitter
• Dual serial audio interface (SAIF) to support full-duplex transmit and receive operations; each
SAIF supports three stereo pairs
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NXP Semiconductors 3
• Five application Universal Asynchronous Receiver-Transmitters (UARTs), up to 3.25 Mbps with
hardware flow control
• One debug UART operating at up to 115 Kb/s using programmed I/O
• Two I2C master/slave interfaces, up to 400 kbps
• Four 32-bit timers and a rotary decoder
• Eight Pulse Width Modulators (PWMs)
• Real-time clock (RTC)
• GPIO with interrupt capability
• Power Management Unit (PMU) supports a triple output DC-DC switching converter, multiple
linear regulators, battery charger, and detector.
• 16-channel Low-Resolution A/D Converter (LRADC). There are 16 physical channels but they can
only be mapped to 8 virtual channels at a time.
• Single channel High Speed A/D Converter (HSADC), up to 2 Msps data rate
• 4/5-wire touchscreen controller
• Up to 8X8 keypad matrix with button-detect circuit
• Security features:
— Read-only unique ID for Digital Rights Management (DRM) algorithms
— Secure boot using 128-bit AES hardware decryption
— SHA-1 and SHA256 hashing hardware
— High assurance boot (HAB4)
• Offered in 289-pin Ball Grid Array (BGA)
1.2 Ordering Information and Functional Part Differences
Table 1 provides the ordering information for the i.MX28.
Table 1. Ordering Information
Part Number Projected Temperature Range (°C) Package
MCIMX280DVM4B –20 to +70 14 x 14 mm, 0.8mm pitch, MAPBGA-289
MCIMX280DVM4C –20 to +70 14 x 14 mm, 0.8mm pitch, MAPBGA-289
MCIMX280CVM4B –40 to +85 14 x 14 mm, 0.8mm pitch, MAPBGA-289
MCIMX280CVM4C –40 to +85 14 x 14 mm, 0.8mm pitch, MAPBGA-289
MCIMX283DVM4B –20 to +70 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX283DVM4C –20 to +70 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX283CVM4B –40 to +85 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX283CVM4C –40 to +85 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX286DVM4B –20 to +70 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX286DVM4C –20 to +70 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
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NXP Semiconductors4
Table 2 provides the functional differences between the i.MX280, i.MX283, i.MX286, and i.MX287.
MCIMX286CVM4B –40 to +85 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX286CVM4C –40 to +85 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX287CVM4B –40 to +85 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
MCIMX287CVM4C –40 to +85 14 x 14 mm, 0.8 mm pitch, MAPBGA-289
Table 2. i.MX28 Functional Differences
Function i.MX280 i.MX283 i.MX286 i.MX287
Application UART x5 x5 x5 x5
Debug UART x1 x1 x1 x1
CAN — — x2 x2
Ethernet x1 x1 x1 x2
High-speed ADC x1 x1 x1 x1
L2 Switch — — — Yes
LCD Interface — Yes Yes Yes
LRADC1
1There are 16 physical channels but they can only be mapped to 8 virtual channels at a time.
x8 x8 x8 x8
PWM x8 x8 x8 x8
S/PDIF Tx — — Yes Yes
SD/SDIO/MMC2
2For SD/SDIO/MMC, four synchronous serial ports (SSP) are available: SSP0, SSP1, SSP2, and SSP3. SSP0 and SSP1 can
support three modes,1-bit, 4-bit, and 8-bit, whereas SSP2 and SSP3 can support only 1-bit and 4-bit modes.
x4 x4 x4 x4
Securi ty Yes Yes Yes Yes
SPI x4 x4 x4 x4
Touch Screen — Yes Yes Yes
USB 2.0 OTG HS with
HS PHY x1
OTG HS with HS PHY x1 OTG HS with HS PHY x1 OTG HS with HS PHY x1
HS Host with
HS PHY x1
HS Host with HS PHY x1 HS Host with HS PHY x1 HS Host with HS PHY x1
Table 1. Ordering Information (continued)
Part Number Projected Temperature Range (°C) Package
Features
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NXP Semiconductors6
2Features
Table 3 shows the device functions.
Table 3. i.MX28 Functions
Function BGA289
External Memory Interface (EMI)
(1.5 V LV-DDR2, 1.8 V DDR2, 1.8 V LP-DDR1)
Yes
General-Purpose Media Interface (GPMI):
• NAND data width
• Number of external NANDs supported
8-bit
4 dedicated / 8 with muxing
Pulse Width Modulator (PWM) 5 dedicated / 8 with muxing
Application UART (AUART): Interfaces supported 4 dedicated / 5 with muxing
Synchronous Serial Port (SSP): Supported through dedicated pins 3 dedicated / 4 with muxing
I2C 1 dedicated / 2 with muxing
SPDIF 1
SAIF 2
FlexCAN 2
LCD interface 24 bits
High-speed ADC Yes
LRADC (touchscreen, keypad...) Yes
Ethernet MAC and switch Up to 2 MACs with switch
Universal Serial Bus (USB) 2
Features
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NXP Semiconductors 7
Table 4 describes the digital and analog modules of the device.
Table 4. i.MX28 Digital and Analog Modules
Block
Mnemonic Block Name Subsystem Brief Description
APBHDMA AHB to APBH
Bridge with
DMA
System control The AHB to APBH bridge with DMA includes the AHB-to-APB PIO bridge for
memory-mapped I/O to the APB devices, as well a central DMA facility for
devices on this bus. The bridge provides a peripheral attachment bus
running on the AHB’s HCLK. (The ‘H’ in APBH denotes that the APBH is
synchronous to HCLK, as compared to APBX, which runs on the
crystal-derived XCLK.) The DMA controller transfers read and write data to
and from each peripheral on APBH bridge.
APBXDMA AHB to APBX
Bridge with
DMA
System control The AHB-to-APBX bridge includes the AHB-to-APB PIO bridge for
memory-mapped I/O to the APB devices, as well a central DMA facility for
devices on this bus. The AHB-to-APBX bridge provides a peripheral
attachment bus running on the AHB’s XCLK. (The ‘X’ in APBX denotes that
the APBX runs on a crystal-derived clock, as compared to APBH, which is
synchronous to HCLK.) The DMA controller transfers read and write data to
and from each peripheral on APBX bridge.
Arm9 or
ARM926
ARM926EJ-S
CPU
Arm®The ARM926 Platform consists of the ARM926EJ-S™ core and the ETM
real-time debug modules. It contains the 16-Kbyte L1 instruction cache,
32-Kbyte L1 data cache, 128-Kbyte ROM and 128-Kbyte RAM.
AUART(5) Application
UART
interface
Connectivity
peripherals
Each of the UART modules supports the following serial data
transmit/receive protocols and configurations:
• 7- or 8-bit data words, one or two stop bits, programmable parity (even,
odd, or none)
• Programmable baud rates up to 3.25 MHz. This is a higher maximum
baud rate than the 1.875 MHz specified by the TIA/EIA-232-F standard
and previous NXP UART modules. 16-byte FIFO on Tx and 16-byte FIFO
on Rx supporting auto-baud detection
BCH Bit-correcting
ECC
accelerator
Connectivity
peripherals
The Bose, Ray-Chaudhuri, Hocquenghem (BCH) Encoder and Decoder
module is capable of correcting from 2 to 20 single bit errors within a block of
data no larger than about 900 bytes (512 bytes is typical) in applications such
as protecting data and resources stored on modern NAND Flash devices.
BSI Boundary
Scan Interface
Connectivity
peripherals
The boundary scan interface is provided to enable board level testing.
There are five pins on the device which is used to implement the IEEE Std
1149.1™ boundary scan protocol.
CLKCTRL Clock control
module
Clocks The clock control module, or CLKCTRL, generates the clock domains for all
components in the i.MX28 system. The crystal clock or PLL clock are the two
fundamental sources used to produce most of the clock domains. For lower
performance and reduced power consumption, the crystal clock is selected.
The PLL is selected for higher performance requirements but requires
increased power consumption. In most cases, when the PLL is used as the
source, a Phase Fractional Divider (PFD) can be programmed to reduce the
PLL clock frequency by up to a factor of 2.
DCP Data
co-processor
Security This module provides support for general encryption and hashing functions
typically used for security functions. Because its basic job is moving data
from memory to memory, it also incorporates a memory-copy (memcopy)
function for both debugging and as a more efficient method of copying data
between memory blocks than the DMA-based approach.
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NXP Semiconductors8
DFLPT Default
first-level
page table
System control The DFLPT provides a unique method of implementing the Arm MMU
first-level page table (L1PT) using a hardware-based approach.
DIGCTL Digital control
and on-chip
RAM
System control The digital control module includes sections for controlling the SRAM, the
performance monitors, high-entropy pseudo-random number seed,
free-running microseconds counter, and other chip control functions.
DUART Debug UART Connectivity
peripherals
The Debug UART performs the following data conversions:
• Serial-to-parallel conversion on data received from a peripheral device
• Parallel-to-serial conversion on data transmitted to the peripheral device
EMI External
memory
interface
Connectivity
peripherals
The i.MX28 supports off-chip DRAM storage through the EMI controller,
which is connected to the four internal AHB/AXI busses. The EMI supports
multiple external memory types, including:
• 1.8-V Mobile DDR1 (LP-DDR1)
• Standard 1.8-V DDR2
• Low Voltage 1.5-V DDR2 (LV-DDR2)
ENET Ethernet MAC
Controller
Connectivity
peripherals
Ethernet MAC controller connected to the uDMA (unified DMA). Supports
10/100 Mbps with TCP/UDP/IP Acceleration and IEEE 1588 Functions; also
supports RMII or MII connectivity.
FlexCAN(2) Controller
area network
module
Connectivity
peripherals
The Controller Area Network (CAN) protocol is a message based protocol
used for serial data. It was designed specifically for automotive but is also
used in industrial control and medical applications. The serial data bus runs
at 1 Mbps.
GPMI General-pur-
pose media
interface
Connectivity
peripherals
The General-Purpose Media Interface (GPMI) controller is a flexible NAND
Flash controller with 8-bit data width, up to 50-MBps I/O speed and individual
chip-select and DMA channels for up to 8 NAND devices. It also provides a
interface to 20-bit BCH for ECC.
HSADC High-speed
ADC
Connectivity
peripherals
The high-speed ADC block is designed to sample an analog input with 12-bit
resolution and a sample rate of up to 2 Msps. The output of the HSADC block
can be moved to the external memory through APBH-DMA. A typical user
case of the HSADC is to work with the PWM block to drive an external linear
image scanner sensor.
I2C(2) I2C module Connectivity
peripherals
The I2C is a standard two-wire serial interface used to connect the chip with
peripherals or host controllers. The I2C operates up to 400 kbps in either I2C
master or I2C slave mode. Each I2C has a dedicated DMA channel and can
also controlled by CPU in PIO or PIO queue modes. It supports both 7-bit and
10-bit device address in master mode, and has programmable 7-bit address
in slave mode.
ICOLL Interrupt
Collector
System control The Arm9 CPU core has two interrupt input lines, IRQ and FIQ. The interrupt
collector (ICOLL) can steer any of 128 interrupt sources to either the FIQ or
IRQ line of the Arm9 CPU.
L2 Switch 3-Port L2
Switch
Network Control Programmable 3-Port Ethernet Switch with QOS
Table 4. i.MX28 Digital and Analog Modules (continued)
Block
Mnemonic Block Name Subsystem Brief Description
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NXP Semiconductors 9
LCDIF LCD Interface Multimedia
peripherals
The LCDIF provides display data for external LCD panels from simple
text-only displays to WVGA, 16/18/24 bpp color TFT panels. The LCDIF
supports all of these different interfaces by providing fully programmable
functionality and sharing register space, FIFOs, and ALU resources at the
same time. The LCDIF supports RGB (DOTCLK) modes as well as system
mode including both VSYNC and WSYNC modes.
LRADC Low resolution
ADC module
Connectivity
peripherals
The sixteen-channel 12-bit low-resolution ADC (LRADC) block is used for
voltage measurement. Channels 0 – 6 measure the voltage on the seven
application-dependent LRADC pins. The auxiliary channels can be used for
a variety of uses, including a resistor-divider-based wired remote control,
external temperature sensing, touch-screen, and other measurement
functions.
OCOTP
Controller
On-chip OTP
controller
Security The on-chip one-time-programmable (OCOTP) ROM serves the functions of
hardware and software capability bits, NXP operations and unique-ID, the
customer-programmable cryptography key, and storage of various ROM
configuration bits.
PINCTRL Pin control
and GPIO
System control
peripherals
Used for general purpose input/output to external ICs. Each GPIO bank
supports 32 bits of I/O.
PMU Power
management
Unit (DC-DC)
Power
management
system
The i.MX28 integrates a comprehensive power supply subsystem, including
the following features:
• One integrated DC-DC converter that supports Li-Ion battery.
• Four linear regulators directly power the supply rails from 5-V.
• Linear battery charger for Li-Ion cells.
• Battery voltage and brownout detection monitoring for VDDD, VDDA,
VDDIO, VDD4P2 and 5-V supplies.
• Integrated current limiter from 5-V power source.
• Reset controller.
• System monitors for temperature and speed.
• Generates USB-Host 5-V from Li-Ion battery (using PWM).
• Support for on-the-fly transitioning between 5-V and battery power.
• VDD4P2, a nominal 4.2-V supply, is available when the i.MX28 is
connected to a 5-V source and allows the DCDC to run from a 5-V source
with a depleted battery.
• The 4.2-V regulated output also allows for programmable current limits:
– Battery Charge current + DCDC input current < the 5-V current limit
– DCDC input current (which ultimately provides current to the on-chip
and off-chip loads) as the priority and battery charge current is
automatically reduced if the 5-V current limit is reached
PWM(8) Pulse width
modulation
Connectivity
peripherals
There are eight PWM output controllers that can be used in place of GPIO
pins. Applications include HSADC driving signals and LED & backlight
brightness control. Independent output control of each phase allows 0, 1, or
high-impedance to be independently selected for the active and inactive
phases. Individual outputs can be run in lock step with guaranteed
non-overlapping portions for differential drive applications.
PXP Pixel Pipeline Multimedia The pixel pipeline (PXP) is used to perform alpha blending of graphic or video
buffers with graphics data before sending to an LCD display. The PXP also
supports image rotation for hand-held devices that require both portrait and
landscape image support.
Table 4. i.MX28 Digital and Analog Modules (continued)
Block
Mnemonic Block Name Subsystem Brief Description
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NXP Semiconductors10
RTC Real-time
clock, alarm,
watchdog
Clocks The real-time clock (RTC) and alarm share a one-second pulse time domain.
The watchdog reset and millisecond counter run on a one-millisecond time
domain. The RTC, alarm, and persistent bits reside in a special power
domain (crystal domain) that remains powered up even when the rest of the
chip is in its powered-down state.
SAIF(2) Serial audio
interface
Connectivity
peripherals
SAIF provides a half-duplex serial port for communication with a variety of
serial devices, including industry-standard codecs and DSPs. It supports a
continuous range of sample rates from 8 kHz–192 kHz using a
high-resolution fractional divider driven by the PLL. Samples are transferred
to/from the FIFO through the APBX DMA interface, a FIFO service interrupt,
or software polling.
SPDIF SPDIF Connectivity
peripherals
The Sony-Philips Digital Interface Format (SPDIF) transmitter module
transmits data according to the SPDIF digital audio interface standard
(IEC-60958).
SSP(4) Synchronous
serial port
Connectivity
peripherals
The synchronous serial port is a flexible interface for inter-IC and removable
media control and communication. The SSP supports master operation of
SPI, Texas Instruments SSI; 1-bit, 4-bit, and 8-bit SD/SDIO/MMC and 1-bit
and 4-bit MS modes.
The SPI mode has enhancements to support 1-bit legacy MMC cards. SPI
master dual (2-bit) and quad (4-bit) mode reads are also supported. The SSP
also supports slave operation for the SPI and SSI modes. The SSP has a
dedicated DMA channel in the bridge and can also be controlled directly by
the CPU through PIO registers. Each of the four SSP modules is
independent of the other and can have separate SSPCLK frequencies.
TIMROT Timers and
Rotary
Decoder
Timer
peripherals
This module implements four timers and a rotary decoder. The timers and
decoder can take their inputs from any of the pins defined for PWM, rotary
encoders, or certain divisions from the 32-kHz clock input. Thus, the PWM
pins can be inputs or outputs, depending on the application.
USBOTG
USBHOST
High-speed
USB
on-the-go
Connectivity
peripherals
The USB module provides high-performance USB On-The-Go (OTG) and
host functionality (up to 480 Mbps), compliant with the USB 2.0 specification
and the OTG supplement. The module has DMA capabilities for handling
data transfer between internal buffers and system memory.
When the OTG controller works in device mode, it can only work in FS or HS
mode. Two USB2.0 PHYs are also integrated (one for the OTG port, another
for the host port.)
USBPHY Integrated
USB PHY
Connectivity
peripherals
The integrated USB 2.0 PHY macrocells are capable of connecting to USB
host/device systems at the USB low-speed (LS) rate of 1.5 Mbps, full-speed
(FS) rate of 12 Mbps or at the USB 2.0 high-speed (HS) rate of 480 Mbps.
The integrated PHYs provide a standard UTM interface. The USB_DP and
USB_DN pins connect directly to a USB connector.
Table 4. i.MX28 Digital and Analog Modules (continued)
Block
Mnemonic Block Name Subsystem Brief Description
Electrical Characteristics
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NXP Semiconductors 11
2.1 Special Signal Considerations
Special signal considerations are listed in Table 5. The package contact assignment is found in Section 4,
“Package Information and Contact Assignments.” Signal descriptions are provided in the reference
manual.
3 Electrical Characteristics
This section provides the device-level and module-level electrical characteristics for the i.MX28.
3.1 i.MX28 Device-Level Conditions
This section provides the device-level electrical characteristics for the IC.
3.1.1 DC Absolute Maximum Ratings
Table 6 provides the DC absolute maximum operating conditions.
CAUTION
• Stresses beyond those listed under Table 6 may cause permanent
damage to the device.
Table 5. Signal Considerations
Signal Descriptions
PSWITCH The pin is used for chip power on or recovery. VDDIO can be applied to PSWITCH through a 10 kΩ
resistor. This is necessary in order to enter the chip’s firmware recovery. The on-chip circuitry
prevents the actual voltage on the pin from exceeding acceptable levels.
VDDXTAL This pin is an output of i.MX28. Should be coupled to ground with a 0.1 uF capacitor. User should
not supply external power to this pin.
BATTERY This pin should be connected to the battery with minimal resistance. It provides charging current to
the battery.
See the “Power Supply” section of the reference manual for details.
DCDC_BATTERY This pin is an input of i.MX28 that provides supply to the DCDC converter. It should be connected
to the battery with minimal resistance. See the “Power Supply” section of the reference manual for
details.
XTALI
XTALO
These analog pins are connected to an external 24 MHz crystal circuit. This crystal provides the
clock source for on-chip PLLs.
RTC_XTALO
RTC_XTALI
These analog pins are connected to an external 32.768/32.0 kHz crystal circuit. This crystal
provides clock source to the on-chip real-time counter circuits.
RESETN This pin resets the chip if it is low. This pin is pulled up to VDDIO33 with an internal 10 kΩ resistor.
No external pull up resistors are needed.
DEBUG This pin is used for JTAG interface.
DEBUG=0: JTAG interface works for boundary scan.
DEBUG=1: JTAG interface works for Arm debugging.
TESTMODE For NXP factory use only. Must be externally connected to GND for normal operation.
Electrical Characteristics
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NXP Semiconductors12
• Exposure to absolute-maximum-rated conditions for extended periods
may affect device reliability.
•Table 6 gives stress ratings only—functional operation of the device is
not implied beyond the conditions indicated in Table 8.
Table 7 shows the electrostatic discharge immunity.
3.1.2 DC Operating Conditions
Table 8 provides the DC recommended operating conditions.
Table 6. DC Absolute Maximum Ratings
Parameter Symbol Min Max Unit
Battery Pin BATT, VDD4P2V –0.3 4.242 V
5-Volt Source Pin - transient, t<30ms, duty cycle <0.05% VDD5V –0.3 7.00 V
5 Volt Source Pin - static VDD5V –0.3 6.00 V
Analog Supply Voltage VDDA –0.3 2.10 V
Digital Core Supply Voltage VDDD –0.3 1.575 V
Non-EMI Digital I/O Supply VDDIO –0.3 3.63 V
EMI Digital I/O Supply VDDIO.EMI –0.3 3.63 V
DC-DC Converter1
1Application should include a Schottky diode between BATT and VDD4P2.
DCDC_BATT –0.3 BATT V
Input Voltage on Any Digital I/O Pin Relative to Ground — –0.3 VDDIO+0.3 V
Input Voltage on USB_DP and USB_DN Pins Relative to Ground2
2USB_DN and USB_DP can tolerate 5V for up to 24 hours. Note that while 5V is applied to USB_DN or USB_DP, LRADC
readings can be corrupted.
— –0.3 3.63 V
Analog I/O absolute maximum ratings (exceptions: XTALI, XTALO,
RTC_XTALI, RTC_XTALO)
— –0.3 VDDIO+0.3 V
Storage Temperature — –40 125 °C
Table 7. Electrostatic Discharge Immunity
289-Pin BGA Package Tested Level
Human Body Model (HBM)1
1HBM and CDM pass ESD testing per AEC-Q100.
2kV
Charge Device Model (CDM)1500 V
Table 8. Recommended Power Supply Operating Conditions
Parameter Symbol Min Typ Max Unit
Analog Core Supply Voltage VDDA 1.62 — 2.10 V
Digital Core Supply Voltage
Specification dependent on frequency.1, 2
VDDD 1.35 — 1.55 V
Electrical Characteristics
i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018
NXP Semiconductors 13
Table 9 provides the DC operating temperature conditions.
Digital Supply Voltages:
• VDDIO33/VDDIO33_EMI
• VDDIO18
VDDIO33/VDDIO33_EMI/VDDIO18
3.0
1.7
—
—
3.6
1.9
V
EMI Digital I/O Supply Voltage:
• DDR2/mDDR
• LVDDR2
VDDIO.EMI/VDDIO_EMIQ
1.7
1.425
1.8
1.5
1.9
1.625
V
Battery / DCDC Input Voltage—BATT, DCDC_BATT BATT
DCDC_BATT
3.103— 4.242 V
VDD5V Supply Voltage — 4.75 5.00 5.25 V
Offstate Current:4
• 32-kHz RTC off, BATT = 4.2 V — — 21 47 µA
• 32-kHz RTC on, BATT = 4.2 V — — 23 51 µA
1For optimum USB jitter performance, VDDD = 1.35 V or greater.
2VDDD supply minimum voltage includes 75 mV guardband.
3Tested with only the i.MX28 processor loading the MX28 PMU output rails during start up. With external loadings (for
example, one DDR2 device and SD Card/NAND Flash), MX28 PMU was tested at BATT/DCDC_BATT > 3.30 V.
4When the real-time clock is enabled, the chip consumes additional current in the OFF state to keep the crystal oscillator and
the real-time clock running.
Table 9. Operating Temperature Conditions
Parameter1, 2, 3
1In most portable systems designs, battery and display specifications limits the operating range to well within these
specifications. Most battery manufacturers recommend enabling battery charge only when the ambient temperature is
between 0°C and 40°C. To ensure that battery charging does not occur outside the recommended temperature range, the
system ambient temperature may be monitored by connecting a thermistor to the LRADC0 or LRADC6 pin on the i.MX28.
2For applications powered by external 5V only, the Maximum Ambient Operating Temperature specified in Ta b l e 9 may not be
achieved. Application developers need to do the worst-case power consumption estimation, and then calculate the Total
On-chip Power Dissipation based on the equations specified in note 3 below.
Symbol Min Typ Max Unit
Commercial Ambient Operating Temperature Range TA–20 — 70 °C
Commercial Junction Temperature Range TJ–20 — 85 °C
Industrial Ambient Operating Temperature Range TA–40 — 85 °C
Industrial Junction Temperature Range TJ–40 — 105 °C
Table 8. Recommended Power Supply Operating Conditions (continued)
Parameter Symbol Min Typ Max Unit
Electrical Characteristics
i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018
NXP Semiconductors14
Table 10 provides the recommended analog operating conditions.
Table 11 shows the PSWITCH input characteristics. See the reference schematics for the recommended
PSWITCH button circuitry.
Table 12 shows a test case example for Run IDD.
3Maximum Ambient Operating Temperature may be limited due to on-chip power dissipation. TA (MAX) ≤ TJ - (ΘJA x PD) where:
TJ = Maximum Junction Temperature
ΘJA = Package Thermal Resistance. See Section 3.2, “Thermal Characteristics.”
PD = Total On-chip Power Dissipation =PVDD4P2 + PBatteryCharger + PDCDC + PLinearRegulators + PInternal. Depending
on the application, some of these power dissipation terms may not apply.
PVDD4P2 = VDD4P2 On-Chip Power Dissipation = (VDD5V - VDD4P2) x IDD4P2
PBatteryCharger = Battery Charger On-Chip Power Dissipation = (VDD5V - BATT) x ICHARGE
PDCDC = DC-DC Converter On-Chip Power Dissipation = (BATT x DCDC Input Current) x (1 - efficiency)
PLinearRegulators = Linear Regulator On-Chip Power Dissipation = (VDD5V - VDDIO) x (IDDIO + IDDA + IDDD + IDD1P5) +
(VDDIO - VDDA) x (IDDA + IDDD) + (VDDA - VDDD) x IDDD + (VDDA - VDD1P5) x IDD1P5
PInternal = Internal Digital On-Chip Power Dissipation = ~VDDD x IDDD
Table 10. Recommended Analog Operating Conditions
Parameter Min Typ Max Unit
Low Resolution ADC Input Impedance (CH0 - CH5) >1 — — MΩ
Table 11. PSWITCH Input Characteristics
Parameter HW_PWR_STS_PSWITCH Min Max Unit
PSWITCH LOW LEVEL 0x00 0.00 0.30 V
PSWITCH MID LEVEL & STARTUP1
1A MID LEVEL PSWITCH state can be generated by connecting the VDDXTAL output of the SoC to PSWITCH through a
switch.
0x01 0.65 1.50 V
PSWITCH HIGH LEVEL2
2PSWITCH acts like a high impedance input (>300 kΩ) when the voltage applied to it is less than 1.5V. However, above 1.5V
it becomes lower impedance. To simplify design, it is recommended that a 10 kΩ resistor to VDDIO be applied to PSWITCH
to set the HIGH LEVEL state (the PSWITCH input can tolerate voltages greater than 2.45 V as long as there is a 10 kΩ
resistor in series to limit the current).
0x11 (1.1 * VDDXTAL) + 0.58 2.45 V
Table 12. Run IDD Test Case1,2
1CPUCLK = 300 MHz, AHBCLK = 150 MHz.
2Continuous read / write to the cache memory.
Power Rail Conditions Min Typ Max Unit
VDDD 1.57 V — 150 188 mA
VDDIO33 3.62 V — 31 34 mA
VDDA 2.12 V — 1.11 1.17 mA
VDDIO_EMI 1.92 V — 1.01 1.08 mA
VDDIO18 1.92 V — 0.61 2.97 μA
Electrical Characteristics
i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018
NXP Semiconductors 15
Table 13 illustrates the power supply characteristics.
Table 13. Power Supply Characteristics
Parameter Min Typ Max Unit
Linear Regulators
Output Voltage Accuracy (VDDIO, VDDA, VDDM, VDDD)1
1No load.
–3 — +3 %
VDDIO Maximum Output Current (VDDIO = 3.30 V, VDD5V =4.75V)
2, 3
2Maximum output current measured when output voltage droops 100 mV from the programmed target voltage with no load
present.
3Because the internal linear regulators are cascaded, it is not possible to simultaneously operate the VDDIO, VDDA, VDDM, and
VDDD linear regulators at the maximum specified load current. For example, the VDDIO linear regulator provides current to both
the VDDIO 3.3 V supply rail as well as the VDDM and VDDA linear regulator inputs. Likewise, the VDDA linear regulator provides
current to both the 1.8 V supply rail as well as the VDDD linear regulator input. The application designer should ensure the
following two conditions are met:
(VDDIO Load Current + VDDM Load Current + VDDA Load Current) < VDDIO Maximum Output Current
(VDDA Load Current + VDDD Load Current) < VDDA Maximum Output Current
270 — — mA
VDDM Maximum Output Current (VDDM = 1.5 V)2160 — — mA
VDDA Maximum Output Current (VDDA =1.8V)
2, 3 225 — — mA
VDDD Maximum Output Current (VDDD =1.2V)
2, 3 200 — — mA
DCDC Converters
Output Voltage Accuracy (DCDC_VDDIO, DCDC_VDDA,
DCDC_VDDD)1
–3 — +3 %
DCDC_VDDD Maximum Output Current (VDDD = 1.55 V)4, 5
4DCDC Double FETs Enabled, Inductor Value = 15 μH.
5The DCDC Converter is a triple output buck converter. The maximum output current capability of each output of the converter
is dependent on the loads on the other two outputs. For a given output, it may be possible to achieve a maximum output current
higher than that specified by ensuring the load on the other outputs is well below the maximum.
250 — — mA
DCDC_VDDA Maximum Output Current (VDDA =1.8V)
4, 5200 — — mA
DCDC_VDDIO Maximum Output Current (VDDIO = 3.15 V, 3.3 V < BATT
< 4.242 V)4, 5, 6
6Assumes simultaneous load of IDDD = 250 mA@ 1.55 V and IDDA = 200 mA@1.8 V.
250 — — mA
VDD4P2 Regulated Output
VDD4P2 Output Voltage Accuracy (TARGET=4.2V)1–3 — +3 %
VDD4P2 Output Current Limit Accuracy (VDD5V = 4.75 V,
ILIMIT=480 mA)7
7Untuned.
480 500 520 mA
VDD4P2 Output Current Limit Accuracy (VDD5V=4.75 V,
ILIMIT=100 mA)7
100 120 140 mA
Battery Charger
Final Charge Voltage Accuracy (TARGET=4.2 V) -2 — +1 %
Electrical Characteristics
i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018
NXP Semiconductors16
3.1.2.1 Recommended Operating Conditions for Specific Clock Targets
Table 14 through Table 17 provide the recommended operating conditions for specific clock targets.
Table 14. Recommended Operating States—289-Pin BGA Package
VDDD
(V)
VDDD
Brown-out
(V)
HW_
DIGCTRL
ARMCACHE1
1All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
CPUCLK
/ clk_p
Frequency
(MHz)
HW_
CLKCTRL
CPU_DIV_CPU
HW_
CLKCTRL
FRAC_
CPUFRC
/ PFD
AHBCLK
/ clk_h
Frequency
(MHz)
HW_
CLKCTRL
HBUS_DIV
EMICLK
/ clk_emi
Frequency
(MHz)
HW_
CLKCTRL
EMI_
DIV_EMI
HW_
CLKCTRL
FRAC_
EMIFRAC
Supported
DRAM
1.300 1.200 00 64 5 27 64 1 130.91 2 33 DDR2
mDDR
1.350 1.250 00 261.81 1 33 130.91 2 130.91 2 33 DDR2
mDDR
1.350 1.250 00 360 1 24 120.00 3 130.91 2 33 DDR2
mDDR
1.450 1.350 00 392.72 1 22 130.91 3 160.00 2 27 DDR2
mDDR
1.550 1.450 00 454.73 1 19 151.57 3 205.71 2 21 DDR2
mDDR
Table 15. Recommended Operating Conditions—CPU Clock (clk_p)
VDDD (V) VDDDBrown-out (V) HW_DIGCTRL
ARMCACHE1
1All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
HW_CLKCTRL
FRAC_CPUFRC / PFD
CPUCLK / clk_p
Frequency max (MHz)
1.350 1.250 00 18 - 35 360
1.450 1.350 00 18 - 35 392.72
1.550 1.450 00 18 - 35 454.73
Table 16. Recommended Operating Conditions—AHB Clock (clk_h)
VDDD (V) VDDDBrown-out (V) HW_DIGCTRL
ARMCACHE1
1All timing control bit fields in HW_DIGCTRL_ARMCACHE should be set to the same value.
HW_CLKCTRL
FRAC_CPUFRC / PFD
AHBCLK / clk_h
Frequency max (MHz)
1.350 1.250 00 18 - 35 160
1.450 1.350 00 18 - 35 196
1.550 1.45 00 18 - 35 206
Electrical Characteristics
i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018
NXP Semiconductors 17
3.1.3 Fusebox Supply Current Parameters
Table 18 lists the fusebox supply current parameters.
3.1.4 Interface Frequency Limits
Table 19 provides information for interface frequency limits.
3.1.5 Power Modes
Table 20 describes the core, clock, and module settings for the different power modes of the processor.
Table 17. Frequency vs. Voltage for EMICLK—289-Pin BGA Package
VDDD (V) VDDDBrownout (V)
EMICLK Fmax (MHz)
DDR2 mDDR
1.550 1.450 205.71 205.71
1.450 1.350 196.36 196.36
1.350 1.250 196.36 196.36
Table 18. Fusebox Supply Current Parameters
Parameter Symbol Min Typ Max Unit
eFuse Program Current1
Current to program one eFuse bit
efuse_vddq=2.5V
1The current Iprogram is during program time.
Iprogram 21.39 25.05 33.54 mA
eFuse Read Current2
Current to read an 8-bit eFuse word
vdd_fusebox = 3.3 V
2The current Iread is present for approximately 10 ns of the read access to the 8-bit word.
Iread — — 4.07 mA
Table 19. Interface Frequency Limits
Parameter Min Typ Max Unit
JTAG: TCK Frequency of Operation — — 10 MHz
OSC24M_XTAL Oscillator — 24.000 — MHz
OSC32K_XTAL Oscillator — 32.768/32.0 — kHz
Table 20. Power Mode Settings
Core/Clock/Module Offstate Standby Run
Arm Core Off Off On
USB0 PLL (System PLL) Off Off On
OSC24M Off On On
Electrical Characteristics
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NXP Semiconductors18
3.1.6 Supply Power-Up/Power-Down Requirements
There is no special power-up sequence. After applying 5 V or battery in any order, the rest of the power
supplies are internally generated and automatically come up in a safe way.
There is no special power-down sequence. 5 V or the battery can be removed at any time.
3.1.7 Reset Timing
Because the i.MX28 is a PMU and an SoC, power-on reset is generated internally and there is no timing
requirement on external pins.
The i.MX28 can be reset by asserting the external pin RESETN for at least 100 mS and later deasserting
RESETN.
If the reset occurs while the device is only powered by the battery, then the reset kills all of the power
supplies and the system reboots on the assertion of PSWITCH. If auto-restart is set up ahead of time, the
system reboots immediately.
If the chip is powered by 5 V, then the reset serves to reset the digital sections of the chip. If the DCDC is
operating at the time of the reset, then power switches back to the default linear regulators powered by 5 V.
Figure 2. RESETN Timing
3.2 Thermal Characteristics
The thermal resistance characteristics for the device are given in Table 21. These values are measured
under the following conditions:
• Two layer Substrate
• Substrate solder mask thickness: 0.025 mm
• Substrate metal thicknesses: 0.016 mm
• Substrate core thickness: 0.160 mm
• Core via I.D: 0.068 mm, Core via plating 0.016 mm
• Flag: trace style with ground balls under the die connected to the flag
OSC32K On On On
DCDC Off On On
RTC On On On
Other Modules Off On/Off On/Off
Table 20. Power Mode Settings (continued)
Core/Clock/Module Offstate Standby Run
RESETN
At least 100ms
Electrical Characteristics
i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018
NXP Semiconductors 19
• Die Attach: 0.033 mm non-conductive die attach, k = 0.3 W/m K
• Mold Compound: generic mold compound, k = 0.9 W/m K
3.3 I/O DC Parameters
This section includes the DC parameters of the following I/O types:
• DDR I/O: Mobile DDR (LPDDR1), standard 1.8 V DDR2, and low-voltage 1.5 V DDR2
(LVDDR2)
• General purpose I/O (GPIO)
3.3.1 DDR I/O DC Parameters
Table 22 shows the EMI digital pin DC characteristics.
NOTE
The current values and the I-V curves of the I/O DC characteristics are
estimated based on an overly conservative device model. They are updated
upon the measurement results of the first silicon.
Table 21. Thermal Resistance Data
Rating Condition Symbol Value Unit
Junction to ambient1 natural convection
1Junction-to-Ambient Thermal Resistance determined per JEDEC JESD51-2 and JESD51-6. Thermal test board meets
JEDEC specification for this package.
Single layer board (1s) RθJA 62 °C/W
Junction to ambient1 natural convection Four layer board (2s2p) RθJA 36 °C/W
Junction to ambient1 (@200 ft/min) Single layer board (1s) RθJMA 53 °C/W
Junction to ambient1 (@200 ft/min) Four layer board (2s2p) RθJMA 33 °C/W
Junction to boards2
2Junction-to-Board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC specification
for the specified package.
—R
θJB 24 °C/W
Junction to case (top)3
3Junction-to-Case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is
used for the case temperature. Reported value includes the thermal resistance of the interface layer.
—R
θJCtop 15 °C/W
Junction to package top4
4Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
Natural Convection ΨJT 3°C/W
Table 22. EMI Digital Pin DC Characteristics
Parameter Symbol Min Max Unit
Input voltage high (dc) VIH VREF + 0.125 VDDIO_EMI + 0.3 V
Input voltage low (dc) VIL 0.3 VREF – 0.125 V
Output voltage high (dc) VOH 0.8 * VDDIO_EMI — V
Electrical Characteristics
i.MX28 Applications Processors for Consumer Products, Rev. 4, 10/2018
NXP Semiconductors20
Table 23 shows the ON impedance of EMI drivers for different drive strengths.
Table 24 shows the external devices supported by the EMI.
Output voltage low (dc) VOL — 0.2 * VDDIO_EMI V
Output source current (dc)
LVDDR2 Mode
IOH1—Low -6.2 — mA
IOH—Medium -7.2 — mA
IOH—High -9.7 — mA
Output sink current (dc)
LVDDR2 Mode
IOL2—Low 5.7 — mA
IOL—Medium 7.3 — mA
IOL—High 10.0 — mA
Output source current (dc)
mDDR, DDR2 Mode
IOH—Low -5.7 — mA
IOH—High -7.5 — mA
Output sink current (dc)
mDDR, DDR2 Mode
IOL—Low 5.4 — mA
IOL—High 8.8 — mA
1IOH is the output current at which the VOH specification is met.
2IOL is the output current at which the VOL specification is met.
Table 23. ON Impedance of EMI Drivers for Different Drive Strengths1
1ON impedance of the EMI drivers are guaranteed by design and are not tested during production.
Mode Drive Min (Ω)Typ (Ω) Max (Ω)
1.5
LVDDR2
Low 26 38 58
Medium 17 25 36
High 15 20 27
1.8
DDR2/mDDR
Low 36 53 78
Medium 17 27 42
High 16 19 28
Table 24. External Devices Supported by the EMI
DRAM Device Max Load1, 2
1Max load includes capacitive load due to PCB traces, pad capacitance and driver self-loading.
Pad Voltage
DDR2 15 pF 1.8 V
mDDR 15 pF 1.8 V
LVDDR2 15 pF 1.5 V
Table 22. EMI Digital Pin DC Characteristics (continued)
Parameter Symbol Min Max Unit