AMI6G333-PQFP80 - AMI Semiconductor, Inc.

Table of Contents

Features……………………………………………………………………………1

AMI6Gx Gate Array Family………………………………………………………2

AMI6S Standard Cell Family……………………………………………………3

Digital Megacell Family…………………………………………………………3

Architectural Overview……………………………………………………4 - 5

Product Applications……………………………………………………………6

ASIC Design Tools and Methodology……………………………………6 - 7

The Design Library…………………………………………………………8 - 9

DC Specifications…………………………………………………………10 - 11

Library Cell Selection Guide……………………………………………12 - 20

Packaging………………………………………………………………………21

“The new 0.6µm gate array and standard cell families from AMI

provide outstanding quality and selection . . . setting performance

standards in 0.6µm ASIC products . . .”

■ 130 ps gate delays (fanout = 2, interconnect length = 0mm)

■ Double and Triple Metal Interconnect; up to 900,000 gate

designs using megacells, ROM, RAM, and logic

■ An innovative pad cell design method that allows the user

to design pad cell conﬁgurations using predeﬁned pieces

■ Complete package lineup

QFP, PLCC, BGA, PGA . . .

■ Expanded selection of megacells

Families of single and multi-port RAMs, ROMs,

microprocessors, controllers, datapath functions . . .

■ “Made in America” engineering, manufacturing, and support

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

• Extensive library for quick design:

– Complete primary cell and I/O library.

– Asynchronous and synchronous, single and dual-port

RAM compilers with over 2000 compiled RAM sizes

from 32x1 to 2Kx32 bits.

– Synchronous ROM compiler from 64x1 to 16Kx32

bits.

– Megacells include processors, peripherals, and

datapath synthesizers.

– 100% compatible with AMI’s proven ASIC Standard

Library.

• 1 to 24 mA drive per single I/O cell:

Slew rate limiting available for 4, 8, 12, 16, and 24 mA

drive. Custom conﬁgurations for I/O drive up to 96 mA

can be supported.

• Wide range of packaging:

Full QFP and PLCC line, BGAs and PGAs, individual

die. Burn-in capability as required.

• Automatic Test Program Generation:

Includes scan macros (NETSCAN) for high fault

coverage.

• JTAG Boundary Scan macro support

• Full operating voltage range from 2.7V to 5.5V

• ESD protection > 2kV; latchup > 100 mA

• Power dissipation:

2.7µW/MHz/gate (FO=1; VDD=5V) for gate array and

2.5µW/MHz/gate for standard cell.

Description

AMI’s “AMI6Gx” series of 0.6µm gate arrays exploits a

proprietary power grid and track routing architecture on a

compact, channelless, sea-of-gates design to provide

one of the highest performance, cost effective array

products available today.

The “AMI6S” standard cell family continues the AMI

leadership tradition of combining true compact building

block standard cells and megacells with high speed

memory and datapath functions. Using a 0.6µm high

performance CMOS process, the AMI6S product can

offer a lower cost alternative to gate array for high volume

applications.

Features

• Excellent performance:

– 395 MHz maximum toggle rate on clocked ﬂip-ﬂops

(TJ = 135°C).

– 215 ps delay (FO=2; L=2mm) for a 2-input NAND

gate.

– 130 ps delay (FO=2; L=0mm) for a 2-input NAND

gate.

• Operating Temperatures range from -55 to 125oC:

Few competing products allow this range.

• Clock grid generation:

≤ 300ps clock skew (fan out = 3500 at 80 MHz).

• User-designed pad cells:

AMI allows the user to design pad cells by piecing

together predeﬁned components.

• Cost driven architecture:

– Offers both 2 and 3 level metal interconnect to

provide the lowest user cost for the number of gates

and pads required.

– Compiled memory blocks on standard cells are

compacted precisely to parameters. No leaf cell

overhead.

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

AMI6Gx Gate Array Family Overview

Note 1: Exact usable gate count will vary depending on design interconnect and macro selection.

Note 2: The AMI6GS series has AMI’s proprietary enhanced I/O for tighter pad pitches.

PART NUMBER2RAW GATES USABLE GATES1BOND PADS I/O CELLS

2LM 3LM

AMI6G4 4.01 2.01 2.67 44 52

AMI6G16S 15.71 7.85 10.46 100 100

AMI6G33S 32.87 16.44 21.89 144 144

AMI6G41S 40.49 20.25 26.97 160 160

AMI6G70S 69.28 34.64 46.14 208 208

AMI6G106S 105.74 52.87 70.42 256 256

AMI6G150S 149.88 74.94 99.82 304 304

AMI6G202S 201.71 100.86 134.34 352 352

AMI6G333 333.51 166.76 222.12 384 452

AMI6G471 470.53 235.27 313.37 456 536

AMI6G603 602.77 301.39 401.44 520 608

AMI6G713 712.94 356.47 474.82 564 660

AMI6G876 875.63 437.82 583.17 624 732

AMI6G1046 1045.91 522.96 696.58 684 800

AMI6G1210 1210.35 605.18 806.09 736 860

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

AMI6S Standard Cell Family Overview

Digital Megacell Family Overview

Note 1: Compact memory arrays greatly increase gate count on an equivalent gate basis.

Feature Description Comment

Complexity Up to 900,000 gates1

Up to 500,000 gates 50% memory, 50% megacell and user deﬁned logic

100% user deﬁned logic

I/O Count Up to 512 pins

Up to 836 pins Test equipment limit; signal pins only

Die size limit; includes power supply pins

Delay

Time

Internal Gate 102 ps (Fanout=1, L=0mm)

215 ps (Fanout=2, L=2mm) 2 input NAND gate, T=25°C, VDD=5V

Input Buffer 675 ps (Fanout=2, L=2mm) CMOS Input buffer, T=25°C, VDD=5V

Output Buffer 860 ps (CL=15pf) CMOS Output buffer,T=25°C, VDD=5V

Feature Description Comment

Core Processors MG29C01,MG29C10,MG65C02,

M8042, M8048, MG80C85, MGMC51,

MGMC51I, MGMC51FB, MGMC51SD

Functionally compatible with popular standard

designs.

Peripherals

MG1468C18, M16C450, M6402,

M6845, M765A, M8251A, M8253,

M82530, MG82C37A, MG82C50A,

MG82C54, MG82C55A, MG82C59A,

M8490, M85C30, M8868A, M91C36,

M91C360, MFDC, MGI2CSL, MI2C

Functionally compatible with popular standard

designs.

FIFOs Fall-through and RAM-based FIFO’s See page 9 for complete list and details

Datapath Synthesizers multipliers, adders, subtracters, barrel

shifters, comparators,... See page 9 for complete list and details

Memory Compilers

synchronous single-port self-timed

SRAM (over 4000 sizes)

synchronous dual-port SRAM

(over 4000 sizes)

synchronous ROM (over 8000 sizes)

asynchronous single-port SRAM

See page 8 for complete list and details

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

Architectural Overview

Some important elements of the AMI6Gx gate array family

are:

• [Note 1] 2 or 3 level metal interconnect selectable.

•[Note 2] Two p-channel and two n-channel transistors

per site (or cell). Sites are arrayed in a sea-of-gates

structure that can allow interconnect routing over active

sites. Also, p-channel transistors are sized larger than

the stronger n-channel transistors in each cell to provide

better matched rise times and fall times.

•[Note 3] Four separate power busses for I/O cells to

allow separate supplies for output buffers, input buffers,

and mixed VDD levels all on an individual I/O cell basis.

Two separate power busses for core logic (not shown).

•Each I/O cell can be conﬁgured as 5V VDD, 3V VDD, VSS,

or signal I/O.

• [Note 4] Each I/O cell has selectable drive from 1mA to

24mA. All I/O cell logic can be built in the I/O cell

prebuffer. Level shifting (3V to 5V or 5V to 3V) may

require the use of a few core gates.

Core cell sites with 4 transistors [note 2]

2 P-channel

2 N-channel

Separately conﬁgured power busses for I/O and core [note 3]

Large I/O driver with prebuffer [note 4]

Selectable 2 or 3 metal interconnect [note 1]

FIGURE 1: GATE ARRAY ARCHITECTURE

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

Architectural Overview

Some important elements of the AMI6S standard cell

family are:

•2 or 3 level metal interconnect selectable.

•[Note 1] Each cell function is tightly compacted to a

ﬁxed bus height. Cells are then placed in rows allowing

VDD and VSS supplies to feed through the cells. Since

some functions require more gates than others, their

widths and heights may increase to allow for the added

gates. Transistor sizes and routing are optimized for

their function, giving a much tighter cell design than

with gate arrays or ﬁxed pad ring embedded array

products.

• [Note 2] Rows of cells can be placed adjacently if little

routing is required between them, or largely separated

to allow a large data bus to route through. Tracks of

ROM

BLOCK

RAM

BLOCK

MG29C01

Soft Megacell

DF101

Individually compacted cells [note 1]

Fixed bus height, variable height

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

Product Applications

The Gate Array’s extended temperature and voltage

operation range make it well suited for telecom, industrial,

and military applications. The low cost structure also

makes it ideal in computer and ofﬁce automation ASIC

requirements.

The AMI6S standard cells are targeted at higher volume

digital ASIC products. The lower cost also ﬁts designs

requiring signiﬁcant on-board memory, datapath logic, or

megacells.

FPGA OR PAL CONVERSION: Using NETRANS AMI

can convert netlists from most gate array, FPGA, and PAL

devices to a more cost and performance effective AMI6X

design for volume production.

2ND SOURCE EXISTING PRODUCTS: Netlist

conversion capabilities from AMI allow a competitive

alternate supply with AMI6X components for current high

volume designs.

NEW DESIGN CAPTURE: AMI6X design is supported by

many popular 3rd party software platforms, as well as

AMI’s Enhanced Design Utilities (EDU) environment.

PROCESS UPGRADE: Designs done in AMI’s 1.25µm,

1.0µm, and 0.8µm ASIC products can easily be upgraded

to the AMI6X family. The AMI ASIC Standard Library

provides a common netlist design base.

ADDING CUSTOM BLOCKS: AMI specializes in adding

custom logic to ASIC designs. Simple analog functions

are also possible.

ASIC Design Tools and Methodology

AMI6X and other AMI ASIC families are supported on

many front-end design environments:

• Cadence

• Mentor Graphics

• Synopsys

• Viewlogic

• Intergraph

• Compass

• Verilog simulation

• IKOS simulation accelerator

(AMI’s sign-off simulator)

AMI has maintained critical proprietary software tools to

ensure a tight, well coupled design to our silicon process.

This methodology includes our expert-system design

analysis tools, AMI’s Enhanced Design Utilities (EDU), a

software support methodology that covers the complete

set of wafer processing possibilities, and a dedicated,

experienced engineering staff that can assist at any level

of the design process.

AMI Design Flow

AMI will supply an AMI6X design kit which includes a cell

library containing symbols, simulation models and

software for design veriﬁcation, timing calculations, and

netlist generation. For pre-layout timing simulations,

capacitance and resistance values derived from statistical

FIGURE 3: ASIC DESIGN FLOW

Speciﬁcation

Design

Std. Library

AMI ASIC

Synthesis Tool

AMI supported

Schematic

Capture

Logic / Timing

Simulation

Fault

Test VectorsNetlist transfer

to AMI

Simulation

Veriﬁcation

Place and Route

Extraction

Layout Parameter

Back Annotation

to Customer Post Layout

Simulation

Physical Design

Veriﬁcation

Final Review

Customer

Approval

Mask Creation

Fabricate and Test

Prototypes

Test

Development

Prototype Approval

to AMI

Customer

Design

Activity

AMI megacell

or memory block

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

averages of known layouts are used. Once actual layout is

completed by AMI, a post-layout interconnect capacitance

and resistance table will be supplied for ﬁnal validation of

device timing.

Figure 3 shows a typical design ﬂow for a new design.

Working with an AMI design center, the customer is

responsible for capturing and verifying the design using the

AMI ASIC Standard Library. He is also responsible for

creating the test vectors that will eventually serve as the

logical part of the manufacturing test. Software aids such

as logic synthesis, megacells, automatic test program

generation, netlist rule checkers, etc. can greatly speed up

this process. (A fault coverage check of the test vector set

is optional and can be done as an additional service.)

When the design is received by the factory, the “Design

Start Package” is reviewed by AMI engineers. This start

package, which is completed by the customer, contains the

device speciﬁcation, netlist, pinlist ﬁle, critical timing paths,

and test vectors. The design is pre-screened on the

Enhanced Design Utilities (EDU) and then resimulated on

IKOS, AMI’s sign-off simulator. The results are compared

to the customer’s simulation from the third-party CAE

tool.

Once the design has passed the initial screening it is then

ready for placement and routing. The layout proceeds by

ﬁrst placing memory and megacells, assigning priority to

critical paths, and designing the distribution and buffering

of clocks. Next, the layout is completed with automatic

place-and-route on the balance of the circuit.

After layout has been completed the interconnect data is

extracted from the physical layout to be fed back to the

sign-off simulator for ﬁnal circuit veriﬁcation. This post

layout interconnect data can be sent to the customer for

ﬁnal validation on his simulator. When the post-layout

simulation has been completed and approved by the

customer the design is then released for mask and wafer

fabrication.

The test program is developed in parallel using internal

automatic test program generation software. Prototypes

can then be tested before they are shipped.

AMI Environment

Memory

Compiler

Models &

Symbols

Physical Data

Design

Veriﬁcation

Place and Route

Post Route

Veriﬁcation

ATPG

AMI ASIC

Std. Library

Synthesis Tool

Logic Synthesis

Schematic

Translation

HDL

VHDL

Schematic

Entry

Design

Database

Timing

Simulation

Estimated

Delays

Vector

Generation

Enhanced

Design Utilities

Netlist

Translation

AMI ASIC

Stnd. Library

Optional

Third Party

Environment

FIGURE 4: DESIGN ENVIRONMENT WITH THIRD PARTY SOFTWARE

in AMI Design Kit

Elements supplied

AMI Design Flow (cont.)

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

Figure 4 outlines a typical software environment when

using third party tools. AMI uses EDIF to speed ports

between various software products.

AMI’s Enhanced Design Utilities Tools are intended to be

used interactively at each stage of the design. EDU

software is a set of design analysis tools that check both

the design and test vectors for correctness and

compatibility with in-house ASIC testers, and analyze the

design for inefﬁciencies and possible ﬂaws that could

cause problems in manufacturing the device.

The Design Library

AMI provides a robust collection of building blocks for the

AMI6X family. A broad range of primary cells is

complemented with memory cell compilers and useful

megafunctions. With such broad, US-based design talent,

AMI can quickly design speciﬁc cells that customers need

to add an edge in customization.

The AMI ASIC Standard Library

The AMI ASIC Standard Library contains a rich set of core

and conﬁgurable pad cells which allow great ﬂexibility in

building competitive devices for customer applications.

The library is portable across all AMI’s gate array and

standard cell families. The ASIC Standard Library is listed

in detail on pages 12 to 20.

Memory Compilers

The AMI6X family includes the line of memory compilers

shown above. Each of the thousands of possible memory

blocks is optimized precisely to the customers’

parameters rather than built from a presized leaf cell that

covers a range of sizes. This yields a better size and

performance match for each application.

Upon supplying the cell speciﬁcation to AMI, the customer

can receive an accurate simulation timing speciﬁcation

overnight by facsimile and a full simulation model for any

AMI supported software environment within ﬁve working

days.

Digital Soft Megacells

The AMI6X gate array and standard cell families support

soft megacells that are compatible with many popular

functions. These megacells are functionally and logically

compatible with the stand-alone products.

A soft megacell is deﬁned only at the functional schematic

level. Each instance of the megacell will have exactly the

same functional deﬁnition; however, the physical mask

layout will be different depending on other functions being

used, the place-and-route tools, and process technology.

The megacell becomes part of the design netlist, requiring

back annotation of interconnect capacitance after place-

and-route for ﬁnal veriﬁcation.

Because AMI’s soft megacells are deﬁned at the gate

level, simulation models are more accurate than that of

behavioral models. Since our soft megacells use AMI’s

ASIC Standard Library they have the advantages of

design ﬂexibility, portability, and a path for future cost

reduction by process migration.

AMI’s selection of soft megacells include Core Processors

and Peripherals which duplicate the function of industry

standard parts. In addition AMI offers FIFOs and Datapath

megacells which are developed using synthesizers. These

products are listed in the following tables.

Core Processors and Peripherals

The Core Processor and Peripheral megacells are

designed to duplicate the function of industry standard,

stand-alone parts. Detailed functional information can be

found in any standard device datasheet.

Memory Compiler Library

Memory Compiler Process Size Increment

min. max.

SRAM (single-port, synchronous, self-timed) gate array 16 x 1 1K x 32 16 words, 1 bit

SRAM (single-port, synchronous, self-timed) standard cell 32 x 1 2K x 32 16 words, 1 bit

ROM (synchronous) standard cell 64 x 1 16K x 32 64 words, 1 bit

SRAM (single-port, asynchronous) standard cell 32 x 1 2K x 32 16 words, 1 bit

SRAM (dual-port, synchronous) standard cell 32 x 1 1K x 32 16 words, 1 bit

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

Core Processors

Peripherals

Name Function

MG29C01 4-bit microprocessor slice

MG29C10 Microprogram controller/sequencer

MG65C02 8-bit microprocessor

M8042 8-bit slave microcontroller

M8048 8-bit microcontroller

MG80C85 8-bit microprocessor

MGMC51 Core processor, 8051 compatible

MGMC51I MGMC51 with ICE port

MGMC51FB Core processor, 8051FB compatible

MGMC51SD Reduced function MGMC51

Name Function

MG1468C18 Real-time clock

M16C450 UART

M6402 UART

M6845 CRT controller

M765A Floppy disk controller

M8251A Communication interface USART

M8253 Programmable interval timer

M82530 Serial communications controller

MG82C37A Programmable DMA controller

MG82C50A Asynchronous comm. element

MG82C54 Programmable interval timer

MG82C55A Programmable peripheral interface

MG82C59A Programmable interrupt controller

M8490 SCSI controller

M85C30 Serial communications controller

M8868A UART

M91C36 Digital data separator

M91C360 Digital data separator

MFDC Floppy disk controller

MGI2CSL I2C Serial bus slave transceiver

MI2C I2C Bus Interface

FIFOs

The AMI6X library supports both latched-based and dual-

port ram based FIFOs. The latch-based FIFO has a fall-

through architecture and is applicable when the FIFO

size is limited. For large sizes the RAM based FIFO is

appropriate.

FIFOs

Datapath

AMI also supports the complex datapath logic functions

listed here. These functions are synthesized from an

input set of design parameters. They can be optimized for

either minimum delay, minimum gate count or can be

designed to meet a speciﬁed delay. Contact AMI for the

size range and parameter set for any desired functions.

These logic synthesizers produce soft megacell

schematics in the ASIC Standard Library, and a

schematic symbol for incorporation and simulation with

the design netlist.

Datapath

Ordering information

With each megacell, AMI supplies schematics and test

vectors on the requested EDA tool. To order a megacell,

use the Digital Soft Megacell order form. Contact the

factory for information on the delivery of soft megacells

on various EDA tools or for information on speciﬁc

speeds and sizes of particular Datapath megacells.

Name Function

MGFxxyyC1 Fall-through FIFO

MGFxxxxyyD Synchronous FIFO

MGFxxxxyyE Asynchronous FIFO

Name Function

MGAxxyyDv Adder

MGAxxyyEv Adder-subtractor

MGBxxyyAv Barrel/arithmetic shifter

MGBxxBv Barrel shifter

MGBxxyyCv Arithmetic shifter

MGCxxAv 2-function binary comparator

MGCxxBv 6-function binary comparator

MGDxxAv Decrementer

MGIxxAv Incrementer

MGIxxBv Incrementer/decrementer

MGMxxyyDv Signed/unsigned multiplier

MGMxxyyEv Multiplier-accumulator

MGSxxyyAv Signed/unsigned subtractor

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

DC Speciﬁcations

Operating Speciﬁcations

Parameter Minimum Maximum Units

VDD, Supply Voltage 2.7 5.5 Volts

Ambient Temperature - Military -55 125 °C

- Commercial 0 70 °C

CMOS Input Speciﬁcations (4.5V<VDD<5.5V; 0°C<T<70°C)

Vil Low Level Input Voltage 0.3*VDD Volts

Vih High Level Input Voltage 0.7*VDD Volts

Iil Low Level Input Current -1.0 µA

Iih High Level Input Current 1.0 µA

Iil Input Pull-Up Current -25 -120 µA

Iih Input Pull-Down Current 25 145 µA

Vt- Schmitt Negative Threshold 0.2*VDD Volts

Vt+ Schmitt Positive Threshold 0.8*VDD Volts

Vh Schmitt Hysteresis 1.0 Volts

TTL Input Speciﬁcations (4.5V<VDD<5.5V; 0oC<T<70oC)

Vil Low Level Input Voltage 0.8 Volts

Vih High Level Input Voltage 2.0 Volts

Iil Low Level Input Current -1.0 µA

Iih High Level Input Current 1.0 µA

Iil Input Pull-Up Current -25 -120 µA

Iih Input Pull-Down Current 25 145 µA

Vt- Schmitt Negative Threshold 0.7 Volts

Vt+ Schmitt Positive Threshold 2.1 Volts

Vh Schmitt Hysteresis 0.4 Volts

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

Output Operating Speciﬁcations (4.5V<VDD<5.5V;0°C<T<70°C)

Vol = Low Level Output Voltage given in Volts lol = Low Level Output Current given in mA

Voh = High Level Output Voltage given in Volts Ioh = High Level Output Current given in mA

Absolute Maximum Ratings

Note that these speciﬁcations are to indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions.

Further, operation at absolute maximum conditions for extended periods may adversely affect the long term reliability of the device.

Driver Vol

Maximum Voh

Minimum Iol

Maximum Ioh

Maximum

1 mA Driver 0.4 2.4 1.0 -1.0

2 mA Driver 0.4 2.4 2.0 -2.0

4 mA Driver 0.4 2.4 4.0 -4.0

8 mA Driver 0.4 2.4 8.0 -8.0

12 mA Driver 0.4 2.4 12.0 -12.0

16 mA Driver 0.4 2.4 16.0 -16.0

24 mA Driver 0.4 2.4 24.0 -24.0

Parameter Minimum Maximum Units

VDD, Supply Voltage -0.3 6.0 Volts

Input Pin Voltage -0.3 VDD+0.3 Volts

Input Pin Current -10.0 10.0 mA

Storage Temperature - Plastic Packages -55 125 °C

- Ceramic Packages -65 150 °C

Lead Temperature 300 °C for 10 sec.

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

Core Cells

Simple Gates

Name Description Name Description

AA21 2-input AND gate NA61 6-input NAND gate

AA22 2-input AND gate NA81 8-input NAND gate

AA31 3-input AND gate NO21 2-input NOR gate

AA32 3-input AND gate NO22 2-input NOR gate

AA41 4-input AND gate NO31 3-input NOR gate

AA42 4-input AND gate NO32 3-input NOR gate

EN21 2-input Exclusive NOR gate NO41 4-input NOR gate

EO21 2-input Exclusive OR gate NO42 4-input NOR gate

EO31 3-input Exclusive OR gate NO51 5-input NOR gate

NA21 2-input NAND gate NO52 5-input NOR gate

NA22 2-input NAND gate OR21 2-input OR gate

NA31 3-input NAND gate OR22 2-input OR gate

NA32 3-input NAND gate OR31 3-input OR gate

NA41 4-input NAND gate OR32 3-input OR gate

NA42 4-input NAND gate OR41 4-input OR gate

NA51 5-input NAND gate OR42 4-input OR gate

NA52 5-input NAND gate

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

Complex Gates

Name Description Name Description

AN11 Two 2-input ANDs into 2-input NOR ON11 Two 2-input ORs into 2-input NAND

AN21 2-input AND into 2-input NOR ON21 2-input OR into 2-input NAND

AN31 2-input AND into 3-input NOR ON31 2-input OR into 3-input NAND

AN41 3-input AND into 2-input NOR ON41 3-input OR into 2-input NAND

AN51 2-input AND and 3-input AND into

2-input NOR ON51 2-input OR and 3-input OR into

2-input NAND

AN61 Two 3-input ANDs into 2-input NOR ON61 Two 3-input ORs into 2-input NAND

AN71 3-input AND into 3-input NOR ON71 3-input OR into 3-input NAND

AN81 Two 2-input ANDs into 3-input NOR ON81 Two 2-input ORs into 3-input NAND

AN91 2-input AND and 3-input AND into

3-input NOR ON91 2-input OR and 3-input OR into

3-input NAND

ANA1 Two 3-input ANDs into 3-input NOR ONA1 Two 3-input ORs into 3-input NAND

ANB1 Three 2-input ANDs into 3-input NOR ONB1 Three 2-input ORs into 3-input NAND

ANC1 Two 2-input ANDs and 3-input AND

into 3-input NOR ONC1 Two 2-input ORs and 3-input OR into

3-input NAND

AND1 2-input AND and two 3-input ANDs

into 3-input NOR OND1 2-input OR and two 3-input ORs into

3-input NAND

ANE1 Three 3-input ANDs into 3-input NOR ONE1 Three 3-input ORs into 3-input NAND

AU11 One-bit full adder

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

Inverting Drivers

Internal 3-State Drivers

Clock Drivers

Muxes and Decoders

Name Description Name Description

INV1 Inverter INV4 Inverter

INV2 Inverter INV5 Inverter

INV3 Inverter INV6 Inverter

Name Description Name Description

ITA1 Internal non-inverting tri-state buffer ITD1 Internal inverting tri-state buffer

ITA2 Internal non-inverting tri-state buffer ITD2 Internal inverting tri-state buffer

ITB1 Internal inverting tri-state buffer ITE1 Internal inverting tri-state buffer

ITB2 Internal inverting tri-state buffer ITE2 Internal inverting tri-state buffer

Name Description Name Description

IID1 Non-inverting clock driver IID4 Non-inverting clock driver

IID2 Non-inverting clock driver IID6 Non-inverting clock driver

Name Description Name Description

DC24 2:4 line decoder MX41 4:1 digital multiplexer

DC38 3:8 line decoder MX81 8:1 digital multiplexer

MX21 2:1 digital multiplexer MXI21 Inverting 2:1 digital multiplexer

MX212 2:1 digital multiplexer MXI212 Inverting 2:1 digital multiplexer

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

Sequential Logic

Name Description Name Description

DF081 D-type F/F without set or reset DFAB1 D-type F/F with active low set and

reset (only available in gate array)

DF091 D-type F/F with active low set DFB01 D-type buffered F/F with active low

set (only available in gate array)

DF0A1 D-type F/F with active low reset DFB11 D-type buffered F/F with active low

reset (only available in gate array)

DF0B1 D-type F/F with active low set and

reset DFB21 D-type buffered F/F with active low

set and reset (only in gate array)

DF101 D-type buffered F/F with active low

set DL531 D-type latch without set or reset

DF111 D-type buffered F/F with active low

reset DL541 D-type latch with active low reset

DF121 D-type buffered F/F with active low

set and reset DL551 D-type latch with active low set

DF281 D-type unbuffered mux scan F/F with-

out set or reset DL561 D-type latch with active low set and

reset

DF291 D-type unbuffered mux scan F/F with

active low set DL641 D-type buffered latch with active low

reset

DF2A1 D-type unbuffered mux scan F/F with

active low reset DL651 D-type buffered latch with active low

set

DF2B1 D-type unbuffered mux scan F/F with

active low set and reset DL661 D-type buffered latch with active low

set and reset

DF401 D-type buffered mux scan F/F with

active low set DLZ01 D-type latch without set or reset and

a dual-enable tri-state output

DF411 D-type buffered mux scan F/F with

active low reset DLZ11 D-type latch with active low reset and

a dual-enable tri-state output

DF421 D-type buffered mux scan F/F with

active low set and reset JK091 JK-type unbuffered F/F with active

low set

DFA81 D-type F/F without set or reset (only

available in gate array) JK0A1 JK-type unbuffered F/F with active

low reset

DFA91 D-type F/F with active low set (only

available in gate array) JK0B1 JK-type unbuffered F/F with active

low set and reset

DFAA1 D-type F/F with active low reset (only

available in gate array) JKBB1 JK-type buffered F/F with active low

set and reset

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

Power Core Cells

Special Core Cells

Name Description Name Description

CVDD Core cell input resistive tie-up to core

VDD bus CVSS Core cell input resistive tie-down to

core VSS bus

Name Description Name Description

BL02 Tri-state bus latch TD02 Time delay cell, non-inverting

BR02 Tri-state bus receivers TD03 Time delay cell, non-inverting

BR04 Tri-state bus receivers TD08 Time delay cell, non-inverting

BR06 Tri-state bus receivers

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

Pad Cells

AMI provides an innovative method for designing pad

cells. This method allows the ASIC designer to deﬁne pad

cells by choosing from a vast array of pad pieces. These

pieces can be assembled to perform the desired

functions. The AMI6x libraries include categories of input

drive, output drive, and pullup/pulldown pieces. One or

zero pieces from each category is chosen and connected

at a common node to form a unique pad cell. The AMI6x

libraries also offer several conventional pad cells as well

(i.e. not made from pieces).

Input Drive Pieces

Pullup/pulldown Pieces

Name Description Name Description

IDCI3 Inverting CMOS input IDQC0 Oscillator input (no drive)

IDCR0 CMOS protected (no drive) IDQC3 Oscillator CMOS input

IDCS3 CMOS schmitt input IDQS3 Oscillator schmitt input

IDCX3 CMOS input IDTS3 TTL schmitt input

IDPX3 PCI input IDTX3 TTL input

Name Description Name Description

PLB4 Tri-state biasing (PosSupply/2) PLP3 Programmable Pull-up/down

PLD3 Active pull-down PLU3 Active pull-up

PLH4 Tri-state holding (latch)

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

Output Drive Pieces

From the piece listings it is noted that this method provides in excess of 1,500 unique pad cell possibilities, some of

which may not be feasible or practical. The AMI6x data books and design manuals have more detailed information

regarding design implementations using pad pieces.

Name ## Output Drive (mA) Description

ODCSIP## 04, 08, 12 CMOS inverting P-channel open drain w/ slew rate control output

ODCSXE## 04, 08, 12, 16, 24 CMOS tri-statable non-inverting w/ slew rate control output

ODCSXX## 04, 08, 12, 16, 24 CMOS non-inverting w/ slew rate control output

ODCXIP## 01, 02, 04, 08 CMOS inverting P-channel open drain output

ODCXXE## 01, 02, 04, 08, 12, 16, 24 CMOS tri-statable non-inverting output

ODCXXX## 01, 02, 04, 08, 12, 16, 24 CMOS non-inverting output

ODPSXE## 24 PCI tri-statable non-inverting w/ slew rate control output

ODQFE20M (2 mA) Crystal oscillator drive, fundamental mode to 20 MHz w/ enable

ODQFE99K (1 mA) Crystal oscillator drive, fundamental mode to 99 KHz w/ enable

ODQTE60M (4 mA) Crystal oscillator drive, third overtone to 60 MHz w/ enable

ODTSXN## 04, 08, 12, 16, 24 TTL non-inverting N-channel open drain w/ slew rate control output

ODTSXE## 04, 08, 12, 16, 24 TTL tri-statable non-inverting w/ slew rate control output

ODTSXX## 04, 08, 12, 16, 24 TTL non-inverting w/ slew rate control output

ODTXXN## 01, 02, 04, 08, 12, 16, 24 TTL non-inverting N-channel open drain output

ODTXXE## 01, 02, 04, 08, 12, 16, 24 TTL tri-statable non-inverting output

ODTXXX## 01, 02, 04, 08, 12, 16, 24 TTL non-inverting output

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

Clock Driver Pad Cells

Power Pad Cells

In the interest of maintaining backward compatibility with previous AMI pad cell libraries, all pad cells from the AMI ASIC

Standard set are supported through soft cell implementations included with each AMI supported EDA design kit.

As an additional feature of the AMI6x pad libraries, AMI physical pad designs are voltage supply independent. With this

feature, ASIC designers have the capability of doing mixed supply designs. AMI supports mixed supply designs with a

single core supply and one or two supplies in the pad ring (one of which must be the same as the core supply). AMI also

supports single pad ring supply designs with an adjustable core supply voltage. Mixed supply designs are advanced

features of the AMI6x libraries with more detailed information available in the AMI6x design manual. All ASIC designers

should consult the AMI6x data book and design manual to become familiar with ASIC pad cell design using the

enhanced AMI pad libraries.

Special Pad Cells

Name Description Name Description

IBF1X5 CMOS-level input clock driver IIF1X5 CMOS-level pad clock driver

IBF7X5 TTL-level input clock driver

Name Description Name Description

PP6GXBG VSS power pad for core and pad PP6GXCG VSS power pad for core and input

buffer cells only

PP6GXBP VDD power pad for core and pad PP6GXPG VSS power pad for output buffers only

PP6GXCW Power pad pin for additional bus PP6GXCE ESD protected power pad for use

with core signals. No series res.

Name Description Name Description

IBCNX3 N-channel differential comparator IBCNH3 N-channel differential comparator

with hysteresis

IBEXX3 ECL differential comparator IBCPX3 P-channel differential comparator

IBCPH3 P-channel differential comparator

with hysteresis

Digital ASICs

Products and Services November 1995

0.6 micron CMOS

Gate Array & Standard Cell

Simple Analog Embedded Cells

NOTE 1: The ofﬁcial names, details, and rules of instantiation for these cells will be released upon characterization and model generation.

The analog functions are embedded in the corners of each gate array and are available as corner cells in standard cells.

Analog functions like the PLL, voltage reference and op-amp are metal or netlist programmable to allow the user more

ﬂexibility in their simple analog needs.

Name Description

POR Power-on-reset

OP-AMP1Operational ampliﬁer

SB-OSC1Self biased crystal oscillator

VRef1Bandgap voltage reference

DAC1Digital to analog converter (8-bit)

ADC1Analog to digital converter (8-bit)

PLL1Phase lock loop

COMP1Comparator with rail to rail input range

OD-OSC1Low power 32 KHz crystal oscillator

Digital ASICs

November 1995 Products and Services

0.6 micron CMOS

Gate Array & Standard Cell

Packaging

The AMI6X family can be packaged in a variety of popular packages.

New packages are in development which will extend the package offering. Some special packages or packaging

requirements can be supplied if requested. More details on special packages are available from an AMI sales

representative.

Available Packages ( ) = Lead time required

Note 1: The 304 pin PowerQuad2 package has an added heat slug to improve power dissipation.

Package Type Pin Count

Plastic Quad Flatpack (PQFP) 44, 52, 64, 80, 100, 120, 128, 144, 160, 208, 240, 256, (3041)

Thin Quad Flatpack (TQFP) 44, 48, 64, 80, 100, 128, 144, 176

Metal Quad Flatpack (MQUAD®) 128, 144, 208

Power Quad 2 (PQ2) 128, 144, 160, 208

Ceramic Quad Flatpack (CQFP) 40, 44, 52, 64, 84, 100, 132, 144, 172, 196

Plastic Leaded Chip Carrier (PLCC) 20, 28, 44, 52, 68, 84

Ceramic Leaded Chip Carrier (JLDCC) 28, 44, 68, 84

Ceramic Leadless Chip Carrier (CLCC) 20, 24, 28, 40, 44, 48, 52, 68, 84

Plastic Pin Grid Array (PPGA) 69, 85, 101, 109, 121, 132, 145, 180

Ceramic Pin Grid Array (CPGA) 65, 68, 69, 84, 85, 101, 109, 121, 132, 145, 155, 177, 181, 208, 225, 257,

299, 476

Ball Grid Array (BGA) (121), (169), (225), (256), (313), (352)