"The new 0.6m gate array and standard cell families from AMI provide outstanding quality and selection . . . setting performance standards in 0.6m ASIC products . . . " 130 ps gate delays (fanout = 2, interconnect length = 0mm) Double and Triple Metal Interconnect; up to 900,000 gate designs using megacells, ROM, RAM, and logic An innovative pad cell design method that allows the user to design pad cell configurations using predefined pieces Complete package lineup QFP, PLCC, BGA, PGA . . . Expanded selection of megacells Families of single and multi-port RAMs, ROMs, microprocessors, controllers, datapath functions . . . "Made in America" engineering, manufacturing, and support Table of Contents Features ....................................................................................... 1 AMI6Gx Gate Array Family ............................................................... 2 AMI6S Standard Cell Family ............................................................ 3 Digital Megacell Family .................................................................. 3 Architectural Overview ............................................................ 4 - 5 Product Applications ..................................................................... 6 ASIC Design Tools and Methodology .......................................... 6 - 7 The Design Library .................................................................. 8 - 9 DC Specifications .................................................................. 10 - 11 Library Cell Selection Guide ................................................... 12 - 20 Packaging ................................................................................. 21 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Description * Extensive library for quick design: - Complete primary cell and I/O library. - Asynchronous and synchronous, single and dual-port RAM compilers with over 2000 compiled RAM sizes from 32x1 to 2Kx32 bits. - Synchronous ROM compiler from 64x1 to 16Kx32 bits. - Megacells include processors, peripherals, and datapath synthesizers. - 100% compatible with AMI's proven ASIC Standard Library. AMI's "AMI6Gx" series of 0.6m gate arrays exploits a proprietary power grid and track routing architecture on a compact, channelless, sea-of-gates design to provide one of the highest performance, cost effective array products available today. The "AMI6S" standard cell family continues the AMI leadership tradition of combining true compact building block standard cells and megacells with high speed memory and datapath functions. Using a 0.6m high performance CMOS process, the AMI6S product can offer a lower cost alternative to gate array for high volume applications. * 1 to 24 mA drive per single I/O cell: Slew rate limiting available for 4, 8, 12, 16, and 24 mA drive. Custom configurations for I/O drive up to 96 mA can be supported. Features * Excellent performance: - 395 MHz maximum toggle rate on clocked flip-flops (TJ = 135C). - 215 ps delay (FO=2; L=2mm) for a 2-input NAND gate. - 130 ps delay (FO=2; L=0mm) for a 2-input NAND gate. * Wide range of packaging: Full QFP and PLCC line, BGAs and PGAs, individual die. Burn-in capability as required. * Automatic Test Program Generation: Includes scan macros (NETSCAN) for high fault coverage. * Operating Temperatures range from -55 to 125oC: Few competing products allow this range. * JTAG Boundary Scan macro support * Clock grid generation: 300ps clock skew (fan out = 3500 at 80 MHz). * Full operating voltage range from 2.7V to 5.5V * ESD protection > 2kV; latchup > 100 mA * User-designed pad cells: AMI allows the user to design pad cells by piecing together predefined components. * Power dissipation: 2.7W/MHz/gate (FO=1; VDD=5V) for gate array and 2.5W/MHz/gate for standard cell. * Cost driven architecture: - Offers both 2 and 3 level metal interconnect to provide the lowest user cost for the number of gates and pads required. - Compiled memory blocks on standard cells are compacted precisely to parameters. No leaf cell overhead. 1 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 AMI6Gx Gate Array Family Overview PART NUMBER2 RAW GATES USABLE GATES1 BOND PADS I/O CELLS 2.67 44 52 7.85 10.46 100 100 32.87 16.44 21.89 144 144 AMI6G41S 40.49 20.25 26.97 160 160 AMI6G70S 69.28 34.64 46.14 208 208 AMI6G106S 105.74 52.87 70.42 256 256 AMI6G150S 149.88 74.94 99.82 304 304 AMI6G202S 201.71 100.86 134.34 352 352 AMI6G333 333.51 166.76 222.12 384 452 AMI6G471 470.53 235.27 313.37 456 536 AMI6G603 602.77 301.39 401.44 520 608 AMI6G713 712.94 356.47 474.82 564 660 AMI6G876 875.63 437.82 583.17 624 732 AMI6G1046 1045.91 522.96 696.58 684 800 AMI6G1210 1210.35 605.18 806.09 736 860 2LM 3LM 4.01 2.01 AMI6G16S 15.71 AMI6G33S AMI6G4 Note 1: Exact usable gate count will vary depending on design interconnect and macro selection. Note 2: The AMI6GS series has AMI's proprietary enhanced I/O for tighter pad pitches. 2 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 AMI6S Standard Cell Family Overview Feature Comment gates1 Up to 900,000 Up to 500,000 gates 50% memory, 50% megacell and user defined logic 100% user defined logic Up to 512 pins Up to 836 pins Test equipment limit; signal pins only Die size limit; includes power supply pins Internal Gate 102 ps (Fanout=1, L=0mm) 215 ps (Fanout=2, L=2mm) 2 input NAND gate, T=25C, VDD=5V Input Buffer 675 ps (Fanout=2, L=2mm) CMOS Input buffer, T=25C, VDD=5V 860 ps (CL=15pf) CMOS Output buffer,T=25C, VDD=5V Complexity I/O Count Delay Time Description Output Buffer Digital Megacell Family Overview Feature Description Comment Core Processors MG29C01,MG29C10,MG65C02, M8042, M8048, MG80C85, MGMC51, MGMC51I, MGMC51FB, MGMC51SD Functionally compatible with popular standard designs. Peripherals MG1468C18, M16C450, M6402, M6845, M765A, M8251A, M8253, M82530, MG82C37A, MG82C50A, MG82C54, MG82C55A, MG82C59A, M8490, M85C30, M8868A, M91C36, M91C360, MFDC, MGI2CSL, MI2C Functionally compatible with popular standard designs. FIFOs Fall-through and RAM-based FIFO's See page 9 for complete list and details Datapath Synthesizers multipliers, adders, subtracters, barrel shifters, comparators,... See page 9 for complete list and details Memory Compilers synchronous single-port self-timed SRAM (over 4000 sizes) synchronous dual-port SRAM (over 4000 sizes) synchronous ROM (over 8000 sizes) asynchronous single-port SRAM See page 8 for complete list and details Note 1: Compact memory arrays greatly increase gate count on an equivalent gate basis. 3 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 FIGURE 1: GATE ARRAY ARCHITECTURE Selectable 2 or 3 metal interconnect [note 1] Large I/O driver with prebuffer [note 4] Core cell sites with 4 transistors [note 2] 2 P-channel 2 N-channel Separately configured power busses for I/O and core [note 3] Architectural Overview * [Note 3] Four separate power busses for I/O cells to allow separate supplies for output buffers, input buffers, and mixed VDD levels all on an individual I/O cell basis. Two separate power busses for core logic (not shown). Some important elements of the AMI6Gx gate array family are: * [Note 1] 2 or 3 level metal interconnect selectable. * [Note 2] Two p-channel and two n-channel transistors per site (or cell). Sites are arrayed in a sea-of-gates structure that can allow interconnect routing over active sites. Also, p-channel transistors are sized larger than the stronger n-channel transistors in each cell to provide better matched rise times and fall times. * Each I/O cell can be configured as 5V VDD, 3V VDD, VSS, or signal I/O. * [Note 4] Each I/O cell has selectable drive from 1mA to 24mA. All I/O cell logic can be built in the I/O cell prebuffer. Level shifting (3V to 5V or 5V to 3V) may require the use of a few core gates. 4 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 RAM BLOCK ROM BLOCK DF101 MG29C01 Soft Megacell Individually compacted cells [note 1] Fixed bus height, variable height Architectural Overview Some important elements of the AMI6S standard cell family are: * 2 or 3 level metal interconnect selectable. * [Note 1] Each cell function is tightly compacted to a fixed bus height. Cells are then placed in rows allowing VDD and V SS supplies to feed through the cells. Since some functions require more gates than others, their widths and heights may increase to allow for the added gates. Transistor sizes and routing are optimized for their function, giving a much tighter cell design than with gate arrays or fixed pad ring embedded array products. * [Note 2] Rows of cells can be placed adjacently if little routing is required between them, or largely separated to allow a large data bus to route through. Tracks of 5 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Product Applications AMI Design Flow The Gate Array's extended temperature and voltage operation range make it well suited for telecom, industrial, and military applications. The low cost structure also makes it ideal in computer and office automation ASIC requirements. AMI will supply an AMI6X design kit which includes a cell library containing symbols, simulation models and software for design verification, timing calculations, and netlist generation. For pre-layout timing simulations, capacitance and resistance values derived from statistical The AMI6S standard cells are targeted at higher volume digital ASIC products. The lower cost also fits designs requiring significant on-board memory, datapath logic, or megacells. FIGURE 3: ASIC DESIGN FLOW Design Specification FPGA OR PAL CONVERSION: Using NETRANS AMI can convert netlists from most gate array, FPGA, and PAL devices to a more cost and performance effective AMI6X design for volume production. AMI ASIC Std. Library AMI megacell or memory block 2ND SOURCE EXISTING PRODUCTS: Netlist conversion capabilities from AMI allow a competitive alternate supply with AMI6X components for current high volume designs. AMI supported Synthesis Tool Schematic Capture Logic / Timing Simulation Customer Design Activity Fault Simulation NEW DESIGN CAPTURE: AMI6X design is supported by many popular 3rd party software platforms, as well as AMI's Enhanced Design Utilities (EDU) environment. Netlist transfer to AMI PROCESS UPGRADE: Designs done in AMI's 1.25m, 1.0m, and 0.8m ASIC products can easily be upgraded to the AMI6X family. The AMI ASIC Standard Library provides a common netlist design base. Test Vectors to AMI Simulation Verification ADDING CUSTOM BLOCKS: AMI specializes in adding custom logic to ASIC designs. Simple analog functions are also possible. Place and Route ASIC Design Tools and Methodology AMI6X and other AMI ASIC families are supported on many front-end design environments: * * * * * * * * Layout Parameter Extraction Cadence Mentor Graphics Synopsys Viewlogic Intergraph Compass Verilog simulation IKOS simulation accelerator (AMI's sign-off simulator) Test Development Back Annotation to Customer Post Layout Simulation Physical Design Verification Customer Approval Final Review AMI has maintained critical proprietary software tools to ensure a tight, well coupled design to our silicon process. This methodology includes our expert-system design analysis tools, AMI's Enhanced Design Utilities (EDU), a software support methodology that covers the complete set of wafer processing possibilities, and a dedicated, experienced engineering staff that can assist at any level of the design process. Mask Creation Fabricate and Test Prototypes Prototype Approval 6 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 AMI Design Flow (cont.) averages of known layouts are used. Once actual layout is completed by AMI, a post-layout interconnect capacitance and resistance table will be supplied for final validation of device timing. IKOS, AMI's sign-off simulator. The results are compared to the customer's simulation from the third-party CAE tool. Once the design has passed the initial screening it is then ready for placement and routing. The layout proceeds by first placing memory and megacells, assigning priority to critical paths, and designing the distribution and buffering of clocks. Next, the layout is completed with automatic place-and-route on the balance of the circuit. Figure 3 shows a typical design flow for a new design. Working with an AMI design center, the customer is responsible for capturing and verifying the design using the AMI ASIC Standard Library. He is also responsible for creating the test vectors that will eventually serve as the logical part of the manufacturing test. Software aids such as logic synthesis, megacells, automatic test program generation, netlist rule checkers, etc. can greatly speed up this process. (A fault coverage check of the test vector set is optional and can be done as an additional service.) After layout has been completed the interconnect data is extracted from the physical layout to be fed back to the sign-off simulator for final circuit verification. This post layout interconnect data can be sent to the customer for final validation on his simulator. When the post-layout simulation has been completed and approved by the customer the design is then released for mask and wafer fabrication. When the design is received by the factory, the "Design Start Package" is reviewed by AMI engineers. This start package, which is completed by the customer, contains the device specification, netlist, pinlist file, critical timing paths, and test vectors. The design is pre-screened on the Enhanced Design Utilities (EDU) and then resimulated on The test program is developed in parallel using internal automatic test program generation software. Prototypes can then be tested before they are shipped. FIGURE 4: DESIGN ENVIRONMENT WITH THIRD PARTY SOFTWARE AMI Environment * AMI ASIC Std. Library Logic Synthesis Memory Compiler HDL Optional Synthesis Tool Schematic Translation * Schematic Entry AMI ASIC Stnd. Library Physical Data * Design Database Netlist Translation Third Party Environment * * Enhanced Design Utilities Elements supplied in AMI Design Kit Vector Generation Estimated Delays * Models & Symbols VHDL Timing Simulation Design Verification Place and Route Post Route Verification ATPG 7 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Memory Compiler Library Memory Compiler SRAM (single-port, synchronous, self-timed) SRAM (single-port, synchronous, self-timed) ROM (synchronous) SRAM (single-port, asynchronous) SRAM (dual-port, synchronous) Process gate array standard cell standard cell standard cell standard cell Figure 4 outlines a typical software environment when using third party tools. AMI uses EDIF to speed ports between various software products. Size min. 16 x 1 32 x 1 64 x 1 32 x 1 32 x 1 max. 1K x 32 2K x 32 16K x 32 2K x 32 1K x 32 Increment 16 words, 1 bit 16 words, 1 bit 64 words, 1 bit 16 words, 1 bit 16 words, 1 bit Digital Soft Megacells The AMI6X gate array and standard cell families support soft megacells that are compatible with many popular functions. These megacells are functionally and logically compatible with the stand-alone products. AMI's Enhanced Design Utilities Tools are intended to be used interactively at each stage of the design. EDU software is a set of design analysis tools that check both the design and test vectors for correctness and compatibility with in-house ASIC testers, and analyze the design for inefficiencies and possible flaws that could cause problems in manufacturing the device. A soft megacell is defined only at the functional schematic level. Each instance of the megacell will have exactly the same functional definition; however, the physical mask layout will be different depending on other functions being used, the place-and-route tools, and process technology. The megacell becomes part of the design netlist, requiring back annotation of interconnect capacitance after placeand-route for final verification. The Design Library AMI provides a robust collection of building blocks for the AMI6X family. A broad range of primary cells is complemented with memory cell compilers and useful megafunctions. With such broad, US-based design talent, AMI can quickly design specific cells that customers need to add an edge in customization. Because AMI's soft megacells are defined at the gate level, simulation models are more accurate than that of behavioral models. Since our soft megacells use AMI's ASIC Standard Library they have the advantages of design flexibility, portability, and a path for future cost reduction by process migration. The AMI ASIC Standard Library The AMI ASIC Standard Library contains a rich set of core and configurable pad cells which allow great flexibility in building competitive devices for customer applications. The library is portable across all AMI's gate array and standard cell families. The ASIC Standard Library is listed in detail on pages 12 to 20. AMI's selection of soft megacells include Core Processors and Peripherals which duplicate the function of industry standard parts. In addition AMI offers FIFOs and Datapath megacells which are developed using synthesizers. These products are listed in the following tables. Core Processors and Peripherals Memory Compilers The Core Processor and Peripheral megacells are designed to duplicate the function of industry standard, stand-alone parts. Detailed functional information can be found in any standard device datasheet. The AMI6X family includes the line of memory compilers shown above. Each of the thousands of possible memory blocks is optimized precisely to the customers' parameters rather than built from a presized leaf cell that covers a range of sizes. This yields a better size and performance match for each application. Upon supplying the cell specification to AMI, the customer can receive an accurate simulation timing specification overnight by facsimile and a full simulation model for any AMI supported software environment within five working days. 8 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Core Processors Name MG29C01 MG29C10 MG65C02 M8042 M8048 MG80C85 MGMC51 MGMC51I MGMC51FB MGMC51SD FIFOs The AMI6X library supports both latched-based and dualport ram based FIFOs. The latch-based FIFO has a fallthrough architecture and is applicable when the FIFO size is limited. For large sizes the RAM based FIFO is appropriate. Function 4-bit microprocessor slice Microprogram controller/sequencer 8-bit microprocessor 8-bit slave microcontroller 8-bit microcontroller 8-bit microprocessor Core processor, 8051 compatible MGMC51 with ICE port Core processor, 8051FB compatible Reduced function MGMC51 FIFOs Name MGFxxyyC1 MGFxxxxyyD MGFxxxxyyE Datapath AMI also supports the complex datapath logic functions listed here. These functions are synthesized from an input set of design parameters. They can be optimized for either minimum delay, minimum gate count or can be designed to meet a specified delay. Contact AMI for the size range and parameter set for any desired functions. Peripherals Name MG1468C18 M16C450 M6402 M6845 M765A M8251A M8253 M82530 MG82C37A MG82C50A MG82C54 MG82C55A MG82C59A M8490 M85C30 M8868A M91C36 M91C360 MFDC MGI2CSL MI2C Function Fall-through FIFO Synchronous FIFO Asynchronous FIFO Function Real-time clock UART UART CRT controller Floppy disk controller Communication interface USART Programmable interval timer Serial communications controller Programmable DMA controller Asynchronous comm. element Programmable interval timer Programmable peripheral interface Programmable interrupt controller SCSI controller Serial communications controller UART Digital data separator Digital data separator Floppy disk controller I2C Serial bus slave transceiver I2C Bus Interface These logic synthesizers produce soft megacell schematics in the ASIC Standard Library, and a schematic symbol for incorporation and simulation with the design netlist. Datapath Name MGAxxyyDv MGAxxyyEv MGBxxyyAv MGBxxBv MGBxxyyCv MGCxxAv MGCxxBv MGDxxAv MGIxxAv MGIxxBv MGMxxyyDv MGMxxyyEv MGSxxyyAv Function Adder Adder-subtractor Barrel/arithmetic shifter Barrel shifter Arithmetic shifter 2-function binary comparator 6-function binary comparator Decrementer Incrementer Incrementer/decrementer Signed/unsigned multiplier Multiplier-accumulator Signed/unsigned subtractor Ordering information With each megacell, AMI supplies schematics and test vectors on the requested EDA tool. To order a megacell, use the Digital Soft Megacell order form. Contact the factory for information on the delivery of soft megacells on various EDA tools or for information on specific speeds and sizes of particular Datapath megacells. 9 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 DC Specifications Operating Specifications Parameter Minimum Maximum Units VDD, Supply Voltage 2.7 5.5 Volts Ambient Temperature - Military -55 125 C 0 70 C 0.3*VDD Volts - Commercial CMOS Input Specifications (4.5V<VDD<5.5V; 0C<T<70C) Vil Low Level Input Voltage Vih High Level Input Voltage Iil Low Level Input Current -1.0 A Iih High Level Input Current 1.0 A Iil Input Pull-Up Current -25 -120 A Iih Input Pull-Down Current 25 145 A Vt- Schmitt Negative Threshold Vt+ Schmitt Positive Threshold Vh Schmitt Hysteresis TTL Input Specifications 0.7*VDD Volts 0.2*VDD Volts 0.8*VDD 1.0 Volts Volts (4.5V<VDD<5.5V; 0oC<T<70oC) 0.8 Volts Vil Low Level Input Voltage Vih High Level Input Voltage Iil Low Level Input Current -1.0 A Iih High Level Input Current 1.0 A Iil Input Pull-Up Current -25 -120 A Iih Input Pull-Down Current 25 145 A Vt- Schmitt Negative Threshold 0.7 Vt+ Schmitt Positive Threshold Vh Schmitt Hysteresis 2.0 Volts Volts 2.1 0.4 10 Volts Volts 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Output Operating Specifications (4.5V<VDD<5.5V;0C<T<70C) Driver Vol Maximum Voh Minimum Iol Maximum Ioh Maximum 1 mA Driver 0.4 2.4 1.0 -1.0 2 mA Driver 0.4 2.4 2.0 -2.0 4 mA Driver 0.4 2.4 4.0 -4.0 8 mA Driver 0.4 2.4 8.0 -8.0 12 mA Driver 0.4 2.4 12.0 -12.0 16 mA Driver 0.4 2.4 16.0 -16.0 24 mA Driver 0.4 2.4 24.0 -24.0 Vol = Low Level Output Voltage given in Volts lol = Low Level Output Current given in mA Voh = High Level Output Voltage given in Volts Ioh = High Level Output Current given in mA Absolute Maximum Ratings Parameter Minimum Maximum Units VDD, Supply Voltage -0.3 6.0 Volts Input Pin Voltage -0.3 VDD+0.3 Volts Input Pin Current -10.0 10.0 mA Storage Temperature - Plastic Packages -55 125 C -65 150 C 300 C for 10 sec. - Ceramic Packages Lead Temperature Note that these specifications are to indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Further, operation at absolute maximum conditions for extended periods may adversely affect the long term reliability of the device. 11 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Core Cells Simple Gates Name Description Name Description AA21 2-input AND gate NA61 6-input NAND gate AA22 2-input AND gate NA81 8-input NAND gate AA31 3-input AND gate NO21 2-input NOR gate AA32 3-input AND gate NO22 2-input NOR gate AA41 4-input AND gate NO31 3-input NOR gate AA42 4-input AND gate NO32 3-input NOR gate EN21 2-input Exclusive NOR gate NO41 4-input NOR gate EO21 2-input Exclusive OR gate NO42 4-input NOR gate EO31 3-input Exclusive OR gate NO51 5-input NOR gate NA21 2-input NAND gate NO52 5-input NOR gate NA22 2-input NAND gate OR21 2-input OR gate NA31 3-input NAND gate OR22 2-input OR gate NA32 3-input NAND gate OR31 3-input OR gate NA41 4-input NAND gate OR32 3-input OR gate NA42 4-input NAND gate OR41 4-input OR gate NA51 5-input NAND gate OR42 4-input OR gate NA52 5-input NAND gate 12 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Complex Gates Name Description Name Description AN11 Two 2-input ANDs into 2-input NOR ON11 Two 2-input ORs into 2-input NAND AN21 2-input AND into 2-input NOR ON21 2-input OR into 2-input NAND AN31 2-input AND into 3-input NOR ON31 2-input OR into 3-input NAND AN41 3-input AND into 2-input NOR ON41 3-input OR into 2-input NAND AN51 2-input AND and 3-input AND into 2-input NOR ON51 2-input OR and 3-input OR into 2-input NAND AN61 Two 3-input ANDs into 2-input NOR ON61 Two 3-input ORs into 2-input NAND AN71 3-input AND into 3-input NOR ON71 3-input OR into 3-input NAND AN81 Two 2-input ANDs into 3-input NOR ON81 Two 2-input ORs into 3-input NAND AN91 2-input AND and 3-input AND into 3-input NOR ON91 2-input OR and 3-input OR into 3-input NAND ANA1 Two 3-input ANDs into 3-input NOR ONA1 Two 3-input ORs into 3-input NAND ANB1 Three 2-input ANDs into 3-input NOR ONB1 Three 2-input ORs into 3-input NAND ANC1 Two 2-input ANDs and 3-input AND into 3-input NOR ONC1 Two 2-input ORs and 3-input OR into 3-input NAND AND1 2-input AND and two 3-input ANDs into 3-input NOR OND1 2-input OR and two 3-input ORs into 3-input NAND ANE1 Three 3-input ANDs into 3-input NOR ONE1 Three 3-input ORs into 3-input NAND AU11 One-bit full adder 13 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Inverting Drivers Name Description Name Description INV1 Inverter INV4 Inverter INV2 Inverter INV5 Inverter INV3 Inverter INV6 Inverter Internal 3-State Drivers Name Description Name Description ITA1 Internal non-inverting tri-state buffer ITD1 Internal inverting tri-state buffer ITA2 Internal non-inverting tri-state buffer ITD2 Internal inverting tri-state buffer ITB1 Internal inverting tri-state buffer ITE1 Internal inverting tri-state buffer ITB2 Internal inverting tri-state buffer ITE2 Internal inverting tri-state buffer Clock Drivers Name Description Name Description IID1 Non-inverting clock driver IID4 Non-inverting clock driver IID2 Non-inverting clock driver IID6 Non-inverting clock driver Muxes and Decoders Name Description Name Description DC24 2:4 line decoder MX41 4:1 digital multiplexer DC38 3:8 line decoder MX81 8:1 digital multiplexer MX21 2:1 digital multiplexer MXI21 Inverting 2:1 digital multiplexer MX212 2:1 digital multiplexer MXI212 Inverting 2:1 digital multiplexer 14 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Sequential Logic Name Description Name Description DF081 D-type F/F without set or reset DFAB1 D-type F/F with active low set and reset (only available in gate array) DF091 D-type F/F with active low set DFB01 D-type buffered F/F with active low set (only available in gate array) DF0A1 D-type F/F with active low reset DFB11 D-type buffered F/F with active low reset (only available in gate array) DF0B1 D-type F/F with active low set and reset DFB21 D-type buffered F/F with active low set and reset (only in gate array) DF101 D-type buffered F/F with active low set DL531 D-type latch without set or reset DF111 D-type buffered F/F with active low reset DL541 D-type latch with active low reset DF121 D-type buffered F/F with active low set and reset DL551 D-type latch with active low set DF281 D-type unbuffered mux scan F/F without set or reset DL561 D-type latch with active low set and reset DF291 D-type unbuffered mux scan F/F with active low set DL641 D-type buffered latch with active low reset DF2A1 D-type unbuffered mux scan F/F with active low reset DL651 D-type buffered latch with active low set DF2B1 D-type unbuffered mux scan F/F with active low set and reset DL661 D-type buffered latch with active low set and reset DF401 D-type buffered mux scan F/F with active low set DLZ01 D-type latch without set or reset and a dual-enable tri-state output DF411 D-type buffered mux scan F/F with active low reset DLZ11 D-type latch with active low reset and a dual-enable tri-state output DF421 D-type buffered mux scan F/F with active low set and reset JK091 JK-type unbuffered F/F with active low set DFA81 D-type F/F without set or reset (only available in gate array) JK0A1 JK-type unbuffered F/F with active low reset DFA91 D-type F/F with active low set (only available in gate array) JK0B1 JK-type unbuffered F/F with active low set and reset DFAA1 D-type F/F with active low reset (only available in gate array) JKBB1 JK-type buffered F/F with active low set and reset 15 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Power Core Cells Name CVDD Description Name Core cell input resistive tie-up to core VDD bus CVSS Description Core cell input resistive tie-down to core VSS bus Special Core Cells Name Description Name Description BL02 Tri-state bus latch TD02 Time delay cell, non-inverting BR02 Tri-state bus receivers TD03 Time delay cell, non-inverting BR04 Tri-state bus receivers TD08 Time delay cell, non-inverting BR06 Tri-state bus receivers 16 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Pad Cells drive, output drive, and pullup/pulldown pieces. One or zero pieces from each category is chosen and connected at a common node to form a unique pad cell. The AMI6x libraries also offer several conventional pad cells as well (i.e. not made from pieces). AMI provides an innovative method for designing pad cells. This method allows the ASIC designer to define pad cells by choosing from a vast array of pad pieces. These pieces can be assembled to perform the desired functions. The AMI6x libraries include categories of input Input Drive Pieces Name Description Name Description IDCI3 Inverting CMOS input IDQC0 Oscillator input (no drive) IDCR0 CMOS protected (no drive) IDQC3 Oscillator CMOS input IDCS3 CMOS schmitt input IDQS3 Oscillator schmitt input IDCX3 CMOS input IDTS3 TTL schmitt input IDPX3 PCI input IDTX3 TTL input Pullup/pulldown Pieces Name Description Name Description PLB4 Tri-state biasing (PosSupply/2) PLP3 Programmable Pull-up/down PLD3 Active pull-down PLU3 Active pull-up PLH4 Tri-state holding (latch) 17 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Output Drive Pieces Name ## Output Drive (mA) Description ODCSIP## 04, 08, 12 CMOS inverting P-channel open drain w/ slew rate control output ODCSXE## 04, 08, 12, 16, 24 CMOS tri-statable non-inverting w/ slew rate control output ODCSXX## 04, 08, 12, 16, 24 CMOS non-inverting w/ slew rate control output ODCXIP## 01, 02, 04, 08 CMOS inverting P-channel open drain output ODCXXE## 01, 02, 04, 08, 12, 16, 24 CMOS tri-statable non-inverting output ODCXXX## 01, 02, 04, 08, 12, 16, 24 CMOS non-inverting output ODPSXE## 24 PCI tri-statable non-inverting w/ slew rate control output ODQFE20M (2 mA) Crystal oscillator drive, fundamental mode to 20 MHz w/ enable ODQFE99K (1 mA) Crystal oscillator drive, fundamental mode to 99 KHz w/ enable ODQTE60M (4 mA) Crystal oscillator drive, third overtone to 60 MHz w/ enable ODTSXN## 04, 08, 12, 16, 24 TTL non-inverting N-channel open drain w/ slew rate control output ODTSXE## 04, 08, 12, 16, 24 TTL tri-statable non-inverting w/ slew rate control output ODTSXX## 04, 08, 12, 16, 24 TTL non-inverting w/ slew rate control output ODTXXN## 01, 02, 04, 08, 12, 16, 24 TTL non-inverting N-channel open drain output ODTXXE## 01, 02, 04, 08, 12, 16, 24 TTL tri-statable non-inverting output ODTXXX## 01, 02, 04, 08, 12, 16, 24 TTL non-inverting output From the piece listings it is noted that this method provides in excess of 1,500 unique pad cell possibilities, some of which may not be feasible or practical. The AMI6x data books and design manuals have more detailed information regarding design implementations using pad pieces. 18 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Clock Driver Pad Cells Name Description IBF1X5 CMOS-level input clock driver IBF7X5 TTL-level input clock driver Name IIF1X5 Description CMOS-level pad clock driver Power Pad Cells Name Description Name Description PP6GXBG VSS power pad for core and pad PP6GXCG VSS power pad for core and input buffer cells only PP6GXBP VDD power pad for core and pad PP6GXPG VSS power pad for output buffers only PP6GXCW Power pad pin for additional bus PP6GXCE ESD protected power pad for use with core signals. No series res. In the interest of maintaining backward compatibility with previous AMI pad cell libraries, all pad cells from the AMI ASIC Standard set are supported through soft cell implementations included with each AMI supported EDA design kit. As an additional feature of the AMI6x pad libraries, AMI physical pad designs are voltage supply independent. With this feature, ASIC designers have the capability of doing mixed supply designs. AMI supports mixed supply designs with a single core supply and one or two supplies in the pad ring (one of which must be the same as the core supply). AMI also supports single pad ring supply designs with an adjustable core supply voltage. Mixed supply designs are advanced features of the AMI6x libraries with more detailed information available in the AMI6x design manual. All ASIC designers should consult the AMI6x data book and design manual to become familiar with ASIC pad cell design using the enhanced AMI pad libraries. Special Pad Cells Name Description Name Description IBCNX3 N-channel differential comparator IBCNH3 N-channel differential comparator with hysteresis IBEXX3 ECL differential comparator IBCPX3 P-channel differential comparator IBCPH3 P-channel differential comparator with hysteresis 19 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Simple Analog Embedded Cells Name POR Description Power-on-reset OP-AMP1 Operational amplifier SB-OSC1 Self biased crystal oscillator VRef 1 Bandgap voltage reference DAC1 Digital to analog converter (8-bit) ADC1 Analog to digital converter (8-bit) PLL1 Phase lock loop COMP1 OD-OSC1 Comparator with rail to rail input range Low power 32 KHz crystal oscillator NOTE 1: The official names, details, and rules of instantiation for these cells will be released upon characterization and model generation. The analog functions are embedded in the corners of each gate array and are available as corner cells in standard cells. Analog functions like the PLL, voltage reference and op-amp are metal or netlist programmable to allow the user more flexibility in their simple analog needs. 20 0.6 micron CMOS Gate Array & Standard Cell Digital ASICs Products and Services November 1995 Packaging The AMI6X family can be packaged in a variety of popular packages. New packages are in development which will extend the package offering. Some special packages or packaging requirements can be supplied if requested. More details on special packages are available from an AMI sales representative. Available Packages ( ) = Lead Package Type time required Pin Count Plastic Quad Flatpack (PQFP) 44, 52, 64, 80, 100, 120, 128, 144, 160, 208, 240, 256, (3041) Thin Quad Flatpack (TQFP) 44, 48, 64, 80, 100, 128, 144, 176 Metal Quad Flatpack (MQUAD(R)) 128, 144, 208 Power Quad 2 (PQ2) 128, 144, 160, 208 Ceramic Quad Flatpack (CQFP) 40, 44, 52, 64, 84, 100, 132, 144, 172, 196 Plastic Leaded Chip Carrier (PLCC) 20, 28, 44, 52, 68, 84 Ceramic Leaded Chip Carrier (JLDCC) 28, 44, 68, 84 Ceramic Leadless Chip Carrier (CLCC) 20, 24, 28, 40, 44, 48, 52, 68, 84 Plastic Pin Grid Array (PPGA) 69, 85, 101, 109, 121, 132, 145, 180 Ceramic Pin Grid Array (CPGA) 65, 68, 69, 84, 85, 101, 109, 121, 132, 145, 155, 177, 181, 208, 225, 257, 299, 476 Ball Grid Array (BGA) (121), (169), (225), (256), (313), (352) Note 1: The 304 pin PowerQuad2 package has an added heat slug to improve power dissipation. 21