©2001 Fairchild Semiconductor Corporation
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A2
File N umber
4886
FSPYC264 R, FSPYC264F
Radiation Hardened, SEGR Resistant
N-Channel Power MOSFETs
Fairchild Star*Power™ Rad Hard
MOSFETs have been specifi cally
developed for hi gh performance
appli cations in a com me rci al or
military space environment. Star*Power MOSFETs offer the
system designer both extremely low rDS(ON) and Gat e
Charge allowing the development of low l oss Power
Subsystems. Star*Powe r FETs combi ne this electrical
capabilit y wit h total dose ra diation har dness up to 300K
RADs whil e maintaining the guaranteed performance for
Singl e Event Effects (SEE) which the F air child FS famili es
have always fe atured.
The Fairchild portfolio of Star*Power FETs includes a family
of devices in various vol tage, current and package styles.
The Star*Power fami ly consists of Star*Power and
Star*Power Gold pr oducts. Star*Power FETs are optimi zed
for total dose and rDS(ON) perfor mance while exhi biti ng SEE
capabilit y at full rated vo lt age up to an LET of 3 7.
Star*Power Gold FETs have been optimized for SEE and
Gate Charge providing SEE performance to 80% of the
rated voltage for an LET of 82 with extremely low gate
charge characteristics.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS)
structure. It is sp ecifical ly designed and processed to be
radiation tol erant. The MOSFET is well sui ted for
applications exposed to radiation environments such as
switching re gulation, switching co nverters, power
distribu ti on, motor drives and rela y dri vers as well as ot her
power control and co nditioning applications. As wit h
conventional MOSFETs these Radi ati on Hardened
MOSFETs offer ease of voltage control, fast switching
speeds and ability to parallel switching devices.
Reliability screening is available as either TXV or Space
equivalent of MIL-S-19500.
Formerly available as type TA45217 W.
Features
45A, 250V, rDS(ON) = 0.04 6
UIS Rated
Total Dose
- Meet s Pre-RAD Specifications to 100K RAD (Si)
- Rated to 300K RAD ( Si)
Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunit y for LET of 36MeV/mg /cm2 with
VDS up to 100% of Rated Breakdown and
VGS of 10V Off-Bias
Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BVDSS
- Typically Survives 2E12 if Current Limited to IAS
Photo Cur rent
- 21nA Per-RAD (Si)/s Typically
Neutron
- Maintain Pre-R AD Specifications
for 1E13 Neu tr ons/cm 2
- Usable to 1E14 Neut rons/cm2
Symbol
Packaging
SMD2
Ordering Information
RAD LEVEL SCREENING LEVEL P ART NUMBER/BRAND
10K Engineering Samples FSP YC264D1
100K TXV FSPYC264R3
100K Space FSPYC264R4
300K TXV FSPYC264F3
300K Space FSPYC264F4
TM
D
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S
June 2001
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Data S heet
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A1
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSPYC264R, FSPYC264F UNITS
Drain to Source Vo ltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS 250 V
Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 250 V
Continuous Drain Current
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID45 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID29 A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 160 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±30 V
Maximum Power Dissipation
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PT208 W
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
T83 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.67 W/oC
Single Pulsed Avala nche Current, L = 100µH (See Test Figure). . . . . . . . . . . . . . . . . . . . . . . . . IAS 85 A
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I S45 A
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM 160 A
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 150 oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
(Distance >0.063in (1.6mm) from Case, 10s Max) 300 oC
Weight (Typical) 3.3(Typical) g
CAUTIO N: S tresses abov e those l is ted in “ A bsolute Max imum R a tings” may cause per manen t dam age to th e de vice. This is a s tress on ly r ating and ope rat ion of th e
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Speci fications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Dr ain to Source Breakdow n Voltage BVDSS ID = 1mA, VGS = 0V 250 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS,
ID = 1mA TC = -55oC--5.5V
TC = 25oC 2.0 - 4.5 V
TC = 125oC1.0--V
Z ero Gat e V ol tage D rai n C urr e nt IDSS VDS = 200V,
VGS = 0V TC = 25oC--25
µA
TC = 125oC--250
µA
Gate to Source Leakage Current IGSS VGS = ±30V TC = 2 5oC - - 100 nA
TC = 125oC - - 200 nA
Drain to Source On-State Voltage VDS(ON) VGS = 12V, ID = 45A - - 2.21 V
Drain to Source On Resistance rDS(ON)12 ID = 29A,
VGS = 12V TC = 25oC - 0.040 0.046
TC = 125oC--0.087
Turn -On Delay Time td(ON) VDD = 12 5V, ID = 45 A,
RL = 2 .8, VGS = 12V,
RGS = 2.35
--35ns
Rise Time tr--70ns
Turn-Off Delay Time td(OFF) --70ns
Fa ll Time tf--15ns
Total Gate Charge Qg(12) VGS = 0V to 12V 125V < VDD < 200
VID = 45A - 115 140 nC
Gate Charge Source Qgs -3545nC
Gate Charge Drain Qgd -3545nC
Gate Charge at 20V Qg(20) VGS = 0V to 20V - 195 - nC
Threshold Gate Charge Qg(TH) VGS = 0V to 2V - 12 - nC
Plateau Voltage V(PLATEAU) ID = 45A, VDS = 15V - 7 - V
Input Capacitance CISS VDS = 25V, VGS = 0V,
f = 1MHz - 6100 - pF
Output Capacitance COSS -875- pF
Reverse Transfer Capacita nce CRSS -35-pF
Thermal Resistance Junction to Case RθJC - - 0.60 oC/W
FS PYC 264R, FS PYC264 F
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A1
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage VSD ISD = 45A - - 1.2 V
Reverse Recovery Time trr ISD = 45A, dISD/dt = 100A/µs - - 590 ns
Reverse Recovery Charge QRR -6.8- µC
Electrical Specification s up to 300K RAD TC = 25oC, Unless O therwise Specified
PARAMET ER SYMBOL TEST CONDITIONS MIN MAX MIN MAX UNITS100K RAD 300K RAD
Drain to Source Breakdown Volts (Note 3) BVDSS VGS = 0, ID = 1mA 250 - 250 - V
Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA 2.0 4.5 1.5 4.5 V
Gate to Body Leakage (Notes 2, 3) IGSS VGS = ±30V, VDS = 0V -100-100nA
Z ero Gat e Leak ag e (Note 3) IDSS VGS = 0, VDS = 200V - 25 - 50 µA
Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = 12V, ID = 45A - 2. 21 2.7 0 V
Dr ain to Source On Re sistance (N otes 1, 3) rDS(ON)12 VGS = 12V, ID = 29A - 0.046 - 0.055
NOTES:
1 . Pulse test, 300µs Ma x .
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = 12V, VDS = 0V and VGS = 0V , VDS = 80% BVDSS.
Single Event Effects (SEB, SEGR) Note 4
TEST SYMBOL
ENVIRONMENT (NOTE 5) APPLIED
VGS BIAS
(V)
(NOTE 7)
MAXIMUM
VDS BIAS (V)
(NOTE 6)
TYPICAL LET
(MeV/mg/cm) TYPICAL RANGE (µ)
Single Event Effects Safe Operating Area SEESOA 37 36 -10 250
37 36 -15 200
60 32 -2 200
60 32 -8 150
82 28 0 150
82 28 -5 100
NOTES:
4. Te sting conducted at Brookhaven National La bs or Texas A& M .
5 . Fl uence = 1E5 ions/cm2 (typical), T = 25oC.
6. Ion Species: LET = 37, Br or Kr; LET = 60, I or Xe; LET = 82, Au.
7. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
Performance Curves
Unless Otherwise Specified
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. TYPICAL SEE SIGNATURE CURVE
120
80
40
00-20
160
LET = 60MeV/mg/cm2, RANGE = 32µ
LET = 37MeV/mg/cm2, RANGE = 36µ
LET = 82MeV/mg/cm2, RANGE = 28µ
VDS (V)
200
240
-4 -8 -12 -16
VGS (V)
TEMP = 25oC
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
280
VDS (V)
LET = 82 GOLD
LET = 60 IODINE
240
200
160
120
80
40
0
-30
0
-5
-15
-20
-25
V
GS
(V)
280
LET = 37 BROMINE
FS PYC 264R, FS PYC264 F
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A1
FIGURE 3. TYPICAL DRAIN INDUCT ANCE REQUIRED T O
LIMIT GAMMA DOT CURRENT TO IAS
FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
FIGURE 5. FORWAR D BIAS SAFE OPERATING AREA FIGURE 6. BASIC GATE CHARGE WAVEFORM
FIGURE 7. TY PICA L NOR MAL IZED rDS(ON) vs JUNCTION
TEMPERATURE FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS
Performance Curves
Unless Otherwise Specified (Continued)
30010010
LIMITING INDUCTANCE (HENRY)
DRAIN SUPPLY (V)
1000
ILM = 10A
300A
1E-4
1E-5
1E-6
30
100A
30A
1E-7
1E-3
ID, DRAIN (A)
TC
, CASE TEMPERATURE (
o
C)
150
100
50
0
-50
0
20
40
30
10
50
100
10
1
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
10 100
0.1
500
ID, DRAIN CURRENT (A)
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
1ms
1000
TC = 25oC
CHARGE
Q
GD
QG
VG
Q
GS
12V
2.5
2.0
1.5
1.0
0.5
0.0-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED rDS(ON)
PULSE DURATION = 250ms, VGS = 12V, ID = 29A
10
86420
200
160
120
80
40
0
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN TO SOURCE CURRENT (A)
V
GS
= 6V
V
GS
= 8V
V
GS
= 10V
V
GS
= 12V
V
GS
= 14V
V
GS
= 6 VOLTS
12
14
DESCENDING ORDER
FS PYC 264R, FS PYC264 F
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A1
FIGURE 9. NORM ALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING
Performance Curves
Unless Otherwise Specified (Continued)
NORMALIZED THERMAL RESPONSE (ZqJC)
t, RECTANGULAR PULSE DURATION (s)
10-5 10-4 10-3 10-2 10-1 100101
SINGLE PULSE
0.01
0.02
0.05
0.1
0.2
0.5
10-3
10-2
10-1
100
101
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
PDM
t1t2
300
100
10
10.01 0.1 1
tAV, TIME IN AVALANCHE (ms)
10
0.001
IAS, AVALANCHE CURRENT (A)
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
IF R = 0
STARTING TJ = 150oC
STARTING TJ = 25oC
IF R 0
Test Circuits and Waveforms
FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 12. UNCLAMPED ENERGY WAVEFORMS
tP
VGS 20V
L
+
-
VDS
VDD
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
50
50
50V-150V
IAS
+
-
ELECTRONIC SWITCH OPENS
WHEN IAS IS REACHED
CURRENT
TRANSFORMER
V
DD
V
DS
BV
DSS
tP
I
AS
t
AV
FS PYC 264R, FS PYC264 F
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A1
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
FIGURE 13. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 14. RESISTIVE SWITCHING WAVEFORMS
Test Circuits and Waveforms
(Continued)
VDS
DUT
RGS
0V
VGS = 12V
VDD
RL
t
d(ON)
tr
90%
10%
V
DS
90%
10%
tf
t
d(OFF)
t
OFF
90%
50%
50%
10%
PULSE WIDTH
V
GS
t
ON
Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified
PARAMET ER SYMBOL TEST CONDITIO NS MAX UNITS
Gate to Source Leakage Current IGSS VGS = ±30V ±20 (Note 7) nA
Z ero Gat e V ol tage D rai n C urr e nt IDSS VDS = 80% Rated Value ±25 (Note 7) µA
Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID±20% (Note 8)
Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 8) V
NOTES:
8. Or 100% of Initial Reading (whichever is greater).
9. Of Initial Reading.
Screenin
g
Information
TEST JANTXV EQUIVAL ENT JANS EQUIVAL ENT
Unclamped Inductive Switching VGS(PEAK) = 20V, L = 0.1mH; Limit = 85A VGS(PEAK) = 20V, L = 0.1mH; Limit = 85A
Thermal Response tH = 10ms; VH = 25V; IH = 4A; LIM IT = 55m V t H = 10ms; VH = 25V; IH = 4A; LIMIT = 55mV
Ga te Stres s VGS = 45V, t = 250µsV
GS = 45V, t = 250µs
Pind Optional Required
Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate
Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
MIL-STD-750, Met hod 1042, Co nditi on B
VGS = 80% of Rated Value,
TA = 150 oC, Time = 48 hours
Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests
and Limits Table All Delta Parameters Listed in the Delta Tests
and Limit s Table
Steady State Reverse
Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 160 hours
MIL-STD-750, Met hod 1042, Co nditi on A
VDS = 80% of Rated Value,
TA = 150 oC, Time = 240 hours
PDA 10% 5%
Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
10. Test limits are identical pre and post burn-in.
Additional Tests
PARAMET ER SYMBOL TEST CONDITIO NS MAX UNITS
Safe Operating Area SOA VDS = 200V, t = 10ms 1.0 A
T he rm al I m pe da nc e VSD tH = 500ms; VH =20V; IH = 4A
HEAT SINK REQUIRED 115 mV
FS PYC 264R, FS PYC264 F
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A1
Rad Hard Data Packages - Fairchild Power Transistors
TXV Equ iv a lent
1. RAD HARD TXV EQUI VALENT - STANDARD DATA
PACKAGE
A. Certificate of Compliance
B. Assembly Flow Chart
C. Pr econditioning - Attributes Data Sheet
D. G r ou p A - Attribute s Dat a She et
E. G roup B - Attr ib utes Dat a Sheet
F. Group C - Attributes Data Sheet
G. Gr ou p D - At t r ib ute s Dat a S he et
2. RAD HARD TXV EQUI VALENT - OPTIONAL DATA
PACKAGE
A. Certificate of Compliance
B. Assembly Flow Chart
C. Pr econditioning - Attributes Data Sheet
- Pre and Post Burn-In Read and Record
Data
D. G r ou p A - Attribute s Dat a She et
E. G roup B - At t ributes Dat a She et
- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup B3)
- Bond Strength Data (Subgroup B3)
- Pre and Post High Temperature Operating
Life Read and Record Data (Subgroup B6)
F. Group C - Attributes Data Sheet
- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup C6)
- Bond Strength Data (Subgroup C6)
G. Gr ou p D - At t r ib ute s Dat a S he et
- Pre and Post RAD Read and Record Data
Class S - Equivalents
1. RAD HARD “S” EQUIVALENT - STANDARD DATA
PACKAGE
A. Certificate of Compliance
B. Serializa tion Records
C. Assembly Flow Cha rt
D. SE M Photos and Report
E. Preconditi oning - At tributes Data Sheet
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
F. Group A - Attributes Data Sheet
G. Gr ou p B - Att r ib utes Dat a Sheet
H. G r ou p C - A tt r ib ute s Dat a S he et
I. Group D - Attributes Data Sheet
2. RAD HARD MAX. “S” EQUIVALENT - O PTIONAL
DATA PACKAGE
A. Certificate of Compliance
B. Serializa tion Records
C. Assembly Flow Cha rt
D. SE M Photos and Report
E. Preconditi oning - At tributes Data Sheet
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X- Ray an d X -R ay Report
F. Group A - Attributes Data Sheet
- Subgroup s A2, A3, A4, A5 and A7 D ata
G. Gr ou p B - Att r ib utes Dat a Sheet
- Subgroup s B1, B3, B4, B5 and B6 D ata
H. G r ou p C - A tt r ib ute s Dat a S he et
- Subgroups C1, C2, C3 and C6 Data
I. Group D - Attributes Data Sheet
- Pr e and P o st R ad ia t io n Da t a
FS PYC 264R, FS PYC264 F
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A1
FS PYC 264R, FS PYC264 F
SMD2
3 PAD CERAMIC LEADLESS CHIP CARRIER
D
A
D1
E1E2
b
D2
E
1
2
3
1 - GATE
2 - SOURCE
3 - DRAIN
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.130 0.142 3.30 3.60 3
b 0.135 0.145 3.43 3.68 -
D 0.520 0.530 13.20 13.46 -
D10.435 0.445 11.05 11.30 -
D20.115 0.125 2.92 3.17 -
E 0.685 0.695 17.40 17.65 -
E10.470 0.480 11.94 12.19 -
E20.152 0.162 3.86 4.11 -
NOTES:
1. No current JEDEC outline for this package.
2. Co ntrolling dimension: I NCH.
3. Measurement prior to pre-solder coating the mounting pads.
4. Revision 3 dated 5-00.
©2001 Fairchild Semiconductor Corporation FSPYC264R, FSPYC264F Rev. A1
FS PYC 264R, FS PYC264 F
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information Formative or In
Design This datasheet contains the design specifications for
product development. Specific ations may chang e in
any manner without notice.
Prelimin ary First Production This datasheet contains prelimina ry data, and
supplementary data will be p ublished at a later date.
Fairchild Semiconduc tor reserves the right to make
changes at any tim e without notice in order to improve
design.
No I denti ficat ion Needed Full Produc tion This datasheet c ontains final spec ifications . Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improv e design.
Obsolete Not In Produc tion This datasheet c ontains specifi c ations on a product
that h as been disc ontinued by Fairchild semi conductor.
The datasheet is printed for reference information only.
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The following ar e registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not int ended to be an exhausti v e list o f all suc h trademarks.
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Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOS™
EnSigna
FACT™
FACT Quiet Series™
FAST®
FASTr™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET
MicroFET™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
PowerTrench™
QFET
QS
QT Opt oelectronics
Quiet S eri es™
SILENT SWITCHER®
SMAR T STA RT
St ar* Po we r
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
UHC™
UltraFET®
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support d evices o r systems are devices or systems
wh ich, (a) a re inten ded for sur gic al im plan t i nto th e bo dy,
or ( b) su pp ort or su st ai n lif e, or ( c) w h os e fai l ure t o pe rfo rm
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reaso nably expected to ca use the failure of the life support
device or system, o r to affect its safety or effe ctiveness.