1
LTC3736-1
37361f
Dual 2-Phase, No RSENSETM,
Synchronous Controller with
Spread Spectrum
Low Noise, 2-Phase, Dual Synchronous DC/DC Step-Down Converter
■
Spread Spectrum Operation
■
Tracking Function
■
No Current Sense Resistors Required
■
Out-of-Phase Controllers Reduce Required
Input Capacitance
■
Wide V
IN
Range: 2.75V to 9.8V
■
Current Mode Operation
■
0.6V ±1.5% Voltage Reference
■
Low Dropout Operation: 100% Duty Cycle
■
Pulse Skipping Operation at Light Loads
■
Internal Soft-Start Circuitry
■
Power Good Output Voltage Monitor
■
Output Overvoltage Protection
■
Micropower Shutdown: I
Q
= 9µA
■
Tiny Low Profile (4mm × 4mm) QFN and Narrow
SSOP Packages
, LTC and LT are registered trademarks of Linear Technology Corporation.
The LTC
®
3736-1 is a 2-phase dual synchronous step-
down switching regulator controller with tracking that
drives external complementary power MOSFETs using
few external components. The constant frequency current
mode architecture with MOSFET V
DS
sensing eliminates
the need for sense resistors and improves efficiency.
Power loss and noise due to the ESR of the input capaci-
tance are minimized by operating the two controllers out
of phase.
A unique spread spectrum architecture randomly varies
the LTC3736-1’s switching frequency from 450kHz to
580kHz, significantly reducing the peak radiated and con-
ducted noise on both the input and output supplies,
making it easier to comply with electromagnetic interfer-
ence (EMI) standards.
Pulse skipping operation provides high efficiency at light
loads. 100% duty cycle capability provides low dropout op-
eration, extending operating time in battery-powered sys-
tems. The high switching frequencies allow for the use of
small surface mount inductors and capacitors.
The LTC3736-1 is available in the low profile (0.75mm)
24-pin thermally enhanced (4mm × 4mm) QFN package
and 24-lead narrow SSOP packages.
No R
SENSE
is a trademark of Linear Technology Corporation.
Protected by U.S. Patents including 5481178, 5929620, 6144194, 6580258, 6304066,
6611131, 6498466.
■
One or Two Lithium-Ion Powered Devices
■
Notebook and Palmtop Computers, PDAs
■
Portable Instruments
■
Distributed DC Power Systems
+
SENSE1
+
V
IN
LTC3736-1
SGND
SENSE2
+
TG1 TG2
SW1 SW2
BG1 BG2
PGND PGND
V
FB1
V
FB2
220pF
V
OUT1
2.5V
V
OUT2
1.8V
47µF
+
47µF
15k
220pF
15k
59k 59k
187k 118k
2.2µH2.2µH
I
TH1
37361 TA01a
I
TH2
10µF
×2
V
IN
2.75V TO 9.8V
410k 450k 490k 530k 570k 610k
SPREAD SPECTRUM
ENABLED
SPREAD SPECTRUM
DISABLED
FREQUENCY (Hz)
–80
AMPLITUDE (dBm)
–20
–10
–90
–100
–30
–60
–40
–50
–70
37361 TA01b
–110
FIGURE 13 CIRCUIT
V
OUT
= 2.5V
R
BW
= 30Hz
Output Voltage Frequency
Spectrum
FEATURES
DESCRIPTIO
U
APPLICATIO S
U
TYPICAL APPLICATIO
U
2
LTC3736-1
37361f
Input Supply Voltage (V
IN
) ........................ –0.3V to 10V
FREQ, RUN/SS, SSDIS,
TRACK, SENSE1
+
, SENSE2
+
,
IPRG1, IPRG2 Voltages ................. –0.3V to (V
IN
+ 0.3V)
V
FB1
, V
FB2
, I
TH1
, I
TH2
Voltages .................. –0.3V to 2.4V
SW1, SW2 Voltages ............ –2V to V
IN
+ 1V or 10V Max
PGOOD ..................................................... –0.3V to 10V
ABSOLUTE AXI U RATI GS
WWWU
(Note 1)
TG1, TG2, BG1, BG2 Peak Output Current (<10µs) ..... 1A
Operating Temperature Range (Note 2) ... –40°C to 85°C
Storage Temperature Range .................. –65°C to 125°C
Junction Temperature (Note 3) ............................ 125°C
Lead Temperature (Soldering, 10 sec)
(LTC3736EGN-1) .................................................. 300°C
PACKAGE/ORDER I FOR ATIO
UU
W
24 23 22 21 20 19
789
TOP VIEW
25
UF PACKAGE
24-LEAD (4mm × 4mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18
ITH1
IPRG2
FREQ
SGND
VIN
TRACK
SSDIS
TG1
PGND
TG2
RUN/SS
BG2
VFB1
IPRG1
SW1
SENSE1+
PGND
BG1
VFB2
ITH2
PGOOD
SW2
SENSE2+
PGND
T
JMAX
= 125°C, θ
JA
= 37°C/W
EXPOSED PAD (PIN 25) IS PGND
MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
GN PACKAGE
24-LEAD PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
SW1
IPRG1
VFB1
ITH1
IPRG2
FREQ
SGND
VIN
TRACK
VFB2
ITH2
PGOOD
SENSE1+
PGND
BG1
SSDIS
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2+
SW2
ORDER PART
NUMBER
UF PART MARKING
3736-1
LTC3736EUF-1
T
JMAX
= 125°C, θ
JA
= 130°C/ W
ORDER PART
NUMBER
LTC3736EGN-1
Consult LTC Marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loops
Input DC Supply Current (Note 4)
Normal Mode 500 850 µA
Shutdown RUN/SS = 0V 9 20 µA
UVLO V
IN
< UVLO Threshold 3 10 µA
Undervoltage Lockout Threshold V
IN
Falling ●1.95 2.25 2.55 V
V
IN
Rising ●2.15 2.45 2.75 V
Shutdown Threshold at RUN/SS 0.45 0.65 0.85 V
Start-Up Current Source RUN/SS = 0V 0.5 0.7 1 µA
Regulated Feedback Voltage 0°C to 85°C (Note 5) 0.591 0.6 0.609 V
–40°C to 85°C●0.588 0.6 0.612 V
Output Voltage Line Regulation 2.75V < V
IN
< 9.8V (Note 5) 0.05 0.2 mV/V
3
LTC3736-1
37361f
ELECTRICAL CHARACTERISTICS
The ● denotes specifications that apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: The LTC3736E-1 is guaranteed to meet specified performance
from 0°C to 70°C. Specifications over the –40°C to 85°C operating range
are assured by design, characterization and correlation with statistical
process controls.
Note 3: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formula:
T
J
= T
A
+ (P
D
• θ
JA
°C/W)
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency.
Note 5: The LTC3736-1 is tested in a feedback loop that servos I
TH
to a
specified voltage and measures the resultant V
FB
voltage.
Note 6: Peak current sense voltage is reduced dependent on duty cycle to
a percentage of value as shown in Figure 2.
PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Voltage Load Regulation I
TH
= 0.9V (Note 5) 0.12 0.5 %
I
TH
= 1.7V –0.12 –0.5 %
V
FB1,2
Input Current (Note 5) 10 50 nA
TRACK Input Current TRACK = 0.6V 10 50 nA
Overvoltage Protect Threshold Measured at V
FB
0.66 0.68 0.7 V
Overvoltage Protect Hysteresis 20 mV
Top Gate (TG) Drive 1, 2 Rise Time C
L
= 3000pF 40 ns
Top Gate (TG) Drive 1, 2 Fall Time C
L
= 3000pF 40 ns
Bottom Gate (BG) Drive 1, 2 Rise Time C
L
= 3000pF 50 ns
Bottom Gate (BG) Drive 1, 2 Fall Time C
L
= 3000pF 40 ns
Maximum Current Sense Voltage IPRG = Floating (Note 6) ●110 125 140 mV
(SENSE
+
– SW)(∆V
SENSE(MAX)
) IPRG = 0V ●70 85 100 mV
IPRG = V
IN
●185 204 223 mV
Soft-Start Time Time for V
FB1
to Ramp from 0.05V to 0.55V 0.667 0.833 1 ms
Spread Spectrum Oscillator
Oscillator Frequency Spread Spectrum Disabled (SSDIS = V
IN
)
V
FREQ
= Floating ●480 550 600 kHz
V
FREQ
= 0V ●260 300 340 kHz
V
FREQ
= V
IN
●650 750 825 kHz
Spread Spectrum Frequency Range SSDIS = GND
Minimum Switching Frequency 450 kHz
Maximum Switching Frequency 580 kHz
PGOOD Output
PGOOD Voltage Low I
PGOOD
Sinking 1mA 125 mV
PGOOD Trip Level V
FB
with Respect to Set Output Voltage
V
FB
< 0.6V, Ramping Positive –13 –10.0 –7 %
V
FB
< 0.6V, Ramping Negative –16 –13.3 –10 %
V
FB
> 0.6V, Ramping Negative 7 10.0 13 %
V
FB
> 0.6V, Ramping Positive 10 13.3 16 %
4
LTC3736-1
37361f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Efficiency and Power Lost vs
Load Current
LOAD CURRENT (mA)
1 100 1000 10000
37361 G01
10
VOUT = 2.5V
VOUT = 1.8V
FIGURE 13 CIRCUIT
VIN = 5V
POWER LOST (W)
1
10
0.01
0.1
0.001
65
EFFICIENCY (%)
95
100
60
55
90
75
85
80
70
50
V
OUT
AC-COUPLED
100mV/DIV
V
IN
= 3.3V
V
OUT
= 1.8V
I
LOAD
= 300mA TO 3A
SSDIS = GND
FIGURE 15 CIRCUIT
100µs/DIV
37361 G02
I
L
2A/DIV
V
OUT
AC-COUPLED
100mV/DIV
V
IN
= 3.3V
V
OUT
= 1.8V
I
LOAD
= 300mA TO 3A
SSDIS = V
IN
FIGURE 15 CIRCUIT
100µs/DIV 37361 G03
I
L
2A/DIV
Load Step
(Spread Spectrum Enabled)
Load Step
(Spread Spectrum Disabled)
Input Voltage Noise
(Spread Spectrum Disabled)
V
IN
= 5V
R
LOAD1
= R
LOAD2
= 1Ω
SSDIS = GND
FIGURE 15 CIRCUIT
200µs/DIV
37361 G06
500mV/
DIV
V
OUT1
2.5V
V
OUT2
1.8V
Input Voltage Noise
(Spread Spectrum Enabled)
Tracking Start-Up with Internal
Soft-Start (CSS = 0µF)
VIN = 5V
RLOAD1 = RLOAD2 = 1Ω
SSDIS = VIN
FIGURE 15 CIRCUIT
40ms/DIV
37361 G07
500mV/
DIV
VOUT1
2.5V
VOUT2
1.8V
INPUT VOLTAGE (V)
2
–5
NORMALIZED FREQUENCY SHIFT (%)
–4
–2
–1
0
5
2
467
37361 G08
–3
3
4
1
35 8910
SSDIS = VIN
Oscillator Frequency
vs Input Voltage
Tracking Start-Up with External
Soft-Start (CSS = 0.15µF)
T
A
= 25°C unless otherwise noted.
FREQUENCY (Hz)
–80
AMPLITUDE (dBm)
–20
–10
–90
–100
–30
–60
–40
–50
–70
410k 450k 490k 530k 570k 610k
37361 G04
–110
FIGURE 13 CIRCUIT
V
IN
= 5V
V
OUT
= 2.5V
R
BW
= 30Hz
SSDIS = V
IN
FREQUENCY (Hz)
–80
AMPLITUDE (dBm)
–20
–10
–90
–100
–30
–60
–40
–50
–70
410k 450k 490k 530k 570k 610k
37361 G05
–110
FIGURE 13 CIRCUIT
V
IN
= 5V
V
OUT
= 2.5V
R
BW
= 30Hz
SSDIS = GND
Output Voltage Ripple
FIGURE 15 CIRCUIT
ENVELOPE OF 100 SAMPLES
1µs/DIV
37361 G20
50mV/DIV
AC-COUPLED
SSDIS = V
IN
CONSTANT
550kHz
OPERATION
SSDIS = GND
SPREAD
SPECTRUM
5
LTC3736-1
37361f
Maximum Current Sense Voltage
vs ITH Pin Voltage
ITH VOLTAGE (V)
0.5
–20
CURRENT LIMIT (%)
0
20
40
60
100
1 1.5
37361 G09
2
80
LOAD CURRENT (mA)
POWER LOST (W)
1
10
0.01
0.1
1 100 1000 10000
37361 G10
0.001
65
EFFICIENCY (%)
95
100
60
55
90
75
85
80
70
50
10
FIGURE 13 CIRCUIT
VOUT = 2.5V
VIN = 5V
VIN = 3.3V
VIN = 4.2V
VIN = 7.2V
Efficiency and Power Lost vs
Load Current
Shutdown (RUN) Threshold
vs Temperature
RUN/SS Pull-Up Current
vs Temperature
TEMPERATURE (°C)
–60
0
RUN/SS VOLTAGE (V)
0.1
0.3
0.4
0.5
1.0
0.7
–20 20 40
37361 G12
0.2
0.8
0.9
0.6
–40 0 60 80 100
TEMPERATURE (°C)
–60
0.4
RUN/SS PULL-UP CURRENT (µA)
0.5
0.6
0.7
0.8
–20 20 60 100
37361 G13
0.9
1.0
–40 0 40 80
Oscillator Frequency
vs Temperature
TEMPERATURE (°C)
–60
–10
NORMALIZED FREQUENCY (%)
–8
–4
–2
0
10
4
–20 20 40
37361 G15
–6
6
8
2
–40 0 60 80 100
SSDIS = V
IN
TEMPERATURE (°C)
–60
INPUT (V
IN
) VOLTAGE (V)
2.30
2.40
100
37361 G16
2.20
2.10 –20 20 60
–40 040 80
2.50
2.25
2.35
2.15
2.45 V
IN
RISING
V
IN
FALLING
Undervoltage Lockout Threshold
vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
T
A
= 25°C unless otherwise noted.
Maximum Current Sense Threshold
vs Temperature
TEMPERATURE (°C)
–60
115
MAXIMUM CURRENT SENSE THRESHOLD (mV)
120
125
130
135
–40 –20 0 20
37361 G14
40 60 80 100
I
PRG
= FLOAT
TEMPERATURE (°C)
–60
FEEDBACK VOLTAGE (V)
0.601
0.603
0.605
100
37361 G11
0.599
0.597
0.591 –20 20 60
–40 040 80
0.595
0.593
0.609
0.607
Regulated Feedback Voltage
vs Temperature
LOAD CURRENT (mA)
65
EFFICIENCY (%)
95
100
60
55
90
75
85
80
70
1 100 1000 10000
37361 G19
50
10
SPREAD SPECTRUM
CONSTANT 550kHz
FIGURE 13 CIRCUIT
V
OUT
= 2.5V
V
IN
= 5V
Efficiency vs Load Current
6
LTC3736-1
37361f
UU
U
PI FU CTIO S
I
TH1
/I
TH2
(Pins 1, 8/Pins 4, 11): Current Threshold and
Error Amplifier Compensation Point. Nominal operating
range on these pins is from 0.7V to 2V. The voltage on
these pins determines the threshold of the main current
comparator.
FREQ (Pin 3/Pin 6): Frequency Filter and Adjust Pin. Nor-
mally, when spread spectrum operation is enabled (SSDIS
= GND), a capacitor (1nF to 4.7nF) is connected from this
pin to SGND or V
IN
to filter and smooth the changes in fre-
quency of the LTC3736-1’s internal oscillator.
When spread spectrum operation is disabled (SSDIS = V
IN
),
this pin serves as a frequency adjust pin. In this mode, tying
this pin to GND selects 300kHz operation; tying this pin to
V
IN
selects 750kHz operation; floating this pin selects
550kHz operation.
When spread spectrum operation is enabled (SSDIS =
GND), an external voltage between approximately 0.7V and
1.5V may be applied to this pin to adjust (in an analog
manner) the LTC3736-1’s frequency.
SGND (Pin 4/Pin 7): Small-Signal Ground. This pin serves
as the ground connection for most internal circuits.
V
IN
(Pin 5/Pin 8): Chip Signal Power Supply. This pin
powers the entire chip except for the gate drivers. Externally
filtering this pin with a lowpass RC network (e.g.,
(UF/GN Package)
R = 10Ω, C = 1µF) is suggested to minimize noise pickup,
especially in high load current applications.
TRACK (Pin 6/Pin 9): Tracking Input for Second Control-
ler. Allows the start-up of V
OUT2
to “track” that of V
OUT1
according to a ratio established by a resistor divider on
V
OUT1
connected to the TRACK pin. For one-to-one track-
ing of V
OUT1
and V
OUT2
during start-up, a resistor divider
with a ratio equal to those connected to V
FB2
from V
OUT2
should be used to connect to TRACK from V
OUT1
.
PGOOD(Pin 9/Pin 12): Power Good Output Voltage Moni-
tor Open-Drain Logic Output. This pin is pulled to ground
when the voltage on either feedback pin (V
FB1
, V
FB2
) is not
within ±13.3% of its nominal set point.
PGND (Pins 12, 16, 20, 25/Pins 15, 19, 23): Power Ground.
These pins serve as the ground connection for the gate
drivers and the negative input to the reverse current com-
parators. The Exposed Pad (UF package) must be soldered
to PCB ground.
RUN/SS (Pin 14/Pin 17): Run Control Input and Optional
External Soft-Start Input. Forcing this pin below 0.65V shuts
down the chip (both channels). Driving this pin to V
IN
or
releasing this pin enables the chip, using the chip’s inter-
nal soft-start. An external soft-start can be programmed by
connecting a capacitor between this pin and ground.
Shutdown Quiescent Current
vs Input Voltage
INPUT VOLTAGE (V)
2
0
SHUTDOWN CURRENT (µA)
2
6
8
10
20
14
467
37361 G17
4
16
18
12
35 8910
RUN/SS = 0V
RUN/SS Start-Up Current
vs Input Voltage
INPUT VOLTAGE (V)
2
RUN/SS PIN PULL-UP CURRENT (µA)
0.5
0.6
0.7
10
37361 G18
0.4
0.3
0
0.1
468
3579
0.2
0.9
0.8
RUN/SS = 0V
TYPICAL PERFOR A CE CHARACTERISTICS
UW
T
A
= 25°C unless otherwise noted.
7
LTC3736-1
37361f
FU CTIO AL DIAGRA
UU
W
–
+
–
+
–
+
SHDN
0.6V
V
REF
EXTSS
0.7µA
CLK1
CLK2
0.54V
V
FB1
V
FB2
SLOPE1
SLOPE2
RUN/SS
V
IN
C
VIN
V
IN
(TO CONTROLLER 1, 2)
R
VIN
SSDIS
FREQ
UNDERVOLTAGE
LOCKOUT
SPREAD
SPECTRUM
OSCILLATOR
SLOPE
COMP
VOLTAGE
REFERENCE
t
SEC
= 1ms
INTSS
IPROG1
IPROG2
IPRG1
IPRG2
VOLTAGE
CONTROLLED
OSCILLATOR
MAXIMUM
SENSE VOLTAGE
SELECT
PGOOD
SHDN
OV1
UV1
UV2 OV2
37361 FD
(Common Circuitry)
TG1/TG2 (Pins 17, 15/Pins 20, 18): Top (PMOS) Gate Drive
Output. These pins drive the gates of the external P-channel
MOSFETs. These pins have an output swing from PGND to
SENSE
+
.
SSDIS (Pin 18/Pin 21): Spread Spectrum Disable Input. Tie
this pin to V
IN
to disable spread spectrum operation. In this
mode, the LTC3736-1 operates at a constant frequency
determined by the voltage on the FREQ pin. Tie this pin to
GND to enable spread spectrum operation.
BG1/BG2 (Pins 19, 13/Pins 22, 16): Bottom (NMOS) Gate
Drive Output. These pins drive the gates of the external N-
channel MOSFETs. These pins have an output swing from
PGND to SENSE
+
.
SENSE1
+
/SENSE2
+
(Pins 21, 11/Pins 24, 14): Positive
Input to Differential Current Comparator. Also powers the
gate drivers. Normally connected to the source of the ex-
ternal P-channel MOSFET.
SW1/SW2 (Pins 22, 10/Pins 1, 13): Switch Node Connec-
tion to Inductor. Also the negative input to differential peak
current comparator and an input to the reverse current
comparator. Normally connected to the drain of the exter-
nal P-channel MOSFETs, the drain of the external N-channel
MOSFET and the inductor.
IPRG1/IPRG2 (Pins 23, 2/Pins 2, 5): Three-State Pins to
Select Maximum Peak Sense Voltage Threshold. These pins
select the maximum allowed voltage drop between the
SENSE
+
and SW pins (i.e., the maximum allowed drop
across the external P-channel MOSFET) for each channel.
Tie to V
IN
, GND or float to select 204mV, 85mV or 125mV
respectively.
V
FB1
/V
FB2
(Pins 24, 7/Pins 3, 10): Feedback Pins. Receives
the remotely sensed feedback voltage for its controller from
an external resistor divider across the output.
Exposed Pad (Pin 25/NA): The exposed pad (UF Package)
must be soldered to the PCB ground.
UU
U
PI FU CTIO S
(UF/GN Package)
8
LTC3736-1
37361f
FU CTIO AL DIAGRA
UU
W
Q
OV1
CLK1
SC1
SKIP1
SLOPE1
SW1
SENSE1+
IREV1
S
R
RS1
ANTISHOOT
THROUGH
PGND
TG1
SENSE1+
VIN
VOUT1
CIN
COUT1
MP1
MN1
BG1
R1B
L1
PGND
VFB1
ITH1
RITH1
CITH1
0.6V
0.12V
SC1
VFB1
SW1
SENSE1+
R1A
–
+
–
+
EXTSS
INTSS
EAMP
SHDN
–
+
SKIP1
IPROG1
–
+
ICMP
0.15V
–
+
VFB1
OV1
0.68V
–
+
PGND
IREV1
IPROG1
SW1
37361 CONT1
–
+
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
SCP
RICMPOVP
(Controller 1)
9
LTC3736-1
37361f
FU CTIO AL DIAGRA
UU
W
(Controller 2)
Q
OV2
CLK2
SC2
SKIP2
SLOPE2
SW2
SENSE2+
SHDN
IREV2
S
R
RS2
ANTISHOOT
THROUGH
PGND
SENSE2+
TG2
SENSE2+VIN
VOUT2
COUT2
MP2
MN2
BG2
R2B
RTRACKB
RTRACKA
L2
PGND
VFB2
ITH2
TRACK
RITH2
CITH2
0.6V
0.12V
SC2
TRACK
VFB2
SW2
R2A
VOUT1
–
+
–
+
EAMP
–
+
SKIP2
–
+
ICMP
0.15V
–
+
VFB2
OV2
0.68V
–
+
PGND
IREV2
IPROG2
SW2
37361 CONT2
–
+
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
OVP
SCP
10
LTC3736-1
37361f
Main Control Loop
The LTC3736-1 uses a current mode architecture with the
two controllers operating 180 degrees out of phase.
During normal operation, the top external P-channel power
MOSFET is turned on when the clock for that channel sets
the RS latch, and turned off when the current comparator
(I
CMP
) resets the latch. The peak inductor current at which
I
CMP
resets the RS latch is determined by the voltage on
the I
TH
pin, which is driven by the output of the error
amplifier (EAMP). The V
FB
pin receives the output voltage
feedback signal from an external resistor divider. This
feedback signal is compared to the internal 0.6V reference
voltage by the EAMP. When the load current increases, it
causes a slight decrease in V
FB
relative to the 0.6V refer-
ence, which in turn causes the I
TH
voltage to increase until
the average inductor current matches the new load cur-
rent. While the top P-channel MOSFET is off, the bottom
N-channel MOSFET is turned on until either the inductor
current starts to reverse, as indicated by the current
reversal comparator, I
RCMP
, or the beginning of the next
cycle.
Shutdown, Soft-Start and Tracking Start-Up
(RUN/SS and TRACK Pins)
The LTC3736-1 is shut down by pulling the RUN/SS pin
low. In shutdown, all controller functions are disabled and
the chip draws only 9µA. The TG outputs are held high (off)
and the BG outputs low (off) in shutdown. Releasing
RUN/SS allows an internal 0.7µA current source to charge
up the RUN/SS pin. When the RUN/SS pin reaches 0.65V,
the LTC3736-1’s two controllers are enabled.
The start-up of V
OUT1
is controlled by the LTC3736-1’s
internal soft-start. During soft-start, the error amplifier
EAMP compares the feedback signal V
FB1
to the internal
soft-start ramp (instead of the 0.6V reference), which rises
linearly from 0V to 0.6V in about 1ms. This allows the
output voltage to rise smoothly from 0V to its final value,
while maintaining control of the inductor current.
The 1ms soft-start time can be increased by connecting
the optional external soft-start capacitor C
SS
between the
RUN/SS and SGND pins. As the RUN/SS pin continues to
rise linearly from approximately 0.65V to 1.3V (being
OPERATIO
U
charged by the internal 0.7µA current source), the EAMP
regulates the V
FB1
proportionally linearly from 0V to 0.6V.
The start-up of V
OUT2
is controlled by the voltage on the
TRACK pin. When the voltage on the TRACK pin is less
than the 0.6V internal reference, the LTC3736-1 regulates
the V
FB2
voltage to the TRACK pin instead of the 0.6V
reference. Typically, a resistor divider on V
OUT1
is con-
nected to the TRACK pin to allow the start-up of V
OUT2
to
“track” that of V
OUT1
. For one-to-one tracking during start-
up, the resistor divider would have the same ratio as the
divider on V
OUT2
that is connected to V
FB2
.
Light Load Operation
The LTC3736-1 operates in PWM pulse skipping mode at
light loads. In this mode, the current comparator I
CMP
may
remain tripped for several cycles and force the external P-
channel MOSFET to stay off for the same number of cycles.
The inductor current is not allowed to reverse (discontinu-
ous operation). This mode exhibits low output ripple as
well as low audio noise and reduced RF interference, while
providing high light load efficiency.
Spread Spectrum Operation
Switching regulators can be particularily troublesome in
applications where electromagnetic interference (EMI) is
a concern. Switching regulators operate on a cycle-by-
cycle basis to transfer power to an output. In most cases,
the frequency of operation is either fixed or is a constant
based on the output load. This method of conversion
creates large components of noise at the frequency of
operation (fundamental) and multiples of the operating
frequency (harmonics). Figures 1a and 1b depict the
output noise spectrum of a conventional buck switching
converter (1/2 of LTC3736-1 with spread spectrum opera-
tion disabled) with V
IN
= 5V, V
OUT
= 2.5V and I
OUT
= 2A.
Unlike conventional buck converters, the LTC3736-1’s
internal oscillator is designed to produce a clock pulse
whose frequency is randomly varied between 450kHz and
580kHz. This has the benefit of spreading the switching
noise over a range of frequencies, thus significantly reduc-
ing the peak noise. Figures 1c and 1d show the output
noise spectrum of the LTC3736-1 (with spread spectrum
(Refer to Functional Diagram)
11
LTC3736-1
37361f
FREQUENCY (Hz)
–80
AMPLITUDE (dBm)
–20
–10
–90
–100
–30
–60
–40
–50
–70
0 6M 12M 18M 24M 30M
37361 F01a
–110
R
BW
= 3kHz
OPERATIO
U
(Refer to Functional Diagram)
operation enabled) with V
IN
= 5V, V
OUT
= 2.5V and I
OUT
=
1A. Note the significant reduction in peak output noise
(>20dBm).
Short-Circuit Protection
When an output is shorted to ground (V
FB
< 0.12V), the
switching frequency of that controller is reduced to 1/5 of
the normal operating frequency. The other controller is
unaffected and maintains normal operation.
The short-circuit threshold on V
FB2
is based on the smaller
of 0.12V and a fraction of the voltage on the TRACK pin.
This also allows V
OUT2
to start up and track V
OUT1
more
easily. Note that if V
OUT1
is truly short-circuited
(V
OUT1
= V
FB1
= 0V), then the LTC3736-1 will try to
regulate V
OUT2
to 0V if a resistor divider on V
OUT1
is
connected to the TRACK pin.
Figure 1a. Output Noise Spectrum of Conventional Buck
Switching Converter (LTC3736-1 with Spread Spectrum
Disabled) Showing Fundamental and Harmonic Frequencies
FREQUENCY (Hz)
–80
AMPLITUDE (dBm)
–20
–10
–90
–100
–30
–60
–40
–50
–70
37361 F01b
–110
R
BW
= 30Hz
410k 450k 490k 530k 570k 610k
Figure 1b. Zoom-In of Fundamental Frequency of Conventional
Buck Switching Converter
FREQUENCY (Hz)
–80
AMPLITUDE (dBm)
–20
–10
–90
–100
–30
–60
–40
–50
–70
0 6M 12M 18M 24M 30M
37361 F01c
–110
R
BW
= 3kHz
Figure 1c. Output Noise Spectrum of the LTC3736-1 Spread
Spectrum Buck Switching Converter. Note the Reduction in
Fundamental and Harmonic Peak Spectral Amplitude
Compared to Figure 1a.
FREQUENCY (Hz)
–80
AMPLITUDE (dBm)
–20
–10
–90
–100
–30
–60
–40
–50
–70
37361 F01d
–110
R
BW
= 30Hz
410k 450k 490k 530k 570k 610k
Figure 1d. Zoom-In of Fundamental Frequency of the
LTC3736-1 Spread Spectrum Switching Converter. Note the
>20dB Reduction in Peak Amplitude and Spreading of the
Frequency Spectrum (Between Approximately 450kHz and
580kHz) Compared to Figure 1b.
Output Overvoltage Protection
As a further protection, the overvoltage comparator (OV)
guards against transient overshoots, as well as other more
serious conditions that may overvoltage the output. When
the feedback voltage on the V
FB
pin has risen 13.33%
above the reference voltage of 0.6V, the external P-chan-
nel MOSFET is turned off and the N-channel MOSFET is
turned on until the overvoltage is cleared.
Frequency Selection (FREQ Pin)
(Spread Spectrum Operation Disabled)
The switching frequency of the LTC3736-1 can be selected
using the FREQ pin when spread spectrum operation is
disabled (SSDIS = V
IN
).
12
LTC3736-1
37361f
OPERATIO
U
(Refer to Functional Diagram)
The FREQ pin can be floated, tied to V
IN
or tied to SGND to
select 550kHz, 750kHz or 300kHz respectively.
The selection of switching frequency is a tradeoff between
efficiency and component size. Low frequency operation
increases efficiency by reducing MOSFET switching losses,
but requires larger inductance and/or capacitance to main-
tain low output ripple voltage.
Dropout Operation
When the input supply voltage (V
IN
) decreases towards
the output voltage, the rate of change of the inductor
current while the external P-channel MOSFET is on (ON
cycle) decreases. This reduction means that the P-channel
MOSFET will remain on for more than one oscillator cycle
if the inductor current has not ramped up to the threshold
set by the EAMP on the I
TH
pin. Further reduction in the
input supply voltage will eventually cause the P-channel
MOSFET to be turned on 100%; i.e., DC. The output
voltage will then be determined by the input voltage minus
the voltage drop across the P-channel MOSFET and the
inductor.
Undervoltage Lockout
To prevent operation of the external MOSFETs below safe
input voltage levels, an undervoltage lockout is incorporated
in the LTC3736-1. When the input supply voltage (V
IN
)
drops below 2.3V, the external P- and N-channel MOSFETs
and all internal circuitry are turned off except for the und-
ervoltage block, which draws only a few microamperes.
Peak Current Sense Voltage Selection and Slope
Compensation (IPRG1 and IPRG2 Pins)
When a controller is operating below 20% duty cycle, the
peak current sense voltage (between the SENSE
+
and SW
pins) allowed across the external P-channel MOSFET is
determined by:
∆=
()
VAV V
SENSE MAX ITH
()
–.07
10
where A is a constant determined by the state of the IPRG
pins. Floating the IPRG pin selects A = 1; tying IPRG to V
IN
selects A = 5/3; tying IPRG to SGND selects A = 2/3. The
maximum value of V
ITH
is typically about 1.98V, so the
maximum sense voltage allowed across the external
P-channel MOSFET is 125mV, 85mV or 204mV for the
three respective states of the IPRG pin. The peak sense
voltages for the two controllers can be independently
selected by the IPRG1 and IPRG2 pins.
However, once the controller’s duty cycle exceeds 20%,
slope compensation begins and effectively reduces the
peak sense voltage by a scale factor given by the curve in
Figure 2.
DUTY CYCLE (%)
10
SF = I/I
MAX
(%)
60
80
110
100
90
37361 F02
40
20
50
70
90
30
10
030 50 70
200 40 60 80 100
Figure 2. Maximum Peak Current vs Duty Cycle
The peak inductor current is determined by the peak sense
voltage and the on-resistance of the external P-channel
MOSFET:
IV
R
PK SENSE MAX
DS ON
=∆
()
()
Power Good (PGOOD) Pin
A window comparator monitors both feedback voltages
and the open-drain PGOOD output pin is pulled low when
either or both feedback voltages are not within ±10% of
the 0.6V reference voltage. PGOOD is low when the
LTC3736-1 is shut down or in undervoltage lockout.
2-Phase Operation
Why the need for 2-phase operation? Until recently, con-
stant frequency dual switching regulators operated both
controllers in phase (i.e., single phase operation). This
means that both topside MOSFETs (P-channel) are turned
13
LTC3736-1
37361f
OPERATIO
U
(Refer to Functional Diagram)
Figure 3. Example Waveforms for a Single Phase
Dual Controller vs the 2-Phase LTC3736-1
Single Phase
Dual Controller
2-Phase
Dual Controller
SW1 (V)
SW2 (V)
I
L1
I
L2
I
IN
37361 F03
INPUT VOLTAGE (V)
2
0
INPUT CAPACITOR RMS CURRENT
0.2
0.6
0.8
1.0
2.0
1.4
467
37361 F04
0.4
1.6
1.8
1.2
35 8910
SINGLE PHASE
DUAL CONTROLLER
2-PHASE
DUAL CONTROLLER
V
OUT1
= 2.5V/2A
V
OUT2
= 1.8V/2A
Figure 4. RMS Input Current Comparison
on at the same time, causing current pulses of up to twice
the amplitude of those from a single regulator to be drawn
from the input capacitor. These large amplitude pulses
increase the total RMS current flowing in the input capaci-
tor, requiring the use of larger and more expensive input
capacitors, and increase both EMI and power losses in the
input capacitor and input power supply.
With 2-phase operation, the two controllers of the
LTC3736-1 are operated 180 degrees out of phase. This
effectively interleaves the current pulses coming from the
topside MOSFET switches, greatly reducing the time where
they overlap and add together. The result is a significant
reduction in the total RMS current, which in turn allows the
use of smaller, less expensive input capacitors, reduces
shielding requirements for EMI and improves real world
operating efficiency.
Figure 3 shows qualitatively example waveforms for a
single phase dual controller versus a 2-phase LTC3736-1
system. In this case, 2.5V and 1.8V outputs, each drawing
a load current of 2A, are derived from a 7V (e.g., a 2-cell
Li-Ion battery) input supply. In this example, 2-phase
operation would reduce the RMS input capacitor current
from 1.79A
RMS
to 0.91A
RMS
. While this is an impressive
reduction by itself, remember that power losses are pro-
portional to I
RMS2
, meaning that actual power wasted is
reduced by a factor of 3.86.
The reduced input ripple current also means that less
power is lost in the input power path, which could include
batteries, switches, trace/connector resistances, and pro-
tection circuitry. Improvements in both conducted and
radiated EMI also directly accrue as a result of the reduced
RMS input current and voltage. Significant cost and board
footprint savings are also realized by being able to use
smaller, less expensive, lower RMS current-rated input
capacitors.
Of course, the improvement afforded by 2-phase opera-
tion is a function of the relative duty cycles of the two
controllers, which in turn are dependent upon the input
supply voltage. Figure 4 depicts how the RMS input
current varies for single phase and 2-phase dual control-
lers with 2.5V and 1.8V outputs over a wide input voltage
range.
It can be readily seen that the advantages of 2-phase
operation are not limited to a narrow operating range, but
in fact extend over a wide region. A good rule of thumb for
most applications is that 2-phase operation will reduce the
input capacitor requirement to that for just one channel
operating at maximum current and 50% duty cycle.
14
LTC3736-1
37361f
The typical LTC3736-1 application circuit is shown in
Figure 13. External component selection for each of the
LTC3736-1’s controllers is driven by the load requirement
and begins with the selection of the inductor (L) and the
power MOSFETs (MP and MN).
Power MOSFET Selection
Each of the LTC3736-1’s two controllers requires two
external power MOSFETs: a P-channel MOSFET for the
topside (main) switch and an N-channel MOSFET for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the breakdown voltage V
BR(DSS)
,
threshold voltage V
GS(TH)
, on-resistance R
DS(ON)
, reverse
transfer capacitance C
RSS
, turn-off delay t
D(OFF)
and the
total gate charge Q
G
.
The gate drive voltage is the input supply voltage. Since the
LTC3736-1 is designed for operation down to low input
voltages, a sublogic level MOSFET (R
DS(ON)
guaranteed at
V
GS
= 2.5V) is required for applications that work close to
this voltage. When these MOSFETs are used, make sure
that the input supply to the LTC3736-1 is less than the
absolute maximum MOSFET V
GS
rating, which is
typically 8V.
The P-channel MOSFET’s on-resistance is chosen based
on the required load current. The maximum average
output load current I
OUT(MAX)
is equal to the peak inductor
current minus half the peak-to-peak ripple current I
RIPPLE
.
The LTC3736-1’s current comparator monitors the drain-
to-source voltage V
DS
of the P-channel MOSFET, which is
sensed between the SENSE
+
and SW pins. The peak
inductor current is limited by the current threshold, set by
the voltage on the I
TH
pin of the current comparator. The
voltage on the I
TH
pin is internally clamped, which limits
the maximum current sense threshold ∆V
SENSE(MAX)
to
approximately 125mV when IPRG is floating (85mV when
IPRG is tied low; 204mV when IPRG is tied high).
The output current that the LTC3736-1 can provide is
given by:
IV
R
I
OUT MAX SENSE MAX
DS ON
RIPPLE
() ()
()
–=∆
2
A reasonable starting point is setting ripple current I
RIPPLE
to be 40% of I
OUT(MAX)
. Rearranging the above equation
yields:
RV
I
DS ON MAX SENSE MAX
OUT MAX
()( ) ()
()
•=∆
5
6
for Duty Cycle < 20%.
However, for operation above 20% duty cycle, slope
compensation has to be taken into consideration to select
the appropriate value of R
DS(ON)
to provide the required
amount of load current:
RSF
V
I
DS ON MAX SENSE MAX
OUT MAX
()( ) ()
()
••=∆
5
6
where SF is a scale factor whose value is obtained from the
curve in Figure 1.
These must be further derated to take into account the
significant variation in on-resistance with temperature.
The following equation is a good guide for determining the
required R
DS(ON)MAX
at 25°C (manufacturer’s specifica-
tion), allowing some margin for variations in the
LTC3736-1 and external component values:
RSF
V
I
DS ON MAX SENSE MAX
OUT MAX T
()( ) ()
()
•.• • •
=∆
5
609 ρ
The ρ
T
is a normalizing term accounting for the tempera-
ture variation in on-resistance, which is typically about
0.4%/°C, as shown in Figure 5. Junction to case tempera-
ture T
JC
is about 10°C in most applications. For a maxi-
mum ambient temperature of 70°C, using ρ
80°C
~ 1.3 in
the above equation is a reasonable choice.
The power dissipated in the top and bottom MOSFETs
strongly depends on their respective duty cycles and load
current. When the LTC3736-1 is operating in continuous
mode, the duty cycles for the MOSFETs are:
TopP ChannelDuty Cycle V
V
BottomN ChannelDuty Cycle VV
V
OUT
IN
IN OUT
IN
− =
− =
–
APPLICATIO S I FOR ATIO
WUUU
15
LTC3736-1
37361f
The MOSFET power dissipations at maximum output
current are:
PV
VIRV
ICf
PVV
VIR
TOP OUT
IN OUT MAX T DS ON IN
OUT MAX RSS OSC
BOT IN OUT
IN OUT MAX T DS ON
=+
=
••• •
•••
–•••
() ()
()
() ()
22
2
2ρ
ρ
Both MOSFETs have I
2
R losses and the P
TOP
equation
includes an additional term for transition losses, which are
largest at high input voltages. The bottom MOSFET losses
are greatest at high input voltage or during a short circuit
when the bottom duty cycle is nearly 100%.
The LTC3736-1 utilizes a nonoverlapping, antishoot-
through gate drive control scheme to ensure that the P-
and N-channel MOSFETs are not turned on at the same
time. To function properly, the control scheme requires
that the MOSFETs used are intended for DC/DC switching
applications. Many power MOSFETs, particularly P-chan-
nel MOSFETs, are intended to be used as static switches
and therefore are slow to turn on or off.
Reasonable starting criteria for selecting the P-channel
MOSFET are that it must typically have a gate charge (Q
G
)
less than 25nC to 30nC (at 4.5V
GS
) and a turn-off delay
(t
D(OFF)
) of less than approximately 140ns. However, due
to differences in test and specification methods of various
MOSFET manufacturers, and in the variations in Q
G
and
t
D(OFF)
with gate drive (V
IN
) voltage, the P-channel MOSFET
ultimately should be evaluated in the actual LTC3736-1
application circuit to ensure proper operation.
Shoot-through between the P-channel and N-channel
MOSFETs can most easily be spotted by monitoring the
input supply current. As the input supply voltage in-
creases, if the input supply current increases dramatically,
then the likely cause is shoot-through. Note that some
MOSFETs that do not work well at high input voltages (e.g.,
V
IN
> 5V) may work fine at lower voltages (e.g., 3.3V).
Table 1 shows a selection of P-channel MOSFETs from
different manufacturers that are known to work well in
LTC3736-1 applications.
Selecting the N-channel MOSFET is typically easier, since
for a given R
DS(ON)
, the gate charge and turn-on and turn-
off delays are much smaller than for a P-channel MOSFET.
Table 1. Selected P-Channel MOSFETs Suitable for LTC3736-1
Applications
PART
NUMBER MANUFACTURER TYPE PACKAGE
Si7540DP Siliconix Complementary PowerPak
P/N SO-8
Si9801DY Siliconix Complementary SO-8
P/N
FDW2520C Fairchild Complementary TSSOP-8
P/N
FDW2521C Fairchild Complementary TSSOP-8
P/N
Si3447BDV Siliconix Single P TSOP-6
Si9803DY Siliconix Single P SO-8
FDC602P Fairchild Single P TSOP-6
FDC606P Fairchild Single P TSOP-6
FDC638P Fairchild Single P TSOP-6
FDW2502P Fairchild Dual P TSSOP-8
FDS6875 Fairchild Dual P SO-8
HAT1054R Hitachi Dual P SO-8
NTMD6P02R2-D On Semi Dual P SO-8
APPLICATIO S I FOR ATIO
WUUU
JUNCTION TEMPERATURE (°C)
–50
ρT
NORMALIZED ON RESISTANCE
1.0
1.5
150
37361 F05
0.5
0050 100
2.0
Figure 5. RDS(ON) vs Temperature
16
LTC3736-1
37361f
Operating Frequency
When spread spectrum operation is enabled (SSDIS =
GND), the frequency of the LTC3736-1 is randomly varied
over the range of frequencies between 450kHz and 580kHz.
In this case, a capacitor (1nF to 4.7nF) should be connected
between the FREQ pin and SGND (or V
IN
) to smooth out the
changes in frequency. This not only provides a smoother
frequency spectrum but also ensures that the switching
regulator remains stable by preventing abrupt changes
in frequency. A value of 2200pF is suitable in most
applications.
When the spread spectrum operation is disabled (SSDIS =
V
IN
), the LTC3736-1’s frequency may be selected from
among three discrete, constant frequencies using the FREQ
pin. Floating the FREQ pin selects 550kHz operation; tying
this pin to V
IN
selects 750kHz, while tying this pin to GND
selects 300kHz. Table 2 summarizes the different states in
which the FREQ pin can be used.
Table 2
FREQ PIN SSDIS PIN FREQUENCY
0V V
IN
300kHz
Floating V
IN
550kHz
V
IN
V
IN
750kHz
Capacitor to GND GND Spread Spectrum (450kHz to 580kHz)
or V
IN
Note that when spread spectrum operation is disabled, the
LTC3736-1 operates like the standard, constant frequency
LTC3736, except that at light loads, the LTC3736-1 oper-
ates in pulse skipping mode. This mode is not available on
the LTC3736 unless the device is synchronized to an ex-
ternal clock signal using its phase-locked loop (PLL). Thus,
if an LTC3736 with pulse skipping function is needed, then
the LTC3736-1 with spread spectrum disabled is the appro-
priate solution. Table 3 summarizes the key differences in
the available features on the LTC3736 and LTC3736-1.
Table 3
AVAILABLE FEATURES/OPTIONS LTC3736 LTC3736-1
Selectable Constant Frequency Yes Yes
Spread Spectrum No Yes
Synchronizable (PLL) Yes No
Burst Mode®Yes No
Forced Continuous Mode Yes No
Pulse Skipping Mode When Synchronized Yes
Inductor Value Calculation
Given the desired input and output voltages, the inductor
value and operating frequency f
OSC
directly determine the
inductor’s peak-to-peak ripple current:
IV
V
VV
fL
RIPPLE OUT
IN
IN OUT
OSC
=⎛
⎝
⎜⎞
⎠
⎟
–
•
Lower ripple current reduces core losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Thus, highest efficiency operation is obtained at
low frequency with a small ripple current. Achieving this,
however, requires a large inductor.
A reasonable starting point is to choose a ripple current
that is about 40% of I
OUT(MAX)
. Note that the largest ripple
current occurs at the highest input voltage. To guarantee
that ripple current does not exceed a specified maximum,
the inductor should be chosen according to:
LVV
fI
V
V
IN OUT
OSC RIPPLE
OUT
IN
≥–
••
Inductor Core Selection
Once the inductance value is determined, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of ferrite, molyper-
malloy or Kool Mµ
®
cores. Actual core loss is independent
of core size for a fixed inductor value, but it is very
dependent on inductance selected. As inductance in-
creases, core losses go down. Unfortunately, increased
inductance requires more turns of wire and therefore
copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
APPLICATIO S I FOR ATIO
WUUU
Burst Mode is a registered trademark of Linear Technology Corporation.
Kool Mµ is a registered trademark of Magnetics, Inc.
17
LTC3736-1
37361f
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive
than ferrite. A reasonable compromise from the same
manufacturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire.
Because they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Schottky Diode Selection (Optional)
The Schottky diodes D1 and D2 in Figure 15 conduct
current during the dead time between the conduction of
the power MOSFETs . This prevents the body diode of the
bottom N-channel MOSFET from turning on and storing
charge during the dead time, which could cost as much as
1% in efficiency. A 1A Schottky diode is generally a good
size for most LTC3736-1 applications, since it conducts a
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance. This diode may be omitted if the efficiency
loss can be tolerated.
C
IN
and C
OUT
Selection
The selection of C
IN
is simplified by the 2-phase architec-
ture and its impact on the worst-case RMS current drawn
through the input network (battery/fuse/capacitor). It can
be shown that the worst-case capacitor RMS current
occurs when only one controller is operating. The control-
ler with the highest (V
OUT
)(I
OUT
) product needs to be used
in the formula below to determine the maximum RMS
capacitor current requirement. Increasing the output cur-
rent drawn from the other controller will actually decrease
the input RMS ripple current from its maximum value. The
out-of-phase technique typically reduces the input
capacitor’s RMS ripple current by a factor of 30% to 70%
when compared to a single phase power supply solution.
In continuous mode, the source current of the P-channel
MOSFET is a square wave of duty cycle (V
OUT
)/(V
IN
). To
prevent large voltage transients, a low ESR capacitor sized
for the maximum RMS current of one channel must be
used. The maximum RMS capacitor current is given by:
C quiredI I
VVVV
IN RMS MAX
IN OUT IN OUT
Re – /
≈
()( )
[]
12
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT
/2. This simple worst-case condition is commonly
used for design because even significant deviations do not
offer much relief. Note that capacitor manufacturers’
ripple current ratings are often based on only 2000 hours
of life. This makes it advisable to further derate the
capacitor, or to choose a capacitor rated at a higher
temperature than required. Several capacitors may be
paralleled to meet size or height requirements in the
design. Due to the high operating frequency of the
LTC3736-1, ceramic capacitors can also be used for C
IN
.
Always consult the manufacturer if there is any question.
The benefit of the LTC3736-1 2-phase operation can be
calculated by using the equation above for the higher power
controller and then calculating the loss that would have
resulted if both controller channels switched on at the
same time. The total RMS power lost is lower when both
controllers are operating due to the reduced overlap of
current pulses required through the input capacitor’s ESR.
This is why the input capacitor’s requirement calculated
above for the worst-case controller is adequate for the
dual controller design. Also, the input protection fuse re-
sistance, battery resistance, and PC board trace resistance
losses are also reduced due to the reduced peak currents
in a 2-phase system. The overall benefit of a multiphase
design will only be fully realized when the source imped-
ance of the power supply/battery is included in the effi-
ciency testing. The sources of the P-channel MOSFETs
should be placed within 1cm of each other and share a
common C
IN
(s). Separating the sources and C
IN
may pro-
duce undesirable voltage and current resonances at V
IN
.
A small (0.1µF to 1µF) bypass capacitor between the chip
V
IN
pin and ground, placed close to the LTC3736-1, is also
suggested. A 10Ω resistor placed between C
IN
(C1) and
the V
IN
pin provides further isolation between the two
channels.
The selection of C
OUT
is driven by the effective series
resistance (ESR). Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering. The
output ripple (∆V
OUT
) is approximated by:
∆≈ +
⎛
⎝
⎜⎞
⎠
⎟
V I ESR fC
OUT RIPPLE OUT
1
8
APPLICATIO S I FOR ATIO
WUUU
18
LTC3736-1
37361f
allows C
SS
to ramp up slowly providing the soft-start
function. This diode (and capacitor) can be deleted if the
external soft-start is not needed.
During soft-start, the start-up of V
OUT1
is controlled by
slowly ramping the positive reference to the error amplifier
from 0V to 0.6V, allowing V
OUT1
to rise smoothly from 0V
to its final value. The default internal soft-start time is 1ms.
This can be increased by placing a capacitor between the
RUN/SS pin and SGND. In this case, the soft-start time will
be approximately:
tC mV
A
SS SS1 600
07
=µ
•.
It is recommended that C
SS
have a value of at least twice
that of the frequency filtering capacitor connected to the
FREQ pin when spread sprectrum operation is enabled
(see Operation Frequency section).
Tracking
The start-up of V
OUT2
is controlled by the voltage on the
TRACK pin. Normally this pin is used to allow the start-up
of V
OUT2
to track that of V
OUT1
as shown qualitatively in
Figures 8a and 8b. When the voltage on the TRACK pin is
less than the internal 0.6V reference, the LTC3736-1
regulates the V
FB2
voltage to the TRACK pin voltage
instead of 0.6V. The start-up of V
OUT2
may ratiometrically
track that of V
OUT1
, according to a ratio set by a resistor
divider (Figure 8c):
V
V
RA
R
RR
RB RA
OUT
OUT TRACKA
TRACKA TRACKB1
2
2
22
=+
+
•
For coincident tracking (V
OUT1
= V
OUT2
during start-up),
R2A/R2B = R
TRACKA
/R
TRACKB
APPLICATIO S I FOR ATIO
WUUU
3.3V OR 5V RUN/SS RUN/SS
C
SS
C
SS
D1
37361 F07
Figure 7. RUN/SS Pin Interfacing
where f is the operating frequency, C
OUT
is the output
capacitance and I
RIPPLE
is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I
RIPPLE
increases with input voltage.
Setting Output Voltage
The LTC3736-1 output voltages are each set by an external
feedback resistor divider carefully placed across the out-
put, as shown in Figure 6. The regulated output voltage is
determined by:
VV
R
R
OUT B
A
=+
⎛
⎝
⎜⎞
⎠
⎟
06 1.•
To improve the frequency response, a feed-forward ca-
pacitor, C
FF
, may be used. Great care should be taken to
route the V
FB
line away from noise sources, such as the
inductor or the SW line. When spread spectrum operation
is enabled, it is recommended that R
A
and R
B
be large-
valued, preferably on the order of hundreds of kilohms.
Run/Soft Start Function
The RUN/SS pin is a dual purpose pin that provides the
optional external soft-start function and a means to shut
down the LTC3736-1.
Pulling the RUN/SS pin below 0.65V puts the LTC3736-1
into a low quiescent current shutdown mode (I
Q
= 9µA). If
RUN/SS has been pulled all the way to ground, there will
be a delay before the LTC3736-1 comes out of shutdown
and is given by:
tV
C
AsFC
DELAY SS SS
=µ=µ065 07 093.•
../•
This pin can be driven directly from logic as shown in
Figure 6. Diode D1 in Figure 7 reduces the start delay but
1/2 LTC3736-1
V
FB
V
OUT
R
B
C
FF
R
A
37361 F06
Figure 6. Setting Output Voltage
19
LTC3736-1
37361f
The ramp time for V
OUT2
to rise from 0V to its final value
is:
tt
R
RA
RA RB
RR
SS SS TRACKA
TRACKA TRACKB
211
11
=+
+
••
For coincident tracking,
tt
V
V
SS SS OUT F
OUT F
21 2
1
=•
where V
OUT1F
and V
OUT2F
are the final, regulated values of
V
OUT1
and V
OUT2
. V
OUT1
should always be greater than
V
OUT2
when using the TRACK pin. If no tracking function
is desired, then the TRACK pin may be tied to V
IN
. How-
ever, in this situation there would be no (internal nor
external) soft-start on V
OUT2
.
When using tracking with spread spectrum operation
enabled, the tracking resistors R
TRACKA
and R
TRACKB
should have value at least 10 times smaller than corre-
sponding feedback resistors R2A and R2B.
Fault Condition: Short Circuit and Current Limit
To prevent excessive heating of the bottom MOSFET,
foldback current limiting can be added to reduce the
current in proportion to the severity of the fault.
Foldback current limiting is implemented by adding di-
odes D
FB1
and D
FB2
between the output and the I
TH
pin as
shown in Figure 9. In a hard short (V
OUT
= 0V), the current
will be reduced to approximately 50% of the maximum
output current.
Low Supply Operation
Although the LTC3736-1 can function down to below
2.4V, the maximum allowable output current is reduced as
V
IN
decreases below 3V. Figure 10 shows the amount of
APPLICATIO S I FOR ATIO
WUUU
LTC3736-1
V
FB2
V
OUT2
V
OUT1
V
FB1
TRACK
R2B
R2A
37361 F08a
R1B
R1A
R
TRACKA
R
TRACKB
Figure 8a. Using the TRACK Pin
TIME
(8b) Coincident Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
TIME
37361 F08b,c
(8c) Ratiometric Tracking
V
OUT1
V
OUT2
OUTPUT VOLTAGE
Figures 8b and 8c. Two Different Modes of Output
Voltage Tracking
+
1/2 LTC3736-1
VFB
ITH
R2 DFB1
VOUT
DFB2
37361 F09
R1
Figure 9. Foldback Current Limiting
INPUT VOLTAGE (V)
75
NORMALIZED VOLTAGE OR CURRENT (%)
85
95
105
80
90
100
2.2 2.4 2.6 2.8
37361 F10
3.02.12.0 2.3 2.5 2.7 2.9
V
REF
MAXIMUM
SENSE VOLTAGE
Figure 10. Line Regulation of VREF and
Maximum Sense Voltage for Low Input Supply
20
LTC3736-1
37361f
APPLICATIO S I FOR ATIO
WUUU
change as the supply is reduced down to 2.4V. Also shown
is the effect on V
REF
.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
,
is the smallest amount of time
in which the LTC3736-1 is capable of turning the top
P-channel MOSFET on and then off. It is determined by
internal timing delays and the gate charge required to turn
on the top MOSFET. Low duty cycle and high frequency
applications may approach the minimum on-time limit
and care should be taken to ensure that:
tV
fV
ON MIN OUT
OSC IN
() •
<
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3736-1 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase. The
minimum on-time for the LTC3736
-1
is typically about
250ns. However, as the peak sense voltage (IL(PEAK) •
RDS(ON)) decreases, the minimum on-time gradually in-
creases up to about 300ns.
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting efficiency and which change would produce the
most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + …)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, five main sources usually account for most of the
losses in LTC3736-1 circuits: 1) LTC3736-1 DC bias
current, 2) MOSFET gate charge current, 3) I
2
R losses,
and 4) transition losses.
1) The V
IN
(pin) current is the DC supply current, given in
the electrical characteristics, excluding MOSFET driver
currents. V
IN
current results in a small loss that in-
creases with V
IN
.
2) MOSFET gate charge current results from switching the
gate capacitance of the power MOSFETs. Each time a
MOSFET gate is switched from low to high to low again,
a packet of charge dQ moves from SENSE
+
to ground.
The resulting dQ/dt is a current out of SENSE
+
, which is
typically much larger than the DC supply current. In
continuous mode, I
GATECHG
= f • Q
P
.
3) I
2
R losses are calculated from the DC resistances of the
MOSFETs and inductor. In continuous mode, the aver-
age output current flows through L but is “chopped”
between the top P-channel MOSFET and the bottom
N-channel MOSFET. The MOSFET R
DS(ON)
s multiplied
by duty cycle can be summed with the resistance of L
to obtain I
2
R losses.
4) Transition losses apply to the top external P-channel
MOSFET and increase with higher operating frequen-
cies and input voltages. Transition losses can be esti-
mated from:
Transition Loss = 2 (V
IN
)
2
I
O(MAX)
C
RSS
(f)
Other losses, including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses, generally account for less
than 2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current. When
a load step occurs, V
OUT
immediately shifts by an amount
equal to (∆I
LOAD
)(ESR), where ESR is the effective series
resistance of
COUT
. ∆I
LOAD
also begins to charge or dis-
charge C
OUT
, which generates a feedback error signal. The
regulator loop then returns V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for over-
shoot or ringing. OPTI-LOOP compensation allows the
transient response to be optimized over a wide range of
output capacitance and ESR values.
The I
TH
series R
C
-C
C
filter (see Functional Diagram) sets
the dominant pole-zero loop compensation. The I
TH
exter-
nal components shown in the Typical Application on the
front page of this data sheet will provide an adequate
starting point for most applications. The values can be
21
LTC3736-1
37361f
APPLICATIO S I FOR ATIO
WUUU
modified slightly (from 0.2 to 5 times their suggested
values) to optimize transient response once the final PC
layout is done and the particular output capacitor type and
value have been determined. The output capacitors need
to be decided upon because the various types and values
determine the loop feedback factor gain and phase. An
output current pulse of 20% to 100% of full load current
having a rise time of 1µs to 10µs will produce output
voltage and I
TH
pin waveforms that will give a sense of the
overall loop stability. The gain of the loop will be increased
by increasing R
C
, and the bandwidth of the loop will be
increased by decreasing C
C
. The output voltage settling
behavior is related to the stability of the closed-loop
system and will demonstrate the actual overall supply
performance. For a detailed explanation of optimizing the
compensation components, including a review of control
loop theory, refer to Application Note 76.
A second, more severe transient is caused by switching in
loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
deliver enough current to prevent this problem if the load
switch resistance is low and it is driven quickly. The only
solution is to limit the rise time of the switch drive so that
the load rise time is limited to approximately (25)(C
LOAD
).
Thus a 10µF capacitor would require a 250µs rise time,
limiting the charging current to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3736-1. These items are illustrated in the layout dia-
gram of Figure 11. Figure 12 depicts the current wave-
forms present in the various branches of the 2-phase dual
regulator.
1) The power loop (input capacitor, MOSFETs, inductor,
output capacitor) of each channel should be as small as
possible and isolated as much as possible from the power
loop of the other channel. Ideally, the drains of the P- and
N-channel FETs should be connected close to one another
with an input capacitor placed across the FET sources
(from the P-channel source to the N-channel source) right
SW1
IPRG1
V
FB1
I
TH1
IPRG2
FREQ
SGND
V
IN
TRACK
V
FB2
I
TH2
PGOOD
SENSE1
+
PGND
BG1
SSDIS
TG1
PGND
TG2
RUN/SS
BG2
PGND
SENSE2
+
SW2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
LTC3736EGN-1
+
+
C
OUT1
C
OUT2
C
VIN1
C
VIN
V
OUT1
V
OUT2
BOLD LINES INDICATE HIGH CURRENT PATHS
37361 F11
L1
L2
MN1 MP1
MN2 MP2
V
IN
C
VIN2
Figure 11. LTC3736-1 Layout Diagram
22
LTC3736-1
37361f
APPLICATIO S I FOR ATIO
WUUU
Figure 12. Branch Current Waveforms
R
L1
L1
MP1 V
OUT1
C
OUT1
MN1
MN2
V
IN
C
IN
R
IN +
R
L2
BOLD LINES INDICATE
HIGH, SWITCHING
CURRENT LINES.
KEEP LINES TO A
MINIMUM LENGTH
L2
MP2
37361 F12
V
OUT2
C
OUT2
+
+
at the FETs. It is better to have two separate, smaller valued
input capacitors (e.g., two 10µF—one for each channel)
than it is to have a single larger valued capacitor (e.g.,
22µF) that the channels share with a common connection.
2) The signal and power grounds should be kept separate.
The signal ground consists of the feedback resistor divid-
ers, I
TH
compensation networks and the SGND pin.
The power grounds consist of the (–) terminal of the input
and output capacitors and the source of the N-channel
MOSFET. Each channel should have its own power ground
for its power loop (as described in (1) above). The power
grounds for the two channels should connect together at
a common point. It is most important to keep the ground
paths with high switching currents away from each other.
The PGND pins on the LTC3736-1 IC should be shorted
together and connected to the common power ground
connection (away from the switching currents).
3) Put the feedback resistors close to the V
FB
pins. The
trace connecting the top feedback resistor (R
B
) to the
output capacitor should be a Kelvin trace. The I
TH
compen-
sation components should also be very close to the
LTC3736-1.
4) The current sense traces (SENSE
+
and SW) should be
Kelvin connections right at the P-channel MOSFET source
and drain.
5) Keep the switch nodes (SW1, SW2) and the gate driver
nodes (TG1, TG2, BG1, BG2) away from the small-signal
components, especially the opposite channels feedback
resistors, I
TH
compensation components and the current
sense pins (SENSE
+
and SW).
23
LTC3736-1
37361f
TYPICAL APPLICATIO S
U
SGND
FREQ
IPRG2
IPRG1
VFB1
ITH1
SW1
RVIN 10Ω
RITH2
15k
CITH2
220pF
CSS
10nF
CIN
10µF
×2
CVIN
1µF
VIN
5V
VIN
CITH2B
100pF
RITH1
15k
CITH1
220pF
2200pF
CITH1A
100pF
RFB1B
562k
RFB1A
178k
PGOOD
VFB2
TRACK
25
ITH2
TG2
LTC3736EUF-1
PGND
TG1
SSDIS
BG1
PGND
22 21
20
19
18
17
16
15
14
13
12
11
10
23
24
1
2
3
4
5
9
8
7
6
SENSE1+MP1
MP2
L1
1.5µH
L2
1.5µH
MN1
Si7540DP
MN2
Si7540DP
RUN/SS
BG2
PGND
PGND
SW2
SENSE2+
RTRACKB
1.18k
RTRACKA
590Ω
RFB2A
453k
RFB2B
909k
COUT2
150µF
COUT1
150µF
VOUT1
2.5V
5A
VOUT2
1.8V
5A
37361 F13
+
+
L1, L2: VISHAY IHLP-2525CZ-01
COUT1, COUT2: SANYO 4TPB150MC
Figure 13. 2-Phase, Spread Spectrum, Dual Output Synchronous DC/DC Converter
24
LTC3736-1
37361f
SGND
FREQ
IPRG2
IPRG1
V
FB1
I
TH1
SW1
R
VIN
10Ω
R
ITH2
22k
C
ITH2
470pF
C
SS
10nF
C
IN
22µF
C
VIN
1µF
V
IN
3.3V
V
IN
C
ITH2A
47pF
R
ITH1
22k
C
ITH1
470pF
C
ITH1A
47pF
R
FB1B
187k
R
FB1A
59k
PGOOD
V
FB2
TRACK
PGND
I
TH2
TG2
LTC3736EUF-1
PGND
TG1
SSDIS
BG1
PGND
22 21
20
19
18
17
16
15
14
13
12
11
10
25
23
24
1
2
3
4
5
9
8
7
6
SENSE1
+
MP1
MP2
L1
1.5µH
L2
1.5µH
MN1
Si7540DP
MN2
Si7540DP
RUN/SS
BG2
PGND
SW2
SENSE2
+
R
TRACKB
1.18k
R
TRACKA
590Ω
R
FB2A
59k
R
FB2B
118k
C
OUT2
100µF
C
OUT1
100µF
V
OUT1
2.5V
2A
V
OUT2
1.8V
2A
37361 F14
L1, L2: VISHAY IHLP-2525CZ-01
C
OUT1
, C
OUT2
: MURATA GRM32EROJ107M
2200pF
68pF
100pF
Figure 14. 2-Phase, Spread Spectrum, Dual Output Synchronous DC/DC Converter with Ceramic Output Capacitors
TYPICAL APPLICATIO S
U
Efficiency vs Load Current
LOAD CURRENT (mA)
EFFICIENCY (%)
100
60
90
80
70
1 100 1000 10000
37361 F14b
0
50
10
40
30
20
10
V
OUT
= 2.5V
V
OUT
= 1.8V
V
OUT
AC-COUPLED
100mV/DIV
V
OUT
= 2.5V
I
LOAD
= 100mA TO 1A
100µs/DIV 37361 F14c
I
L
1A/DIV
V
OUT
AC-COUPLED
50mV/DIV
V
OUT
= 1.8V
I
LOAD
= 100mA TO 1A
100µs/DIV 37361 F14d
I
L
1A/DIV
Load Step Load Step
25
LTC3736-1
37361f
SGND
FREQ
IPRG2
IPRG1
V
FB1
I
TH1
SW1
R
VIN
10Ω
R
ITH2
15k
C
ITH2
220pF
C
IN
22µF
C
VIN
1µF
V
IN
3.3V
V
IN
R
ITH1
15k
C
ITH1
220pF
C
FF1
100pF
C
FF1
100pF
2200pF
R
FB1B
187k
R
FB1A
59k
PGOOD
V
FB2
TRACK
I
TH2
TG2
LTC3736EGN-1
PGND
TG1
SSDIS
BG1
PGND
124
23
22
21
20
19
18
17
16
15
14
13
C
OUT1
, C
OUT2
: SANYO 4TPB150MC
L1, L2: VISHAY IHLP-2525CZ-01
D1, D2: OPTIONAL SCHOTTKY DIODE
2
3
4
5
6
7
5
12
11
10
9
SENSE1
+
MP1 SW1
D1
SW2
SSDIS
MP2
L1
1.5µH
L2
1.5µH
MN1
Si7540DP
MN2
Si7540DP
RUN/SS
BG2
PGND
SW2
SENSE2
+
R
TRACKB
1.18k
R
TRACKA
590Ω
R
FB2A
59k
R
FB2B
118k
C
OUT2
150µF
C
OUT1
150µF
V
OUT1
2.5V
3A
V
OUT2
1.8V
4A
37361 F15
+
+
4.7nF
D2
Figure 15. 2-Phase, Fixed 550kHz or Spread Spectrum, Dual Output Synchronous DC/DC Converter
TYPICAL APPLICATIO S
U
26
LTC3736-1
37361f
U
PACKAGE DESCRIPTIO
UF Package
24-Lead Plastic QFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1697)
4.00 ± 0.10
(4 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-X)—TO BE APPROVED
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.38 ± 0.10
24
0.23 TYP
(4 SIDES)
23
1
2
BOTTOM VIEW—EXPOSED PAD
2.45 ± 0.10
(4-SIDES)
0.75 ± 0.05 R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
0.200 REF
0.00 – 0.05
(UF24) QFN 1103
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
0.70 ±0.05
0.25 ±0.05
0.50 BSC
2.45 ± 0.05
(4 SIDES)
3.10 ± 0.05
4.50 ± 0.05
PACKAGE OUTLINE
27
LTC3736-1
37361f
U
PACKAGE DESCRIPTIO
GN Package
24-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
.337 – .344*
(8.560 – 8.738)
GN24 (SSOP) 0204
12
345678 9 10 11 12
.229 – .244
(5.817 – 6.198)
.150 – .157**
(3.810 – 3.988)
161718192021222324 15 14 13
.016 – .050
(0.406 – 1.270)
.015 ± .004
(0.38 ± 0.10) × 45°
0° – 8° TYP
.0075 – .0098
(0.19 – 0.25)
.0532 – .0688
(1.35 – 1.75)
.008 – .012
(0.203 – 0.305)
TYP
.004 – .0098
(0.102 – 0.249)
.0250
(0.635)
BSC
.033
(0.838)
REF
.254 MIN
RECOMMENDED SOLDER PAD LAYOUT
.150 – .165
.0250 BSC.0165 ±.0015
.045 ±.005
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
INCHES
(MILLIMETERS)
NOTE:
1. CONTROLLING DIMENSION: INCHES
2. DIMENSIONS ARE IN
3. DRAWING NOT TO SCALE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
28
LTC3736-1
37361f
PART NUMBER DESCRIPTION COMMENTS
LTC1628/ Dual High Efficiency, 2-Phase Synchronous Constant Frequency, Standby, 5V and 3.3V LDOs, V
IN
to 36V,
LTC1628-PG Step-Down Controllers 28-Lead SSOP
LTC1735 High Efficiency Synchronous Step-Down Controller Burst Mode Operation, 16-Pin Narrow SSOP, Fault Protection,
3.5V ≤ V
IN
≤ 36V
LTC1772 Constant Frequency Current Mode Step-Down 2.5V ≤ V
IN
≤ 9.8V, I
OUT
Up to 4A, SOT-23 Package, 550kHz
DC/DC Controller
LTC1773 Synchronous Step-Down Controller 2.65V ≤ V
IN
≤ 8.5V, I
OUT
Up to 4A, 10-Lead MSOP
LTC1778 No R
SENSE
TM Synchronous Step-Down Controller Current Mode Operation Without Sense Resistor,
Fast Transient Response, 4V ≤ V
IN
≤ 36V
LTC2923 Power Supply Tracking Controller Controls Up to Three Supplies, 10-Lead MSOP
LTC3251 Series 500mA High Efficiency, Low Noise, Inductorless 2-Phase, Spread Spectrum Operation, 10-Pin MSOP Package
Step-Down DC/DC Converters
LTC3252 Dual, Low Noise, Inductorless Step-Down DC/DC Converter Spread Spectrum Operation, 4mm × 3mm 12-Pin DFN Package
LTC3416 4A, 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, V
IN
: 2.25V to 5.5V, I
SD
= <1µA,
with Output Tracking TSSOP-20E Package
LTC3701 2-Phase, Low Input Voltage Dual Step-Down DC/DC Controller 2.5V ≤ V
IN
≤ 9.8V, 550kHz, PGOOD, PLL, 16-Lead SSOP
LTC3708 Fast 2-Phase, No R
SENSE
Buck Controller with Constant On-Time Dual Controller, V
IN
Up to 36V, Very Low
Output Tracking Duty Cycle Operation, 5mm × 5mm QFN Package
LTC3728/LTC3728L Dual, 550kHz, 2-Phase, Synchronous Step-Down Constant Frequency, V
IN
to 36V, 5V and 3.3V LDOs,
Switching Regulator 5mm × 5mm QFN or 28-Lead SSOP
LTC3736 Dual, 2-Phase, No R
SENSE
, Synchronous Controller with Output V
IN
: 2.75V to 9.8V, I
OUT
Up to 5A, 4mm × 4mm QFN Package
Tracking
LTC3737 Dual, 2-Phase, No R
SENSE
Controller with Output Tracking V
IN
: 2.75V to 9.8V, I
OUT
Up to 5A, 4mm × 4mm QFN Package
LTC6902 Multiphase Oscillator with Spread Spectrum Frequency Resistor Programs Nominal Frequency and Spreading;
Modulation 2-, 3-, or 4-Phase Outputs; 10-Pin MSOP Package
LT/TP 0804 1K • PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2004
RELATED PARTS
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
TYPICAL APPLICATIO
U
SGND
FREQ
IPRG2
IPRG1
V
FB1
I
TH1
SW1
R
VIN
10Ω
R
ITH2
15k
C
ITH2
220pF
C
SS
10nF
C
IN
10µF
×2
C
VIN
1µF
V
IN
5V
V
IN
C
ITH2B
100pF
R
ITH1
15k
C
ITH1
220pF
2200pF
C
ITH1A
100pF
R
FB1B
187k
R
FB1A
59k
PGOOD
V
FB2
TRACK
25
I
TH2
TG2
LTC3736EUF-1
PGND
TG1
SSDIS
BG1
PGND
22 21
20
19
18
17
16
15
14
13
12
11
10
23
24
1
2
3
4
5
9
8
7
6
SENSE1
+
MP1
MP2
L1
1.5µH
L2
1.5µH
MN1
MN2
RUN/SS
BG2
PGND
PGND
SW2
SENSE2
+
R
TRACKB
1.18k
R
TRACKA
590Ω
R
FB2A
59k
R
FB2B
118k
C
OUT2
150µF
C
OUT1
150µF
V
OUT1
2.5V
2A
V
OUT2
1.8V
2A
37361 TA02
+
+
MP1, MP2: FDC638P
MN1, MN2: FDC637N
L1, L2: VISHAY IHLP-2525CZ-01
C
OUT1
, C
OUT2
: SANYO 4TPB150MC
2-Phase, Spread Spectrum Dual Output, Synchronous DC/DC Converter
No R
SENSE
is a trademark of Linear Technology Corporation.
