GBPC2501WE4/51 - VISHAY - Datasheet.Live

CY7C1360C

CY7C1362C

9-Mbit (256K × 36/512K × 18)

Pipelined SRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 38-05540 Rev. *U Revised March 22, 2019

9-Mbit (256K × 36/512K × 1 8) Pipelined SR AM

Features

■Supports bus operation up to 200 MHz

■Available speed grades: 200 MHz, and 166 MHz

■Registered inputs and outputs for pipelined operation

■3.3 V core power supply (VDD)

■2.5 V/3.3 V I/O operation (VDDQ)

■Fast clock-to-output times

❐3.0 ns (for 200 MHz device)

■Provide high performance 3-1-1-1 access rate

■User selectable burst counter supporting IntelPentium®

interleaved or linear burst sequences

■Separate processor and controller address strobes

■Synchronous self-timed writes

■Asynchronous output enable

■Single cycle chip deselect

■Available in Pb-free 100-pin TQFP package, non Pb-free

119-ball BGA package, and 165-ball FBGA package

■TQFP available with 3-chip enable and 2-chip enable

■IEEE 1149.1 JTAG-compatible boundary scan

Functional Description

The CY7C1360C/CY7C1362C SRAM integrates 256K × 36 and

512K × 18 SRAM cells with advanced synchronous peripheral

circuitry and a two-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a

positive-edge-triggered clock input (CLK). The synchronous

inputs include all addresses, all data inputs, address-pipelining

chip enable (CE1), depth-expansion chip enables (CE2 and

CE3[1]), burst control inputs (ADSC, ADSP, and ADV), write

enables (BWX, and BWE), and global write (GW). Asynchronous

inputs include the output enable (OE) and the ZZ pin.

Addresses and chip enables are registered at the rising edge of

clock when either address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self-timed write cycle.This part supports byte write

operations (see Pin Definitions on page 8 and Truth Table on

page 11 for further details). Write cycles can be one to two or four

bytes wide as controlled by the byte write control inputs. GW

when active LOW causes all bytes to be written.

The CY7C1360C/CY7C1362C operate from a +3.3 V core power

supply while all outputs may operate with either a +2.5 or +3.3 V

supply. All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

For a complete list of related documentation, click here.

Selection Guide

Description 200 MHz 166 MHz Unit

Maximum access time 3.0 3.5 ns

Maximum operating current 220 180 mA

Maximum CMOS standby current 40 40 mA

Note

1. CE3 is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 2 of 38

Logic Block Diagram – CY7C1360C

ADDRESS

ADV

CLK BURST

COUNTER

AND

LOGIC

CLR

ADSP

ADSC

MODE

BWE

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

OUTPUT

BUFFERS

PIPELINED

ENABLE

INPUT

REGISTERS

0, A1, A

BW B

MEMORY

ARRAY

DQs

DQP

SLEEP

CONTROL

[1:0]

A ,

DQP

BYTE

WRITE REGISTER

B ,

DQP

BYTE

WRITE REGISTER

C ,

DQP

BYTE

WRITE REGISTER

D ,

DQP

BYTE

WRITE REGISTER

A ,

DQP

BYTE

WRITE DRIVER

B ,

DQP

BYTE

WRITE DRIVER

C ,

DQP

BYTE

WRITE DRIVER

,DQP

BYTE

WRITE DRIVER

Logic Block Diagram – CY7C1362C

0, A1, A ADDRESS

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSC

DQP

WRITE REGISTER

DQP

WRITE REGISTER

ENABLE

SENSE

AMPS

MEMORY

ARRAY

ADSP

MODE

CE2

CE3

BWE

PIPELINED

ENABLE

DQs

DQP

OUTPUT

REGISTERS

INPUT

REGISTERS

DQP

WRITE DRIVER

OUTPUT

BUFFERS

DQP

WRITE DRIVER

A[1:0]

ZZ SLEEP

CONTROL

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 3 of 38

Contents

Pin Configurations ........................................................... 4

Pin Definitions .................................................................. 8

Functional Overview ........................................................ 9

Single Read Accesses ................................................ 9

Single Write Accesses Initiated by ADSP ...................9

Single Write Accesses Initiated by ADSC ................. 10

Burst Sequences ....................................................... 10

Sleep Mode ............................................................... 10

Interleaved Burst Address Table ...............................10

Linear Burst Address Table ....................................... 10

ZZ Mode Electrical Characteristics ............................10

Truth Table ...................................................................... 11

Partial Truth Table for Read/Write ................................ 12

IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13

Disabling the JTAG Feature ...................................... 13

Test Access Port (TAP) ............................................. 13

PERFORMING A TAP RESET .................................. 13

TAP REGISTERS ...................................................... 13

TAP Instruction Set ................................................... 14

TAP Controller State Diagram ....................................... 15

TAP Controller Block Diagram ...................................... 16

TAP Timing ...................................................................... 16

TAP AC Switching Characteristics ...............................17

3.3 V TAP AC Test Conditions ....................................... 17

3.3 V TAP AC Output Load Equivalent ......................... 17

2.5 V TAP AC Test Conditions ....................................... 17

2.5 V TAP AC Output Load Equivalent ......................... 17

TAP DC Electrical Characteristics

and Operating Conditions ............................................. 18

Identification Register Definitions ................................ 19

Scan Register Sizes ....................................................... 19

Instruction Codes ........................................................... 19

Boundary Scan Order .................................................... 20

Boundary Scan Order .................................................... 21

Maximum Ratings ........................................................... 22

Operating Range ............................................................. 22

Neutron Soft Error Immunity ......................................... 22

Electrical Characteristics ............................................... 22

Capacitance .................................................................... 23

Thermal Resistance ........................................................ 23

AC Test Loads and Waveforms ..................................... 24

Switching Characteristics .............................................. 25

Switching Waveforms .................................................... 26

Ordering Information ...................................................... 30

Ordering Code Definitions ......................................... 30

Package Diagrams .......................................................... 31

Acronyms ........................................................................ 34

Document Conventions ................................................. 34

Units of Measure ....................................................... 34

Document History Page ................................................. 35

Sales, Solutions, and Legal Information ...................... 38

Worldwide Sales and Design Support ....................... 38

Products .................................................................... 38

PSoC® Solutions ...................................................... 38

Cypress Developer Community ................................. 38

Technical Support ..................................................... 38

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 4 of 38

Pin Configurations

Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (3 Chip Enables - A Version)

NC/72M

NC/36M

VSS

VDD

NC/18M

DQPB

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQPA

DQPC

DQC

DQc

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1360C

(256K × 36)

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 5 of 38

Figure 2. 100-pin TQFP (14 × 20 × 1.4 mm) pinout (2 Chip Enables - AJ Version)

Pin Configurations (continued)

NC/72M

NC/36M

VSS

VDD

NC/18M

DQPB

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQPA

DQPC

DQC

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1360C

(256K × 36)

NC/72M

NC/36M

VSS

VDD

VDDQ

VSSQ

DQPA

DQA

VSSQ

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VDD

VSS

DQB

VDDQ

VSSQ

DQB

DQPB

VSSQ

VDDQ

CE1

CE2

BWB

BWA

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1362C

(512K × 18)

NC/18M

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 6 of 38

Figure 3. 119-ball BGA (14 × 22 × 2.4 mm) pinout (2 Chip Enables with JTAG)

Pin Configurations (continued)

2345671

VDDQ

NC/288M

NC/144M

DQPC

DQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

CE2A

DQC

VDDQ

DQC

VDDQ

DQD

VDDQ

VDD

CLK

VDD

VSS

NC/576M

NC/1G

TDOTCKTDITMS

NC/36MNC/72M

VDDQ

AAA

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

BWE

BWD

CY7C1360C (256K × 36)

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 7 of 38

Figure 4. 165-ball FBGA (13 × 15 × 1.4 mm) pinout (3 Chip Enables with JTAG)

Pin Configurations (continued)

CY7C1360C (256K × 36)

234 5671

TDO

NC/288M

NC/144M

DQPC

DQC

DQPD

DQD

CE1BWB CE3

BWCBWE

ACE2

DQC

DQD

MODE

DQC

DQD

NC/36M

NC/72M

VDDQ

BWDBWACLK GW

VSS VSS VSS VSS

VDDQ VSS

VDD VSS

VSS

NC/18M

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD

VSS

VDD

VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCK

VSS

TDI

DQCVSS

DQC

VSS

DQD

VDDQ

VSS

TMS

891011

ADV A

ADSC NC

OE ADSP A

NC/576M

VSS VDDQ NC/1G DQPB

VDDQ

VDD DQB

DQB

DQA

VDD VDDQ

VDD VDDQ DQB

VDD

DQA

VDD VDDQ DQA

VDDQ

VDD

VDD VDDQ

VDD VDDQ DQA

VDDQ

VSS

DQB

DQA

DQPA

DQA

VDDQ

VSS

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 8 of 38

Pin Definitions

Name I/O Description

A0, A1, A Input-

synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK

if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active. A1:A0 are fed to the

two-bit counter.

BWA, BWB,

BWC, BWD

Input-

synchronous

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled

on the rising edge of CLK.

GW Input-

synchronous

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write

is conducted (all bytes are written, regardless of the values on BWX and BWE).

BWE Input-

synchronous

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted

LOW to conduct a byte write.

CLK Input-

clock

Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV is asserted LOW, during a burst operation.

CE1Input-

synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2

and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a

new external address is loaded.

CE2Input-

synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1

and CE3[2] to select/deselect the device. CE2 is sampled only when a new external address is loaded.

CE3[2] Input-

synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1

and CE2 to select/deselect the device. Not available for AJ package version. Not connected for BGA.

Where referenced, CE3[2] is assumed active throughout this document for BGA. CE3 is sampled only

when a new external address is loaded.

OE Input-

asynchronous

Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data

pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

ADV Input-

synchronous

Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP Input-

synchronous

Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is

ignored when CE1 is deasserted HIGH.

ADSC Input-

synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

ZZ Input-

asynchronous

ZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”

condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ

pin has an internal pull-down.

DQs, DQPXI/O-

synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

addresses presented during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX

are placed in a tristate condition.

VDD Power supply Power supply inputs to the core of the device.

VSS Ground Ground for the core of the device.

VSSQ I/O ground Ground for the I/O circuitry.

VDDQ I/O power

supply

Power supply for the I/O circuitry.

MODE Input-

static

Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating

selects interleaved burst sequence. This is a strap pin and should remain static during device operation.

Mode pin has an internal pull-up.

Note

2. CE3 is for A version of 100-pin TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 9 of 38

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock. Maximum

access delay from the clock rise (tCO) is 3.0 ns (200 MHz de vice).

The CY7C1360C/CY7C1362C supports secondary cache in

systems using either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486 processors.

The linear burst sequence is suited for processors that use a

linear burst sequence. The burst order is user selectable, and is

determined by sampling the MODE input. Accesses can be

initiated with either the processor address strobe (ADSP) or the

controller address strobe (ADSC). Address advancement

through the burst sequence is controlled by the ADV input. A

two-bit on-chip wraparound burst counter captures the first

address in a burst sequence and automatically increments the

address for the rest of the burst access.

Byte write operations are qualified with the byte write enable

(BWE) and byte write select (BWX) inputs. A global write enable

(GW) overrides all byte write inputs and writes data to all four

bytes. All writes are simplified with on-chip synchronous

self-timed write circuitry.

Three synchronous chip selects (CE1, CE2, CE3[3]) and an

asynchronous output enable (OE) provide for easy bank

selection and output tristate control. ADSP is ignored if CE1 is

HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) CE1, CE2, CE3[3] are all asserted active, and (3) the write

signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if

CE1 is HIGH. The address presented to the address inputs (A)

is stored into the address advancement logic and the address

corresponding data is allowed to propagate to the input of the

output registers. At the rising edge of the next clock, the data is

allowed to propagate through the output register and on the data

bus within 3.0 ns (200 MHz device) if OE is active LOW. The only

exception occurs when the SRAM is emerging from a deselected

state to a selected state, its outputs are always tristated during

the first cycle of the access. After the first cycle of the access,

the outputs are controlled by the OE signal. Consecutive single

read cycles are supported. After the SRAM is deselected at clock

rise by the chip select and either ADSP or ADSC signals, its

output tristates immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions are

satisfied at clock rise: (1) ADSP is asserted LOW and (2) CE1,

CE2, CE3[3] are all asserted active. The address presented to A

is loaded into the address register and the address advancement

logic while being delivered to the memory array. The write signals

(GW, BWE, and BWX) and ADV inputs are ignored during this

first cycle.

ADSP-triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQs inputs is written into the

corresponding address location in the memory array. If GW is

HIGH, then the write operation is controlled by BWE and BWX

signals. The CY7C1360C/CY7C1362C provides byte write

capability that is described in the Write Cycle Descriptions table.

Asserting the byte write enable input (BWE) with the selected

byte write (BWX) input, will selectively write to only the desired

bytes. Bytes not selected during a byte write operation remain

unaltered. A synchronous self-timed write mechanism has been

provided to simplify the write operations.

Because the CY7C1360C/CY7C1362C is a common I/O device,

the output enable (OE) must be deasserted HIGH before

presenting data to the DQs inputs. Doing so tristates the output

drivers. As a safety precaution, DQs are automatically tristated

whenever a Write cycle is detected, regardless of the state of OE.

TDO JTAG serial

output

synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is

not being used, this pin should be disconnected. This pin is not available on TQFP packages.

TDI JTAG serial

input

synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being

used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.

TMS JTAG serial

input

synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is not being

used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages.

TCK JTAG-

clock

Clock input to the JTAG circuitry. If the JTAG feature is not being used, this pin must be connected

to VSS. This pin is not available on TQFP packages.

NC – No connects. Not internally connected to the die

NC (18, 36,

72, 144,

288, 576,

1G)

–These pins are not connected. They will be used for expansion to the 18M, 36M, 72M, 144M 288M,

576M, and 1G densities.

Pin Definitions (continued)

Name I/O Description

Note

3. CE3 is for A version of TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 10 of 38

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following conditions

are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted

HIGH, (3) CE1, CE2, CE3[4] are all asserted active, and (4) the

appropriate combination of the write inputs (GW, BWE, and

BWX) are asserted active to conduct a write to the desired

byte(s). ADSC-triggered write accesses require a single clock

cycle to complete. The address presented to A is loaded into the

address register and the address advancement logic while being

delivered to the memory array. The ADV input is ignored during

this cycle. If a global write is conducted, the data presented to

the DQs is written into the corresponding address location in the

memory core. If a byte write is conducted, only the selected bytes

are written. Bytes not selected during a byte write operation

remains unaltered. A synchronous self-timed write mechanism

has been provided to simplify the write operations.

Because the CY7C1360C/CY7C1362C is a common I/O device,

the output enable (OE) must be deasserted HIGH before

presenting data to the DQs inputs. Doing so tristates the output

drivers. As a safety precaution, DQs are automatically tristated

whenever a write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1360C/CY7C1362C provides a two-bit wraparound

counter, fed by A1:A0, that implements either an interleaved or

linear burst sequence. The interleaved burst sequence is

designed specifically to support Intel Pentium applications. The

linear burst sequence is designed to support processors that

follow a linear burst sequence. The burst sequence is user

selectable through the MODE input.

Asserting ADV LOW at clock rise automatically increments the

burst counter to the next address in the burst sequence. Both

read and write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation ‘sleep’ mode. Two clock

cycles are required to enter into or exit from this ‘sleep’ mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the ‘sleep’ mode are not considered valid

nor is the completion of the operation guaranteed. The device

must be deselected prior to entering the ‘sleep’ mode. CE1, CE2,

CE3[4], ADSP, and ADSC must remain inactive for the duration

of tZZREC after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 50 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns

tZZI ZZ active to sleep current This parameter is sampled – 2tCYC ns

tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 – ns

Note

4. CE3 is for A version of 100-pin TQFP (3 Chip Enable option) and 165-ball FBGA package only. 119-ball BGA is offered only in 2 Chip Enable.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 11 of 38

Truth Table

The Truth Table for CY7C1360C and CY7C1362C follows. [5, 6, 7, 8, 9, 10]

Operation Address Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect cycle, power-down None H X X L X L X X X L–H Tri-state

Deselect cycle, power-down None L L X L L X X X X L–H Tri-state

Deselect cycle, power-down None L X H L L X X X X L–H Tri-state

Deselect cycle, power-down None L L X L H L X X X L–H Tri-state

Deselect cycle, power-down None L X H L H L X X X L–H Tri-state

Sleep mode, power-down None X X X H X X X X X X Tri-state

READ cycle, begin burst External L H L L L X X X L L–H Q

READ cycle, begin burst External L H L L L X X X H L–H Tri-state

WRITE cycle, begin burst External L H L L H L X L X L–H D

READ cycle, begin burst External L H L L H L X H L L–H Q

READ cycle, begin burst External L H L L H L X H H L–H Tri-state

READ cycle, continue burst Next X X X L H H L H L L–H Q

READ cycle, continue burst Next X X X L H H L H H L–H Tri-state

READ cycle, continue burst Next H X X L X H L H L L–H Q

READ cycle, continue burst Next H X X L X H L H H L–H Tri-state

WRITE cycle, continue burst Next X X X L H H L L X L–H D

WRITE cycle, continue burst Next H X X L X H L L X L–H D

READ cycle, suspend burst Current X X X L H H H H L L–H Q

READ cycle, suspend burst Current X X X L H H H H H L–H Tri-state

READ cycle, suspend burst Current H X X L X H H H L L–H Q

READ cycle, suspend burst Current H X X L X H H H H L–H Tri-state

WRITE cycle, suspend burst Current X X X L H H H L X L–H D

WRITE cycle, suspend burst Current H X X L X H H L X L–H D

Notes

5. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.

6. WRITE = L when any one or more byte write enable signals and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

8. CE1, CE2, and CE3 are available only in the TQFP package. BGA package has only two chip selects CE1 and CE2.

9. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the

ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a don't care for

the remainder of the write cycle.

10. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-State when OE is inactive

or when the device is deselected, and all data bits behave as output when OE is active (LOW).

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Document Number: 38-05540 Rev. *U Page 12 of 38

Partial Truth Table for Read/Write

The Partial Truth Table for Read/Write for CY7C1360C follows. [11, 12]

Function (CY7C1360C) GW BWE BWDBWCBWBBWA

Read H H X X X X

Read HLHHHH

Write byte A – (DQA and DQPA)HLHHHL

Write byte B – (DQB and DQPB)HLHHLH

Write bytes B, A H L H H L L

Write byte C – (DQC and DQPC)HLHLHH

Write bytes C, A HLHLHL

Write bytes C, B H L H L L H

Write bytes C, B, A H L H L L L

Write byte D – (DQD and DQPD)HLLHHH

Write bytes D, A H L L H H L

Write bytes D, B H L L H L H

Write bytes D, B, A H L L H L L

Write bytes D, C H L L L H H

Write bytes D, C, A H L L L H L

Write bytes D, C, B H L L L L H

Write all bytes HLLLLL

Write all bytes L X X X X X

Partial Truth Table for Read/Write

The Partial Truth Table for Read/Write for CY7C1362C follows. [11, 12]

Function (CY7C1362C) GW BWE BWBBWA

Read H H X X

Read H L H H

Write byte A – (DQA and DQPA)HLHL

Write byte B – (DQB and DQPB)HLLH

Write bytes B, A H L L L

Write all bytes H L L L

Write all bytes L X X X

Notes

11. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

12. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.

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IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1360C incorporates a serial boundary scan test

access port (TAP) in the BGA package only. The TQFP package

does not offer this functionality. This part operates in accordance

with IEEE Standard 1149.1-1900, but does not have the set of

functions required for full 1149.1 compliance. These functions

from the IEEE specification are excluded because their inclusion

places an added delay in the critical speed path of the SRAM.

Note that the TAP controller functions in a manner that does not

conflict with the operation of other devices using 1149.1 fully

compliant TAPs. The TAP operates using JEDEC-standard 3.3 V

or 2.5 V I/O logic levels.

The CY7C1360C contains a TAP controller, instruction register,

boundary scan register, bypass register, and ID register.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are

internally pulled up and may be unconnected. They may

alternately be connected to VDD through a pull-up resistor. TDO

should be left unconnected. Upon power-up, the device comes

up in a reset state which does not interfere with the operation of

the device.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to leave

this ball unconnected if the TAP is not used. The ball is pulled up

internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information into the registers

and can be connected to the input of any of the registers. The

is loaded into the TAP instruction register. For information on

loading the instruction register, see TAP Controller State

Diagram on page 15. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) of any register.

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-out from the

registers. The output is active depending upon the current state

of the TAP state machine (see Instruction Codes on page 19).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This RESET does not affect the operation of the

SRAM and may be performed while the SRAM is operating.

At power-up, the TAP is reset internally to ensure that TDO

comes up in a high Z state.

TAP Registers

Registers are connected between the TDI and TDO balls and

enable data to be scanned into and out of the SRAM test circuitry.

Only one register can be selected at a time through the

instruction register. Data is serially loaded into the TDI ball on the

rising edge of TCK. Data is output on the TDO ball on the falling

edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

and TDO balls as shown in the TAP Controller Block Diagram on

page 16. Upon power-up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

When the TAP controller is in the Capture-IR state, the two least

significant bits are loaded with a binary “01” pattern to enable

fault isolation of the board-level serial test data path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

TDI and TDO balls. This enables data to be shifted through the

SRAM with minimal delay. The bypass register is set LOW (VSS)

when the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the input and

bidirectional balls on the SRAM.

The boundary scan register is loaded with the contents of the

RAM I/O ring when the TAP controller is in the Capture-DR state

and is then placed between the TDI and TDO balls when the

controller is moved to the Shift-DR state. The EXTEST,

SAMPLE/PRELOAD and SAMPLE Z instructions can be used to

capture the contents of the I/O ring.

The Boundary Scan Order on page 20 and Boundary Scan Order

on page 21 show the order in which the bits are connected. Each

bit corresponds to one of the bumps on the SRAM package. The

MSB of the register is connected to TDI and the LSB is

connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in Identification Register Definitions on

page 19.

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TAP Instruction Set

Overview

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in Instruction

Codes on page 19. Three of these instructions are listed as

RESERVED and should not be used. The other five instructions

are described in detail in this section.

The TAP controller used in this SRAM is not fully compliant to the

1149.1 convention because some of the mandatory 1149.1

instructions are not fully implemented.

The TAP controller cannot be used to load address data or

control signals into the SRAM and cannot preload the I/O buffers.

The SRAM does not implement the 1149.1 commands EXTEST

or INTEST or the PRELOAD portion of SAMPLE/PRELOAD;

rather, it performs a capture of the I/O ring when these

instructions are executed.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO balls. To execute

the instruction once it is shifted in, the TAP controller needs to be

moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is to be

executed whenever the instruction register is loaded with all 0s.

EXTEST is not implemented in this SRAM TAP controller, and

therefore this device is not compliant to 1149.1. The TAP

controller does recognize an all-0 instruction.

When an EXTEST instruction is loaded into the instruction

instruction has been loaded. There is one difference between the

two instructions. Unlike the SAMPLE/PRELOAD instruction,

EXTEST places the SRAM outputs in a high Z state.

IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO balls and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state.

The IDCODE instruction is loaded into the instruction register

upon power up or whenever the TAP controller is given a test

logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to

be connected between the TDI and TDO balls when the TAP

controller is in a Shift-DR state. It also places all SRAM outputs

into a high Z state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because there

is a large difference in the clock frequencies, it is possible that

during the Capture-DR state, an input or output will undergo a

transition. The TAP may then try to capture a signal while in

transition (metastable state). This will not harm the device, but

there is no guarantee as to the value that will be captured.

Repeatable results may not be possible.

To guarantee that the boundary scan register will capture the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller’s capture setup plus hold

times (tCS and tCH). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK captured in the boundary scan register.

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

PRELOAD enables an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells prior

to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required - that is, while data captured

is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO balls. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

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TAP Controller State Diagram

The 0/1 next to each state represents the value of TMS at the rising edge of TCK.

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 1

0 0

1 1

0 0

1 0

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TAP Controller Block Diagram

TAP Timing

Bypass Register

Instruction Register

012

Identication Register

012293031 ...

Boundary Scan Register

012..x ...

Selection

Circuitry

TCK

TMS TAP CONTROLLER

TDI TDO

Selection

Circuitry

tTL

Test Clock

(TCK)

123456

est Mode Select

(TMS)

tTH

Test Data-Out

(TDO)

tCYC

Test Data-In

(TDI)

tTMSH

tTMSS

tTDIH

tTDIS

tTDOX

tTDOV

DON’T CARE UNDEFINED

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Document Number: 38-05540 Rev. *U Page 17 of 38

3.3 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 3.3 V

Input rise and fall times ...................................................1 ns

Input timing reference levels ......................................... 1.5 V

Output reference levels ................................................ 1.5 V

Test load termination supply voltage ............................ 1.5 V

3.3 V TAP AC Output Load Equivalent

2.5 V TAP AC Test Conditions

Input pulse levels ...............................................VSS to 2.5 V

Input rise and fall time ....................................................1 ns

Input timing reference levels ....................................... 1.25 V

Output reference levels .............................................. 1.25 V

Test load termination supply voltage .......................... 1.25 V

2.5 V TAP AC Output Load Equivalent

TAP AC Switching Characteristics

Over the Operating Range

Parameter [13, 14] Description Min Max Unit

Clock

tTCYC TCK clock cycle time 50 –ns

tTF TCK clock frequency –20 MHz

tTH TCK clock HIGH time 20 –ns

tTL TCK clock LOW time 20 –ns

Output Times

tTDOV TCK clock LOW to TDO valid –10 ns

tTDOX TCK clock LOW to TDO invalid 0 – ns

Setup Times

tTMSS TMS setup to TCK clock rise 5 – ns

tTDIS TDI setup to TCK clock rise 5 – ns

tCS Capture setup to TCK rise 5 – ns

Hold Times

tTMSH TMS hold after TCK clock rise 5 – ns

tTDIH TDI hold after clock rise 5 – ns

tCH Capture hold after clock rise 5 – ns

TDO

1.5V

20pF

Z = 50Ω

50Ω

TDO

1.25V

20pF

Z = 50Ω

50Ω

Notes

13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

14. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.

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TAP DC Electrical Characteristics and Operating Conditions

(0 °C < TA < +70 °C; VDD = 3.3 V ± 0.165 V unless otherwise noted)

Parameter [15] Description Conditions Min Max Unit

VOH1 Output HIGH voltage IOH = –4.0 mA VDDQ = 3.3 V 2.4 – V

IOH = –1.0 mA VDDQ = 2.5 V 2.0 – V

VOH2 Output HIGH voltage IOH = –100 µA VDDQ = 3.3 V 2.9 – V

VDDQ = 2.5 V 2.1 – V

VOL1 Output LOW voltage IOL = 8.0 mA VDDQ = 3.3 V – 0.4 V

IOL = 8.0 mA VDDQ = 2.5 V – 0.4 V

VOL2 Output LOW voltage IOL = 100 µA VDDQ = 3.3 V – 0.2 V

VDDQ = 2.5 V – 0.2 V

VIH Input HIGH voltage VDDQ = 3.3 V 2.0 VDD + 0.3 V

VDDQ = 2.5 V 1.7 VDD + 0.3 V

VIL Input LOW voltage VDDQ = 3.3 V –0.5 0.7 V

VDDQ = 2.5 V –0.3 0.7 V

IXInput load current GND < VIN < VDDQ –5 5 µA

Note

15. All voltages referenced to VSS (GND).

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Identification Register Definitions

Instruction Field CY7C1360C

(256K × 36) Description

Revision number (31:29) 000 Describes the version number

Device depth (28:24) [16] 01011 Reserved for internal use

Device width (23:18) 119-ball BGA 101000 Defines memory type and architecture

Device width (23:18) 165-ball FBGA 000000 Defines memory type and architecture

Cypress device ID (17:12) 100110 Defines width and density

Cypress JEDEC ID code (11:1) 00000110100 Allows unique identification of SRAM vendor

ID register presence indicator (0) 1 Indicates the presence of an ID register

Scan Register Sizes

Instruction 3

Bypass 1

ID 32

Boundary scan order (119-ball BGA package) 71

Boundary scan order (165-ball FBGA package) 71

Instruction Codes

Instruction Code Description

EXTEST 000 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces

all SRAM outputs to high Z state.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operations.

SAMPLE Z 010 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces

all SRAM output drivers to a high Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does

not affect SRAM operation.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

Note

16. Bit #24 is “1” in the Register Definitions for both 2.5 V and 3.3 V versions of this device.

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Boundary Scan Order

165-ball FBGA

CY7C1360C (256K × 36)

Bit# Ball ID Signal Name Bit# Ball ID Signal Name

1B6CLK 37 R6 A0

2B7GW 38 P6 A1

3A7BWE 39 R4 A

4B8OE 40 P4 A

5A8ADSC 41 R3 A

6B9ADSP 42 P3 A

7A9ADV 43 R1 MODE

8B10A 44N1DQP

9A10A 45L2DQ

10 C11 DQPB46 K2 DQD

11 E10 DQB47 J2 DQD

12 F10 DQB48 M2 DQD

13 G10 DQB49 M1 DQD

14 D10 DQB50 L1 DQD

15 D11 DQB51 K1 DQD

16 E11 DQB52 J1 DQD

17 F11 DQB53 Internal Internal

18 G11 DQB54 G2 DQC

19 H11 ZZ 55 F2 DQC

20 J10 DQA56 E2 DQC

21 K10 DQA57 D2 DQC

22 L10 DQA58 G1 DQC

23 M10 DQA59 F1 DQC

24 J11 DQA60 E1 DQC

25 K11 DQA61 D1 DQC

26 L11 DQA62 C1 DQPC

27 M11 DQA63 B2 A

28 N11 DQPA64 A2 A

29 R11 A 65 A3 CE1

30 R10 A 66 B3 CE2

31 P10 A 67 B4 BWD

32 R9 A 68 A4 BWC

33 P9 A 69 A5 BWB

34 R8 A 70 B5 BWA

35 P8 A 71 A6 CE3

36 P11 A

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Document Number: 38-05540 Rev. *U Page 21 of 38

Boundary Scan Order

119-ball BGA

CY7C1360C (256K × 36)

Bit# Ball ID Signal Name Bit# Ball ID Signal Name

1K4 CLK 37 P4 A0

2H4GW 38 N4 A1

3M4BWE 39 R6 A

4F4OE 40 T5 A

5B4ADSC 41 T3 A

6A4ADSP 42 R2 A

7G4ADV 43 R3 MODE

8C3A 44P2DQP

9B3A 45P1DQ

10 D6 DQPB46 L2 DQD

11 H7 DQB47 K1 DQD

12 G6 DQB48 N2 DQD

13 E6 DQB49 N1 DQD

14 D7 DQB50 M2 DQD

15 E7 DQB51 L1 DQD

16 F6 DQB52 K2 DQD

17 G7 DQB53 Internal Internal

18 H6 DQB54 H1 DQC

19 T7 ZZ 55 G2 DQC

20 K7 DQA56 E2 DQC

21 L6 DQA57 D1 DQC

22 N6 DQA58 H2 DQC

23 P7 DQA59 G1 DQC

24 N7 DQA60 F2 DQC

25 M6 DQA61 E1 DQC

26 L7 DQA62 D2 DQPC

27 K6 DQA63 C2 A

28 P6 DQPA64 A2 A

29 T4 A 65 E4 CE1

30 A3 A 66 B2 CE2

31 C5 A 67 L3 BWD

32 B5 A 68 G3 BWC

33 A5 A 69 G5 BWB

34 C6 A 70 L5 BWA

35 A6 A 71 Internal Internal

36 B6 A

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Document Number: 38-05540 Rev. *U Page 22 of 38

Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage temperature ................................ –65 °C to +150 °C

Ambient temperature with

power applied .......................................... –55 °C to +125 °C

Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V

Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD

DC voltage applied to outputs

in tri-state ..........................................–0.5 V to VDDQ + 0.5 V

DC input voltage ................................. –0.5 V to VDD + 0.5 V

Current into outputs (LOW) ........................................ 20 mA

Static discharge voltage

(per MIL-STD-883, method 3015) ......................... > 2001 V

Latch-up current .................................................... > 200 mA

Operating Range

Range Ambient

Temperature VDD VDDQ

Commercial 0 °C to +70 °C 3.3 V– 5 % /

+ 10%

2.5 V – 5% to

VDD

Industrial –40 °C to +85 °C

Neutron Soft Error Immunity

Parameter Description Test

Conditions Typ Max* Unit

LSBU Logical

single-bit

upsets

25 °C 361 394 FIT/

LMBU Logical

multi-bit

upsets

25 °C 0 0.01 FIT/

SEL Single event

latch-up

85 °C 0 0.1 FIT/

Dev

* No LMBU or SEL events occurred during testing; this column represents a

statistical 2, 95% confidence limit calculation. For more details refer to Application

Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial

Failure Rates”.

Electrical Characteristics

Over the Operating Range

Parameter [17, 18] Description Test Conditions Min Max Unit

VDD Power supply voltage 3.135 3.6 V

VDDQ I/O supply voltage for 3.3 V I/O 3.135 VDD V

for 2.5 V I/O 2.375 2.625 V

VOH Output HIGH voltage for 3.3 V I/O, IOH = –4.0 mA 2.4 – V

for 2.5 V I/O, IOH = –1.0 mA 2.0 – V

VOL Output LOW voltage for 3.3 V I/O, IOL = 8.0 mA – 0.4 V

for 2.5 V I/O, IOL = 1.0 mA – 0.4 V

VIH Input HIGH voltage[17] for 3.3 V I/O 2.0 VDD + 0.3 V V

for 2.5 V I/O 1.7 VDD + 0.3 V V

VIL Input LOW voltage[17] for 3.3 V I/O –0.3 0.8 V

for 2.5 V I/O –0.3 0.7 V

IXInput leakage current except ZZ

and MODE

GND  VI  VDDQ –5 5 A

Input current of MODE Input = VSS –30 – A

Input = VDD –5A

Input current of ZZ Input = VSS –5 – A

Input = VDD –30A

IOZ Output leakage current GND  VI  VDDQ, output disabled –5 5 A

Notes

17. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).

18. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

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IDD VDD operating supply current VDD = Max, IOUT = 0 mA,

f = fMAX = 1/tCYC

5 ns cycle,

200 MHz

–220mA

6 ns cycle,

166 MHz

–180mA

ISB1 Automatic CE power-down

current – TTL inputs

VDD = Max, device deselected,

VIN  VIH or VIN  VIL,

f = fMAX = 1/tCYC

5 ns cycle,

200 MHz

–120mA

6 ns cycle,

166 MHz

–110mA

ISB2 Automatic CE power-down

current – CMOS inputs

VDD = Max, device deselected,

VIN  0.3 V or VIN > VDDQ – 0.3 V,

f = 0

All speeds – 40 mA

ISB3 Automatic CE power-down

current – CMOS inputs

VDD = Max, device deselected, or

VIN  0.3 V or VIN > VDDQ – 0.3 V,

f = fMAX = 1/tCYC

5 ns cycle,

200 MHz

–110mA

6 ns cycle,

166 MHz

–100mA

ISB4 Automatic CE power-down

current – TTL inputs

VDD = Max, device deselected,

VIN  VIH or VIN  VIL, f = 0

All speeds – 40 mA

Electrical Characteristics (continued)

Over the Operating Range

Parameter [17, 18] Description Test Conditions Min Max Unit

Capacitance

Parameter [19] Description Test Conditions 100-pin TQFP

Max

119-ball BGA

Max

165-ball FBGA

Max Unit

CIN Input capacitance TA = 25 °C, f = 1 MHz,

VDD = 3.3 V, VDDQ = 2.5 V

555pF

CCLK Clock input capacitance 5 5 5 pF

CI/O Input/output capacitance 5 7 7 pF

Thermal Resistance

Parameter [19] Description Test Conditions 100-pin TQFP

Package

119-ball BGA

Package

165-ball FBGA

Package Unit

JA Thermal resistance

(junction to ambient)

Test conditions follow

standard test methods and

procedures for measuring

thermal impedance,

according to EIA/JESD51.

29.41 34.1 16.8 °C/W

JC Thermal resistance

(junction to case)

6.13 14.0 3 °C/W

Note

19. Tested initially and after any design or process change that may affect these parameters.

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Document Number: 38-05540 Rev. *U Page 24 of 38

AC Test Loads and Waveforms

Figure 5. AC Test Loads and Waveforms

OUTPUT

R = 317 

R = 351 

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50 

Z0= 50 

= 1.5 V

3.3 V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

1 ns 1 ns

(c)

OUTPUT

R = 1667 

R =1538 

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50 

Z0= 50 

VT = 1.25 V

2.5 V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

1 ns 1 ns

(c)

3.3 V I/O Test Load

2.5 V I/O Test Load

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 25 of 38

Switching Characteristics

Over the Operating Range

Parameter [20, 21] Description -200 -166 Unit

Min Max Min Max

tPOWER VDD(typical) to the first access [22] 1–1–ms

Clock

tCYC Clock cycle time 5.0 – 6.0 – ns

tCH Clock HIGH 2.0 – 2.4 – ns

tCL Clock LOW 2.0 – 2.4 – ns

Output Times

tCO Data output valid after CLK rise – 3.0 – 3.5 ns

tDOH Data output hold after CLK rise 1.25 – 1.25 – ns

tCLZ Clock to low Z [23, 24, 25] 1.25 – 1.25 – ns

tCHZ Clock to high Z [23, 24, 25] 1.25 3.0 1.25 3.5 ns

tOEV OE LOW to output valid – 3.0 – 3.5 ns

tOELZ OE LOW to output low Z [23, 24, 25] 0–0–ns

tOEHZ OE HIGH to output high Z [23, 24, 25] – 3.0 – 3.5 ns

Set-up Times

tAS Address setup before CLK rise 1.5 – 1.5 – ns

tADS ADSC, ADSP setup before CLK rise 1.5 – 1.5 – ns

tADVS ADV setup before CLK rise 1.5 – 1.5 – ns

tWES GW, BWE, BWX setup before CLK rise 1.5 – 1.5 – ns

tDS Data input setup before CLK rise 1.5 – 1.5 – ns

tCES Chip enable setup before CLK rise 1.5 – 1.5 – ns

Hold Times

tAH Address hold after CLK rise 0.5 – 0.5 – ns

tADH ADSP, ADSC hold after CLK rise 0.5 – 0.5 – ns

tADVH ADV hold after CLK rise 0.5 – 0.5 – ns

tWEH GW, BWE, BWX hold after CLK rise 0.5 – 0.5 – ns

tDH Data input hold after CLK rise 0.5 – 0.5 – ns

tCEH Chip enable hold after CLK rise 0.5 – 0.5 – ns

Notes

20. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.

21. Test conditions shown in (a) of Figure 5 on page 24 unless otherwise noted.

22. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can

be initiated.

23. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 5 on page 24. Transition is measured ± 200 mV from steady-state voltage.

24. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

high Z prior to low Z under the same system conditions.

25. This parameter is sampled and not 100% tested.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 26 of 38

Switching Waveforms

Figure 6. Read Cycle Timing [26]

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

GW, BWE,

BWx

ata Out (Q) High-Z

tCLZ

tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

ADV

suspends

burst.

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2) Q(A2 + 1) Q(A2 + 2)

Q(A1) Q(A2) Q(A2 + 1)Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

DON’T CARE UNDEFINED

Note

26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 27 of 38

Figure 7. Write Cycle Timing [27, 28]

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

ata Out (Q)

High-Z

ADV

BURST READ BURST WRITE

D(A2) D(A2 + 1) D(A2 + 1)

D(A1) D(A3) D(A3 + 1) D(A3 + 2)D(A2 + 3)

A2 A3

Data In (D)

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

tOEHZ

tADVH

ADVS

tWEH

tWES

tDH

tDS

tWEH

tWES

Byte write signals are

ignored for rst cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

Notes

27. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

28. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 28 of 38

Figure 8. Read/Write Cycle Timing [29, 30, 31]

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

ata Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READBack-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4) Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

DON’T CARE UNDEFINED

Notes

29. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

30. The data bus (Q) remains in high Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.

31. GW is HIGH.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 29 of 38

Figure 9. ZZ Mode Timing [32, 33]

Switching Waveforms (continued)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

Notes

32. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

33. DQs are in high Z when exiting ZZ sleep mode.

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 30 of 38

Ordering Code Definitions

Ordering Information

The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your

local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary

page at http://www.cypress.com/products

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the

office closest to you, visit us at http://www.cypress.com/go/datasheet/offices

Speed

(MHz) Ordering Code Package

Diagram Part and Package Type Operating

Range

166 CY7C1360C-166AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (3 chip enable) Commercial

CY7C1362C-166AJXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (2 chip enable)

CY7C1360C-166BZC 51-85180 165-ball FBGA (13 × 15 × 1.4 mm)

CY7C1360C-166AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (3 chip enable) Industrial

200 CY7C1360C-200AXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (3 chip enable) Commercial

CY7C1360C-200AJXC 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free (2 chip enable)

CY7C1360C-200BGC 51-85115 119-ball BGA (14 × 22 × 2.4 mm)

Temperature range: X = C or I

C = Commercial; I = Industrial

Pb-free

Package Type: XX = A or AJ or BZ or BG

A = 100-pin TQFP (3 chip enable)

AJ = 100-pin TQFP (2 chip enable)

BZ = 165-ball FBGA

BG = 119-ball BGA

Speed Grade: XXX = 166 MHz or 200 MHz

Process Technology: C  90 nm

Part Identifier: 13XX = 1360 or 1362

1360 = SCD, 256K × 36 (9Mb)

1362 = SCD, 512K × 18 (9Mb)

Technology Code: C = CMOS

Marketing Code: 7 = SRAM

Company ID: CY = Cypress

C 13XX C - XXX XXXCY 7 X

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 31 of 38

Package Diagrams

Figure 10. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050

ș1

ș2

NOTE:

3. JEDEC SPECIFICATION NO. REF: MS-026.

2. BODY LENGTH DIMENSION DOES NOT

MOLD PROTRUSION/END FLASH SHALL

1. ALL DIMENSIONS ARE IN MILLIMETERS.

BODY SIZE INCLUDING MOLD MISMATCH.

L11.00 REF

0.45 0.60 0.75

0.20

NOM.MIN.

0°

0.08

1.35 1.40

SYMBOL MAX.

7°

0.20

1.45

1.60

0.15

b0.22 0.30 0.38

e0.65 TYP

DIMENSIONS

R0.08

L20.25 BSC

0.05

0.20

INCLUDE MOLD PROTRUSION/END FLASH.

15.80 16.00 16.20

13.90 14.00 14.10 NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.

BODY LENGTH DIMENSIONS ARE MAX PLASTIC

21.80 22.00 22.20

19.90 20.00 20.10

L30.20

0°ș1

11° 13°ș212°

51-85050 *G

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 32 of 38

Figure 11. 119-ball PBGA (14 × 22 × 2.4 mm) BG119 Package Outline, 51-85115

Package Diagrams (continued)

51-85115 *D

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 33 of 38

Figure 12. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.5 Ball Diameter) Package Outline, 51-85180

Package Diagrams (continued)

51-85180 *G

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 34 of 38

Acronyms Document Conventions

Units of Measure

Acronym Description

BGA Ball Grid Array

CE Chip Enable

CMOS Complementary Metal Oxide Semiconductor

EIA Electronic Industries Alliance

FBGA Fine-Pitch Ball Grid Array

I/O Input/Output

JEDEC Joint Electron Devices Engineering Council

JTAG Joint Test Action Group

LMBU Logical Multi-Bit Upsets

LSB Least Significant Bit

LSBU Logical Single-Bit Upsets

MSB Most Significant Bit

OE Output Enable

PBGA Plastic Ball Grid Array

SEL Single Event Latch-up

SRAM Static Random Access Memory

TAP Test Access Port

TCK Test Clock

TDI Test Data-In

TDO Test Data-Out

TMS Test Mode Select

TQFP Thin Quad Flat Pack

TTL Transistor-Transistor Logic

Symbol Unit of Measure

°C degree Celsius

MHz megahertz

µA microampere

mA milliampere

mm millimeter

ms millisecond

mV millivolt

ns nanosecond

ohm

% percent

pF picofarad

Vvolt

Wwatt

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 35 of 38

Document History Page

Document Title: CY7C1360C/CY7C1362C, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM

Document Number: 38-05540

Rev. ECN No. Orig. of

Change

Submission

Date Description of Change

** 241690 RKF 07/12/2004 New data sheet.

*A 278130 RKF 10/15/2004 Updated Boundary Scan Order (Changed to match the B rev of these devices).

Updated Boundary Scan Order (Changed to match the B rev of these devices).

Updated Ordering Information (Updated part numbers; added comment of

Lead-free BG and BZ packages availability).

*B 248929 VBL 11/01/2004 Updated Functional Overview (Updated ZZ Mode Electrical Characteristics

(Changed maximum value of IDDZZ parameter from 35 mA to 50 mA)).

Updated Electrical Characteristics:

Changed maximum value of ISB1 and ISB3 parameter from 50 mA to the values

as follows:

ISB1: 225 MHz -> 130 mA, 200 MHz -> 120 mA, 166 MHz -> 110 mA

ISB3: 225 MHz -> 120 mA, 200 MHz -> 110 mA, 166 MHz -> 100 mA.

Updated Ordering Information (Updated part numbers).

*C 323636 PCI 02/22/2005 Updated Features (Changed frequency from 225 MHz to 250 MHz).

Updated Selection Guide (Changed frequency from 225 MHz to 250 MHz).

Updated Pin Configurations (Modified address expansion as per JEDEC

Standard).

Updated Electrical Characteristics (Changed frequency from 225 MHz to

250 MHz).

Updated Thermal Resistance (Changed value of JA and JC parameters for

100-pin TQFP Package from 25 C/W and 9 C/W to 29.41 C/W and

6.13 C/W respectively; changed value of JA and JC parameters for 119-ball

BGA Package from 25 C/W and 6 C/W to 34.1 C/W and 14.0 C/W

respectively; changed value of JA and JC parameters for 165-ball FBGA

Package from 27 C/W and 6 C/W to 16.8 C/W and 3.0 C/W respectively).

Updated Switching Characteristics (Changed frequency from 225 MHz to

250 MHz; replaced minimum value of tCYC parameter from 4.4 ns to 4.0 ns for

250 MHz frequency).

Updated Ordering Information (No change in part numbers; removed comment

of Lead-free BG and BZ packages availability).

*D 332879 PCI 03/13/2005 Updated Selection Guide (Unshaded 200 and 166 MHz frequency

information).

Updated Pin Definitions (Added Address Expansion pins).

Updated Identification Register Definitions (Splitted Device Width (23:18) into

two rows; retained the same values for 165-ball FBGA, changed Device Width

(23:18) for 119-ball BGA from 000000 to 101000).

Updated Electrical Characteristics (Updated Test Conditions of VOH, VOL

parameters; unshaded 200 and 166 MHz frequency information).

Updated Switching Characteristics (Unshaded 200 and 166 MHz frequency

information).

Updated Ordering Information (Updated part numbers).

*E 357258 PCI 05/05/2005 Changed status from Preliminary to Final.

Updated Selection Guide (Unshaded 250 MHz frequency information).

Updated Electrical Characteristics (Unshaded 250 MHz frequency information,

changed maximum value of ISB2 parameter from 30 to 40 mA).

Updated Switching Characteristics (Unshaded 250 MHz frequency

information)

Updated Ordering Information (Updated part numbers).

*F 377095 PCI 06/10/2005 Updated Electrical Characteristics (Updated Note 18 (Modified test condition

from VDDQ < VDD to VDDQ  VDD)).

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 36 of 38

*G 408298 RXU 11/16/2005 Changed address of Cypress Semiconductor Corporation from “3901 North

First Street” to “198 Champion Court”.

Updated Electrical Characteristics (Changed “Input Load Current except ZZ

and MODE” to “Input Leakage Current except ZZ and MODE” in the description

of IX parameter).

Updated Ordering Information (Updated part numbers; replaced Package

Name column with Package Diagram in the Ordering Information table).

Replaced three-state with tri-state in all instances across the document.

Updated to new template.

*H 501793 VKN 09/13/2006 Updated TAP AC Switching Characteristics (Changed minimum value of tTH,

tTL parameters from 25 ns to 20 ns, and maximum value of tTDOV parameter

from 5 ns to 10 ns).

Updated Maximum Ratings (Added Maximum Rating for Supply Voltage on

VDDQ Relative to GND).

Updated Ordering Information (Updated part numbers).

*I 2756340 VKN /

AESA

08/26/2009 Added Neutron Soft Error Immunity.

Updated Ordering Information (Updated part numbers; and modified the

disclaimer for the Ordering information).

Updated to new template.

*J 3046851 NJY 10/04/2010 Updated Ordering Information:

No change in part numbers.

Added Ordering Code Definitions.

Updated Package Diagrams

spec 51-85050 – Changed revision from *B to *C.

spec 51-85115 – Changed revision from *B to *C.

spec 51-85180 – Changed revision from *B to *C.

Added Acronyms and Units of Measure.

Minor edits.

Updated to new template.

Completing Sunset Review.

*K 3052882 NJY 10/11/2010 Updated Ordering Information (Updated part numbers).

*L 3367594 PRIT 09/09/2011 Updated Package Diagrams:

spec 51-85050 – Changed revision from *C to *D.

Updated to new template.

Completing Sunset Review.

*M 3612494 PRIT 05/09/2012 Updated Features (Removed 250 MHz frequency related information).

Updated Functional Description (Removed the Note “For best-practices

recommendations, refer to the Cypress application note System Design

Guidelines on www.cypress.com.” and its reference).

Updated Selection Guide (Removed 250 MHz frequency related information).

Updated Pin Configurations ( Up da te d Figure 1 (Removed CY7C1362C related

information, updated Figure 3 (Removed CY7C1362C related information),

updated Figure 4 (Removed CY7C1362C related information)).

Updated Functional Overview (Removed 250 MHz frequency related

information).

Updated IEEE 1149.1 Serial Boundary Scan (JTAG) (Removed CY7C1362C

related information).

Updated Identification Register Definitions (Removed CY7C1362C related

information).

Updated Scan Register Sizes (Removed “Bit Size (× 18)” column).

Updated Boundary Scan Order (Removed CY7C1362C related information).

Document History Page (continued)

Document Title: CY7C1360C/CY7C1362C, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM

Document Number: 38-05540

Rev. ECN No. Orig. of

Change

Submission

Date Description of Change

CY7C1360C

CY7C1362C

Document Number: 38-05540 Rev. *U Page 37 of 38

*M (cont.) 3612494 PRIT 05/09/2012 Updated Electrical Characteristics (Removed 250 MHz frequency related

information).

Updated Switching Characteristics (Removed 250 MHz frequency related

information).

Updated Package Diagrams:

spec 51-85180 – Changed revision from *C to *E.

*N 3754566 PRIT 09/25/2012 Updated Package Diagrams:

spec 51-85115 – Changed revision from *C to *D.

spec 51-85180 – Changed revision from *E to *F.

Completing Sunset Review.

*O 4539022 PRIT 10/15/2014 Updated Package Diagrams:

spec 51-85050 – Changed revision from *D to *E.

Updated to new template.

Completing Sunset Review.

*P 4574263 PRIT 11/19/2014 Updated Functional Description:

Added “For a complete list of related documentation, click here.” at the end.

*Q 4973995 PRIT 10/19/2015 Updated Package Diagrams:

spec 51-85180 – Changed revision from *F to *G.

Updated to new template.

Completing Sunset Review.

*R 5515711 PRIT 11/09/2016 Updated Package Diagrams:

spec 51-85050 – Changed revision from *E to *F.

Updated to new template.

Completing Sunset Review.

*S 6026108 RMES 01/11/2018 Updated Package Diagrams:

spec 51-85050 – Changed revision from *F to *G.

Updated to new template.

Completing Sunset Review.

*T 6112808 NILE 03/28/2018 Updated Package Diagrams:

No change in revisions.

Replaced “16.0 × 22.0 × 1.6 mm” with “14.0 × 20.0 × 1.4 mm” in caption of spec

51-85050 *G.

*U 6518507 RMES 03/22/2019 Updated Ordering Information:

Updated part numbers.

Updated to new template.

Document History Page (continued)

Document Title: CY7C1360C/CY7C1362C, 9-Mbit (256K × 36/512K × 18) Pipelined SRAM

Document Number: 38-05540

Rev. ECN No. Orig. of

Change

Submission

Date Description of Change

Document Number: 38-05540 Rev. *U Revised March 22, 2019 Page 38 of 38

i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation.

CY7C1360C

CY7C1362C

firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress

reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property

rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants

you a personal, non-exclusive, nontransferable license (without the right to subl icense) (1) under its copyr ight rights in the Software (a) for Software provided in source code form, to modify and reproduce

the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or

indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as provided by

Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the

Software is prohibited.

TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE

OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing

device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such

as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING

CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, “Security

Breach”). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In

addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted

by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or

circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the

responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. “High-Risk Device”

means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other

medical devices. “Critical Component” means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk

Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of

a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from

and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress

product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)

Cypress’s published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to

use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.

Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in

the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.

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closest to you, visit us at Cypress Locations.

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