S-35390A
www.ablicinc.com 2-WIRE REAL-TIME CLOCK
© ABLIC Inc., 2004-2016 Rev.4.2_03
1
The S-35390A is a CMOS 2-wire real-time clock IC which operates with the very low current consumption in the wide range of
operation voltage. The operation voltage is 1.3 V to 5.5 V so that the S-35390A can be used for various power supplies from
main supply to backup battery. Due to the 0.25 A current consumption and wide range of power supply voltage at time
keeping, the S-35390A makes the battery life longer. In the system which operates with a backup battery, the included free
registers can be used as the function for user's backup memory. Users always can take back the information in the registers
which is stored before power-off the main power supply, after the voltage is restored.
The S-35390A has the function to correct advance / delay of the clock data speed, in the wide range, which is caused by the
crystal oscillation circuit's frequency deviation. Correcting according to the temperature change by combining this function
and a temperature sensor, it is possible to make a high precise clock function which is not affected by the ambient
temperature.
Features
Low current consumption: 0.25 A typ. (VDD = 3.0 V, Ta = 25C)
Wide range of operating voltage: 1.3 V to 5.5 V
Built-in clock correction function
Built-in free user register
2-wire (I2C-bus) CPU interface
Built-in alarm interrupter
Built-in flag generator during detection of low power voltage or at power-on
Auto calendar up to the year 2099, automatic leap year calculation function
Built-in constant voltage circuit
Built-in 32.768 kHz crystal oscillator (built-in Cd, external Cg)
Lead-free, Sn 100%, halogen-free*1
*1. Refer to " Product Name Structure" for details.
Applications
Mobile game device
Mobile AV device
Digital still camera
Digital video camera
Electronic power meter
DVD recorder
TV, VCR
Mobile phone, PHS
Packages
8-Pin SOP (JEDEC)
8-Pin TSSOP
SNT-8A
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
2
Block Diagram
Real-time data register
Status register 1
Oscillation
circuit
SCL
SDA
Low power supply
voltage detector
VDD
VSS
Comparator 1
Shift register Serial
interface
XIN
XOUT
INT2
Comparator 2
Clock correction register
INT1
controller
Divider,
timing generator
INT2
controller
Constant-voltage
circuit
Status register 2
INT1 register
INT2 register
Power-on
detection circuit
Free register
INT1
Day Month Year
Day of
the week
Minute
Hour
Second
Figure 1
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
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Product Name Structure
1. Product name
1. 1 8-Pin SOP (JEDEC), 8-Pin TSSOP
S-35390A - xxxx x
Product name
Environmental code
U: Lead-free (Sn 100%), halogen-free
G: Lead-free (for details, please contact our sales office)
Package name (abbreviation) and IC packing specification*1
J8T1: 8-Pin SOP (JEDEC), Tape
T8T1: 8-Pin TSSOP, Tape
*1. Refer to the tape drawing.
1. 2 SNT-8A
S-35390A - I8T1 U
Product name
Environmental code
U: Lead-free (Sn 100%), halogen-free
Package name (abbreviation) and IC packing specification*1
I8T1: SNT-8A, Tape
*1. Refer to the tape drawing.
2. Packages
Table 1 Package Drawing Codes
Package Name Dimension Tape Reel Land
8-Pin SOP (JEDEC) Environmental code = G FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-SD
Environmental code = U FJ008-A-P-SD FJ008-D-C-SD FJ008-D-R-S1
8-Pin TSSOP Environmental code = G FT008-A-P-SD FT008-E-C-SD FT008-E-R-SD
Environmental code = U FT008-A-P-SD FT008-E-C-SD FT008-E-R-S1
SNT-8A PH008-A-P-SD PH008-A-C-SD PH008-A-R-SD PH008-A-L-SD
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
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Pin Configurations
1. 8-Pin SOP (JEDEC)
7
6
5
8
2
3
4
1
Top view
Figure 2 S-35390A-J8T1x
2. 8-Pin TSSOP
7
6
5
8
2
3
4
1
Top view
Figure 3 S-35390A-T8T1x
3. SNT-8A
7
6
5
8
2
3
4
1
Top view
Figure 4 S-35390A-I8T1U
Table 2 List of Pins
Pin No Symbol Description I/O Configuration
1 1INT Output pin for
interrupt signal 1 Output Nch open-drain output
(no protective diode at VDD)
2 XOUT Connection pins
for crystal
oscillator
3 XIN
4 VSS GND pin
5 2INT Output pin for
interrupt signal 2 Output Nch open-drain output
(no protective diode at VDD)
6 SCL Input pin for
serial clock Input CMOS input
(no protective diode at VDD)
7 SDA I/O pin for serial
data Bi-directional
Nch open-drain output
(no protective diode at VDD)
CMOS input
8 VDD Pin for positive
power supply
Remark 1. x: G or U
2. Please select products of environmental code = U for Sn 100%, halogen-free products.
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
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Pin Functions
1. SDA (I/O for serial data) pin
This is a data input / output pin of I2C-bus interface. This pin inputs / outputs data by synchronizing with a clock pulse
from the SCL pin. This pin has CMOS input and Nch open-drain output. Generally in use, pull up this pin to the VDD
potential via a resistor, and connect it to any other device having open drain or open collector output with wired-OR
connection.
2. SCL (input for serial clock) pin
This pin is to input a clock pulse for I2C-bus interface. The SDA pin inputs / outputs data by synchronizing with the
clock pulse.
3. XIN, XOUT (crystal oscillator connect) pins
Connect a crystal oscillator between XIN and XOUT.
4. INT1 (output for interrupt signal 1) pin
This pin outputs a signal of interrupt, or a clock pulse. By using the status register 2, users can select either of; alarm 1
interrupt, output of user-set frequency, minute-periodical interrupt 1, minute-periodical interrupt 2, or 32.768 kHz output.
This pin has Nch open-drain output.
5. INT2 (output for interrupt signal 2) pin
This pin outputs a signal of interrupt, or a clock pulse. By using the status register 2, users can select either of; alarm 2
interrupt, output of user-set frequency, or minute-periodical interrupt 1. This pin has Nch open-drain output.
6. VDD (positive power supply) pin
Connect this VDD pin with a positive power supply. Regarding the values of voltage to be applied, refer to
" Recommended Operation Conditions".
7. VSS pin
Connect this VSS pin to GND.
Equivalent Circuits of Pins
SDA
Figure 5 SDA Pin
SCL
Figure 6 SCL Pin
INT1, INT2
Figure 7 INT1 Pin, INT2 Pin
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
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Absolute Maximum Ratings
Table 3
Item Symbol Applied Pin Absolute Maximum Rating Unit
Power supply voltage VDD V
SS 0.3 to VSS 6.5 V
Input voltage VIN SCL, SDA VSS 0.3 to VSS 6.5 V
Output voltage VOUT SDA,
INT1, INT2 V
SS 0.3 to VSS 6.5 V
Operating ambient
temperature*1 Topr 40 to 85 C
Storage temperature Tst
g
55 to 125 C
*1. Conditions with no condensation or frost. Condensation or frost causes short-circuiting between pins, resulting in a
malfunction.
Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical
damage. These values must therefore not be exceeded under any conditions.
Recommended Operation Conditions
Table 4
(VSS = 0 V)
Item Symbol Condition Min. Typ. Max. Unit
Power supply voltage*1 VDD Ta = 40C to 85C 1.3 3.0 5.5 V
Time keeping power
supply voltage*2 VDDT Ta = 40C to 85C VDET 0.15 5.5 V
Crystal oscillator CL value CL 6 7 pF
*1. The power supply voltage that allows communication under the conditions shown in Table 9 of " AC Electrical
Characteristics".
*2. The power supply voltage that allows time keeping. For the relationship with VDET (low power supply voltage detection
voltage), refer to " Characteristics (Typical Data)".
Oscillation Characteristics
Table 5
(Ta =
25
C, V
DD
= 3.0 V, V
SS
= 0 V, VT-200 crystal oscillator (C
L
= 6 pF, 32.768 kHz) manufactured by Seiko Instruments Inc.)
Item Symbol Condition Min. Typ. Max. Unit
Oscillation start voltage VSTA Within 10 seconds 1.1 5.5 V
Oscillation start time tSTA 1 s
IC-to-IC frequency
deviation*1 IC 10 10 ppm
Frequency voltage
deviation V VDD = 1.3 V to 5.5 V 3 3 ppm/V
External capacitance C
g
Applied to XIN pin 9.1 pF
Internal oscillation
capacitance Cd Applied to XOUT pin 8 pF
*1. Reference value
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
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DC Electrical Characteristics
Table 6 DC Characteristics (VDD = 3.0 V)
(Ta
40
C to
85
C, V
SS
= 0 V,VT-200 crystal oscillator (C
L
= 6 pF, 32.768 kHz, C
g
= 9.1 pF) manufactured by Seiko Instruments Inc.)
Item Symbol Applied Pin Condition Min. Typ. Max. Unit
Current consumption 1 IDD1 Out of communication 0.25 0.93 A
Current consumption 2 IDD2 During communication
(SCL = 100 kHz) 6 14 A
Input current leakage 1 IIZH SCL, SDA VIN = VDD 0.5 0.5 A
Input current leakage 2 IIZL SCL, SDA VIN = VSS 0.5 0.5 A
Output current leakage 1 IOZH
SDA, 1INT ,
2INT
VOUT = VDD 0.5 0.5 A
Output current leakage 2 IOZL
SDA, 1INT ,
2INT
VOUT = VSS 0.5 0.5 A
Input voltage 1 VIH SCL, SDA 0.8 VDD V
SS 5.5 V
Input voltage 2 VIL SCL, SDA V
SS 0.3 0.2 VDD V
Output current 1 IOL1 1INT , 2INT VOUT = 0.4 V 3 5 mA
Output current 2 IOL2 SDA VOUT = 0.4 V 5 10 mA
Power supply voltage
detection voltage VDET 0.65 1 1.35 V
Table 7 DC Characteristics (VDD = 5.0 V)
(Ta
40
C to
85
C, V
SS
= 0 V, VT-200 crystal oscillator (C
L
= 6 pF, 32.768 kHz, C
g
= 9.1 pF) manufactured by Seiko Instruments Inc.)
Item Symbol Applied Pin Condition Min. Typ. Max. Unit
Current consumption 1 IDD1 Out of communication 0.3 1.1 A
Current consumption 2 IDD2 During communication
(SCL = 100 kHz) 14 30 A
Input current leakage 1 IIZH SCL, SDA VIN = VDD 0.5 0.5 A
Input current leakage 2 IIZL SCL, SDA VIN = VSS 0.5 0.5 A
Output current leakage 1 IOZH
SDA, 1INT ,
2INT
VOUT = VDD 0.5 0.5 A
Output current leakage 2 IOZL
SDA, 1INT ,
2INT
VOUT = VSS 0.5 0.5 A
Input voltage 1 VIH SCL, SDA 0.8 VDD V
SS 5.5 V
Input voltage 2 VIL SCL, SDA V
SS 0.3 0.2 VDD V
Output current 1 IOL1 1INT , 2INT VOUT = 0.4 V 5 8 mA
Output current 2 IOL2 SDA VOUT = 0.4 V 6 13 mA
Power supply voltage
detection voltage VDET 0.65 1 1.35 V
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
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AC Electrical Characteristics
Table 8 Measurement Conditions
SDA
C = 100 pF
V
DD
R = 1 k
Input pulse voltage VIH = 0.9 VDD, VIL = 0.1 VDD
Input pulse rise / fall time 20 ns
Output determination voltage VOH = 0.5 VDD, VOL = 0.5 VDD
Output load 100 pF pull-up resistor 1 k
Remark The power supplies of the IC
and load have the same
electrical potential.
Figure 8 Output Load Circuit
Table 9 AC Electrical Characteristics
(Ta = 40C to 85C)
Item Symbol VDD*2 1.3 V VDD*2 3.0 V Unit
Min. Typ. Max. Min. Typ. Max.
SCL clock frequency fSCL 0 100 0 400 kHz
SCL clock low time tLOW 4.7
1.3
s
SCL clock high time tHIGH 4 0.6 s
SDA output delay time*1 tPD 3.5 0.9 s
Start condition setup time tSU.STA 4.7 0.6 s
Start condition hold time tHD.STA 4
0.6
s
Data input setup time tSU.DAT 250 100 ns
Data input hold time tHD.DAT 0 0 s
Stop condition setup time tSU.STO 4.7 0.6 s
SCL, SDA rise time tR 1 0.3 s
SCL, SDA fall time tF
0.3
0.3 s
Bus release time tBUF 4.7 1.3 s
Noise suppression time tI 100 50 ns
*1. Since the output format of the SDA pin is Nch open-drain output, SDA output delay time is determined by the values of
the load resistance (RL) and load capacity (CL) outside the IC. Therefore, use this value only as a reference value.
*2. Regarding the power supply voltage, refer to " Recommended Operation Conditions".
SCL
SDA
(S-35390A input)
SDA
(S-35390A output)
t
BUF
t
R
t
SU.STO
t
SU.DAT
t
HD.DAT
t
PD
t
HIGH
t
LOW
t
HD.STA
t
SU.STA
t
F
Figure 9 Bus Timing
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
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Configuration of Data Communication
1. Data communication
For data communication, the master device in the system generates a start condition for the S-35390A. Next, the
master device transmits 4-bit device code "0110", 3-bit command and 1-bit read / write command to the SDA line. After
that, output or input is performed from B7 of data. If data I/O has been completed, finish communication by inputting a
stop condition to the S-35390A. The master device generates an acknowledgment signal for every 1-byte. Regarding
details, refer to " Serial Interface".
Command
0 1 1 0 C2 C1 C0 R / W
Device code
ACK
Read / write bit
Acknowledgment bit
B7 B6 B5 B4 B3 B2 B1 B0 ACK
Start condition
Stop condition
1-byte data
STA
STP
Figure 10 Data Communication
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
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2. Configuration of command
8 types of command are available for the S-35390A. The S-35390A reads / writes the various registers by inputting
these codes and commands. The S-35390A does not perform any operation with any codes and commands other than
those below.
Table 10 List of Commands
Device
Code
Command
Data
C2 C1 C0
Description
B7 B6 B5 B4 B3 B2 B1 B0
0110
0 0 0
Status register 1 access
RESET
*1 24 / 12 SC0*2 SC1*2 INT1*3 INT2*3 BLD*4 POC*4
0 0 1
Status register 2 access INT1FE INT1ME INT1AE
32kE
INT2FE
INT2ME INT2AE
TEST*5
0 1 0
Real-time data 1 access
(year data to)
Y1
M1
D1
W1
H1
m1
s1
Y2
M2
D2
W2
H2
m2
s2
Y4
M4
D4
W4
H4
m4
s4
Y8
M8
D8
*6
H8
m8
s8
Y10
M10
D10
*6
H10
m10
s10
Y20
*6
D20
*6
H20
m20
s20
Y40
*6
*6
*6
PM / AM
m40
s40
Y80
*6
*6
*6
*6
*6
*6
0 1 1
Real-time data 2 access
(hour data to)
H1
m1
s1
H2
m2
s2
H4
m4
s4
H8
m8
s8
H10
m10
s10
H20
m20
s20
PM / AM
m40
s40
*6
*6
*6
1 0 0
INT1 register access
(alarm time 1: week / hour / minute)
(INT1AE = 1, INT1ME = 0,
INT1FE = 0)
W1
H1
m1
W2
H2
m2
W4
H4
m4
*6
H8
m8
*6
H10
m10
*6
H20
m20
*6
PM / AM
m40
A1WE
A1HE
A1mE
INT1 register access
(output of user-set frequency)
(INT1ME = 0, INT1FE = 1)
1 Hz 2 Hz 4 Hz 8 Hz 16 Hz SC2*2 SC3*2 SC4*2
1 0 1
INT2 register access
(alarm time 2: week / hour / minute)
(INT2AE = 1, INT2ME = 0,
INT2FE = 0)
W1
H1
m1
W2
H2
m2
W4
H4
m4
*6
H8
m8
*6
H10
m10
*6
H20
m20
*6
PM / AM
m40
A2WE
A2HE
A2mE
INT2 register access
(output of user-set frequency)
(INT2ME = 0, INT2FE = 1)
1 Hz 2 Hz 4 Hz 8 Hz 16 Hz SC5*2 SC6*2 SC7*2
1 1 0
Clock correction register access
V0 V1 V2 V3 V4 V5 V6 V7
1 1 1
Free register access
F0 F1 F2 F3 F4 F5 F6 F7
*1. Write-only flag. The S-35390A initializes by writing "1" in this register.
*2. Scratch bit. This is a register which is available for read / write operations and can be used by users freely.
*3. Read-only flag. Valid only when using the alarm function. When the alarm time matches, this flag is set to "1", and it is
cleared to "0" when reading.
*4. Read-only flag. "POC" is set to "1" when power is applied. It is cleared to "0" when reading. Regarding "BLD", refer to
" Low Power Supply Voltage Detection Circuit".
*5. Test bit for ABLIC Inc. Be sure to set to "0" in use.
*6. No effect when writing. It is "0" when reading.
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
11
Configuration of Registers
1. Real-time data register
The real-time data register is a 7-byte register that stores the data of year, month, day, day of the week, hour, minute,
and second in the BCD code. To write / read real-time data 1 access, transmit / receive the data of year in B7, month,
day, day of the week, hour, minute, second in B0, in 7-byte. When you skip the procedure to access the data of year,
month, day, day of the week, read / write real-time data 2 accesses. In this case, transmit / receive the data of hour in B7,
minute, second in B0, in 3-byte.
The S-35390A transfers a set of data of time to the real-time data register when it recognizes a reading instruction.
Therefore, the S-35390A keeps precise time even if time-carry occurs during the reading operation of the real-time data
register.
Year data (00 to 99)
Month data (01 to 12)
Day data (01 to 31)
Hour data (00 to 23 or 00 to 11)
Minute data (00 to 59)
Second data (00 to 59)
Y80
Y40
Y4 Y8 Y10 Y20
Y2
Y1
B7 B0
M1 M2 M4 M8 M10 0 0 0
D1 D2 D4 D8 D10 D20 0 0
W1 W2 W4 0 0 0 0 0
H1 H4 H8 H10 H20
H2 0
m1
s2 s4 s8 s10 s20 s40 0
m8 m10 m20 m40 0
m4 m2
AM / PM
s1
Start bit of real-time data 2 data access
Start bit of real-time data 1 data access
Day of the week data (00 to 06)
B7 B0
B7 B0
B7 B0
B7 B0
B7 B0
B7 B0
Figure 11 Real-Time Data Register
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
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Year data (00 to 99): Y1, Y2, Y4, Y8, Y10, Y20, Y40, Y80
Sets the lower two digits of the Western calendar year (00 to 99) and links together with the auto calendar
function until 2099.
Example: 2053 (Y1, Y2, Y4, Y8, Y10, Y20, Y40, Y80) = (1, 1, 0, 0, 1, 0, 1, 0)
Month data (01 to 12): M1, M2, M4, M8, M10
Example: December (M1, M2, M4, M8, M10, 0, 0, 0) = (0, 1, 0, 0, 1, 0 ,0 ,0)
Day data (01 to 31): D1, D2, D4, D8, D10, D20
The count value is automatically changed by the auto calendar function.
1 to 31: Jan., Mar., May, July, Aug., Oct., Dec., 1 to 30: April, June, Sep., Nov.
1 to 29: Feb. (leap year), 1 to 28: Feb. (non-leap year)
Example: 29 (D1, D2, D4, D8, D10, D20, 0, 0) = (1, 0, 0, 1, 0, 1, 0, 0)
Day of the week data (00 to 06): W1, W2, W4
A septenary up counter. Day of the week is counted in the order of 00, 01, 02, …, 06, and 00. Set up day of the
week and the count value.
Hour data (00 to 23 or 00 to 11): H1, H2, H4, H8, H10, H20, AM / PM
In 12-hour mode, write 0; AM, 1; PM in the PM/AM bit. In 24-hour mode, users can write either 0 or 1. 0 is
read when the hour data is from 00 to 11, and 1 is read when from 12 to 23.
Example (12-hour mode): 11 p.m. (H1, H2, H4, H8, H10, H20, PM/AM , 0) = (1, 0, 0, 0, 1, 0, 1, 0)
Example (24-hour mode): 22 (H1, H2, H4, H8, H10, H20, PM/AM , 0) = (0, 1, 0, 0, 0, 1, 1, 0)
Minute data (00 to 59): m1, m2, m4, m8, m10, m20, m40
Example: 32 minutes (m1, m2, m4, m8, m10, m20, m40, 0) = (0, 1, 0, 0, 1, 1, 0, 0)
Example: 55 minutes (m1, m2, m4, m8, m10, m20, m40, 0) = (1, 0, 1, 0, 1, 0, 1, 0)
Second data (00 to 59): s1, s2, s4, s8, s10, s20, s40
Example: 19 seconds (s1, s2, s4, s8, s10, s20, s40, 0) = (1, 0, 0, 1, 1, 0, 0, 0)
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
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2. Status register 1
Status register 1 is a 1-byte register that is used to display and set various modes. The bit configuration is shown below.
B7
RESET 12 / 24
R
R
R
R / W R / W
SC1
B6 B5 B4 B3 B2 B1 B0
BLD INT2 POC INT1
SC0
R
R / W
W
R: Read
W: Write
R / W: Read / write
Figure 12 Status Register 1
B0: POC
This flag is used to confirm whether the power is on. The power-on detection circuit operates at power-on and B0 is
set to "1". This flag is read-only. Once it is read, it is automatically set to "0". When this flag is "1", be sure to initialize.
Regarding the operation after power-on, refer to " Power-on Detection Circuit and Register Status".
B1: BLD
This flag is set to "1" when the power supply voltage decreases to the level of detection voltage (VDET) or less. Users
can detect a drop in the power supply voltage. Once this flag is set to "1", it is not set to "0" again even if the power
supply increases to the level of detection voltage (VDET) or more. This flag is read-only. When this flag is "1", be sure
to initialize. Regarding the operation of the power supply voltage detection circuit, refer to " Low Power Supply
Voltage Detection Circuit".
B2: INT2, B3: INT1
This flag indicates the time set by alarm and when the time has reached it. This flag is set to "1" when the time that
users set by using the alarm interrupt function has come. The INT1 flag at alarm 1 interrupt mode and the INT2 flag
at alarm 2 interrupt mode are set to "1". Set "0" in INT1AE (B5 in the status register 2) or in INT2AE (B1 in the status
register 2) after reading "1" in the INT1 flag or in the INT2 flag. This flag is read-only. Once this flag is read, it is set to
"0" automatically.
B4: SC1, B5: SC0
These flags are SRAM type registers, they are 2 bits as a whole, can be freely set by users.
B6: 24 / 12
This flag is used to set 12-hour or 24-hour mode. Set the flag ahead of write operation of the real-time data register in
case of 24-hour mode.
0: 12-hour mode
1: 24-hour mode
B7: RESET
The internal IC is initialized by setting this bit to "1". This bit is write-only. It is always "0" when reading. When
applying the power supply voltage to the IC, be sure to write "1" to this bit to initialize the circuit. Regarding each
status of registers after initialization, refer to " Register Status After Initialization".
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
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3. Status register 2
Status register 2 is a 1-byte register that is used to display and set various modes. The bit configuration is shown below.
B7
INT1FE INT1ME
R / W R / W
32kE
B6 B5 B4 B3 B2 B1 B0
INT2MEINT2FE
INT1AE
R / W R / W R / W R / W R / W R / W
INT2AE TEST
R / W: Read / write
Figure 13 Status Register 2
B0: TEST
This is a test flag for ABLIC Inc. Be sure to set this flag to "0" in use. If this flag is set to "1", be sure to initialize to set
"0".
B1: INT2AE, B2: INT2ME, B3: INT2FE
These bits are used to select the output mode for the 2INT pin. Table 11 shows how to select the mode. To use an
alarm 2 interrupt, set alarm interrupt mode, then access the INT2 register.
Table 11 Output Modes for 2INT Pin
INT2AE INT2ME INT2FE 2INT Pin Output Mode
0 0 0 No interrupt
*1 0 1 Output of user-set frequency
*1 1 0 Per-minute edge interrupt
*1 1 1 Minute-periodical interrupt 1 (50% duty)
1 0 0 Alarm 2 interrupt
*1. Don't care (both of 0 and 1 are acceptable).
B4: 32kE, B5: INT1AE, B6: INT1ME, B7: INT1FE
These bits are used to select the output mode for the 1INT pin. Table 12 shows how to select the mode. To use
alarm 1 interrupt, access the INT1 register after setting the alarm interrupt mode.
Table 12 Output Modes for 1INT Pin
32kE INT1AE INT1ME INT1FE 1INT Pin Output Mode
0 0 0 0 No interrupt
0 *1 0 1 Output of user-set frequency
0 *1 1 0 Per-minute edge interrupt
0 0 1 1 Minute-periodical interrupt 1 (50% duty)
0 1 0 0 Alarm 1 interrupt
0 1 1 1 Minute-periodical interrupt 2
1 *1 *1 *1 32.768 kHz output
*1. Don't care (both of 0 and 1 are acceptable).
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
15
4. INT1 register and INT2 register
The INT1 and INT2 registers are to set up the output of user-set frequency, or to set up alarm interrupt. Users are able to
switch the output mode by using the status register 2. If selecting to use the output mode for alarm interrupt by status
register 2; these registers work as alarm-time data registers. If selecting the output of user-set frequency by status
register 2; these registers work as data registers to set the frequency for clock output. From each INT1 and INT2 pin,
a clock pulse and alarm interrupt are output.
4. 1 Alarm interrupt
Users can set the alarm time (the data of day of the week, hour, minute) by using the INT1 and INT2 registers which
are 3-byte data registers. The configuration of register is as well as the data register of day of the week, hour, minute,
in the real-time data register; is expressed by the BCD code. Do not set a nonexistent day. Users are necessary to
set up the alarm-time data according to the 12 / 24 hour mode that they set by using the status register 1.
H8H4 H2
H1
A1mE
m8
m4
m2
m1
H20
H10
m10 m20 m40
H8
H4
H2
H1
A2mE
m8
m4m2
m1
H20
H10
m10 m20 m40
AM /
PM
A1WE
0
0
W4
W2 W1
B7 B0
0 0
INT1 register
0
0
W4
W2
W1 0
INT2 register
A2WE
A1HE A2HE
AM /
PM
B7 B0
B7 B0
B7 B0
B7 B0
B7 B0
0
Figure 14 INT1 Register and INT2 Register (Alarm-Time Data)
The INT1 register has A1WE, A1HE, A1mE at B0 in each byte. It is possible to make data valid; the data of day of
the week, hour, minute which are in the corresponding byte; by setting these bits to "1". This is as well in A2WE,
A2HE, A2mE in the INT2 register.
Setting example: alarm time "7:00 pm" in the INT1 register
(1) 12-hour mode (status register 1 B6 = 0)
Set up 7:00 PM
Data written to INT1 register
Day of the week *1 *1 *1 *1 *1 *1 *1 0
Hour 1 1 1 0 0 0 1 1
Minute 0 0 0 0 0 0 0 1
B7 B0
*1. Don't care (both of 0 and 1 are acceptable).
(2) 24-hour mode (status register 1 B6 = 1)
Set up 19:00 PM
Data written to INT1 register
Day of the week *1 *1 *1 *1 *1 *1 *1 0
Hour 1 0 0 1 1 0
1*2 1
Minute 0 0 0 0 0 0 0 1
B7 B0
*1. Don't care (both of 0 and 1 are acceptable).
*2. Set up the PM/AM flag along with the time setting.
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
16
4. 2 Output of user-set frequency
The INT1 and INT2 registers are 1-byte data registers to set up the output frequency. Setting each bit B7 to B3 in the
register to "1", the frequency which corresponds to the bit is output in the AND-form. SC2 to SC4 in the INT1 register,
and SC5 to SC7 in the INT2 register are 3-bit SRAM type registers that can be freely set by users.
B7
R / W R / W
8 Hz
B6 B5 B4 B3 B2 B1 B0
SC2 16 Hz
4 Hz
R / W R / W R / W R / W R / W R / W
SC3 SC4
2 Hz 1 Hz
R / W: Read / write
Figure 15 INT1 Register (Data Register for Output Frequency)
B7
R / W R / W
8 Hz
B6 B5 B4 B3 B2 B1 B0
SC5 16 Hz
4 Hz
R / W R / W R / W R / W R / W R / W
SC6 SC7
2 Hz 1 Hz
R / W: Read / write
Figure 16 INT2 Register (Data Register for Output Frequency)
Example: B7 to B3 = 50h
16 Hz
8 Hz
4 Hz
2 Hz
1 Hz
INT1 pin /
INT2 pin output
Status register 2
•
Set to INT1FE or INT2FE = 1
Figure 17 Example of Output from INT1 and INT2 Registers (Data Register for Output Frequency)
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
17
1 Hz clock output is synchronized with second-counter of the S-35390A.
INT1
pin /
INT2
pin
output (1 Hz)
Second-counter n 1 n 2
n
Figure 18 1 Hz Clock Output and Second-counter
5. Clock correction register
The clock correction register is a 1-byte register that is used to correct advance / delay of the clock. When not using this
function, set this register to "00h". Regarding the register values, refer to " Function of Clock Correction".
B7
R / W R / W
V3
B6 B5 B4 B3 B2 B1 B0
V5 V4
V2
R / W R / W R / W R / W R / W R / W
V6 V7
V1 V0
R / W: Read / write
Figure 19 Clock Correction Register
6. Free register
This free register is a 1-byte SRAM type register that can be set freely by users.
B7
R / W R / W
F3
B6 B5 B4 B3 B2 B1 B0
F5 F4
F2
R / W R / W R / W R / W R / W R / W
F6 F7
F1 F0
R / W: Read / write
Figure 20 Free Register
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
18
Power-on Detection Circuit and Register Status
The power-on detection circuit operates by power-on the S-35390A, as a result each register is cleared; each register is
set as follows.
Real-time data register: 00 (Y), 01 (M), 01 (D), 0 (day of the week), 00 (H), 00 (M), 00 (S)
Status register 1: "01h"
Status register 2: "80h"
INT1 register: "80h"
INT2 register: "00h"
Clock correction register: "00h"
Free register: "00h"
"1" is set in the POC flag (B0 in the status register 1) to indicate that power has been applied. To correct the oscillation
frequency, the status register 2 goes in the mode the output of user-set frequency, so that 1 Hz clock pulse is output from
the 1INT pin. When "1" is set in the POC flag, be sure to initialize. The POC flag is set to "0" due to initialization so that
the output of user-set frequency mode is cleared (Refer to " Register Status After Initialization").
For the regular operation of power-on detection circuit, as seen in Figure 21, the period to power-up the S-35390A is that
the voltage reaches 1.3 V within 10 ms after setting the IC’s power supply voltage at 0 V. When the power-on detection
circuit is not working normally is; the POC flag (B0 in the status register 1) is not in "1", or 1 Hz is not output from the 1INT
pin. In this case, power-on the S-35390A once again because the internal data may be in the indefinite status.
Moreover, regarding the processing right after power-on, refer to " Flowchart of Initialization and Example of
Real-time Data Set-up".
Within 10 ms
1.3 V
0 V
*1
*1. 0 V indicates that there are no potential differences between the VDD
pin and VSS pin of S-35390A.
Figure 21 How to Raise the Power Supply Voltage
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
19
Register Status After Initialization
The status of each register after initialization is as follows.
Real-time data register: 00 (Y), 01 (M), 01 (D), 0 (day of the week), 00 (H), 00 (M), 00 (S)
Status register 1: "0 B6 B5 B4 0 0 0 0 b"
(In B6, B5, B4, the data of B6, B5, B6 in the status register 1 at initialization is set.
Refer to Figure 22.)
Status register 2: "00h"
INT1 register: "00h"
INT2 register: "00h"
Clock correction register: "00h"
Free register: "00h"
18
9 1
0 0 0 1 1 0
START
SCL
SDA
Device code
command
STOP
00
B7 B5
00 0 0 0
0
1 1
18
9 1
000110
START
STOP
01
B7 B5 : Not reset
L L L L
L
LL H
00
Write to status register 1
Read from status register 1
A
CK
A
CK
A
CK
NO_ACK
: S-35390A output data
: Master device input data
R / W R / W
Device code
command
Write "1" to reset flag and SC0.
Figure 22 Data of Status Register 1 at Initialization
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
20
Low Power Supply Voltage Detection Circuit
The S-35390A has a low power supply voltage detection circuit, so that users can monitor drops in the power supply
voltage by reading the BLD flag (B1 in the status register 1). There is a hysteresis width of approx. 0.15 V typ. between
detection voltage and release voltage (refer to " Characteristics (Typical Data)"). The low power supply voltage
detection circuit does the sampling operation only once in one sec for 15.6 ms.
If the power supply voltage decreases to the level of detection voltage (VDET) or less, "1" is set to the BLD flag so that
sampling operation stops. Once "1" is detected in the BLD flag, no sampling operation is performed even if the power
supply voltage increases to the level of release voltage or more, and "1" is held in the BLD flag.
Furthermore, the S-35390A does not initialize the internal circuit even if "1" is set to the BLD flag. If the BLD flag is "1"
even after the power supply voltage is recovered, the internal circuit may be in the indefinite status. In this case, be sure to
initialize the circuit. Without initializing, if the next BLD flag reading is done after sampling, the BLD flag gets reset to "0". In
this case, be sure to initialize although the BLD flag is in "0" because the internal circuit may be in the indefinite status.
V
DD
BLD flag
Stop Stop Stop
Sampling pulse
Hysteresis width
0.15 V approximately
BLD flag reading
Detection voltage
Release
voltage
15.6 ms
1 s 1 s
Time keeping power
supply voltage (min.)
Figure 23 Timing of Low Power Supply Voltage Detection Circuit
Circuits Power-on and Low Power Supply Voltage Detection
Figure 24 shows the changes of the POC flag and BLD flag due to VDD fluctuation.
VDD
BLD flag
Status register 1
readin
g
POC flag
VSS
Low power supply voltage
detection voltage Low power supply voltage
detection voltage
Figure 24 POC Flag and BLD Flag
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
21
Correction of Nonexistent Data and End-of-Month
When users write the real-time data, the S-35390A checks it. In case that the data is invalid, the S-35390A does the
following procedures.
1. Processing of nonexistent data
Table 13 Processing of Nonexistent Data
Register Normal Data Nonexistent Data Result
Year data 00 to 99 XA to XF, AX to FX 00
Month data 01 to 12 00, 13 to 19, XA to XF 01
Day data 01 to 31 00, 32 to 39, XA to XF 01
Day of the week data 0 to 6 7 0
Hour data*1 24-hour 0 to 23 24 to 29, 3X, XA to XF 00
12-hour 0 to 11 12 to 20, XA to XF 00
Minute data 00 to 59 60 to 79, XA to XF 00
Second data*2 00 to 59 60 to 79, XA to XF 00
*1. In 12-hour mode, write the PM/AM flag (B1 in hour data in the real-time data register).
In 24-hour mode, the PM/AM flag in the real-time data register is omitted. However in the flag of reading, users are
able to read 0; 0 to 11, 1; 12 to 23.
*2. Processing of nonexistent data, regarding second data, is done by a carry pulse which is generated in 1 second, after
writing. At this point the carry pulse is sent to the minute-counter.
2. Correction of end-of-month
A nonexistent day, such as February 30 and April 31, is set to the first day of the next month.
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
22
1INT Pin and 2INT Pin Output Mode
These are selectable for the output mode for 1INT and 2INT pins;
Alarm interrupt, the output of user-set frequency, per-minute edge interrupt output, minute-periodical interrupt output 1. In
the 1INT pin output mode, in addition to the above modes, minute-periodical interrupt output 2 and 32.768 kHz output
are also selectable.
To switch the output mode, use the status register 2. Refer to "3. Status register 2" in " Configuration of Registers".
When switching the output mode, be careful of the output status of the pin. Especially, when using alarm interrupt / output
of frequency, switch the output mode after setting "00h" in the INT1 / INT2 register. In 32.768 kHz output / per-minute edge
interrupt output / minute-periodical interrupt output, it is unnecessary to set data in the INT1 / INT2 register for users.
Refer to the followings regarding each operation of output modes.
1. Alarm interrupt output
Alarm interrupt output is the function to output "L" from the 1INT / 2INT pin, at the alarm time which is set by user has
come. If setting the pin output to "H", turn off the alarm function by setting "0" in INT1AE / INT2AE in the status register 2.
To set the alarm time, set the data of day of the week, hour and minute in the INT1 / INT2 register. Refer to "4. INT1
register and INT2 register" in " Configuration of Registers".
1. 1 Alarm setting of "W (day of the week), H (hour), m (minute)"
OFF
*1
INT1AE / INT2AE
mx
Comparator
Hx Wx
INTx register alarm enable flag
• AxHE = AxmE = AxWE = "1"
Status register 2 setting
• INT1 pin output mode
32kE = 0, INT1ME = INT1FE = 0
• INT2 pin output mode
INT2ME = INT2FE = 0
INT1 register
INT2 register
Alarm interrupt
Second
Minute Year
Day of
the week
Day Month
Real-time data
W (day of the week)
01 s 59 s
INT1 pin / INT2 pin
Change by program
Alarm time matches
Period when alarm time matches
Change by program
H h 00 m 00 s
H h (m − 1) m 59 s H h (m + 1) m 00 s
Change by program
Real-time data
Hour
*1. If users clear INT1AE / INT2AE once; "L" is not output from the 1INT / 2INT pin by setting INT1AE / INT2AE enable
again, within a period when the alarm time matches real-time data.
Figure 25 Alarm Interrupt Output Timing
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
23
1. 2 Alarm setting of "H (hour)"
mx
Comparator
Hx Wx Dx Mx Yx
OFF OFF
*1 *1
INT1AE / INT2AE
INT1 pin / INT2 pin
Alarm interrupt
Second
Real-time data
Minute
INT1 register
INT2 register
YearHour
Day of
the week
Day Month
Change by program
Alarm time matches
Period when alarm time matches
Change by program
Real-time data
Alarm time
matches
*2
01 s 59 sH h 00 m 00 s H h 59 m 59 sH h 01 m 00 s (H + 1) h 00 m 00 s
(H - 1) h 59 m 59 s
Change by program Change by program
INTx register alarm enable flag
•
AxHE = AxmE = AxWE = "1"
Status register 2 setting
•
INT1 pin output mode
32kE = 0, INT1ME = INT1FE = 0
•
INT2 pin output mode
INT2ME = INT2FE = 0
*1. If users clear INT1AE / INT2AE once; "L" is not output from the 1INT / 2INT pin by setting INT1AE / INT2AE enable
again, within a period when the alarm time matches real-time data.
*2. If turning the alarm output on by changing the program, within the period when the alarm time matches real-time data,
"L" is output again from the 1INT / 2INT pin when the minute is counted up.
Figure 26 Alarm Interrupt Output Timing
2. Output of user-set frequency
The output of user-set frequency is the function to output the frequency which is selected by using data, from the 1INT
/ 2INT pin, in the AND-form. Set up the data of frequency in the INT1 / INT2 register.
Refer to "4. INT1 register and INT2 register" in " Configuration of Registers".
OFF
INT1FE / INT2FE
INT1 pin / INT2 pin
Change by program
Free-run output starts
Status register 2 setting
• INT1 pin output mode
32kE = 0, INT1AE = Don’t care (0 or 1), INT1ME = 0
• INT2 pin output mode
INT2AE = Don’t care (0 or 1), INT2ME = 0
Figure 27 Output Timing of User-set Frequency
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
24
3. Per-minute edge interrupt output
Per-minute edge interrupt output is the function to output "L" from the 1INT / 2INT pin, when the first minute-carry
processing is done, after selecting the output mode.
To set the pin output to "H", turn off the output mode of per-minute edge interrupt. In the 1INT pin output mode, input
"0" in INT1ME in the status register 2. In the 2INT pin output mode, input "0" in INT2ME.
OFF
INT1ME / INT2ME
INT1 pin / INT2 pin
"L" is output again if this period is within 7.81 ms
*1
.
Change by program
Minute-carry processing Minute-carry
processing
Status register 2 setting
• INT1 pin output mode
32kE = 0, INT1AE = Don’t care (0 or 1), INT1FE = 0
• INT2 pin output mode
INT2AE = Don’t care (0 or 1), INT2FE = 0
*1. Pin output is set to "H" by disabling the output mode within 7.81 ms, because the signal of this procedure is
maintained for 7.81 ms. Note that pin output is set to "L" by setting the output mode enable again.
Figure 28 Timing of Per-Minute Edge Interrupt Output
4. Minute-periodical interrupt output 1
The minute-periodical interrupt 1 is the function to output the one-minute clock pulse (Duty 50%) from the 1INT / 2INT
pin, when the first minute-carry processing is done, after selecting the output mode.
INT1ME, INT1FE
INT2ME, INT2FE
30 s 30 s 30 s 30 s 30 s 30 s 30 s 30 s 30 s
INT1 pin / INT2 pin
Minute-carry
processing Minute-carry
processing
Minute-carry
processing Minute-carry
processing
Minute-carry
processing
"L" is output again if this period is within 7.81 ms
*1
.
Change by program (OFF)
"H" is output again if this period is 7.81 ms or longer.
"L" is output at the next minute-carry processing.
Status register 2 setting
INT1 pin output mode
32kE = 0, INT1AE = 0
INT2 pin output mode
INT2AE = 0
*1. Setting the output mode disable makes the pin output "H", while the output from the 1INT / 2INT pin is in "L".
Note that pin output is set to "L" by setting the output mode enable again.
Figure 29 Timing of Per-Minute Steady Interrupt Output 1
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
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5. Minute-periodical interrupt output 2 (only in the 1INT pin output mode)
The output of minute-periodical interrupt 2 is the function to output "L", for 7.81 ms, from the 1INT pin, synchronizing
with the first minute-carry processing after selecting the output mode. However, during reading in the real-time data
register, the procedure delays at 0.5 seconds max. thus output "L" from the 1INT pin also delays at 0.5 seconds max.
During writing in the real-time data register, some delay is made in the output period due to write timing and the
second-data of writing.
(1) During normal operation
7.81 ms 7.81 ms 7.81 ms
60 s 60 s
INT1 pin
Minute-carry processing Minute-carry processing Minute-carry processing
(2) During reading operation in the real-time data register
7.81 ms 7.81 ms 7.81 ms
INT1 pin
Serial
communication
0.5 s max.
60 s 60 s
Real-time data
read command
Real-time
data reading
Real-time data
read command
Real-time
data reading
Minute-carry processing Minute-carry processing Minute-carry processing
(Normal minute-
carry processing)
(3) During writing operation in the real-time data register
7.81 ms 7.81 ms 7.81 ms
INT1 pin
Real-time data
write timing
55 s 80 s
Minute-carry processing Minute-carry processing Minute-carry processing
45 s 10 s 30 s 50 s
The output period is shorter. The output period is longer.
Second data of writing: "50" s Second data of writing: "10" s
Figure 30 Timing of Minute-periodical Interrupt Output 2
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
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6. Operation of power-on detection circuit (only in the 1INT pin output mode)
When power is applied to the S-35390A, the power-on detection operates to set "1" in the POC flag (B0 in the status
register 1). A 1 Hz clock pulse is output from the 1INT pin.
OFF
INT1FE
• 32kE = 0, INT1AE = INT1ME = 0
Status register 2 setting
INT1 pin
0.5 s
0.5 s
Change by reset command
Figure 31 Output Timing of 1INT Pin during Operation of Power-on Detection Circuit
Function of Clock Correction
The function of clock correction is to correct advance / delay of the clock due to the deviation of oscillation frequency, in
order to make a high precise clock. For correction, the S-35390A adjusts the clock pulse by using a certain part of the
dividing circuit, not adjusting the frequency of the crystal oscillator. Correction is performed once every 20 seconds (or 60
seconds). The minimum resolution is approx. 3 ppm (or approx. 1 ppm) and the S-35390A corrects in the range of 195.3
ppm to 192.2 ppm (or of 65.1 ppm to 64.1 ppm). (Refer to Table 14.) Users can set up this function by using the clock
correction register. Regarding how to calculate the setting data, refer to "1. How to calculate". When not using this
function, be sure to set "00h".
Table 14 Function of Clock Correction
Item B0 = 0 B0 = 1
Correction Every 20 seconds Every 60 seconds
Minimum resolution 3.052 ppm 1.017 ppm
Correction range 195.3 ppm to 192.2 ppm 65.1 ppm to 64.1 ppm
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
27
1. How to calculate
1. 1 If current oscillation frequency > target frequency (in case the clock is fast)
Correction value
*1
= 128 Integral value (Current oscillation frequency
actual measurement value
*2
) (Minimum resolution
*4
)
(Current oscillation frequency
actual measurement value
*2
) (Target oscillation frequency
*3
)
Caution The figure range which can be corrected is that the calculated value is from 0 to 64.
*1. Convert this value to be set in the clock correction register. For how to convert, refer to "(1) Calculation example
1".
*2. Measurement value when 1 Hz clock pulse is output from the 1INT pin (or 2INT pin).
*3. Target value of average frequency when the clock correction function is used.
*4. Refer to "Table 14 Function of Clock Correction".
(1) Calculation example 1
In case of current oscillation frequency actual measurement value = 1.000070 [Hz], target oscillation frequency =
1.000000 [Hz], B0 = 0 (Minimum resolution = 3.052 ppm)
Correction value = 128 Integral value
()
1.000070 ()
1.000000
()
1.000070 ()
3.052 106
= 128
Integral value (22.93) = 128 22 = 106
Convert the correction value "106" to 7-bit binary and obtain "1101010b".
Reverse the correction value "1101010b" and set it to B7 to B1 of the clock correction register.
Thus, set the clock correction register:
(B7, B6, B5, B4, B3, B2, B1, B0) = (0, 1, 0, 1, 0, 1, 1, 0)
1. 2 If current oscillation frequency < target frequency (in case the clock is slow)
Correction value = Integral value (Current oscillation frequency
actual measurement value) (Minimum resolution)
(Current oscillation frequency
actual measurement value)
(Target oscillation frequency)
1
Caution The figure range which can be corrected is that the calculated value is from 0 to 62.
(1) Calculation example 2
In case of current oscillation frequency actual measurement value = 0.999920 [Hz], target oscillation frequency =
1.000000 [Hz]. B0 = 0 (Minimum resolution = 3.052 ppm)
Correction value = Integral value
()
1.000000 ()
0.999920
()
0.999920 ()
3.052 10-6 1
= Integral value (26.21) 1 = 26 1 = 27
Thus, set the clock correction register:
(B7, B6, B5, B4, B3, B2, B1, B0) = (1, 1, 0, 1, 1, 0, 0, 0)
(2) Calculation example 3
In case of current oscillation frequency actual measurement value = 0.999920 [Hz], target oscillation frequency =
1.000000 [Hz], B0 = 1 (Minimum resolution = 1.017 ppm)
Correction value = Integral value
()
1.000000 ()
0.999920
()
0.999920 ()
1.017 10-6 1
= Integral value (78.66) 1
This calculated value exceeds the correctable range 0 to 62.
B0 = "1" (minimum resolution = 1.017 ppm) indicates the correction is impossible.
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
28
2. Setting values for registers and correction values
Table 15 Setting Values for Registers and Correction Values (Minimum Resolution: 3.052 ppm (B0 = 0))
B7 B6 B5 B4 B3 B2 B1 B0 Correction Value
[ppm]
Rate
[s / day]
1 1 1 1 1 1 0 0 192.3 16.61
0 1 1 1 1 1 0 0 189.2 16.35
1 0 1 1 1 1 0 0 186.2 16.09
0 1 0 0 0 0 0 0 6.1 0.53
1 0 0 0 0 0 0 0 3.1 0.26
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 0 3.1 0.26
0 1 1 1 1 1 1 0 6.1 0.53
1 0 1 1 1 1 1 0 9.2 0.79
0 1 0 0 0 0 1 0 189.2 16.35
1 0 0 0 0 0 1 0 192.3 16.61
0 0 0 0 0 0 1 0 195.3 16.88
Table 16 Setting Values for Registers and Correction Values (Minimum Resolution: 1.017 ppm (B0 = 1))
B7 B6 B5 B4 B3 B2 B1 B0 Correction Value
[ppm]
Rate
[s / day]
1 1 1 1 1 1 0 1 64.1 5.54
0 1 1 1 1 1 0 1 63.1 5.45
1 0 1 1 1 1 0 1 62.0 5.36
0 1 0 0 0 0 0 1 2.0 0.18
1 0 0 0 0 0 0 1 1.0 0.09
0 0 0 0 0 0 0 1 0 0
1 1 1 1 1 1 1 1 1.0 0.09
0 1 1 1 1 1 1 1 2.0 0.18
1 0 1 1 1 1 1 1 3.0 0.26
0 1 0 0 0 0 1 1 63.1 5.45
1 0 0 0 0 0 1 1 64.1 5.54
0 0 0 0 0 0 1 1 65.1 5.62
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
29
3. How to confirm setting value for register and result of correction
The S-35390A does not adjust the frequency of the crystal oscillation by using the clock correction function. Therefore
users cannot confirm if it is corrected or not by measuring output 32.768 kHz. When the function of clock correction is
being used, the cycle of 1 Hz clock pulse output from the 1INT pin changes once in 20 times or 60 times, as shown in
Figure 32.
INT1 pin
(1 Hz output)
a a a a
b
In case of B0 = 0: a = 19 times, b = Once
In case of B0 = 1: a = 59 times, b = Once
19 times or 59 times Once
Figure 32 Confirmation of Clock Correction
Measure a and b by using the frequency counter*1. Calculate the average frequency (Tave) based on the measurement
results.
B0 = 0, Tave = (a 19 b) 20
B0 = 1, Tave = (a 59 b) 60
Calculate the error of the clock based on the average frequency (Tave). The following shows an example for
confirmation.
Confirmation example: When B0 = 0, 66h is set
Measurement results: a = 1.000080 Hz, b = 0.998493 Hz
Clock Correction Register Setting Value Average Frequency [Hz] Per Day [s]
Before correction 00 h (Tave = a) 1.000080 86393
After correction 66 h (Tave = (a 19 b) 20) 1.00000065 86399.9
Calculating the average frequency allows to confirm the result of correction.
*1. Use a frequency counter with 7-digit or greater precision.
Caution Measure the oscillation frequency under the usage conditions.
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
30
Serial Interface
The S-35390A transmits / receives various commands via I2C-bus serial interface to read / write data. Regarding
transmission is as follows.
1. Start condition
A start condition is when the SDA line changes "H" to "L" when the SCL line is in "H", so that the access starts.
2. Stop condition
A stop condition is when the SDA line changes "L" to "H" when the SCL line is in "H", and the access stops, so that the
S-35390A gets standby.
t
SU.STA
t
HD.STA
t
SU.STO
Start condition Stop condition
SCL
SDA
Figure 33 Start / Stop Conditions
3. Data transfer and acknowledgment signal
Data transmission is performed for every 1-byte, after detecting a start condition. Transmit data while the SCL line is in
"L", and be careful of spec of tSU.DAT and tHD. DAT when changing the SDA line. If the SDA line changes while the SCL
line is in "H", the data will be recognized as start/stop condition in spite of data transmission. Note that by this case, the
access will be interrupted.
During data transmission, every moment receiving 1-byte data, the devices which work for receiving data send an
acknowledgment signal back. For example, as seen in Figure 34, in case that the S-35390A is the device working for
receiving data and the master device is the one working for sending data; when the 8th clock pulse falls, the master
device releases the SDA line. After that, the S-35390A sends an acknowledgment signal back, and set the SDA line to
"L" at the 9th clock pulse. The S-35390A does not output an acknowledgment signal is that the access is not being
done regularly.
1 89
Output acknowledgment
(Active "L")
t
PD
Start condition
SCL
(S-35390A input)
SDA
(Master device
output)
SDA
(S-35390A output)
SDA is released
t
SU.DAT
t
HD.DAT
High-Z
High-Z
Figure 34 Output Timing of Acknowledgment Signal
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
31
The followings are data reading / writing in the S-35390A.
3. 1 Data reading in the S-35390A
After detecting a start condition, the S-35390A receives device code and command. The S-35390A enters the
read-data mode by the read / write bit "1". The data is output from B7 in 1-byte. Input an acknowledgment signal
from the master device every moment that the S-35390A outputs 1-byte data. However, do not input an
acknowledgment signal (input NO_ACK) for the last data-byte output from the master device. This procedure
notifies the completion of reading. Next, input a stop condition to the S-35390A to finish access.
18
9 1
A
CK
000 1 1 0
START
SCL
SDA
B7 B0
Device code command
NO_ACK
STOP
: S-35390A output data
: Master device input data
01
R / W
Input NO_ACK after the 1st byte
of data has been output.
1-byte data
Figure 35 Example of Data Reading 1 (1-Byte Data Register)
36
9 1
A
CK
1 01 1 0
START
SCL
SDA
B7 B0 B7 B0
NO_ACK
STOP
1
0
A
CK
B0
B7
18 27
A
CK
1
: S-35390A output data
: Master device input data
Input NO_ACK after the 3rd byte of data
has been output.
R / W
3-byte data
Device code command
Figure 36 Example of Data Reading 2 (3-Byte Data Register)
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
32
3. 2 Data writing in the S-35390A
After detecting a start condition, the S-35390A receives device code and command. The S-35390A enters the
write-data mode by the read / write bit "0". Input data from B7 to B0 in 1-byte. The S-35390A outputs an
acknowledgment signal "L" every moment that 1-byte data is input. After receiving the acknowledgment signal
which is for the last byte-data, input a stop condition to the S-35390A to finish access.
18
9 1
A
CK
000110
START
SCL
SDA
B7 B0
A
CK
STOP
: S-35390A output data
: Master device input data
00
R / W
1-byte data
Device code command
Figure 37 Example of Data Writing 1 (1-Byte Data Register)
18
9 1
A
CK
1 0 0 1 10
START
SCL
SDA
B7 B0
A
CK
STOP
: S-35390A output data
: Master device in
p
ut data
1 0
R / W
A
CK
A
CK
27 36
B7 B0 B7 B0
3-byte data
Device code command
Figure 38 Example of Data Reading 2 (3-Byte Data Register)
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
33
4. Data access
4. 1 Real-time data 1 access
72
9 1
ACK
1 0
1
1 0
START
SCL
SDA
Year data Second data
B7 B0 B7 B0
R / W
ACK
*1
STOP
0
0
ACK
*2
I/O mode switching I/O mode switching
ACK
*2
Device code
command
18 63
*1. Set NO_ACK = 1 when reading.
*2. Transmit ACK = 0 from the master device to the S-35390A when reading.
Figure 39 Real-Time Data 1 Access
4. 2 Real-time data 2 access
36
9 1
ACK
1 0 1 1 0
START
SCL
SDA
Hour data Second data
B7 B0 B7 B0
R / W
ACK
*1
STOP
1
0
ACK
*2
I/O mode switching I/O mode switching
B0
B7
Minute data
18 27
ACK
*2
Device code
command
*1. Set NO_ACK = 1 when reading.
*2. Transmit ACK = 0 from the master device to the S-35390A when reading.
Figure 40 Real-Time Data 2 Access
4. 3 Status register 1 access and status register 2 access
18
9
1
ACK
0 0 0 1 1 0
START
I/O mode switching
SCL
SDA
Status data
B7 B0
I/O mode switching
*1 R / W
ACK
*2
STOP
Device code
command
*1. 0: Status register 1 selected, 1: Status register 2 selected
*2. Set NO_ACK = 1 when reading.
Figure 41 Status Register 1 Access and Status Register 2 Access
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
34
4. 4 INT1 register access and INT2 register access
In reading / writing the INT1 and INT2 registers, data varies depending on the setting of the status register 2. Be sure
to read / write after setting the status register 2. When setting the alarm by using the status register 2, these registers
work as 3-byte alarm time data registers, in other statuses, they work as 1-byte registers. When outputting the
user-set frequency, they are the data registers to set up the frequency.
Regarding details of each data, refer to "4. INT1 register and INT2 register" in " Configuration of Registers".
Caution Users cannot use both functions of alarm 1 interrupt and output of user-set frequency for the
1INT pin and 2INT pin simultaneously.
36
9
1
ACK
0 1 0 1 1 0
START
SCL
SDA
Day of the week
data
Minute data
B7 B0 B7 B0
*1 R / W
ACK
*2
STOP
ACK
*3
ACK
*3
I/O mode switching I/O mode switching
27
18
Hour data
B7 B0
Device code
command
*1. 0: INT1 register selected, 1: INT2 register selected
*2. Set NO_ACK = 1 when reading.
*3. Transmit ACK = 0 from the master device to the S-35390A when reading.
Figure 42 INT1 Register Access and INT2 Register Access
18
9
1
ACK
1 0 1 1 0
START
I/O mode switching
SCL
SDA
Frequency
setting data
B7 B0
I/O mode switching
R / W
ACK
*2
STOP
*1
0
Device code
command
*1. 0: INT1 register selected, 1: INT2 register selected
*2. Set NO_ACK = 1 when reading.
Figure 43 INT1 Register and INT2 Register (Data Register for Output Frequency) Access
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
35
4. 5 Clock correction register access
18
9 1
ACK
1 1 0 1 1 0
START
I/O mode switching
SCL
SDA
Clock
correction data
B7 B0
R / W
ACK
*1
STOP
0
I/O mode switching
Device code
command
*1. Set NO_ACK = 1 when reading.
Figure 44 Clock Correction Register Access
4. 6 Free register access
18
9 1
ACK
1 1 0 1 1 0
START
I/O mode switching
SCL
SDA
Free register
data
B7 B0
Device code
command
R / W
ACK
*1
STOP
1
I/O mode switching
*1. Set NO_ACK = 1 when reading.
Figure 45 Free Register Access
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
36
Reset After Communication Interruption
In case of communication interruption in the S-35390A, for example, if the power supply voltage drops and only the master
device is reset during communication, the S-35390A does not perform the next operation because the internal circuit
keeps the status prior to communication interruption. Since the S-35390A does not have a reset pin, users usually reset its
internal circuit by inputting a stop condition. However, if the SDA is outputting "L" (during output of acknowledgment signal
or reading), the S-35390A does not accept a stop condition from the master device. In this case, users are necessary to
finish acknowledgment output or reading of the SDA. Figure 46 shows how to reset.
First, input a start condition from the master device (the S-35390A cannot detect a start condition because the SDA in the
S-35390A H is outputting "L"). Next, input a clock pulse equivalent to 7-byte data access (63-clock) from the SCL. During
this period, release the SDA line for the master device. By this procedure, SDA I/O before communication interruption is
finished, and the SDA line in the S-35390A is released. After that, inputting a stop condition resets the internal circuit and
restores the regular communication. This reset procedure is recommended to be executed at initialization of the system
after the master device's power supply voltage is raised.
If this reset procedure is executed when the S-35390A outputs an acknowledgment signal of a writing instruction, the
writing operation may be performed at the corresponding register, so caution should be exercised.
1 2 62 63
89
Start
condition
Stop
condition
Clocks equivalent to 7-byte data access
SCL
"L" "L" or High-Z High-Z
SDA
(Master device
output)
SDA
(S-35390
A
output)
SDA "L" or High-Z
"L"
Figure 46 How to Reset
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
37
Flowchart of Initialization and Example of Real-time Data Set-up
Figure 47 is a recommended flowchart when the master device shifts to a normal operation status and initiates
communication with the S-35390A. Regarding how to apply power, refer to " Power-on Detection Circuit and Register
Status". It is unnecessary for users to comply with this flowchart of real-time data strictly. And if using the default data at
initializing, it is also unnecessary to set up again.
Confirm data in status
register 1
OK
Set real-time data 1
Read real-time data 1*2
Wait for 0.5 s*1
Read status re
g
ister 1
POC = 0 NO
YES
BLD = 0
YES
OK
END
Read status re
g
ister 1
Read status re
g
ister 1
NO
NO
YES
START
POC = 1
Set 24-hour / 12-hour mode
to status register 1
Initialize
(status register 1 B7 = 1)
BLD = 0
YES
Read real-time data 1
NG
Confirm data in real-time
data 1
NG
NO
*1. Do not communicate for 0.5 seconds since the power-on detection circuit is in operation.
*2. Reading the real-time data 1 should be completed within 1 second after setting the real-time data 1.
Figure 47 Example of Initialization Flowchart
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
38
Examples of Application Circuits
V
CC
XOUT
XIN
S-35390A
SDA
VSS
VDD
SCL
VSS
VCC
CPU
INT1
System
power supply
C
g
10 k
1 k
INT2
10 k
1 k
Caution 1. Because the I/O pin has no protective diode on the VDD side, the relation of VCC VDD is possible,
but pay careful attention to the specifications.
2. Start communication under stable condition after power-on the power supply in the system.
Figure 48 Application Circuit 1
VCC
CPU
S-35390A SDA
VSS
VDD
SCL
INT1
System power
supply
VSS
XOUT
XIN
10 k
INT2
10 k
1 k
1 k
C
g
Caution Start communication under stable condition after power-on the power supply in the system.
Figure 49 Application Circuit 2
Caution The above connection diagrams do not guarantee operation. Set the constants after performing
sufficient evaluation using the actual application.
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
39
Adjustment of Oscillation Frequency
1. Configuration of crystal oscillation circuit
Since the crystal oscillation circuit is sensitive to external noise (the clock accuracy is affected), the following measures
are essential for optimizing the configuration.
Place the S-35390A, crystal oscillator, and external capacitor (Cg) as close to each other as possible.
Increase the insulation resistance between pins and the substrate wiring patterns of XIN and XOUT.
Do not place any signal or power lines close to the crystal oscillation circuit.
Locating the GND layer immediately below the crystal oscillation circuit is recommended.
Locate the bypass capacitor adjacent to the power supply pin of the S-35390A.
S-35390A
XOUT
XIN
R
f
=
100 M(typ.)
R
d
=
100 k(typ.)
C
d
=
8 pF (typ.)
C
g
C
d
R
d
R
f
Parasitic capacitance
*3
Crystal oscillator: 32.768 kHz
Parasitic capacitance
*3
C
L
= 6 pF
*1
C
g
= None
*2
to 9.1 pF
*1. When setting the value for the crystal oscillator's CL as 7 pF, connect Cd externally if necessary.
*2. The crystal oscillation circuit operates even when Cg is not connected. Note that the oscillation frequency is in the
direction that it advances.
*3. Design the board so that the parasitic capacitance is within 5 pF.
Figure 50 Connection Diagram 1
XIN
Crystal
oscillator
XOUT
VSS
C
g
8
7
6
5
1
2
3
4
S-35390A
Locate the GND layer in the
layer immediately below
Figure 51 Connection Diagram 2
Caution 1. When using the crystal oscillator with a CL exceeding the rated value (7 pF) (e.g: CL = 12.5 pF),
oscillation operation may become unstable. Use a crystal oscillator with a CL value of 6 pF or 7 pF.
2. Oscillation characteristics is subject to the variation of each component such as substrate parasitic
capacitance, parasitic resistance, crystal oscillator, and Cg. When configuring a crystal oscillation
circuit, pay sufficient attention for them.
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
40
2. Measurement of oscillation frequency
When the S-35390A is turned on, the internal power-on detector operates and a signal of 1 Hz is output from the 1INT
pin to select the crystal oscillator and optimize the Cg value. Turn the power on and measure the signal with a frequency
counter following the circuit configuration shown in Figure 52.
If 1 Hz signal is not output, the power-on detector does not operate normally. Turn off the power and then turn it on again.
For how to apply power, refer to " Power-on Detection Circuit and Register Status".
Remark If the error range is 1 ppm in relation to 1 Hz, the time is shifted by approximately 2.6 seconds per month
(calculated using the following mode).
10–6 (1 ppm) 60 seconds 60 minutes 24 hours 30 days = 2.592 seconds
INT1
INT2
SDA
SCL S-35390A
VDD
XOUT
XIN
VSS
C
g
1 kΩ
10 kΩ
1 kΩ
Frequency
counter
Open
or pull-up
Figure 52 Configuration of Oscillation Frequency Measurement Circuit
Caution 1. Use a high-accuracy frequency counter of 7 digits or more.
2. Measure the oscillation frequency under the usage conditions.
3. Since the 1 Hz signal continues to be output, initialization must be executed during normal
operation.
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
41
3. Adjustment of oscillation frequency
3. 1 Adjustment by setting Cg
Matching of the crystal oscillator with the nominal frequency must be performed with the parasitic capacitance on the
board included. Select a crystal oscillator and optimize the Cg value in accordance with the flowchart below.
START
END
YES
NO
YES
NO
NO
YES
NO
YES
Set to center
of variable
capacitance*3
Select a crystal
oscillator*1
Variable
capacitance
Change Cg
Optimal
value*2
Frequency
Cg in
specification
Set Cg
Make fine adjustment
of frequency using
variable capacitance
Trimmer capacitor
Fixed capacitor
*1. Request a crystal manufacturer for a matching evaluation between the IC and the crystal oscillator. The
recommended crystal characteristic values are, CL value (load capacitance) = 6 pF, R1 value (equivalent serial
resistance) = 50 k max.
*2. The Cg value must be selected on the actual PCB since it is affected by parasitic capacitance. Select the
external Cg value in a range of 0 pF to 9.1 pF.
*3. Adjust the rotation angle of the variable capacitance so that the capacitance value is slightly smaller than the
center, and confirm the oscillation frequency and the center value of the variable capacitance. This is done in
order to make the capacitance of the center value smaller than one half of the actual capacitance value because
a smaller capacitance value increases the frequency variation.
Figure 53 Crystal Oscillator Setting Flow
Caution 1. The oscillation frequency varies depending on the ambient temperature and power supply
voltage. Refer to " Characteristics (Typical Data)".
2. The 32.768 kHz crystal oscillator operates more slowly at an operating temperature higher or
lower than 20C to 25C. Therefore, it is recommended to set the oscillator to operate
slightly faster at normal temperature.
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
42
Precautions
Do not apply an electrostatic discharge to this IC that exceeds the performance ratings of the built-in electrostatic
protection circuit.
ABLIC Inc. claims no responsibility for any disputes arising out of or in connection with any infringement by products
including this IC of patents owned by a third party.
2-WIRE REAL-TIME CLOCK
Rev.4.2_03 S-35390A
43
Characteristics (Typical Data)
1. Standby current vs. VDD characteristics 2. Current consumption when 32 kHz is output
vs. VDD characteristics
Ta = 25C, CL = 6 pF Ta = 25C, CL = 6 pF
0 5 6
1.0
0.8
0.6
0.4
0.2
0
VDD [V]
IDD1
[A]
1 2 3 4
0 5 6
1.0
0.8
0.6
0.4
0.2
0
VDD [V]
IDD3
[A]
1 2 3 4
3. Current consumption during operation
vs. Input clock characteristics
4. Standby current
vs. Temperature characteristics
Ta = 25C, CL = 6 pF CL = 6 pF
0
50
45
40
35
30
25
20
15
10
5
0
IDD2
[A]
100 200 300 400 500
SCLfrequency [kHz]
VDD = 5.0 V
VDD = 3.0 V
–40 75 85
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
Ta [C]
IDD1
[A]
–25 025 50
VDD = 5.0 V
VDD = 3.0 V
5. Standby current vs. C
g
characteristics 6. Oscillation frequency vs. C
g
characteristics
Ta = 25C, CL = 6 pF Ta = 25C, CL = 6 pF
0 6 8 10
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
DD1
[A]
V
DD
= 5.0 V
V
DD
= 3.0 V
2 4
C
g
[pF]
100
80
60
40
20
0
–20
–40
–60
–80
–100
f/f
[ppm]
0 2 4 6
Cg [pF]
8 10
VDD = 5.0 V
VDD = 3.0 V
2-WIRE REAL-TIME CLOCK
S-35390A Rev.4.2_03
44
7. Oscillation frequency vs. VDD characteristics 8. Oscillation frequency
vs. Temperature characteristics
Ta = 25C, Cg = 7.5 pF C
g
= 7.5 pF
50
40
30
20
10
0
–10
–20
–30
–40
–50
f/f
[ppm]
0 5 6
VDD [V]
1 2 3 4
20
0
–20
–40
–60
–80
–100
–120
–140
f/f
[ppm]
–40 75 85
Ta [ C]
–25 0 25 50
VDD = 5.0 V
VDD = 3.0 V
9. Oscillation start time vs. Cg characteristics 10. Output current characteristics 1
(VOUT vs. IOL1)
Ta = 25C
INT1
pin,
INT2
pin, Ta =
25C
0
500
450
400
350
300
250
200
150
100
50
0
tSTA
[ms]
2 8 10
4 6
Cg [pF]
VDD = 5.0 V
VDD = 3.0 V
0
50
40
30
20
10
0
IOL1
[mA]
1 2 3 4
VOUT [V]
VDD = 5.0 V
VDD = 3.0 V
11. Output current characteristics 2
(VOUT vs. IOL2)
12. BLD detection, release voltage, VDDT (min.)
vs. Temperature characteristics
SDA pin, Ta = 25C CL = 6 pF
0
50
40
30
20
10
0
IOL2
[mA]
0.5 1 1.5 2
VOUT [V]
2.5
VDD = 5.0 V
VDD = 3.0 V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
BLD
[V]
–40 75 85
–25 0 25 50
Ta [ C]
Release voltage
VDDT (min.)
Detection voltage
No.
TITLE
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ANGLE
ABLIC Inc.
No. FJ008-A-P-SD-2.2
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SOP8J-D-PKG Dimensions
FJ008-A-P-SD-2.2
0.4±0.05
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0.20±0.05
5.02±0.2
14
85
No.
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ABLIC Inc.
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8
1
4
ø2.0±0.05
ø1.55±0.05 0.3±0.05
2.1±0.1
8.0±0.1
6.7±0.1
2.0±0.05
Feed direction
4.0±0.1(10 pitches:40.0±0.2)
SOP8J-D-Carrier Tape
No. FJ008-D-C-SD-1.1
FJ008-D-C-SD-1.1
No.
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ABLIC Inc.
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2±0.5
13.5±0.5
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2±0.5
ø13±0.2
ø21±0.8
Enlarged drawing in the central part
SOP8J-D-Reel
No. FJ008-D-R-SD-1.1
FJ008-D-R-SD-1.1
No.
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ø13±0.2
ø21±0.8
Enlarged drawing in the central part
SOP8J-D-Reel
No. FJ008-D-R-S1-1.0
FJ008-D-R-S1-1.0
No.
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FT008-A-P-SD-1.2
0.17±0.05
3.00 +0.3
-0.2
0.65
0.2±0.1
14
5
8
mm
No.
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ABLIC Inc.
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8.0±0.1 ø1.55 +0.1
-0.05
(4.4)
0.3±0.05
1
45
8
4.0±0.1
Feed direction
TSSOP8-E-Carrier Tape
No. FT008-E-C-SD-1.0
FT008-E-C-SD-1.0
+0.4
-0.2
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No.
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Enlarged drawing in the central part
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Enlarged drawing in the central part
2±0.5
ø13±0.5
ø21±0.8
13.4±1.0
17.5±1.0
4,000
QTY.
TSSOP8-E-Reel
FT008-E-R-S1-1.0
mm
No. FT008-E-R-S1-1.0
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
1.97±0.03
0.2±0.05
0.48±0.02
0.08
mm
SNT-8A-A-PKG Dimensions
PH008-A-P-SD-2.1
No. PH008-A-P-SD-2.1
0.5
+0.05
-0.02
123 4
56
78
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
PH008-A-C-SD-2.0
SNT-8A-A-Carrier Tape
No. PH008-A-C-SD-2.0
Feed direction
4.0±0.1
2.0±0.05
4.0±0.1
ø1.5 +0.1
-0
ø0.5±0.1
2.25±0.05
0.65±0.05
0.25±0.05
2134
7865
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
12.5max.
9.0±0.3
ø13±0.2
(60°) (60°)
Enlarged drawing in the central part
QTY.
PH008-A-R-SD-1.0
mm
SNT-8A-A-Reel
No. PH008-A-R-SD-1.0
5,000
No.
TITLE
UNIT
ANGLE
ABLIC Inc.
mm
SNT-8A-A
-Land Recommendation
PH008-A-L-SD-4.1
0.3
0.2
0.52
2.01
0.52
No. PH008-A-L-SD-4.1
Caution 1. Do not do silkscreen printing and solder printing under the mold resin of the package.
2. The thickness of the solder resist on the wire pattern under the package should be 0.03 mm
or less from the land pattern surface.
3. Match the mask aperture size and aperture position with the land pattern.
4. Refer to "SNT Package User's Guide" for details.
1. (0.25 mm min. / 0.30 mm typ.)
2. (1.96 mm ~ 2.06 mm)
1.
2. 0.03 mm
3.
4. SNT
1. Pay attention to the land pattern width (0.25 mm min. / 0.30 mm typ.).
2. Do not widen the land pattern to the center of the package (1.96 mm to 2.06mm).
1
2
1.
2. (1.96 mm ~ 2.06 mm)
(0.25 mm min. / 0.30 mm typ.)
Disclaimers (Handling Precautions)
1. All the information described herein
(product data,
specifications,
figures,
tables,
programs,
algorithms and application
circuit examples,
etc.)
is current as of publishing date of this document and is subject to change without notice.
2. The circuit examples and the usages described herein are for reference only, and do not guarantee the success of
any specific mass-production design.
ABLIC Inc. is not responsible for damages caused by the reasons other than the products described herein
(hereinafter "the products") or infringement of third-party intellectual property right and any other right due to the use
of the information described herein.
3. ABLIC Inc. is not responsible for damages caused by the incorrect information described herein.
4. Be careful to use the products within their specified ranges. Pay special attention to the absolute maximum ratings,
operation voltage range and electrical characteristics, etc.
ABLIC Inc. is not responsible for damages caused by failures and / or accidents, etc. that occur due to the use of the
products outside their specified ranges.
5. When using the products, confirm their applications, and the laws and regulations of the region or country where they
are used and verify suitability, safety and other factors for the intended use.
6. When exporting the products, comply with the Foreign Exchange and Foreign Trade Act and all other export-related
laws, and follow the required procedures.
7. The products must not be used or provided (exported) for the purposes of the development of weapons of mass
destruction or military use. ABLIC Inc. is not responsible for any provision (export) to those whose purpose is to
develop, manufacture, use or store nuclear, biological or chemical weapons, missiles, or other military use.
8. The products are not designed to be used as part of any device or equipment that may affect the human body, human
life, or assets (such as medical equipment, disaster prevention systems, security systems, combustion control
systems, infrastructure control systems, vehicle equipment, traffic systems, in-vehicle equipment, aviation equipment,
aerospace equipment, and nuclear-related equipment), excluding when specified for in-vehicle use or other uses. Do
not apply the products to the above listed devices and equipments without prior written permission by ABLIC Inc.
Especially, the products cannot be used for life support devices, devices implanted in the human body and devices
that directly affect human life, etc.
Prior consultation with our sales office is required when considering the above uses.
ABLIC Inc. is not responsible for damages caused by unauthorized or unspecified use of our products.
9. Semiconductor products may fail or malfunction with some probability.
The user of the products should therefore take responsibility to give thorough consideration to safety design including
redundancy, fire spread prevention measures, and malfunction prevention to prevent accidents causing injury or
death, fires and social damage, etc. that may ensue from the products' failure or malfunction.
The entire system must be sufficiently evaluated and applied on customer's own responsibility.
10. The products are not designed to be radiation-proof. The necessary radiation measures should be taken in the
product design by the customer depending on the intended use.
11. The products do not affect human health under normal use. However, they contain chemical substances and heavy
metals and should therefore not be put in the mouth. The fracture surfaces of wafers and chips may be sharp. Be
careful when handling these with the bare hands to prevent injuries, etc.
12. When disposing of the products, comply with the laws and ordinances of the country or region where they are used.
13. The information described herein contains copyright information and know-how of ABLIC Inc.
The information described herein does not convey any license under any intellectual property rights or any other
rights belonging to ABLIC Inc. or a third party. Reproduction or copying of the information from this document or any
part of this document described herein for the purpose of disclosing it to a third-party without the express permission
of ABLIC Inc. is strictly prohibited.
14. For more details on the information described herein, contact our sales office.
2.0-2018.01
www.ablicinc.com
