OP4004B - RFM (RF Monolithics, Inc.)

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• Quartz SAW Stabilized Differential Output Technology

• Very Low Jitter Fundamental-Mode Operation at 625.00 MHz

• Voltage Tunable for Phase Locked Loop Applications

• Timing Reference for 10G Optical Ethernet Communications Systems

The OP4004B is a voltage-controlled SAW clock (VCSC) designed for phase-locked loop (PLL) applications

in optical data communications systems. The differential outputs of the OP4004B are generated by high-Q,

fundamental mode quartz surface acoustic wave (SAW) technology. This technique provides very low output

jitter and phase noise, plus excellent immunity to power supply noise. The OP4004B differential outputs

feature ±1% symmetry, and can be DC-configured to drive a wide range of high-speed logic families. The

OP4004B is packaged in a hermetic metal-ceramic LCC.

Absolute Maximum Ratings

Rating Value Units

DC Suppy Voltage 0 to 5.5 Vdc

Tune Voltage 0 to 5.5 Vdc

Case Temperature -55 to 100 °C

625.00 MHz

Optical

Timing Clock

OP4004B

CAUTION: Electrostatic Sensitive Device. Observe precautions for handling.

COCOM CAUTION: Approval by the U.S. Department of Commerce is required prior to export of this device.

Notes:

1. Unless otherwise noted, all s pecifications inc l ude the combined effects of load VSWR, VCC and TC.

2. Net tuning range after tuning out the effects of initial manufac turing toleranc es, VSWR pushing/ pulling, V CC, TC and aging.

3. The inte rnal design, manufacturing proc esses, and spec ifications of this device are subjec t to change without notice.

4. Specif ied only for a balanced load with a VSWR < 1.2 ( 50 ohms each side), and a VCC = 3.0 Vd c.

5. Symmetry is defined as the wid th in (% of total period) measure at 50% of the peak -to-peak voltage of either output.

6. Jitter and other noise outputs due to power supply noise or mecha nic al vibration are not included in this specification ex c ep t where noted.

7. Applies to period jitte r of either differen tial output. Measured with a Tektronix CSA80 3 signal analyz er with at least 100 0 samples.

8. See Figure 4.

9. One or more of the following Unit ed States patents apply: 4, 616, 197; 4,670,681; 4,760,352.

Electrical Ch arac ter is tics

Characteristic Sym Notes Minimum Typical Maximum Units

Operating Frequency Absolute Frequency fO1625.00 MHz

Tuning Range 2±100 ppm

Tuning Voltage 10 3.3 Vdc

Tuning Linearity 1, 8 ±5 %

Tuning Sensitivity df/dv 2 140 300 ppm/V

Modulation Bandwidth 50 kHz

Q and Q Output Voltage into 50 Ω (VSWR ≤ 1.2) VO1,3 0.60 1.1 VP-P

Operating Load VSWR 1,3 2:1

Symmetry 3, 4, 5 49 51 %

Harmonic Spurious 3, 4, 6 -30 dBc

Nonharmonic Spurious 3, 4, 6, 7 -60 dBc

Phase Noise @ 100 Hz offset 3, 6 -70 dBc/Hz

@ 1 kHz offset 3, 6 -100 dBc/Hz

@ 10 kHz offset 3, 6 -125 dBc/Hz

Noise Floor 3, 6 -150 dBc/Hz

Q and Q Jitter RMS Jitter 3, 4, 6, 7 2ps

No Noise on VCC 3, 4, 6, 7 12 psP-P

200 mVP-P Noise, from 1 MHz to ½ fO on VCC 312ps

P-P

Input Impedence (Tuning Port) 1KΩ

Output DC Resistance (between Q & Q)1, 3 50 KΩ

DC Power Supply Operating Voltage VCC 1, 3 3.13 3.3 or 5.0 5.25 Vdc

Operating Current ICC 1, 3 70 mA

Operating Case Temperature TC1, 3 -40°C +85°C °C

Lid Symbolization (YY=Year, WW =We ek) RFM OP4004B YYWW

SMC-08

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OP4004B Performance Parameters

The OP4004B has been developed to achieve high performance in five parameters critical to optical data communications applications:

Low Jitter and Phase Noise - low clock jitter (or low phase noise in the frequency domain) is critical to achieving low bit error rates in optical data

communications systems. The OP4004B provides very low free-running jitter and phase noise at 1/16 the 10 G et hernet clock rate, as shown in Figures 1

and 2. This makes the OP4004B an excellent reference for the generation or regeneration of low-jitter clocks and data streams. The OP4004B achieves

this performance over its full -40 to +85 °C operating temperature range using RFM's patented SAW oscillator architecture.

Single-Sid eband Phase Noise

Figure 1

High Power Supply Noise Immunity - the OP4004B uses both differential active devices and differential SAW technology to minimize the effects of power

supply noise on jitter and phase noise, as shown in Figures 2 and 3. Optical data communications circuits must switch relatively high levels of current,

making power supply noise immunity an important clock requirement.

Controlled Tuning Characteristics - the OP4004B voltage tuning constant, KV, is bounded between 140 and 300 ppm/V under locked conditions for

reference signals with ±100 ppm or better stability over the OP4004B's full operating temperature and supply voltage range. This allows a PLL based on

the OP4004B to be designed with a well-controlled loop bandwidth and damping factor, avoiding problems such a jitter peaking, etc. The voltage tuning

characteristic of the OP4004B is monotonic from 0 to 3.3 V, supporting reliable acquisition of phase lock. Figure 4 shows typical OP4004B tuning

characteristics.

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OP4004B Jitter Plot

No Power Supply Noise OP4004B Jitter Plot

200 mV of Power Supply Noise

100

200

300

400

500

600

3.53.02.52.01.500.51.0

625.40

625.30

625.20

625.10

625.00

624.80

624.90

Tuning Voltage

Operating Frequency at +25 °C in MHz

in ppm/V

Typical OP4004B Tuning Characteristics

Frequency

Voltage Tunin g

Rang e for Loc k

-40 to +85 °C

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Output DC Volt age Configurability - the OP4004B differential outputs can be DC-configured to support a wide range of high-speed logic families and ASIC

drive requirements by the selection of f our resistors (see Configuring the OP4004B DC Output Volt age below) and a logic supply volt age. Each dif ferential

output of the OP4004B is AC-coupled to provide this flexibility.

OP4004B Tuning Details

The frequency tuning of the OP4004B is characterized over a voltage range of 0 to 3.3 V. The tuning volt age applied to the OP4004B should be limited to

this range. Figure 4 shows the typical locked tuning range for operation over -40 or +85 °C. The frequency shift of a quartz SAW frequency control device

with temperature has the shape of an inverted parabola, with the highest frequency occurring around +25 °C. At both -40 and +85 °C, there will be a 170

ppm downward shift in the frequency of the SAW device com pared to +25 °C. Tuning to compensate for this temperature shift is the same as tuning

170 ppm higher at +25 °C. This is well within the tuning range of the OP4004B, as shown in Figure 4. Note that the voltage tuning constant, KV, is bounded

between 140 and 300 ppm/V under locked conditions for any temperature within the OP4004B's specified operating range.

Differential Output Symmetry - for balanced output loads, the differential output symmetry of the OP4004B is ±1%.

This differential output symmetry me ets the requirements of the most demanding high-speed logic families.

The OP4004B tuning port presents a input impedance greater than 100 kilohms from DC to 50 kHz, and at least 1 kilohm for any RF frequency up to the

operating frequency of the OP4004B. Most operational amplifiers used in active loop f ilters will be st able when driving the t uning port directly. Special care

are should be taken to avoid ground loops in the path from the output of the phase detector though the loop filter to the tuning input of the OP4004B. For

most applications, the bandwidth of t he loop filter in a OP4004B PLL will be less than 50 Hz, as discussed in the example OP4004B PLL application section

below.

Configuring the OP4004B DC Output Voltage

Each differential output of the OP4004B is AC coupled, allowing the static DC level at each output to be set with a resistive divider to match the logic family

being driven by the clock. The parallel-equivalent resistance of the two resistors in each divider should be approximately 50 ohms. The supply voltage to

the dividers, VLOAD, should be two to three times the value of the static DC voltage, VDC.

Referring to the accompanying figure :

VDC = VLOAD*R1/(R1 + R2)

and

50 = R1*R2/(R1 + R2)

The values of the resistors R2 and R1 are

given directly as:

R2 = 50*VLOAD/VDC

R1 = 1/(0.02 - (1/R2))

R1 R1

3.3 Vdc

VLoadOP4004B

TUNE VDC

VDC

VLOAD

OP4004B DC Output Voltage Adjustment

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The following table provides R1 and R2 values for six high-speed logic families commonly used in optical data communications sy s tems. Note that the

OP4004B can be used with logic families that run from a negative power supply voltage by simply using a negative VLOAD voltage.

Load Type VDC R1 R2 VLOAD

10k 3.3 V PECL 1.95 120 91 3.3 V

100k 3.3 V PECL 1.88 120 91 3.3 V

10k 5 V PECL 3.65 180 68 5.0 V

100k 5 V PECL 3.58 180 68 5.0 V

10k -5 V NECL -1.30 240 62 -5.0 V

100k -5 V NECL -1.42 240 62 -5.0 V

Loop Filter Tune

+Vcc

PLL for Generating a High Stability 625 MHz Clock

OP4004B

External

Reference

Internal

Reference

(holdover)

Phase

Detector

Example OP4004B Phase-Locked Loop Application

One of the most important applications for the OP4004B is in a PLL circuit used to generate a very high quality 625.00 MHz clock. The PLL combines the

long-term stability of a precision external or internal 19.53125 MHz reference clock with the very low jitter and phase noise of the OP4004B. A block diagram

of the PLL is shown in Figure 6. A sample of the OP4004B output is divided by 32 and is compared to a 19.53125 MHz reference clock in the phase detector .

The loop filter at the output of t he phase detector is set to a very low bandwidth (less than 50 Hz typical). This imparts the long-term stability of the precision

19.53125 MHz reference to the OP4004B without degrading the OP4004B's low jitter and phase noise.

OP4004B Enable/Disable

Pin 3 on the OP4004B is the enable/disable control pin for the clock outputs. When Pin 3 is grounded, full output power is available from the clock. When

Pin 3 is pulled to Vcc, the power on the clock outputs is decreased at least 25 dB.

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SMC-8 8-Terminal Surface Mount Case

Dimensio

nmm Inches

MIN MAX MIN MAX

A13.46 13.97 0.530 0.550

B9.14 9.66 0.360 0.380

C1.93 Nominal 0.076 Nominal

D3.56 Nominal 0.141 Nominal

E2.24 Nominal 0.088 Nominal

F1.27 Nominal 0.050 Nominal

G2.54 Nominal 0.100 Nominal

H3.05 Nominal 0.120 Nominal

J1.93 Nominal 0.076 Nominal

K5.54 Nominal 0.218 Nominal

L4.32 Nominal 0.170 Nominal

M4.83 Nominal 0.190 Nominal

N0.50 Nominal 0.020 Nominal

ELECTRICAL CONNECTIONS

Terminal

Number Connection

2 Ground

3 Enable/Disable

4 Q Output

5Q Output

6Ground

8 Tuning Input

LID Ground

T ypically 0.01" to 0.05" or 0.25 mm to

1.25 mm (8 Places)

(The opt imum value of this dimension is

dependent on the PCB assembly process

employed.)

Ty pical Pr inte d C i rcui t Bo a rd Land Pa t t e r n

A typical land pattern for a circuit board is shown on the right.

Grounding of the metallic center pad is optional.

TOP VIEW

L(X2)

(X8)

(X3)

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See Detail "A"

13.0

20.2

2.0

24.4

"C" REF.

"B" REF.

(measurements in millimeters)

Detail "A"

SMC-08 Case

Reel Size Quantity

Per Reel

“B” Nominal “C” Nominal Min Max

13 Inch 330 mm 100 mm 200 1000

Dimensions

Carrier Tape Dimensions Cover Tape

Ao .383 ± .004 (9.7) 21.3mm

Bo .554 ± .004 (14.1)

Ko .130 ± .004 (3.3)

P12mm

W24mm

Tape Length 60M

Pockets/M 83/M

(CARRIER TAPE SIZE)

(PITCH)

COVER TAPE SIZE

COVER TAPE

Orientation in Tape Carrier as Shipped