2SK2569
Silicon N-Channel MOS FET
November 1996
Application
Low frequency power switching
Features
• Low on-resistance.
• RDS(on) = 2.6 Ω max. (at VGS = 4 V, ID = 100mA)
• 2.5V gate drive device.
• Small package (MPAK).
Outline
MPAK
1. Source
2. Gate
3. Drain
S
D
G
21
3
2SK2569
2
Absolute Maximum Ratings (Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 50 V
Gate to source voltage VGSS ±20 V
Drain current ID0.2 A
Drain peak current ID(pulse)*10.4 A
Channel dissipation Pch*2150 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes 1. PW ≤ 10 µs, duty cycle ≤ 1 %
Electrical Characteristics (Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown
voltage V(BR)DSS 50 — — V ID = 100 µA, VGS = 0
Gate to source breakdown
voltage V(BR)GSS ±20 ——V I
G
= ±100 µA, VDS = 0
Zero gate voltage drain current IDSS — — 1.0 µAVDS = 40 V, VGS = 0
Gate to source leak current IGSS ——±2.0 µAV
GS = ±16 V, VDS = 0
Gate to source cutoff voltage VGS(off) 0.5 — 1.5 V ID = 10 µA, VDS = 5 V
Static drain to source on state
resistance RDS(on)1 — 2.0 2.6 ΩID = –100 mA
VGS = –4 V*1
Static drain to source on state
resistance RDS(on)2 — 3.1 5.0 ΩID = 40 mA
VGS = –2.5 V*1
Foward transfer admittance |yfs| 0.13 0.23 — S ID = 100 mA
VDS = 10 V
Input capacitance Ciss — 14.0 — pF VDS = 10 V
VGS = 0
f = 1 MHz
Output capacitance Coss — 17.2 — pF
Reverse transfer capacitance Crss — 1.73 — pF
Turn-on delay time td(on) —40—µsV
GS = 10 V, ID = 100 mA
RL = 300 Ω
Rise time tr—86—µs
Turn-off delay time td(off) — 1120 — µs
Fall time tf— 430 — µs
Notes 1. Pulse Test
2. Marking is "ZN–"
2SK2569
3
200
150
100
50
0
Channel Dissipation Pch (mW)
50 100 150 200
Ambient Temperature Ta (°C)
Maximum Channel
Dissipation Curve
2SK2569
4
Notice
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