TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
DQualification in Accordance With
AEC-Q100†
DQualified for Automotive Applications
DCustomer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval†
DESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Using Human
Body Model (C = 100 pF, R = 1500 Ω)
DPower-On Reset Generator With Fixed
Delay Time of 200 ms (TPS3823/4/5/8)
or 25 ms (TPS3820)
DManual Reset Input (TPS3820/3/5/8)
DReset Output Available in Active-Low
(TPS3820/3/4/5), Active-High (TPS3824) and
Open-Drain (TPS3828)
DSupply Voltage Supervision Range
2.5 V, 3 V, 3.3 V, 5 V
DWatchdog Timer (TPS3820/3/4/8)
DSupply Current of 15 µA (Typ)
DSOT23-5 Package
applications
DApplications Using Automotive DSPs,
Microcontrollers, or Microprocessors
DIndustrial Equipment
DProgrammable Controls
DAutomotive Systems
DBattery-Powered Equipment
DIntelligent Instruments
DWireless Communications Systems
†Contact factory for details. Q100 qualification data available on
request.
description
The TPS382x family of supervisors provides circuit initialization and timing supervision, primarily for DSP and
processor-based systems.
Copyright 2002 – 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
3
2
4
5
TPS3820, TPS3823, TPS3828 . . . DBV PACKAGE
(TOP VIEW)
1
RESET
GND
MR
VDD
WDI
3
2
4
5
TPS3825 . . . DBV PACKAGE
(TOP VIEW)
1
RESET
GND
RESET
VDD
MR
3
2
4
5
TPS3824 . . . DBV PACKAGE
(TOP VIEW)
1
RESET
GND
RESET
VDD
WDI
RESET
MR WDI
100 nF
VDD
GND
TPS3823-33
VDD
RESET
I/O
GND
MSP430C325
3.3 V
typical application
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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description (continued)
During power-on, RESET is asserted when supply voltage VDD becomes higher than 1.1 V. Thereafter, the
supply voltage supervisor monitors VDD and keeps RESET active as long as VDD remains below the threshold
voltage VIT–. An internal timer delays the return of the output to the inactive state (high) to ensure proper system
reset. The delay time, td, starts after VDD has risen above the threshold voltage VIT–. When the supply voltage
drops below the threshold voltage VIT–, the output becomes active (low) again. No external components are
required. All the devices of this family have a fixed-sense threshold voltage VIT– set by an internal voltage
divider.
The TPS3820/3/5/8 devices incorporate a manual reset input, MR. A low level at MR causes RESET to become
active. The TPS3824/5 devices include a high-level output RESET. TPS3820/3/4/8 have a watchdog timer that
is periodically triggered by a positive or negative transition at WDI. When the supervising system fails to retrigger
the watchdog circuit within the time-out interval, ttout, RESET becomes active for the time period td. This event
also reinitializes the watchdog timer. Leaving WDI unconnected disables the watchdog.
In applications where the input to the WDI pin may be active (transitioning high and low) when the
TPS3820/3/4/8 is asserting RESET, the TPS3820/3/4/8 does not return to a non-reset state when the input
voltage is above Vt. If the application requires that input to WDI is active when RESET is asserted, WDI must
be decoupled from the active signal. This can be accomplished by using an N-channel FET in series with the
WDI pin, with the gate of the FET connected to the RESET output as shown in Figure 1.
WDI
RESET
TPS3824
WDI External
Figure 1
The product spectrum is designed for supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The circuits are available
in a 5-pin SOT23-5 package. The TPS382x-xxQ-Q1 devices are characterized for operation over a temperature
range of –40°C to 125°C, and are qualified in accordance with AEC-Q100 stress test qualification for integrated
circuits.
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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3
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PACKAGE INFORMATION
DEVICE NAME THRESHOLD VOLTAGE MARKING
TPS3820-33QDBVRQ1†2.93 V PDEQ
TPS3820-50QDBVRQ1†4.55 V PDDQ
TPS3823-25QDBVRQ1†2.25 V PAPQ
TPS3823-30QDBVRQ1†2.63 V PAQQ
TPS3823-33QDBVRQ1†2.93 V PARQ
TPS3823-50QDBVRQ1†4.55 V PASQ
TPS3824-25QDBVRQ1†2.25 V PATQ
TPS3824-30QDBVRQ1†2.63 V PAUQ
TPS3824-33QDBVRQ1†2.93 V PAVQ
TPS3824-50QDBVRQ1†4.55 V PAWQ
TPS3825-33QDBVRQ1†2.93 V PDGQ
TPS3825-50QDBVRQ1†4.55 V PDFQ
TPS3828-33QDBVRQ1†2.93 V PDIQ
TPS3828-50QDBVRQ1†4.55 V PDHQ
†The DBVR package indicates tape and reel of 3000 parts.
FUNCTION/TRUTH TABLE
INPUTS OUTPUTS
MR‡VDD>VIT RESET RESET§
L 0 L H
L 1 L H
H 0 L H
H 1 H L
‡TPS3820/3/5/8
§TPS3824/5
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
SGLS143A – DECEMBER 2002 – REVISED JANUARY 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
_
+
Watchdog
Timer Logic Reset
Logic
Reset†
Reset
MR‡
WDI
Transition
Detector
52 kΩ
40 kΩ
Vref
VDD
†TPS3824/5
‡TPS3820/3/5/8
timing diagram
undefined
undefined
tdtdtt(out) td
VDD VIT
1.1 V
RESET
WDI
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RESET, RESET, MR, WDI (see Note 1) –0.3 V to (VDD + 0.3 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum low output current, IOL 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum high output current, IOH –5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current range, IIK (VI < 0 or VI > VDD) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current range, IOK (VO < 0 or VO > VDD) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soldering temperature 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltage values are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING OPERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
DBV 437 mW 3.5 mW/°C280 mW 227 mW 87 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 1.1 5.5 V
Input voltage, VI0 VDD + 0.3 V
High-level input voltage at MR and WDI, VIH 0.7 × VDD V
Low-level input voltage, VIL 0.3 × VDD V
Input transition rise and fall rate at MR or WDI, ∆t/∆V 100 ns/V
Operating free-air temperature range, TA–40 125 °C
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TPS382x-25 VDD = VIT– + 0.2 V
IOH = –20 µA
08×V
RESET TPS382x-30
TPS382x-33 VDD = VIT– + 0.2 V
IOH = –30 µA
0.8 × VDD V
TPS382x-50 VDD = VIT– + 0.2 V
IOH = –120 µAVDD – 1.5 V
VOH High-level output voltage TPS3824-25
TPS3825-25 VDD ≥ 1.8 V, IOH = –100 µA
RESET
TPS3824-30
TPS3825-30
08×V
V
RESET TPS3824-33
TPS3825-33 VDD ≥ 1.8 V, IOH = –150 µA0.8 × VDD V
TPS3824-50
TPS3825-50
TPS3824-25
TPS3825-25 VDD = VIT– + 0.2 V
IOL = 1 mA
RESET
TPS3824-30
TPS3825-30 V
DD
= V
IT
– + 0.2 V
04
V
RESET TPS3824-33
TPS3825-33
VDD
=
VIT
–
+
0
.
2
V
IOL = 1.2 mA 0.4 V
VOL Low-level output voltage TPS3824-50
TPS3825-50 VDD = VIT– + 0.2 V
IOL = 3 mA
TPS382x-25 VDD = VIT– – 0.2 V
IOL = 1 mA
RESET
TPS382x-30 V
DD
= V
IT
– –0.2 V
045
V
RESET TPS382x-33
VDD
=
VIT
–
0
.
2
V
IOL = 1.2 mA 0.45 V
TPS382x-50 VDD = VIT– – 0.2 V
IOL = 3 mA
Power-up reset voltage (see Note 2) VDD ≥ 1.1 V, IOL = 20 µA 0.4 V
TPS382x-25 2.21 2.25 2.30
TPS382x-30
T0°Cto85°C
2.59 2.63 2.69
V
TPS382x-33 TA = 0°C to 85°C2.88 2.93 3 V
V
Ne
g
ative-
g
oin
g
input threshold TPS382x-50 4.49 4.55 4.64
VIT–
Negative going
in ut
threshold
voltage (see Note 3) TPS382x-25 2.19 2.25 2.30
TPS382x-30
T 40°Cto125°C
2.55 2.63 2.69
V
TPS382x-33 TA = –40°C to 125°C2.84 2.93 3 V
TPS382x-50 4.44 4.55 4.65
TPS382x-25
V
Hysteresis at V input
TPS382x-30 30
mV
Vhys Hysteresis at VDD input TPS382x-33
30
mV
TPS382x-50 50
NOTES: 2. The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V
3. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) should be placed near the supply terminals.
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IIH(AV) Average high-level input current
WDI
WDI = VDD,
time average (dc = 88%) 120
IIL(AV) Average low-level input current WDI WDI = 0.3 V, VDD = 5.5 V
time average (dc = 12%) –15
WDI WDI = VDD 140 190
µ
A
IIH High-level input current MR MR = VDD × 0.7,
VDD = 5.5 V –40 –60
µA
I
Low level input current
WDI WDI = 0.3 V, VDD = 5.5 V 140 190
IIL Low-level input current MR MR = 0.3 V, VDD = 5.5 V –110 –160
TPS382x-25
I
Output short-circuit current
RESET
TPS382x-30 V
DD
= V
IT,
max
+ 0.2 V, –400
A
IOS
(see Note 4) RESET TPS382x-33
VDD
=
VIT
,
max
+
0
.
2
V
,
VO = 0 V
400
µA
TPS382x-50
O
–800
IDD Supply current WDI and MR unconnected,
Outputs unconnected 15 25 µA
Internal pullup resistor at MR 52 kΩ
CiInput capacitance at MR, WDI VI = 0 V to 5.5 V 5 pF
NOTE 4: The RESET short-circuit current is the maximum pullup current when RESET is driven low by a µP bidirectional reset pin.
timing requirements at RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN MAX UNIT
at VDD VDD = VIT– + 0.2 V, VDD = VIT- - 0.2 V 6µs
twPulse width at MR VDD ≥ VIT– + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD 1µs
w
at WDI VDD ≥ VIT– + 0.2 V, VIL = 0.3 x VDD, VIH = 0.7 x VDD 100 ns
switching characteristics at RL = 1 MΩ, CL = 50 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
Watchdog time out
TPS3820 V
DD
≥ V
IT
– + 0.2 V, 112 200 310 ms
ttout W atchdog time out TPS3823/4/8
VDD
≥
VIT
–
+
0
.
2
V
,
See T iming Diagram 0.9 1.6 2.5 s
t
Delay time
TPS3820 V
DD
≥V
IT
– + 0.2 V, 15 25 37
ms
tdDelay time TPS3823/4/5/8
VDD
≥VIT
–
+
0
.
2
V
,
See timing diagram 120 200 300 ms
t
PHL
Propagation (delay) time,
high-to-low-level out
p
ut
MR to RESET delay
(TPS3820/3/5/8)
VDD ≥VIT– + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD 0.1
µ
s
tPHL
high-to-low-level output VDD to RESET delay VIL = VIT- - 0.2 V,
VIH = VIT- + 0.2 V 25
µs
t
PLH
Propagation (delay) time,
low to high level out
p
ut
MR to RESET delay (TPS3824/5) VDD ≥VIT– + 0.2 V,
VIL = 0.3 x VDD,
VIH = 0.7 x VDD 0.1
µ
s
tPLH
low-to-high-level output VDD to RESET delay (TPS3824/5) VIL = VIT- - 0.2 V,
VIH = VIT- + 0.2 V 25
µs
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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TYPICAL CHARACTERISTICS
Figure 2
–40
1.001
1
0.999
0.998
–15 10 35
TA – Free-Air Temperature – °C
0.997
0.996
0.995
NORMALIZED INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE AT VDD
60 85
Normalized Input Threshold Voltage –VIT(T
A), VIT(25°C)
Figure 3
–0.5
19
7
5
0.5 1.5 2.5 3.5
VDD – Supply Voltage – V
3
1
–1
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
4.5 6.5
MR = Open
WDI = Open
TA = 25°C
11
9
5.5
– Supply Current –IDD Aµ
13
17
15
TPS382x-33
Figure 4
–50
–150
VI – Input Voltage at MR – V
–200
INPUT CURRENT
vs
INPUT VOLTAGE AT MR
50
0
85°C
–100
–40°C
– Input Current –IIAµ
VDD = 5.5 V
WDI = Open
–10 1 2 3 4 65
Figure 5
0
3
2.5
2
1.5
1IOL – Low-Level Output Current – mA
1
0.5
0
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
VDD = 2.66 V
WDI = Open
MR = Open
VOL– Low-Level Output Voltage – V
–40°C
85°C
2345678910
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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TYPICAL CHARACTERISTICS
Figure 6
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
0–50
IOH – High-Level Output Current – µA
VDD = 3.2 V
WDI = Open
MR = Open
VOH– High-Level Output Voltage – V
–40°C
85°C
–100 –150 –200 –250
3
2.5
2
1.5
1
0.5
0
3.5
Figure 7
0IOH – High-Level Output Current – µA
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
VDD = 5.5 V
WDI = Open
MR = Open
VOH – High-Level Output Voltage – V
–40°C
85°C
–100 –200 –300 –400
6
5
4
3
2
1
0–500 –600 –700
Figure 8
0
6
200 400 600 800
4
2
0
– Minimum Pulse Duration at V
MINIMUM PULSE DURATION AT VDD
vs
VDD THRESHOLD OVERDRIVE
1000
8
twsµ
VDD – Threshold Overdrive – mV
10 WDI = Open
MR = Open
DD–
TPS3820-xx-Q1, TPS3823-xx-Q1, TPS3824-xx-Q1, TPS3825-xx-Q1, TPS3828-xx-Q1
PROCESSOR SUPERVISORY CIRCUITS
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MECHANICAL DATA
DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE
0,10
M
0,20
0,95
0°–8°
0,25
0,35
0,55
Gage Plane
0,15 NOM
4073253-4/G 01/02
2,60
3,00
0,50
0,30
1,50
1,70
45
31
2,80
3,00
0,95
1,45 0,05 MIN
Seating Plane
5X
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-178
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