TOSHIBA TMP8085A TMP8085AP-2/T MP8085AHP-2 8-BIT MICROPROCESSOR 1. GENERAL DESCRIPTION The TMP8085AP-2/TMP8085AHP-2, hereafter on referred to as TMP8085A, is a 8 bit micro processing unit (MPU). TMP8085A uses a multiplexed data bus. The address is split between the 8 bit address bus and the 8 bit data bus. The on-chip address latches of TMP8155P-2/TMP8156P-2 allow a direct interface with TMP8085A. 2. FEATURES 0.8ySec Instruction Cycle (CLK Cycle Period @200nSec) e Single +5V Power Supply (TMP8085AP-2: 5V5%, TMP8085AHP-2: 5V 10%) e On-Chip Clock Generator (with External Crystal or RC Network) e On-Chip System Controller; Cycle status information available for Large System Control e 4 Vectored Interrupts (One is Non-Maskable) Decimal, Binary and Double Precision Arithmetic e Serial In/Serial Out Port e Direct Addressing Capability up to 64K Byte Memory Space e Compatible with Intels 8085A e Low Power Consumption (TMP8085AHP-2: Icc max=135mA) MPU85-1TOSHIBA TMP8085A 3. Ay XK? RESET OUT SOD siD TRAP RST?7.5 RST6.5 RST5.5 INTR INTA ADo AD, AD? AD3 ADg ADs ADs AD? Vss PIN CONNECTION (TOP VIEW) L ij 1 40 0 Vec {2 39 HOLD G3 38 0 HLDA a4 37 CLK (OUT) oe) 36 | RESETIN G6 35 0 READY 07 34 1 10/M 08 33 0 Sy a9 TMP8085A 320 RD 10 31 WR O14 30 ALE Q 12 29 {] So 413 28 1] Ais 0 14 27 2D Aja 15 26 0 Ay3 (] 16 250 Ar2 17 240 A G18 23D Aig G19 22 11 Ag 20 210 Ag 050489 Figure 3.1 MPU85-2TOSHIBA TMP8085A 4. BLOCK DIAGRAM INTR RST5,5, 6.5, 7.5 pores see eee a TRAP I I 1 - I ACCUMULATOR LATCK le [ TEMP. REG. | 5 i L INTERRUPT CONTROL ARITHMETIC t Locicunit (ALY) ; SOD INTERRUPT MASK i r SERIAL VOCONTROL j<x 5|D [ ACCUMULATOR | [ FLAG-REG. < ' INSTRUCTION REGISTOR I 1 y TEMP-REG. TEMP-REG, INSTRUCTION B - REG C - REG DECODER & MACHINE CYCLE D - REG - REG Rea Re ENCODING H STACK POINTER (SP) { 1 PROGRAM COUNTER (PC) LL RESET OUT INCREMENTER/DECREMENTER bone TIMING AND CONTROL ADDRESS LATCH RESET IN 16 ; b 4 ADDRESS BUFFER [~*----~ CLK) X2 RD So ALE YHLDA READY DATA/ADDRESS BUFFER ~ 3 X; WR INTA 5, /O/M HOLD {' | DATA/ADDRESS BUS ADDRESS BUS ADQ~7 ADg~15 050489 Figure 4.1 MPU85-3TOSHIBA TMP8085A 5. PIN NAME AND PIN DESCRIPTION X41, Xg Unput) Crystal, LC, or RC network are connected to X1 and Xg to drive the internal clock generator. K, and Xg can also be driven by an external clock source. The input frequency is devided by 2 to give the processors internal operating frequency. CLK(Output) Clock Output for use as a system clock. The period of CLK is twice the X1, X9 input period. RESETIN (Input) The RESETIN Input initializes the processor by clearing the program counter, instruction register, SOD latch, Interrupt Enable flip-flop and HLDA flip-flop. The address and data buses and the control] lines are 3-stated during RESET and because of the asynchronous nature of RESET, the processors internal registers and flags may be altered by RESET with unpredictable results. RESETIN is a Schmitttriggered input, allowing connection to an RC network for power on RESET delay. The TMP8085A is held in the reset condition as long as RESETIN is applied. RESET OUT (Output) The RESET OUT signal indicates that the TMP8085A is being reset. It can be used as a system reset. It is synchronized to the processor clock and lasts an integral number of clock periods. SOD (Output) Serial output data line. The output SOD is set or reset as specified by the SIM instruction. SID (Input) Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed. MPU85-4TOSHIBA TMP80854 e INTR (input) INTERRUPT REQUEST signal provides a mechanism for external devices to modify the instruction flow of the program in progress. It is sampled only during the next to the last clock cycle of an instruction and during Hold and Halt states. If it is recognized, the processor will complete the execution of the current instruction, and then the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by RESET and immediately after an interrupt is accepted. INTA (Output) INTERRUPT ACKNOWLEDGE: Occurs in response to an Interrupt input and indicates that the processor will be ready for an interrupt instruction on the data bus. It is used instead of (and has the same timing as) RD during the instruction cycle after an INTR is accepted. RST 5.5 } RST 6.5 (Inputs) RST 7.5 RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause an internal RESTART to be automatically inserted. These interrupts have a higher priority than INTR. The priority of these interrupts is ordered as shown Table 1. These interrupts are maskable using the SIM instruction. TRAP (Input) Trap interrupt is a nonmaskable RESTART interrupt. It is sampled at the same timing as INTR or RST 5.5-7.5. It is unaffected by SIM or Enable/Disable Interrupt instruction. It has the highest priority of any interrupt. e ADo-AD7 (Input/Output, 3-state) Lower 8 bits of the memory address (or I/O address) appear on the bus during the first clock cycle (Ty state) of a machine cycle. It then becomes the data bus during the second and third clock cycles. Ag-Aji5 (Output, 3-state) Upper 8 bits of the memory address or the 8 bits of the I/O address, 3-stated during Hold and Halt modes and during RESET. MPU85-5TOSHIBA TMP8085A e So, $1, and 10/M (Output) Machine cycle status: IO/MM 84 So Status tf) I 1 Opcode fetch 0 1 0 Memory read 0 0 1 Memory write 1 1 0 I/O read 1 0 1 I/O write 1 1 1 Interrupt Acknowledge TS 0 0 Halt TS x X Hold TS X Xx Reset Note : TS=3-state (high impedance) X=unspecified ALE (Output) Address Latch Enable: It occurs during the first clock state of a machine cycle and enables the address to get latched into the external latch or the on-chip latch of peripherals. The falling edge of ALE can be used to strobe the status information. ALE never goes 3-stated. e WR (Output, 3-state) WRITE control: A low level on WR indicates the data on the Data Bus is to be written into the selected memory or I/O location. Data is set up at the trailing edge of WR. It is 3-stated during Hold and Halt modes and during RESET. e D (Output, 3-state) READ control: A low level on RD indicates the selected memory or I/O device to be read and that the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET. READY (Input) When READY is inactive (low), indicating the external operation has not been complete yet, the processor will enter the Wait state. It will wait for an integral number of clock cycles until READY goes high before completing the read or write cycle. MPU85-6TOSHIBA TMP8085A HOLD (Input) The HOLD input cause TMP8085A to release the control over the address bus and the data bus. When HOLD goes active, the processor completes its current operation, activates the HLDA output, and puts the Address, Data, RD, WR, and IO/M lines into high-impedance state. Internal processing can continue. The Holding device can then utilize the address and data buses instead of TMP8085A. TMP8085A can regain the bus only after the HOLD goes inactive (low). HLDA (Output) The Hold Acknowledge output, HLDA signal isa response to a HOLD input. It indicates that TMP8085A has received the HOLD request and HOLD will release the bus control in the next cycle. HLDA goes low after the HOLD goes inactive (low). TMP8085A takes over the bus control one half clock after HDLA goes low. Vcc +5 volt supply e Vss Ground Reference MPU85-7TOSHIBA TMP8085A 6. FUNCTIONAL DESCRIPTION TMP8085A is a 8-bit central processor. TMP8085A is provided with internal 8-bit registers and 16-bit registers. TMP8085A has eight addressable 8-bit registers. Six of them can be used either as 8-bit registers or as 16-bit register pairs. In addition to the register pairs, the TMP8085A contains two additional 16-bit registers. TMP8085A register set is as follows: The acccumulator (A Register) is the focus of all of the accumulator instructions, which include arithmetic, logic, load and store, and I/O instructions. The program counter (PC) always points to the memory location of the next instrtiction to be executed. General-purpose registers BC, DE, and HL may be used as 8-bit registers or as three 16-bit registers, interchangeably, depending on the instruction being performed. The stack pointer (SP) is a special data pointer that always points to the stack top (next available stack address). The flag register contains five one-bit flags, each of which records processor status information and may also control processor operation. The five flags in TMP8085A are shown below: (MSB} D7 | Dg | Ds | Da | D3 | Dz | Dy | Do 5 Z AC P Cc The carry flag (C) is set and reset by arithmetic operations. An additional operation that resutls in an overflow out of the high-order bit of the accumulator sets the carry flag. The carry flag also acts as a borrow flag for subtract instruction. The auxiliary carry flag (AC) indicates overflow out of bit 3 of the accumulator in the same way that C flag indicates overflow out of bit 7. This flag is commonly used in BCD arithmetic. The sign flag (S) is set to the condition of the most significant (MSB) bit of the accumulator following the execution of arithmetic or logic instructions. The zero flag (Z) is set if the result generated by certain instructions is zero. The zero flag is cleared if the result is not zero. The parity flag (P) is set to 1 if the parity (number of 1-bits) of the accumulator is even. If odd, it is cleared. TMP8085A offers the functions of clock generation, MPU85-8TOSHIBA TMP8085A system bus control, and interrupt priority selection as well as execution of the instruction set. TMP8085A uses a multiplexed Data Bus. The address is split between the higher 8-bit Address Bus and the lower 8-bit Address/Data Bus. During the first T state (Ty clock cycle) of a machine cycle the lower order address is sent out on the Address/Data Bus. These lower 8 bits may be latched externally by the Address Latch Enable signal (ALE). During the rest of the machine cycle, the data bus is used for memory or I/O data transferring. MPU85-9TOSHIBA TMP8085A 7. INTERRUPT AND SERIAL I/O TMP8085A has 5 interrupt inputs: INTR, RST 5.5, RST 6.5, RST 7.5, and TRAP. INTR is identical in function to 8080A INT. Each of three RESTART inputs 5.5, 6.5, 7.5, has a programmable mask. TRAP is also one of RESTART interrupts but it is nonmaskable. The three RESTART interrupts cause the internal execution of RESTART if the interrupts are enabled and if the corresponding interrupt mask is not set. The nonmaskable TRAP always causes internal interrupt execution whether INTR, RST 5.5, RST 6.5 and RST 7.5 interrupts are enable or not. There are two different types of inputs in the restart interrupts. RST 5.5 and RST 6.5 are high-level sensitive like INTR and are recognized with the same timing as INTR. RST 7.5 is rising edge-sensitive. For RST 7.5, only a pulse is required to set an internal flip-flop which generates the interrupt request. The RST 7.5 request flip-flop remains set until the request is serviced. Then it is reset automatically. This flip-flop may also be reset by using the SIM instruction or by issuing a RESETIN to TMP8085A. The RST 7.5 internal flip-flop will be set by a pulse on the RST 7.5 pin even when the RST 7.5 interrupt is masked. The interrupts are arranged in a fixed priority that determines which interrupt is to be recognized if more than one is pending: TRAP-highest priority. RST 7.5, RST 6.5, RST 5.5, INTR-lowest priority. This priority scheme does not take into account the priority of a routine that was started by a higher priority interrupt. RST 5.5 can interrupt a RST 7.5 routine if the interrupts were reenabled before the end of the RST 7.5 routine. The TRAP interrupt is useful for catastrophic errors such as power failure or bus error. It is not affected by any flag or mask. The TRAP input is both edge and level sensitive. The TRAP input must go high and remain high until it is acknowledged. It will not be recognized again until it goes low, then high again. This avoids any false triggering due to noise or logic glitches. MPU85-10TOSHIBA TMP8085A Table 7.1 Interrupt Priority, Restart Address, and Sensitivity Name Priority Address branched to Type Trigger When Interrupt Occurs TRAP 1 24 (Hex. ) Rising edge and high level until sampled. RST 7.5 2 3C (Hex. } Rising edge (latched) . RST 6.5 3 34 (Hex. } High level until sampled. RST 5.5 4 2C (Hex. } High level until sampled. INTR . 5 See Note (2) High level until sampled. Notes: (1) The processor pushes the PC on the stack before branching to the indicated address... (2) The address branched to depends on the instruction provided to TMP8085A when the interrupt is acknowledged, The TRAP interrupt is special in that it disables all other interrupts, but preserves the previous interrupt enable status. Performing the first RIM instruction following a TRAP interrupt allows you to determine whether interrupts were enabled or disabled prior to the TRAP. All subsequent RIM instruction provide current interrupt enable status. Performing a RIM instruction following INTR, or RST 5.5-7.5 will provide current interrupt enable status, revealing that interrupts are disabled. The serial I/O system is also controlled by the RIM and SIM instructions. SID is read by RIM, and SIM sets the SOD date. MPU85-11TOSHIBA TMP8085A 8. BASIC TIMING The execution of each instruction by the TMP8085A consists of a sequence of from one to five machine cycles, and cach machine cycle consists of a minimum of from three to six clock cycles. Most machine cycles consist of three T states, (cycles of the CLK output) with the exception of opecode fetch, which normally has either four or six T states (unless WAIT or HOLD states are forced by the receipt of READY or HOLD inputs). Any T state must be one of ten possible states, shown in Table 3. At the beginning of every machine cycle, TMP8085A sends out three status signals (IO/M, 8}, So) that define what type of machine cycle is about to take piace. TMP8085A also sends out a 16-bit address at the beginning of every machine cycle to identify the particularmemory location or I/O port that the machine cycle applies to. The special timing signal, ADDRESS LATCH ENABLE (ALE), is used a strobe to sample the lower 8-bits of address on the ADg-AD7 lines. ALE is present during Ty of every machine cycle. Control lines RD (INTA) and WR become active later, at the time when the transfer of data is to take plece. Figure 3 shows an instruction fetch, memory read and I/O write cycle (as would occur during processing of the OUT instruction). Table 8.1 TMP8085 Machine Cycle Chart MACHINE CYCLE lo/M $4 So RD WR INTA OPCODE FETCH 0 1 1 0 1 1 MEMORY READ 0 7 0 0 1 1 MEMORY WRITE 0 0 1 1 0 1 1/0 READ 1 1 0 0 1 1 /O WRITE 1 0 1 1 0 1 ACKNOWLEDGE OF INTR 1 1 1 1 1 0 BUS IDLE: DAD 0 1 0 1 1 1 ACK. OF RST, 1 1 1 1 1 1 TRAP HALT TS 0 0 TS TS 1 050489 Notes : 0= Logic 0, 1= Logic 1, TS = High Impedance MPU85-12TOSHIBA TMP8085A Table 8.2 TMP8085 Machine State Chart wee $1.50 | lO/M | Ag-Ars | ad,-A07|RD. WR] INTA | ALE Ty x x x x 1 1 T> x x x x x x 0 Twat x x x x x x 0 T3 x x x x x x 0 Ta 1 O+ x TS 1 1 0 Ts 1 0+ x TS 1 1 0 Te 1 04 x TS 1 1 0 TRESET x TS TS TS TS 1 0 THALT 0 TS Ts Ts TS 1 0 THOLD x TS TS TS TS 1 fs) 950489 Notes: (1) 0=LOGIC 0, 1=Logic 1, TS = High Impedance, X= Unspecified (2) ALE not generated during 2nd and 3rd machine cycles of DAD instruction (3) +IO/M=1 during T4-T of INA maachine cycle M1 M2 M3 7 Tz 13 Ta 1 T2 3 1 T nf hh / clk - AB~AIS PCH (HIGH ORDER ADDRESS) x (PC+1)H xX. 10 PORT AD07 ma X_Y---- OCD eX # (LOW GRDER DATA FROM MEMORY DATA FROM MEMORY DATA TO MEMORY ADDRESS) INSTRUCTION} (uO PORT ADDRESS) OR PERIPHERAL we PX mT \ F711 . lo \ foo" STATUS XK $180.= 11 (FETCH) x 10 (READ) X01 (WRITE) ) 050489 Figure 8.1 TMP8085A Basic System Timing MPU85-13TOSHIBA TMP8085A 9. DRIVING THE X1 AND X2 INPUTS The clock inputs of TMP8085A may be driven by a crystal oscilator, an LC tuned circuit, an RC network or an external clock source. The Minimum driving frequency must be 1 MHz, and must be twice as much as the desired internal clock frequency. (1) Quartz Crystal Clock Driver Ifa crystal used, it must have the following characteristics. e Parallel resonance at twice the clock frequency desired e Cs (shunt capacitance) = 7 pF e = Rg (equivalent shunt resistance) = 75 Ohms C1 {I x1 tt Ez f TMP8085A Ci, Ty C2 to 050489 Figure 9.1 Note : A value of the external capacitors C1 and C2 between X1, X2 and ground. The following values are recommended IMHz =f<4MHz : Cy=20pF,Co=20pF 4MHz =fS 8MHz : C;=10pF,Co=10pF 8MHz <f = 10MHz : C,;=0,Ce=0 (2) LC Turned Circuit Clock Driver A parallel-resonant LC circuit may be used as the frequency-determining network for TMP8085A, providing that its frequency tolerance of approximately 10% is acceptable. The components are chosen from the formula. f= ___1___ 2tnf LD (Coxe + Cine) The use of an LC circuit is not recommended for frequencies higher than approximately 5 MHz. |__| TMP8085A Lext Cext = Cint= 1SpF X2 050489 Figure 9.2 MPU85-14TOSHIBA TMP8085A (3) RC Circuit Clock Driver An RC circuit may be used in the case without precise clock frequency stability. Variations in the on-chip timing generation can cause a wide variation in frequency when using RC circuit. The driving frequency generated by the circuit shown is approximately 3 MHz. It is not recommended that frequencies greatly higher or lower than this be attempted. x1 20pF = 10k TMP8085A f=3MHa2 I X2 050489 Figure 9.3 (4) External clock Driver Circuit +5V Duty 45 ~ 55% 4702 /- { +5V TMP8085A 470Q | X2 osoagg Figure 9.4 MPU85-15TOSHIBA TMP8085A 10. POWER-ON-RESET The TMP8085A is not guaranteed to work until 10 ms after Voc reaches 4.75V. It is suggested that RESETIN be kept low during this period. Note that the 10 ms period does not include the time it takes for the power supply to reach its 4.75V level. For the TMP8085AHP-2, Power-on-reset can be performed when the supply voltage reaches 4.50V. MPU85-16TOSHIBA TMP8085A 11. INSTRUCION SET The code and function of machine instructions are shown as following table. In this table the symbols and abbreviated symbols are used for describing the instructions. However, the symbols required for special attention are explained on the page using them, Explanation of Symbols Division Symbol Description r, g Register B, C, 0, E, H, L, A Register pair BC, DE, HL 5 . Stack pointer SP o q Register pair BC, DE, HL Program status word PSW mn Memory address or immediate data indicated by 16 bits = m expresses higher 8 bits and n expresses lower 8 bits E (mn) Contents of memory address indicated by mn s (HL) Contents of memory address indicated by register pair Contents of memory address indicated by register pair BC ,DE and SP 3 Be reset to 0 Besetto 1 o - No change = * Be affected by operation (be set to 0 or 1.) 3 < Transfer < Exchange a + Addition 6 - Subtraction 3 A Logical AND for every bit a Logical OR for every bit Exclusive OR for every bit IM Interrupt mask register 5 cy Carry flag 050489 MPU85-17TOSHIBA TMP8085A TLCS-85 List of Machine Instruction (1/2) = OBJECT CODE | ASSEMBLER FUNCTION FLAGS ole u BIN HEX > le a MNEMONIC 7 T * 7 wulw z 76 543 210 cy: 2 S Po: AC : 40+gx8+r Td rrr LF ggg | Register Jott. 7. 2) 7) oot c bec ee tetera teense neee 010 Dd o {HL jen 3 | (Ob oy 5 a 100 H om LL ACBC) 240.7) 101 L tO AK DO, OFT O10 TO, 21.7} a} oa 2 LDA mn 00 111 010 3A A<(mn) 4 43 na oomn onan n eect ec TD Leanne ee sneer edirmetnsbesegesegeael ene StAX 00/900 010 02 | Ba sssussafat ge tatiudateeet de 2 [07 STAR OO 00.070 010 ae Oe cas usummanfetutetieictobetak tafe 2 |? STA mn 60 110 010 32 {min} a, 4 43 nn oonn nnn n mommmmrmion | om tt Register LXE t. mn OO ttO 001 Ol4+tx16 temn 3 10 00 BC Ano Aan onan n oI DE bce SMMAM MMMM | ML oe cette terest tittsett tees leeebcederderbeccpeee 10 BL so LHLD mn 00 101 610 2A H (mn + 1) 5 16 i SP 5 np onan onan n Le(mn) Te cee OMIM | cc centtecitinticifeat intended pes * TSHLB mn 00 100 010 | 22 {mn + 1)-H 5 | 16 s an oan onnn n {mnjeL _ a mmmmmmmm | m / SPL PER DTT O01 VRS SP 118 PUSH 4 Vi qqQ 161 Co Gxt {SP - 1){SP - 2)-q 3 12 Register better) cctetr eee chee eee | SPSP 2, oJ 0 BC POP gq 1i qq 001 C1+qx6 q (SP + 1}(SP) 3 10 01 DE SP <S$P +2 10 HL ae RS), we vor orn Tee | BEN tubetaptid tub ted. wf a] | esw = LXTHL 41100 611 | 3 HO@(SP + 1),Le(SP} 5 | 16 A AdCr 1 a PSW only ASA jaf. 7 a Sa a oS o Cc oS we . uv = (HL) - Ecce PEE ie cere ca w . G 3 oo 050489 MPU85-18TOSHIBA TMP8085A TLCS-85 List of Machine Instruction (2/2) Note: PoP psw instruction changes state of flags. (a) Exechange (c) 16bit arithmetic (d) Input and output (ce) Interrupt 2 OBJECT CODE a eT ASSEMBLER FUNCTION FLAGS g a uo \ BIN REX 2 MNEMONIC aI a 76 543 210 Cy: 2 $ Por ac | XRl n y1101 110 J Ef Aecayn Gir iri*e sg [3 7 S nA Ann Ann n fe cere ft wotae etree dpans - - 90 v a E ov oe os o - a2 20 Bole [te cere O19 0 | 76 we cree ev een Pewee eee ees JA 1 4 DD En, OO te O07 FOF etx 10 110. 2 pM 00 tO O11 foset x10 de DCX t OO tt) O11 OB+tx10 RLC 00 000 111 G? a we 2D RAL 00 010 111 WF c a v Pat wf RRC 00 061 111 OF pa Do fee rcc eee cece Pe eee ee ca ealersenseuereneenee ot RAR 00 011 #111 1F JMP ma 11 000 O11 C3 An Anh nan n vee Om Md veo veeteteseeee c [# mn li_ecc 6010 C2+Cx8 | IF ce is t PCemn a ce Condition 5 An nnn ann n otherwise, PCePC +3 000; NZ |} no zero B fon mmmmemmmm | m Seti tdettee tt teers 001) Z| zero " LPCHE JT 701 067 Jeo Pe HE O40) NC] nocarry 2 CALL mn 14 061 101 co (SP 1)(SP - 2}PC, Oy Cc carry 9 an nnn nnn n SP e-SP-2, 100] PO | parity odd = ee mmmrammmm fm 101) PE | parity even cS [ee mn 11 cece 100 C4acx8 140] P sign positive nmonon nnn n 111) M sign negative Blceeceeeecs mmmenmmmm | mn otherwise, PCE? a | RET 11001 001 cy PCE (SP + 1XSP), E ; $P<-SP +2 ; . = | Re Ti eee IF Cs true, PCe(SP + 1)(SP), kha} SPO ene d00) 0 otherwise, PCHPC +1 : oo! 1 RST J ii kkk (SP = 1}(SP - 2}ePC, 010) 2 SPe-SP ~ 2, PCkkk xB O11) 3 IN a 110714 011 DB A &(n) ~ - - - - 3 JO} 100! 4 SD fo. eee en Oc ee teeter . Wr, 5 ~ | OUT n 11,010 041 D3 in) e - - = - - 3 10 110] 6 mnaoann ann n Vii] 7 | RIM 00 100 000 20 A iM ~ - - 1 4 OD fever vce sce eec tee eecees weet tesetit teres phe Fcc e nicer cess eteeeceneeeeseeerenenaea Tet Teh pep. 7 SIM 00 110 000 | 30 IM ea ee | 4 050489 (hb) General purpose arithmetic and MPU control MPU85-19TOSHIBA TMP8085A 12. ELECTRICAL CARACTERISTICS 12.1 ABSOLUTE MAXIMUM RATINGS Symbol Item Ratings Units vcc VCC Supply voltage -0.5to +7.0 V PD Power Dissipation 1.5 Ww Tsolder Soldering Temperature 26G (10 sec) a Tstg Storage Temperature ~55 to 150 C Topr Operating Temperature Oto 70 C 050489 12.2 DC CHARACTERISTICS TA=O0Cto 70C, VCC =5V 45% : TMP8085AP-2 VCC =5V+10% +: TMP8085AHP-2 Symbol Parameter Test Conditions Min. Max. Units VIL Input Low Voltage -05 0.8 V VIH Input High Voltage 2.0 | vcc+05 Vv VOL Output Low Voltage tOL=2mA 0.45 Vv VOH Output High Voltage IOH = 400pA 2.4 V ICC Power Supply Current TMP8085AP/AP-2 170 mA TMP8085AHP/AHP-2 135 IL Input Leakage OSVINS VCC +10 pA ILO Output Leakage 0.455 VOUTS VCC +710 pA VILR Input Low Level (RESET) -0.5 0.8 Vv VIHR Input High Level (RESET) 2.4 | vcc+05 Vv VHY Hysteresis (RESET) 0.25 Vv 050489 MPU85-20TOSHIBA TMP8085A 12.3 AC CHARACTERISTICS TA=0C to 70C, Veco =5V 45% > TMP8085AP-2 VCC=5V+10% : TMP8085AHP-2 Vss = OV, unless otherwise noted. Symbol Parameter Min. Max. Units tCYC CLK Cycle Period 200 2000 ns tL CLK Low Time 40 ns 50* ns tH CLK High Time 70 ns 1 80* ns tr, tf CLK Rise and Fall Time 30 ns tXKR X1 Rising to CLK Rising 30 100 ns tXKF X71 Rising to CLK Falling 30 110 ns tAc A8-15 Valid to Leading Edge of Control [1] 115 ns tACL AQ-7 Valid to Leading of Control 115 ns tAD AQ-15 Valid to Valid Data in 350 ns tAFR Address Float after Leading Edge of ALE READ 0 ns (tNT} tAL 48-15 Valid before Trailing Edge of ALE [1] 50 ns tALL AQ-? Valid before Trailing Edge of ALE 50 ns tARY READY Valid from Address Valid 100 ns tCA Address (A8-15) Valid after Control 60 ns tcc Width of Control Low (RD, WR, INTA) Edge of 230 ns ALE tCL Trailing Edge of Control to Leading Edge of ALE 25 ns tDW Data Valid to Trailing Edge of WRITE 230 ns tHABE |HLDAto Bus Enable 150 ns tHABF Bus Float after HLDA 150 ns tHACK | HLDA Valid to Trailing Edge of CLK 40 ns tHDH HOLD Hold Time 0 ns tHDS HOLD Setup Time to Traiting Edge of CLK 120 ns tINH INTR Hold Time 0 ns tINS INTR, RST and TRAP Setup Time to Falling 150 ns tLA Edge of CLK Address Hold Time after ALE 50 ns tLc Trailing Edge of ALE to Leading Edge of Control 60 ns 050489 MPU85-21TOSHIBA TMP8085A Symbol Parameter Min. Max. Units tLCK ALE Low during CLK High 50 ns tLDR ALE to Valid Data during Read 270 ns tLDW ALE to Valid Data during Write 120 ns tLL ALE Width 80 ns tLRY ALE to READY Stable 30 ns tRAE Trailing Edge of READ to Re-Enabting of Address 90 ns tRD ~ |READ (or INTA) to Valid Data 150 ns tRV Control Trailing Edge of Leading Edge of Next 220 ns Control tROH Data Hold Time After READ INTA Q ns tRYH READY Hold Time 0 ns tRYS READY Setup Time to Leading Edge of CLK 100 ns twD Data Valid After Trailing Edge of WRITE 60 ns tWDL LEADING Edge of WRITE to Data Valid 20 ns Test conditions Notes : CL= 150pF (*: CL=50pF + 1TTL) tcyc = 200ns of Cycle whereas IO/M, 80, and Si are stable. 2. Timing defining signal voltage are; Output High level=2.0V, Low level =0.8V 3. To calculate timing specifications at other value of tCYC use Table 12.1. 950489 1, A8-15 address specs apply to IO/M, $0 and S1 expect A8-15 are undifiend during T4-T6 MPU85-22TOSHIBA TMP8085A 12.4 TIMING WAVEFORMS X17 INPUT CLK OUTPUT 050489 Figure 12.1 Clock Timing Waveform CLK A8~A15 $0, 51, 10/M ADDRESS, STATUS tAD ADO~AD7 DATA IN 050489 Figure 12.2 Read Operation | m | 12 73 | CLK A8~A15 | MAL T. so, $1, 10/M ADDRESS, STTAUS tcA | J ADO~AD? ADDRESS DATA OUT pS \__ttDw tow __||. two | tWOL _ ALE tlc tcl | . th tcc ~ WR 0 re re tAC | 050489 Figure 12.3 Write Operation MPU85-23TOSHIBA TMP8085A T1 T2 TWAIT | T3 | T1 CLK A8~A15 $051 |O/M ADDRESS] STATUS tAD ADDRESS --< tLA ADO~AD?7 t ALE RD/INTA READY 050489 Figure 12.4 Read Operation with Wait Cycle (Typical) - Same Ready Timing Applied to | | m1 T1 | T2 73 fe ee AN Fr INTR ee rite Operation tHDS tHDH| HOLD f L7 i Lea \ st HLDA x - \. tHACK TSH tHABE tHABE A8~A15 lo/M x ADDRESS y- - ae --------- k A00-7 XG) ~~ GUAT) - --- aqngmee7-{ WR 050489 Figure 12.5 Interrupt and Hold Timing MPU85-24TOSHIBA TMP8085A 13. OUTLINE DRAWING (40PINS PLASTIC PACKAGE) DIP40-P-600 Unit: mm 50.7 +0.2 zits Sw 1.22TYP 2 in m 270289 Note: Each lead pitch is 2.54mm, and all the leads are located within +0.25mm from their theoritical positions with respect to No.1 and Na.40 leads. MPU85-25