MOTOROLA CMOS LOGIC DATA 1
MC14585B
  
The MC14585B 4–Bit Magnitude Comparator is constructed with comple-
mentary MOS (CMOS) enhancement mode devices. The circuit has eight
comparing inputs (A3, B3, A2, B2, A1, B1, A0, B0), three cascading inputs
(A < B, A = B, and A > B), and three outputs (A < B, A = B, and A > B). This
device compares two 4–bit words (A and B) and determines whether they
are “less than”, “equal to”, or “greater than” by a high level on the appropriate
output. For words greater than 4–bits, units can be cascaded by connecting
outputs (A > B), (A < B), and (A = B) to the corresponding inputs of the next
significant comparator. Inputs (A < B), (A = B), and (A > B) on the least
significant (first) comparator are connected to a low, a high, and a low,
respectively.
Applications include logic in CPUs, correction and/or detection of
instrumentation conditions, comparator in testers, converters, and controls.
Diode Protection on All Inputs
Expandable
Applicable to Binary or 8421–BCD Code
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
Can be Cascaded – See Fig. 3
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MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
per Pin ± 10 mA
PDPower Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150
_
C
TLLead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
TRUTH TABLE (x = Don’t Care)
Inputs
Outputs
Comparing Cascading
Outputs
A3, B3 A2, B2 A1, B1 A0, B0 A < B A = B A > B A < B A = B A > B
A3 > B3 x x x x x x 0 0 1
A3 = B3 A2 > B2 x x x x x 0 0 1
A3 = B3 A2 = B2 A1 > B1 x x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 > B0 x x x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 x 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 x 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 x 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 x 1 1 0
A3 = B3 A2 = B2 A1 = B1 A0 < B0 x x x 1 0 0
A3 = B3 A2 = B2 A1 < B1 x x x x 1 0 0
A3 = B3 A2 < B2 x x x x x 1 0 0
A3 < B3 x x x x x x 1 0 0

SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94

L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
14
15
1
2
9
7
11
10
5
6
4
13
3
12
VDD = PIN 16
VSS = PIN 8
(A > B)in
(A = B)in
(A < B)in
A0
B0
A1
B1
A2
B2
A3
B3
(A > B)out
(A = B)out
(A < B)out
MOTOROLA CMOS LOGIC DATAMC14585B
2
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
– 55
_
C 25
_
C 125
_
C
Unit
Characteristic
Symbol
VDD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0 VOL 5.0
10
15
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD VOH 5.0
10
15
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10
15
4.95
9.95
14.95
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
3.5
7.0
11
2.75
5.50
8.25
3.5
7.0
11
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
– 1.7
– 0.36
– 0.9
– 2.4
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.8
0.36
0.9
2.4
mAdc
Input Current Iin 15 ±0.1 ±0.00001 ±0.1 ±1.0 µAdc
Input Capacitance
(Vin = 0) Cin 5.0 7.5 pF
Quiescent Current
(Per Package) IDD 5.0
10
15
5.0
10
20
0.005
0.010
0.015
5.0
10
20
150
300
600
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (0.6 µA/kHz) f + IDD
IT = (1.2 µA/kHz) f + IDD
IT = (1.8 µA/kHz) f + IDD
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only at 25
_
C.
To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
(A
t
B)out
(A
u
B)out
B3
A3
VDD
B1
A0
B0
(A
u
B)in
(A = B)out
A2
B2
VSS
A1
(A = B)in
(A
t
B)in
MOTOROLA CMOS LOGIC DATA 3
MC14585B
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ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25
_
C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL 5.0
10
15
100
50
40
200
100
80
ns
Turn–On, Turn–Off Delay Time
tPLH, tPHL = (1.7 ns/pF) CL + 345 ns
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns
tPLH,
tPHL 5.0
10
15
430
180
130
860
360
260
ns
*The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
Figure 1. Dynamic Power Dissipation
Signal Waveforms Figure 2. Dynamic Signal Waveforms
20 ns
20 ns
2f
1
VDD
VSS
VDD
VSS
VOH
VOL
VOH
VOL
VOH
VOL
(A < B)out
(A = B)out
(A > B)out
B3
A3
20 ns 20 ns
VDD
VSS
VOH
VOL
90%
50%
10%
tPLH tPHL
tTLH tTHL
90%
50%
10%
B0
(A = B)out
(A < B)out
Inputs (A>B) and (A=B) high, and inputs B3, A3, B2,
A2, B1, A1, A0, and (A<B) low.
Inputs (A>B) and (A=B) high, and inputs B2, A2, B1,
A1, B0, A0 and (A<B) low.
f in respect to a system clock.
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However ,
precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance
circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must
be left open.
MOTOROLA CMOS LOGIC DATAMC14585B
4
Figure 3. Cascading Comparators
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 VSS VDDVSS
WORD
B =
A =
WORD
MC14585B
MC14585B
MC14585B
B3 A3 B2 A2 B1 A1 B0 A0
(A<B)
(A=B)
(A>B)
INPUTS
(A<B)
(A=B)
(A>B)
OUTPUT
(A<B)
(A=B)
(A>B)
OUTPUTS
WORD B = B11, B10, ..., B0.
WORD A = A11, A10, ..., A0.
15
14
2
1
7
9
10
11
5
6
4
(A > B)in
(A = B)in
(A < B)in
B0
A0
B1
A1
B2
A2
B3
A3
12
3
13
(A < B)out
(A = B)out
(A > B)out
LOGIC DIAGRAM
MOTOROLA CMOS LOGIC DATA 5
MC14585B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
FE
G
NK
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.750 0.785 19.05 19.93
B0.240 0.295 6.10 7.49
C––– 0.200 ––– 5.08
D0.015 0.020 0.39 0.50
E0.050 BSC 1.27 BSC
F0.055 0.065 1.40 1.65
G0.100 BSC 2.54 BSC
H0.008 0.015 0.21 0.38
K0.125 0.170 3.18 4.31
L0.300 BSC 7.62 BSC
M0 15 0 15
N0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
MOTOROLA CMOS LOGIC DATAMC14585B
6
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
RX 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided
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MC14585B/D
*MC14585B/D*