IDT72V265LA15PFI8 - Integrated Device Technology

PRELIMINARY

IDT72V255

IDT72V265

3.3 VOLT CMOS SUPERSYNC FIFO

8,192 x 18, 16,384 x 18

Integrated Device Technology, Inc.

SuperSync FIFO and SyncFIFO are trademarks and the IDT logo is a registered trademark of Integrated Device Technology, Inc.

FUNCTIONAL BLOCK DIAGRAM

FEATURES:

• 3.3 Volt operation saves 60 percent power compared to

the functionally compatible 5 Volt 72255/65 Family

• 8,192 x 18-bit storage capacity (IDT72V255)

• 16,384 x 18-bit storage capacity (IDT72V265)

• 15ns read/write cycle time (10ns access time)

• Retransmit Capability

• Auto power down reduces power consumption

• Master Reset clears entire FIFO, Partial Reset clears

data, but retains programmable settings

• Empty, Full and Half-full flags signal FIFO status

• Programmable Almost Empty and Almost Full flags, each

flag can default to one of two preselected offsets

• Program partial flags by either serial or parallel means

• Select IDT Standard timing (using

and

flags) or

First Word Fall Through timing (using

and

flags)

• Easily expandable in depth and width

• Independent read and write clocks (permit simultaneous

reading and writing with one clock signal)

• Available in the 64-pin Thin Quad Flat Pack (TQFP), 64-

pin Slim Thin Quad Flat Pack (STQFP) the 68-pin Pin

Grid Array (PGA)

• Output enable puts data outputs into high impedance

• High-performance submicron CMOS technology

DESCRIPTION:

The 72V255/72V265 are functionally compatible versions

of the 72255/65 designed to run off a 3.3V supply for excep-

tionally low power consumption. The IDT72V255/72V265 are

monolithic, CMOS, high capacity, high speed, First-In, First-

Out (FIFO) memories with clocked read and write controls.

These FIFOs are applicable for a wide variety of data buffering

needs, such as optical disk controllers, local area networks

(LANs), and inter-processor communication.

Both FIFOs have an 18-bit input port (Dn) and an 18-bit

output port (Qn). The input port is controlled by a free-running

clock (WCLK) and a data input enable pin (

WEN

). Data is

written into the synchronous FIFO on every clock when

WEN

is asserted. The output port is controlled by another clock pin

(RCLK) and enable pin (REN). The read clock can be tied to

the write clock for single clock operation or the two clocks can

run asynchronously for dual clock operation. An output

MILITARY AND COMMERCIAL TEMPERATURE RANGES DECEMBER 1995

INPUT REGISTER

OUTPUT REGISTER

RAM ARRAY

8,192 x 18

16,384 x 18

•

FLAG

LOGIC

PAF

PAE

READ POINTER

READ

CONTROL

LOGIC

WRITE CONTROL

LOGIC

WRITE POINTER

RESET LOGIC

WEN

WCLK D0-D17

MRS

REN

RCLK

Q0-Q17

•

TIMING

OFFSET REGISTER

•

PRS

FWFT/SI

SEN

3478 drw 01

5.04 1

1996 Integrated Device Technology DSC-3478/-

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

5.04 2

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

enable pin (

) is provided on the read port for three-state

control of the outputs.

The IDT72V255/72V265 have two modes of operation: In

the

IDT Standard Mode

, the first word written to the FIFO is

deposited into the memory array. A read operation is required

to access that word. In the

First Word Fall Through Mode

(FWFT), the first word written to an empty FIFO appears

automatically on the outputs, no read operation required. The

state of the FWFT/SI pin during Master Reset determines the

mode in use.

The IDT72V255/72V265 FIFOs have five flag functions,

(Empty Flag or Output Ready),

(Full Flag or Input

Ready), and HF (Half-full Flag). The

and

functions are

selected in the IDT Standard Mode.

The

and

functions are selected in the First Word Fall

Through Mode.

indicates that the FIFO has free space to

receive data.

indicates that data contained in the FIFO is

available for reading.

HF is a flag whose threshold is fixed at the half-way point

in memory. This flag can always be used irrespective of

mode.

PAE

PAF

can be programmed independently to any point

in memory. They, also, can be used irrespective of mode.

Programmable offsets determine the flag threshold and can

be loaded by two methods: parallel or serial. Two default

offset settings are also provided, such that

PAE

can be set at

127 or 1023 locations from the empty boundary and the

PAF

threshold can be set at 127 or 1023 locations from the full

boundary. All these choices are made with

during Master

Reset.

In the serial method,

SEN

together with

are used to load

the offset registers via the Serial Input (SI). In the parallel

method,

WEN

together with

can be used to load the offset

registers via Dn. REN together with

can be used to read

the offsets in parallel from Qn regardless of whether serial or

parallel offset loading is selected.

During Master Reset (

MRS

), the read and write pointers are

set to the first location of the FIFO. The FWFT line selects IDT

Standard Mode or FWFT Mode. The

pin selects one of two

partial flag default settings (127 or 1023) and, also, serial or

PIN CONFIGURATIONS

PIN 1

WEN

SEN

VCC

GND

D17

D16

D15

D14

D13

D12

D11

D10

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q17

Q16

GND

Q15

Q14

VCC

Q13

Q12

Q11

GND

Q10

GND

PN64-1

PP64-1

WCLK

PRS

MRS

FWFT/SI

GND

PAF

PAE

RCLK

REN

GND

3478 drw 02

TQFP

STQFP

TOP VIEW

5.04 3

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

parallel programming. The flags are updated accordingly.

The Partial Reset (

PRS

) also sets the read and write

pointers to the first location of the memory. However, the

mode setting, programming method, and partial flag offsets

are not altered. The flags are updated accordingly.

PRS

useful for resetting a device in mid-operation, when repro-

gramming offset registers may not be convenient.

The Retransmit function allows the read pointer to be reset

to the first location in the RAM array. It is synchronized to

RCLK when

is LOW. This feature is convenient for

sending the same data more than once.

If, at any time, the FIFO is not actively performing a function,

the chip will automatically power down. This occurs if neither

a read nor a write occurs within 10 cycles of the faster clock,

RCLK or WCLK. During the Power Down state, supply current

consumption (ICC2) is at a minimum. Initiating any operation

(by activating control inputs) will immediately take the device

out of the Power Down state.

The IDT72V255/72V265 are depth expandable. The addi-

tion of external components is unnecessary. The

and

functions, together with REN and

WEN

, are used to extend the

total FIFO memory capacity.

The FS line ensures optimal data flow through the FIFO. It

is tied to GND if the RCLK frequency is higher than the WCLK

frequency or to Vcc if the RCLK frequency is lower than the

WCLK frequency

The IDT72V255/72V265 is fabricated using IDT’s high

speed submicron CMOS technology.

NOTES:

1. DNC = Do not connect

PGA

TOP VIEW

PIN CONFIGURATIONS (CONT.)

Pin 1 Designator

ABCDEFGHJKL

Q0D2

PAF

DNC

VCC

RCLK

RENOE

GND

DNC

MRS

WCLK

PRS

VCC

WEN

D17

GND

D15

D16

D11

D14

D12

D10

D7D6

PAE

D3D1

GND

Q3Q4GND

Q8Q7

Q10

DNC

GND

VCC

Q17 Q16

Q15

Q14

Q13 Q12

FWFT/

D13

D5GND

VCC

GND

Q11

G68-1

3478 drw 03

SEN

GND

5.04 4

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

Symbol Name I/O Description

D0–D17 Data Inputs I Data inputs for a 18-bit bus.

MRS

Master Reset I

MRS

initializes the read and write pointers to zero and sets the output register to

all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT

Standard Mode, one of two programmable flag default settings, and serial or

parallel programming of the offset settings.

PRS

Partial Reset I

PRS

initializes the read and write pointers to zero and sets the output register to

all zeroes. During Partial Reset, the existing mode (IDT or FWFT), programming

method (serial or parallel), and programmable flag settings are all retained.

Retransmit I Allows data to be resent starting with the first location of FIFO memory.

FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode.

Through/Serial In After Master Reset, this pin functions as a serial input for loading offset registers

WCLK Write Clock I When enabled by

WEN

, the rising edge of WCLK writes data into the FIFO and

offsets into the programmable registers.

WEN

Write Enable I

WEN

enables WCLK for writing data into the FIFO memory and offset registers.

RCLK Read Clock I When enabled by

REN

, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

REN

Read Enable I

REN

enables RCLK for reading data from the FIFO memory and offset registers.

Output Enable I

controls the output impedance of Qn

SEN

Serial Enable I

SEN

enables serial loading of programmable flag offsets

Load I During Master Reset,

selects one of two partial flag default offsets (127 and

1023) and determines programming method, serial or parallel. After Master

Reset, this pin enables writing to and reading from the offset registers.

FS Frequency Select I The FS setting optimizes data flow through the FIFO.

Full Flag/ O In the IDT Standard Mode, the

function is selected.

indicates whether or

Input Ready not the FIFO memory is full. In the FWFT mode, the

function is selected.

indicates whether or not there is space available for writing to the FIFO memory.

Empty Flag/ O In the IDT Standard Mode, the

function is selected.

indicates whether or

Output Ready not the FIFO memory is empty. In FWFT mode, the

function is selected.

indicates whether or not there is valid data available at the outputs.

PAF

Programmable O

PAF

goes HIGH if the number of free locations in the FIFO memory is more than

Almost Full Flag offset m which is stored in the Full Offset register.

PAF

goes LOW if the num-

ber of free locations in the FIFO memory is less than m.

PAE

Programmable O

PAE

goes LOW if the number of words in the FIFO memory is less than offset n

Almost Empty which is stored in the Empty Offset register.

PAE

goes HIGH if the number of

Flag words in the FIFO memory is greater than offset n.

Half-full Flag O

indicates whether the FIFO memory is more or less than half-full.

Q0–Q17 Data Outputs O Data outputs for a 18-bit bus.

VCC Power +3.3 Volt power supply pins.

GND Ground Ground pins.

PIN DESCRIPTION

3478 tbl 01

5.04 5

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

RECOMMENDED DC

OPERATING CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCCM Military Supply 3.0 3.3 3.6 V

Voltage

VCCC Commercial Supply 3.0 3.3 3.6 V

Voltage

GND Supply Voltage 0 0 0 V

VIH Input High Voltage 2.0 — Vcc+0.5 V

Commercial

VIH Input High Voltage 2.0 — Vcc+0.5 V

Military

VIL(1) Input Low Voltage — — 0.8 V

Commercial & Military

NOTE: 3478 tbl 03

1. 1.5V undershoots are allowed for 10ns once per cycle.

ABSOLUTE MAXIMUM RATINGS(1)

Symbol Rating Commercial MIilitary Unit

VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with respect to GND

TAOperating 0 to +70 –55 to +125 °C

Temperature

TBIAS Temperature Under –55 to +125 –65 to +135 °C

Bias

TSTG Storage –55 to +125 –65 to +155 °C

Temperature

IOUT DC Output Current 50 50 mA

NOTE: 3478 tbl 02

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RAT-

INGS may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

DT72V255L IDT72V255L

IDT72V265L IDT72V265L

Commercial Military

tCLK = 15, 20ns tCLK = 20, 25ns

Symbol Parameter Min. Typ. Max. Min. Typ. Max. Unit

ILI(1) Input Leakage Current (any input) –1 — 1 –10 — 10 µA

ILO(2) Output Leakage Current –10 — 10 –10 — 10 µA

VOH Output Logic “1” Voltage, IOH = –2 mA 2.4 — — 2.4 — — V

VOL Output Logic “0” Voltage, IOL = 8 mA — — 0.4 — — 0.4 V

ICC1(3) Active Power Supply Current — — 100 — — 100 mA

ICC2(3,4) Power Down Current (All inputs = VCC - 0.2V or — — 10 — — 10 mA

GND + 0.2V, RCLK and WCLK are free-running)

NOTES:

1. Measurements with 0.4 ≤ VIN ≤ VCC.

= VIH

3. Tested at f = 20 MHz with outputs unloaded.

4. No data written or read for more than 10 cycles

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Military: VCC = 3.3V ± 0.3V, TA = –55°C to +125°C)

NOTES:

1. With output deselected, (

=HIGH).

2. Characterized values, not currently tested.

Symbol Parameter(1) Conditions Max. Unit

CIN(2) Input VIN = 0V 10 pF

Capacitance

COUT(1,2) Output VOUT = 0V 10 pF

Capacitance

3478 tbl 05

CAPACITANCE (TA = +25°C, f = 1.0MHz)

3478 tbl 04

5.04 6

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC =3.3V ± 0.3V, TA = 0°C to +70°C; Military: VCC = 3.3V ± 0.3V, TA = –55°C to +125°C)

1.5V

3478 tbl 06

Commercial Com'l & Mil. Military

72V255L15 72V255L20 72V255L25

72V265L15 72V265L20 72V265L25

Symbol Parameter Min. Max. Min. Max. Min. Max. Unit

fSClock Cycle Frequency — 66.7 — 50 — 40 MHz

tAData Access Time 2 10 2 14 3 15 n s

tCLK Clock Cycle Time 15 — 20 — 25 — ns

tCLKH Clock High Time 6 — 8 — 10 — ns

tCLKL Clock Low Time 6(2) —8 — 10 —ns

DS Data Set-up Time 4 — 5 — 6 — ns

tDH Data Hold Time 1 — 1 — 1 — ns

tENS Enable Set-up Time 4 — 5 — 6 — ns

tENH Enable Hold Time 1 — 1 — 1 — ns

tLDS Load Set-up Time 4 — 5 — 6 — ns

tLDH Load Hold Time 10 — 10 — 10 — ns

tRS Reset Pulse Width(3) 15 — 20 — 25 — ns

tRSS Reset Set-up Time 15 — 20 — 25 — ns

tRSR Reset Recovery Time 15 — 20 — 25 — ns

tRSF Reset to Flag and Output Time — 15 — 20 — 25 ns

tFWFT Mode Select Time 0 — 0 — 0 — ns

tRTS Retransmit Set-Up Time 4 — 5 — 6 — ns

tOLZ Output Enable to Output in Low Z(4) 0—0—0—ns

OE Output Enable to Output Valid 3 8 3 10 3 13 ns

tOHZ Output Enable to Output in High Z(4) 38310313ns

WFF Write Clock to

— 10 — 12 — 15 ns

tREF Read Clock to

— 10 — 14 — 15 ns

tPAF Write Clock to

PAF

— 10 — 12 — 15 ns

tPAE Read Clock to

PAE

— 10 — 12 — 15 ns

tHF Clock to

— 20 — 25 — 25 ns

tSKEW1 Skew time between RCLK and WCLK 12 — 15 — 20 — ns

for

and

tSKEW2 Skew time between RCLK and 21 — 25 — 35 — ns

WCLK for

PAE

and

PAF

NOTES:

1. All AC timings apply to both Standard IDT Mode and First Word Fall

Through Mode.

2. For the RCLK line: tCLKL (min.) = 7 ns only when reading the offsets from

the programmable flag registers; otherwise, use the table value. For the

WCLK line, use the tCLKL (min.) value given in the table.

3. Pulse widths less than minimum values are not allowed.

4. Values guaranteed by design, not currently tested.

3478 tbl 08

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

See Figure 1

3ns

AC TEST CONDITIONS

Figure 1. Output Load

* Includes jig and scope capacitances.

3478 drw 04

1.1K

30pF*

680Ω

D.U.T.

5.04 7

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

SIGNAL DESCRIPTIONS:

INPUTS:

DATA IN (D0 - D17)

Data inputs for 18-bit wide data.

CONTROLS:

MASTER RESET (

MRS

)

A Master Reset is accomplished whenever the Master

Reset (

MRS

) input is taken to a LOW state. This operation sets

the internal read and write pointers to the first location of the

RAM array.

PAE

will go LOW, PAF will go HIGH, and

will

go HIGH.

If FWFT is LOW during Master Reset then the IDT

Standard Mode, along with

and

are selected.

will

go LOW and

will go HIGH. If FWFT is HIGH, then the First

Word Fall through Mode (FWFT), along with

and

, are

selected.

will go HIGH and

will go LOW.

is LOW during Master Reset, then

PAE

is assigned a

threshold 127 words from the empty boundary and PAF is

assigned a threshold 127 words from the full boundary; 127

words corresponds to an offset value of 07FH. Following

Master Reset, parallel loading of the offsets is permitted, but

not serial loading.

is HIGH during Master Reset, then

PAE

is assigned

a threshold 1023 words from the empty boundary and PAF is

assigned a threshold 1023 words from the full boundary;

1023 words corresponds to an offset value of 3FFH. Following

Master Reset, serial loading of the offsets is permitted, but not

parallel loading.

Regardless of whether serial or parallel offset loading has

been selected, parallel reading of the registers is always

permitted. (See section describing the

line for further

details).

During a Master Reset, the output register is initialized to all

zeroes. A Master Reset is required after power up, before a

write operation can take place.

MRS

is asynchronous.

PARTIAL RESET (

PRS

)

A Partial Reset is accomplished whenever the Partial

Reset (

PRS

) input is taken to a LOW state. As in the case of

the Master Reset, the internal read and write pointers are set

to the first location of the RAM array,

PAE

goes LOW, PAF

goes HIGH, and

goes HIGH.

Whichever mode is active at the time of partial reset, IDT

Standard Mode or First Word Fall-through, that mode will

remain selected. If the IDT Standard Mode is active, then

will go HIGH and

will go LOW. If the First word Fall-through

Mode is active, then

will go HIGH, and

will go LOW.

Following Partial Reset, all values held in the offset regis-

ters remain unchanged. The programming method (parallel

or serial) currently active at the time of Partial Reset is also

retained. The output register is initialized to all zeroes.

PRS

is asynchronous.

A Partial Reset is useful for resetting the device during the

course of operation, when reprogramming flag settings may

not be convenient.

RETRANSMIT (

)

The Retransmit operation allows data that has already

been read to be accessed again. There are two stages: first,

a setup procedure that resets the read pointer to the first

location of memory, then the actual retransmit, which consists

of reading out the memory contents, starting at the beginning

of memory.

Retransmit Setup is initiated by holding

LOW during a

rising RCLK edge.

REN

and

WEN

must be HIGH before

bringing

LOW. At least one word, but no more than Full -

2 words should have been written into the FIFO between

Reset (Master or Partial) and the time of Retransmit Setup

(Full = 8,192 words for the 72V255, 16,384 words for the

72V265).

If IDT Standard mode is selected, the FIFO will mark the

beginning of the Retransmit Setup by setting

LOW. The

change in level will only be noticeable if

was HIGH before

setup. During this period, the internal read pointer is initialized

to the first location of the RAM array.

When

goes HIGH, Retransmit Setup is complete and

read operations may begin starting with the first location in

memory. Since IDT Standard Mode is selected, every word

read including the first word following Retransmit Setup re-

quires a LOW on

REN

to enable the rising edge of RCLK.

Writing operations can begin after one of two conditions have

been met:

is HIGH or 14 cycles of the faster clock (RCLK

or WCLK) have elapsed since the RCLK rising edge enabled

by the

pulse.

The deassertion time of

during Retransmit Setup is

variable. The parameter tRTF1, which is measured from the

rising RCLK edge enabled by

to the rising edge of

described by the following equation:

tRTF1 max. = 14*Tf + 3*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever

is shorter, and TRCLK is the RCLK period.

Regarding

: Note that since no more than Full - 2 writes

are allowed between a Reset and a Retransmit Setup,

will

remain HIGH throughout the setup procedure.

For IDT Standard mode, updating the

PAE

, and PAF

flags begins with the "first"

REN

-enabled rising RCLK edge

following the end of Retransmit Setup (the point at which

goes HIGH). This same RCLK rising edge is used to access

the "first" memory location.

is updated on the first RCLK

rising edge.

PAE

is updated after two more rising RCLK

edges. PAF is updated after the "first" rising RCLK edge,

followed by the next two rising WCLK edges. (If the tskew2

specification is not met, add one more WCLK cycle.)

If FWFT mode is selected, the FIFO will mark the beginning

of the Retransmit Setup by setting

HIGH. The change in

level will only be noticeable if

was LOW before setup.

During this period, the internal read pointer is set to the first

location of the RAM array.

When

goes LOW, Retransmit Setup is complete; at the

same time, the contents of the first location are automatically

displayed on the outputs. Since FWFT Mode is selected, the

5.04 8

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

first word appears on the outputs, no read request necessary.

Reading all subsequent words requires a LOW on

REN

enable the rising edge of RCLK. Writing operations can begin

after one of two conditions have been met:

is LOW or 14

cycles of the faster clock (RCLK or WCLK) have elapsed since

the RCLK rising edge enabled by the

pulse.

The assertion time of

during Retransmit Setup is

variable. The parameter tRTF2, which is measured from the

rising RCLK edge enabled by

to the falling edge of

described by the following equation:

tRTF2 max. = 14*Tf + 4*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever

is shorter, and TRCLK is the RCLK period. Note that a

Retransmit Setup in FWFT mode requires one more RCLK

cycle than in IDT Standard mode.

Regarding

: Note that since no more than Full - 2 writes

are allowed between a Reset and a Retransmit Setup,

will

remain LOW throughout the setup procedure.

For FWFT mode, updating the

PAE

, and PAF flags

begins with the "last" rising edge of RCLK before the end of

Retransmit Setup. This is the same edge that asserts

and

automatically accesses the first memory location. Note that,

in this case,

REN

is not required to initiate flag updating.

is updated on the "last" RCLK rising edge.

PAE

is updated

after two more rising RCLK edges. PAF is updated after the

"last" rising RCLK edge, followed by the next two rising WCLK

edges. (If the tskew2 specification is not met, add one more

WCLK cycle.)

is synchronized to RCLK. The Retransmit operation is

useful in the event of a transmission error on a network, since

it allows a data packet to be resent.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state

of the FWFT/SI helps determine whether the device will

operate in IDT Standard mode or First Word Fall Through

(FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT

Standard mode will be selected. This mode uses the Empty

Flag (

) to indicate whether or not there are any words

present in the FIFO memory. It also uses the Full Flag function

(

) to indicate whether or not the FIFO memory has any free

space for writing. In IDT Standard mode, every word read

from the FIFO, including the first, must be requested using the

Read Enable (

REN

) line.

If, at the time of Master Reset, FWFT/SI is HIGH, then

FWFT mode will be selected. This mode uses Output Ready

(

) to indicate whether or not there is valid data at the data

outputs (Qn). It also uses Input Ready (

) to indicate whether

or not the FIFO memory has any free space for writing. In the

FWFT mode, the first word written to an empty FIFO goes

directly to Qn, no read request necessary. Subsequent words

must be accessed using the Read Enable (

REN

) line.

After Master Reset, FWFT/SI acts as a serial input for

PAE

and PAF offsets into the programmable registers.

The serial input function can only be used when the serial

loading method has been selected during Master Reset.

FWFT/SI functions the same way in both IDT Standard and

FWFT modes.

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the write clock

(WCLK). Data set-up and hold times must be met with respect

to the LOW-to-HIGH transition of the WCLK. The write and

read clocks can either be asynchronous or coincident.

WRITE ENABLE (WEN)

When Write Enable (

WEN

) is LOW, data can be loaded into

the input register on the rising edge of every WCLK cycle.

Data is stored in the RAM array sequentially and indepen-

dently of any on-going read operation.

When

WEN

is HIGH, the input register holds the previous

data and no new data is loaded into the FIFO.

To prevent data overflow in the IDT Standard Mode,

will

go LOW , inhibiting further write operations. Upon the comple-

tion of a valid read cycle,

will go HIGH allowing a write to

occur.

WEN

is ignored when the FIFO is full.

To prevent data overflow in the FWFT mode,

will go

HIGH, inhibiting further write operations. Upon the completion

of a valid read cycle,

will go LOW allowing a write to occur.

WEN

is ignored when the FIFO is full.

READ CLOCK (RCLK)

Data can be read on the outputs, on the rising edge of the

read clock (RCLK), when Output Enable (

) is set LOW. The

write and read clocks can be asynchronous or coincident.

READ ENABLE (

REN

)

When Read Enable (

REN

) is LOW, data is loaded from the

RAM array into the output register on the rising edge of the

RCLK.

When

REN

is HIGH, the output register holds the previous

data and no new data is loaded into the output register.

In the IDT Standard Mode, every word accessed at Qn,

including the first word written to an empty FIFO, must be

requested using

REN

. When all the data has been read from

the FIFO, the Empty Flag (

) will go LOW, inhibiting further

read operations.

REN

is ignored when the FIFO is empty.

Once a write is performed,

will go HIGH after tFWL1 +tREF

and a read is permitted.

In the FWFT Mode, the first word written to an empty FIFO

automatically goes to the outputs Qn, no need for any read

request. In order to access all other words, a read must be

executed using

REN

. When all the data has been read from

the FIFO, Output Ready (

) will go HIGH, inhibiting further

read operations.

REN

is ignored when the FIFO is empty.

Once a write is performed,

will go LOW after tFWL2

+tREF, when the first word appears at Qn ; if a second word

is written into the FIFO, then

REN

can be used to read it out.

SERIAL ENABLE (

SEN

)

Serial Enable is (

SEN

) is an enable used only for serial

programming of the offset registers. The serial programming

method must be selected during Master Reset.

SEN

is always

used in conjunction with

. When these lines are both LOW,

5.04 9

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

data at the SI input can be loaded into the input register one

bit for each LOW-to-HIGH transition of WCLK.

When

SEN

is HIGH, the programmable registers retains

the previous settings and no offsets are loaded.

SEN

functions the same way in both IDT Standard and

FWFT modes.

OUTPUT ENABLE (

)

When Output Enable (

) is enabled (LOW), the parallel

output buffers receive data from the output register. When

is HIGH, the output data bus (Qn) goes into a high impedance

state.

LOAD (

)

This is a dual purpose pin. During Master Reset, the state

of the Load line (

) determines one of two default values (127

or 1023) for the

PAE

and PAF flags, along with the method

by which these flags can be programmed, parallel or serial.

After Master Reset,

enables write operations to and read

operations from the registers. Only the offset loading method

currently selected can be used to write to the registers. Aside

from Master Reset, there is no other way change the loading

method. Registers can be read only in parallel; this can be

accomplished regardless of whether serial or the parallel

loading has been selected.

Associated with each of the programmable flags,

PAE

and

PAF, is one register which can either be written to or read from.

Offset values contained in these registers determine how

many words need to be in the FIFO memory to switch a partial

flag. A LOW on

during Master Reset selects a default

PAE

offset value of 07FH ( a threshold 127 words from the empty

boundary), a default PAF offset value of 07FH (a threshold

127 words from the full boundary), and parallel loading of other

offset values. A HIGH on

during Master Reset selects a

default

PAE

offset value of 3FFH (a threshold 1023 words from

the empty boundary), a default PAF offset value of 3FFH (a

threshold 1023 words form the full boundary), and serial

loading of other offset values.

The act of writing offsets (in parallel or serial) employs a

dedicated write offset register pointer. The act of reading

offsets employs a dedicated read offset register pointer. The

two pointers operate independently; however, a read and a

write should not be performed simultaneously to the offset

registers. A Master Reset initializes both pointers to the

Empty Offset (LSB) register. A Partial Reset has no effect on

the position of these pointers.

Figure 2. Partial Flag Programming Sequence

NOTES:

1. Only one of the two offset programming methods, serial or parallel, is available for use at any given time.

2. The programming method can only be selected at Master Reset.

3. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

4. The programming sequence applies to both IDT Standard and FWFT modes.

Selection

Parallel write to registers:

Empty Offset

Full Offset

Parallel read from registers:

Empty Offset

Full Offset

No Operation

Write Memory

Read Memory

No Operation

WEN

REN

1Serial shift into registers:

26 bits for the 72V255

28 bits for the 72V265

SEN

WCLK

RCLK

1 bit for each rising WCLK edge

Starting with Empty Offset

Ending with Full Offset

3478 tbl 09

5.04 10

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

Once serial offset loading has been selected, then pro-

gramming

PAE

and PAF proceeds as follows: When

and

SEN

are set LOW, data on the SI input are written, one bit for

each WCLK rising edge, starting with the Empty Offset (13 bits

for the 72V255, 14 bits for the 72V265), ending with the Full

Offset (13 bits for the 72V255, 14 bits for the 72V265). A total

of 26 bits are necessary to program the 72V255; a total of 28

bits are necessary to program the 72V265. Individual regis-

ters cannot be loaded serially; rather, both must be pro-

grammed in sequence, no padding allowed.

PAE

and PAF

can show a valid status only after the full set of bits have been

entered. The registers can be re-programmed, as long as

both offsets are loaded. When

is LOW and

SEN

is HIGH,

no serial write to the registers can occur.

Once parallel offset loading has been selected, then

programming

PAE

and PAF proceeds as follows: When

and

WEN

are set LOW, data on the inputs Dn are written into

the Empty Offset Register on the first LOW-to-HIGH transition

of WCLK. Upon the second LOW-to-HIGH transition of

WCLK, data at the inputs are written into the Full Register. The

third transition of WCLK writes, once again, to the Empty

Offset Register.

To ensure proper programming (serial or parallel) of the

offset registers, no read operation is permitted from the time

of reset (master or partial) to the time of programming. (During

this period, the read pointer must be pointing to the first

location of the memory array.) After the programming has

been accomplished, read operations may begin.

Write operations to memory are allowed before and during

the parallel programming sequence. In this case, the pro-

gramming of all offset registers does not have to occur at one

time. One or two offset registers can be written to and then,

by bringing

HIGH, write operations can be redirected to the

FIFO memory. When

is set LOW again, and

WEN

is LOW,

the next offset register in sequence is written to. As an

alternative to holding

WEN

LOW and toggling

, parallel

programming can also be interrupted by setting

LOW and

toggling

WEN

Write operations to memory are allowed before and during

the serial programming sequence. In this case, the program-

ming of all offset bits does not have to occur at once. A select

number of bits can be written to the SI input and then, by

bringing

and

SEN

HIGH, data can be written to FIFO

memory via Dn by toggling

WEN

. When

WEN

is brought HIGH

with

and

SEN

restored to a LOW, the next offset bit in

sequence is written to the registers via SI. If a mere interrup-

tion of serial programming is desired, it is sufficient either to set

LOW and deactivate

SEN

or to set

SEN

LOW and deacti-

vate

. Once

and

SEN

are both restored to a LOW level,

serial offset programming continues from where it left off.

Note that the status of a partial flag (

PAE

or PAF) output is

invalid during the programming process. From the time

parallel programming has begun, a partial flag output will not

be valid until the appropriate offset word has been written to

the register pertaining to that flag. From the time serial

programming has begun, neither partial flag will be valid until

the full set of bits required to fill all the offset registers has been

written. Measuring from the rising WCLK edge that achieves

either of the above criteria; PAF will be valid after two more

rising WCLK edges plus tPAF,

PAE

will be valid after the next

two rising RCLK edges plus tPAE (Add one more RCLK cycle

if tSKEW2 is not met.)

The act of reading the offset registers employs a dedicated

read offset register pointer. The contents of the offset regis-

ters can be read on the output lines when

is set LOW and

REN

is set LOW; then, data are read via Qn from the Empty

Offset Register on the first LOW-to-HIGH transition of RCLK.

Upon the second LOW-to-HIGH transition of RCLK, data are

read from the Full Offset Register. The third transition of

RCLK reads, once again, from the Empty Offset Register.

It is permissible to interrupt the offset register access

sequence with reads or writes to memory . The interruption is

accomplished by deasserting

REN

, or both together.

When

REN

and

are restored to a LOW level, access of the

registers continues where it left off.

functions the same way in both IDT Standard and FWFT

modes.

FREQUENCY SELECT input (FS)

An internal state machine manages the movement of data

through the Supersync FIFO. The FS line determines whether

RCLK or WCLK will synchronize the state machine. Tie FS to

VCC if the RCLK line is running at a lower frequency than the

WCLK line. In this case, the state machine will be synchro-

nized to WCLK. Tie FS to GND if the RCLK line is running at

a higher frequency than the WCLK line. In this case, the state

machine will be synchronized to RCLK. Note that FS must be

set so the clock line running at the higher frequency drives the

state machine; this ensures efficient handling of the data

within the FIFO. If the same clock signal drives both the WCLK

and the RCLK pins, then tie FS to GND.

The frequency of the clock tied to the state machine

(referred to as the "selected clock") may be changed at any

time, so long as it is always greater than or equal to the

frequency of the clock that is not tied to the state machine

(referred to as the "non-selected clock"). The frequency of the

non-selected clock can also be varied with time, so long as it

never exceeds the frequency of the selected clock. To be

more specific, the frequencies of both RCLK and WCLK may

be varied during FIFO operation, provided that, at any given

point in time, the cycle period of the selected clock is equal to

or less than the cycle period of the non-selected clock.

The selected clock must be continuous. It is, however,

permissible to stop the non-selected clock. Note, so long as

RCLK is idle,

and

PAE

will not be updated. Likewise,

as long as WCLK is idle,

and PAF will not be updated.

Changing the FS setting during FIFO operation (i.e. read-

ing or writing) is not permitted; however, such a change at the

time of Master Reset or Partial Reset is all right. FS is an

asynchronous input.

5.04 11

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTE:

1. Any bits of the offset register not being programmed should be set to zero.

Figure 3. Offset Register Location and Default Values

OUTPUTS:

FULL FLAG (

)

This is a dual purpose pin. In IDT Standard Mode, the Full

Flag (

) function is selected. When the FIFO is full (i.e. the

write pointer catches up to the read pointer),

will go LOW,

inhibiting further write operation. When

is HIGH, the FIFO

is not full. If no reads are performed after a reset (either

MRS

PRS

will go LOW after 8,192 writes to the IDT72V255

and 16,384 writes to the IDT72V265.

In FWFT Mode, the Input Ready (

) function is selected.

goes LOW when memory space is available for writing in

data. When there is no longer any free space left,

goes

HIGH, inhibiting further write operation. If no reads are

performed after a reset (either

MRS

PRS

will go HIGH

after 8,193 writes for the IDT72V255 and 16,385 writes for the

IDT72V265.

The

status not only measures the contents of the FIFO

memory, but also counts the presence of a word in the output

necessary to deassert

is one greater than needed to assert

in IDT Standard mode.

is synchronized to WCLK. It is double-registered to

enhance metastable immunity.

EMPTY FLAG (

)

This is a dual purpose pin. In the IDT Standard Mode, the

Empty Flag (

) function is selected. When the FIFO is empty

(i.e. the read pointer catches up to the write pointer),

will go

LOW, inhibiting further read operations. When

is HIGH,

the FIFO is not empty.

When writing the first word to an empty FIFO, the deassertion

time of

is variable, and can be represent by the First Word

EMPTY OFFSET REGISTER

17 0

07FH if

is LOW at Master Reset,

3FFH if

is HIGH at Master Reset

FULL OFFSET REGISTER

17 0

DEFAULT VALUE

07FH if

is LOW at Master Reset,

3FFH if

is HIGH at Master Reset

72V255 – 8,192 x 18–Bit

3478 drw 05

EMPTY OFFSET REGISTER

17 0

07FH if

is LOW at Master Reset,

3FFH if

is HIGH at Master Reset

FULL OFFSET REGISTER

17 0

DEFAULT VALUE

07FH if

is LOW at Master Reset,

3FFH if

is HIGH at Master Reset

72V265 – 16,384 x 18–Bit

3478 drw 06

Latency parameter, tFWL1, which is measured from the rising

WCLK edge that writes the first word to the rising RCLK edge

that updates the flag. tFWL1 includes any delays due to clock

skew and can be expressed as follows:

tFWL1 max. = 10*Tf + 2*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever

is shorter, and TRCLK is the RCLK period. Since no read can

take place until

goes HIGH, the tFWL1 delay determines

how early the first word can be available at Qn. This delay has

no effect on the reading of subsequent words.

In FWFT Mode, the Output Ready (

) function is se-

lected.

goes LOW at the same time that the first word

written to an empty FIFO appears valid on the outputs.

goes HIGH one cycle after RCLK shifts the last word from the

FIFO memory to the outputs. Then further data reads are

inhibited until

goes LOW again.

When writing the first word to an empty FIFO, the assertion

time of

is variable, and can be represented by the First

Word Latency parameter, tFWL2, which is measured from the

rising WCLK edge that writes the first word to the rising RCLK

edge that updates the flag. tFWL2 includes any delay due to

clock skew and can be expressed as follows:

tFWL2 max. = 10*Tf + 3*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever

is shorter, and TRCLK is the RCLK period. Note that the First

Word Latency in FWFT mode is one RCLK cycle longer than

in IDT Standard mode. The tFWL2 delay determines how

early the first word can be available at Qn. This delay has no

effect on the reading of subsequent words.

5.04 12

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

is sychronized to the RCLK. It is double-registered

to enhance metastable immunity.

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

The Programmable Almost-Full Flag (PAF) will go LOW

when the FIFO reaches the Almost-Full condition as specified

by the offset m stored in the Full Offset register.

At the time of Master Reset, depending on the state of

one of two possible default offset values are chosen. If

LOW, then m = 07FH and the PAF switching threshold is 127

words from the Full boundary, if

is HIGH, then m = 3FFH

and the PAF switching threshold is 1023 words away from the

Full boundary.

Any integral value of m from 0 to the maximum FIFO depth

minus 1 (8,191 words for the 72V255, 16,383 words for the

72V265) can be programmed into the Full Offset register.

In IDT Standard Mode, if no reads are performed after reset

(

MRS

PRS

), PAF will go LOW after (8,192-m) writes to the

IDT72V255, and (16,384-m) writes to the IDT72V265.

In FWFT Mode, if no reads are performed after reset (

MRS

PRS

), PAF will go LOW after (8,193-m) writes to the

IDT72V255, and (16,385-m) writes to the IDT72V265. In this

case, the first word written to an empty FIFO does not stay in

memory, but goes unrequested to the output register; there-

fore, it has no effect on determining the state of PAF.

Note that even though PAF is programmed to switch LOW

during the first word latency period (tFWL), attempts to read

data will be ignored until

goes HIGH indicating that data is

available at the output port. This is true for both timing modes.

PAF is synchronous and updated on the rising edge of

WCLK. It is double-registered to enhance metastable immu-

nity.

PROGRAMMABLE ALMOST-EMPTY FLAG (

PAE

)

NOTES:

1. Data in the output register does not count as a 'word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes

unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.

2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.

3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.

4. Following a reset (Master or Partial), the FIFO memory is empty and OR = HIGH. After writing the first word, the FIFO memory remains empty,

the data is placed into the output register, and OR goes LOW. In this case, or any time the last word in the FIFO memory has been read into the

output register; a rising RCLK edge, enabled by REN, will set OR HIGH.

TABLE II –– STATUS FLAGS FOR FWFT MODE

TABLE I –– STATUS FLAGS FOR IDT STANDARD MODE

Number of Words in FIFO Memory

FF PAF

PAF HF

HF PAE

PAE EF

72V255

0HHH

HHH

(n+1) to 4,096 HHH

4,097 to (8192-(m+1)) HHLHH

HLL

8,192 LLL

1 to n

(8,192-m) to 8,191

(2)

(3)

72V265

(n+1) to 8,192

8,193 to (16,384-(m+1))

16,384

1 to n

(16,384-m) to 16,383

(2)

(3)

(1)

Number of Words in FIFO Memory

IR PAF

PAF HF

HF PAE

PAE OR

72V255

HLH

1 to n L HHLL

(n+1) to 4,096 L HHHL

4,097 to (8192-(m+1)) L HLHL

(8,192-m) to 8,191 L LLHL

8,192 H LLHL

(2)

(3)

72V265

1 to n

(n+1) to 8,192

8,193 to (16,384-(m+1))

(16,384-m) to 16,383

16,384

(2)

(3)

(1)

(4)

NOTES:

1. Data in the output register does not count as a 'word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes

unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count.

2. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.

3. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or n=1023 when serial offset loading is selected.

3478 tbl 10

3478 tbl 11

5.04 13

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

The Programmable Almost-Empty Flag (

PAE

) will go LOW

when the FIFO reaches the Almost-Empty condition as speci-

fied by the offset n stored in the Empty Offset register.

At the time of Master Reset, depending on the state of

one of two possible default offset values are chosen. If

LOW, then n = 07FH and the

PAE

switching threshold is 127

words from the Empty boundary, if

is HIGH, then n = 3FFH

and the

PAE

switching threshold is 1023 words away from the

Empty boundary.

Any integral value of n from 0 to the maximum FIFO depth

minus 1 (8,191 words for the 72V255, 16,383 words for the

72V265) can be programmed into the Empty Offset register.

In IDT Standard Mode, if no reads are performed after

reset (

MRS

PRS

), the

PAE

will go HIGH after (n + 1) writes

to the IDT72V255/72V265.

In FWFT Mode, if no reads are performed after reset (

MRS

PRS

), the

PAE

will go HIGH after (n+2) writes to the

IDT72V255/72V265. In this case, the first word written to an

empty FIFO does not stay in memory, but goes unrequested

to the output register; therefore, it has no effect on determin-

ing the state of

PAE

Note that even though

PAE

is programmed to switch HIGH

during the first word latency period (tFWL), attempts to read

data will be ignored until

goes HIGH indicating that data is

available at the output port. This is true for both timing modes.

PAE

is synchronous and updated on the rising edge of

RCLK. It is double-registered to enhance metastable immu-

nity.

HALF-FULL FLAG (

)

This output indicates a half-full memory. The rising WCLK

edge that fills the memory beyond half-full sets

LOW. The

flag remains LOW until the difference between the write and

read pointers becomes less than or equal to half of the total

depth of the device; the rising RCLK edge that accomplishes

this condition also sets

HIGH.

In IDT Standard Mode, if no reads are performed after reset

(

MRS

PRS

will go LOW after (D/2 + 1) writes, where D

is the maximum FIFO depth (8,192 words for the IDT72V255,

16,384 words for the IDT72V265).

In FWFT Mode, if no reads are performed after reset (

MRS

PRS

will go LOW after (D/2+2) writes to the IDT72V255/

72V265. In this case, the first word written to an empty FIFO

does not stay in memory, but goes unrequested to the output

Because

uses both RCLK and WCLK for synchroniza-

tion purposes, it is asynchronous.

DATA OUTPUTS (Q0-Q17)

Q0-Q17 are data outputs for 18-bit wide data.

5.04 14

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

tRS

MRS

tRSR

REN

tRSS

FWFT/SI

3478 drw 07

tRSR

tFWFT

tRSR

WEN

tRSS

tRSRtRSS

(1)

tRSS

SEN

tRSS

tRSF

= HIGH

= LOW

(1)

PAE

PAF

Q0 - Q17

tRSF

tRSF If FWFT = HIGH,

= HIGH

If FWFT = LOW,

= LOW

If FWFT = LOW,

= HIGH

If FWFT = HIGH,

= LOW

Figure 4. Master Reset Timing

5.04 15

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 5. Partial Reset Timing

tRS

PRS

tRSR

REN

tRSS

3478 drw 08

tRSS

tRSR

WEN

tRSS

SEN

tRSS

tRSF

= HIGH

= LOW

(1)

PAE

PAF

Q0 - Q17

tRSF

tRSF If FWFT = HIGH,

= HIGH

If FWFT = LOW,

= LOW

If FWFT = LOW,

= HIGH

If FWFT = HIGH,

= LOW

5.04 16

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

Figure 6. Write Cycle Timing (IDT Standard Mode)

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

will go HIGH (after one WCLK cycle plus tWFF).

If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the

deassertion may be delayed an extra WCLK

cycle.

= HIGH

WCLK

D0 - D17

WEN

RCLK

REN

tWFF tWFF

DATAIN

VALID

OPERATION

(1)

tSKEW1

3478 drw 09

tENS

tENH

tCLKH tCLKL

tCLK

5.04 17

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:

1. tFWL1 contributes a variable delay to the overall first word latency (this parameter includes delays due to skew):

tFWL1 max. (in ns) = 10*Tf + 2* TRCLK

where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period

= HIGH

Figure 7. Read Cycle Timing (IDT Standard Mode)

NO OPERATION

RCLK

REN

CLK

CLKH

CLKL

ENH

REF

LAST WORD

OLZ

- Q

WCLK

(1)

FWL1

WEN

3478 drw 10

- D

ENS

ENH

DHS

FIRST WORD

OHZ

5.04 18

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

NOTES:

1. tFWL1 max. (in ns) = 10* Tf + 2* TRCLK

Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period

= HIGH

Figure 8. First Data Word Latency (IDT Standard Mode)

WCLK

D0 -

D17

WEN

RCLK

Q0 -

Q17

REN

tDS

tENS

D0 D1

first valid

write

3478 drw 11

tREF

tOE

tOLZ

tFWL1

(1)

5.04 19

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

- D

WEN

RCLK

REN

ENH

- Q

DATA READ NEXT DATA READ

DATA IN OUTPUT REGISTER

LOW

SKEW1

DATA

WRITE

3478 drw 12

WCLK

WRITE 1212t

WRITE

WFF

ENS

SKEW1

(1) (1)

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

will go high (after one WCLK cycle pus tWFF).

If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the

deassertion may be delayed an extra

WCLK cycle.

= HIGH Figure 9. Full Flag Timing (IDT Standard Mode)

5.04 20

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

WCLK

D0 - D17

WEN

RCLK

Q0 - Q17

tDS

tENS

DATA WRITE 1

WORD 1

tENH

tDS

tENS

DATA WRITE 2

tENH

REN

DATA IN OUTPUT REGISTER

LOW

3478 drw 13

tREF

tFWL1

tREF

tFWL1(1) (1)

NOTES:

1. tFWL1 max. (in ns) = 10*Tf + 2*TRCLK

Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the period.

= HIGH

Figure 10. Empty Flag Timing (IDT Standard Mode)

5.04 21

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 12. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT modes)

Figure 11. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT modes)

NOTE:

1. For the 72V255, X = 12.

For the 72V265, X = 13.

WCLK

SEN

3478 drw 14

tENH

tENS

tLDS

tDS

BIT 0

EMPTY

OFFSET

BIT X BIT 0

FULL

OFFSET

(1)

tENH

BIT X (1)

tLDH

WCLK

WEN

D0 - D17

3478 drw 15

tLDS

tCLKH tCLKL

tENS

PAE

OFFSET PAF

OFFSET

tDS tDH

tLDH

tENH

tCLK

5.04 22

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

NOTES:

PAE

offset = n

2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested

to the output register (no read operation necessary), it is not included in the FIFO memory count.

3. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for

PAE

to go HIGH (after one RCLK cycle plus tPAE). If the time

between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the

PAE

deassertion may be delayed one extra RCLK cycle.

NOTE:

=LOW

Figure 14. Programmable Almost Empty Flag Timing (IDT Standard and FWFT modes)

RCLK

REN

Q0 - Q17

LDH

LDS

CLKH

CLKL

ENS

DATA IN OUTPUT

OFFSET

ENH

LDH

3478 drw 16

CLK

Figure 13. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT modes)

WCLK

WEN

PAE

RCLK

REN

tENH

tCLKH tCLKL

3478 drw 17

tENS tENH

tENS

n words in FIFO memory

tPAE

n+1 words in FIFO memory

tSKEW2

tPAE

1212

n Words

in FIFO

memory

(1,2)

(3)

5.04 23

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTE:

1. D = maximum FIFO depth = 8,192 for IDT 72V255, 16,384 word for IDT 72V265.

Figure 16. Half - Full Flag Timing (IDT Standard and FWFT modes)

WCLK

WEN

PAF

RCLK

REN

ENH

CLKH

CLKL

(3)

PAF

3478 drw 18

ENS

ENH

ENS

D - (m+1) Words in

FIFO Memory

PAF

D - m Words in

FIFO Memory

(1,2)

SKEW2

1212

D-(m+1)

Words in

FIFO

Memory

NOTES:

PAF

offset = m, D = 8,192 for IDT 72V255, 16,384 word for IDT 72V265.

2. Data in the output register does not count as a "word in FIFO memory". Since, in FWFT mode, the first word written to an empty FIFO goes unrequested

to the output register (no read operation necessary), it is not included in the FIFO memory count.

3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for

PAF

to go HIGH (after one WCLK cycle plus tPAF). If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the

PAF

deassertion time may be delayed an extra WCLK cycle.

Figure 15. Programmable Almost Full Flag Timing (IDT Standard and FWFT modes)

WCLK

WEN

RCLK

REN

CLKH

CLKL

ENS

ENH

D/2 + 1 Words D/2 Words

ENS

3478 drw 19

D/2 Words

5.04 24

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

WCLK

WEN

RCLK

REN

D0 - D17

PAF

PAE

Q0 - Q17

(4)

tREF

tRTStENH

tDH

tRTS

W[y+1]

tENS tENH

tRTF1

3037 drw 20

tENS

(1,2)

tENS

tENH

W[x + 1]

tSKEW2

tENS

tDS

tPAF

tHF

tPAE

tENH

tENS

tDS tDH

tENH

tREF

(3)

NOTES:

1. tRTF1 contributes a variable delay to the overall retransmit recovery time:

tRFTF1 max = 14*Tf + 3*TRCLK (in ns)

Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.

2. Retransmit set up is complete after

returns HIGH, only then can a read operation begin. Write operations are permitted after one of two conditions

have been met:

is HIGH or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the

pulse.

3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of

PAE

, and

PAF

4. No more than D-2 words (D = 8,192 words for the 72V255, 16,384 words for the 72V265) should have been written to the FIFO between Reset (Master

or Partial) and Retransmit Setup. Therefore,

will be HIGH throughout the Restransmit Setup procedure.

=LOW

Figure 17. Retransmit Timing (IDT Standard mode)

5.04 25

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

WEN

D0 - D17

RCLK

REN

Q0 - Q17

PAF

PAE

W1W2Wn+1 W[n +2] W[D/2+1] W[D/2+2] W[D-m+1]

W[D-m)] WDW[D+1]

W[n+3] W[n+4] W[D-m+2] W[D-m+3]

tDHtDS

tENS

tFWL2

tDS tDS tDS

tSKEW2

tREF

tPAE

tHF

tPAF

tWFF

W[D/2+3] W[D-m+4]

tENH

3478 drw 21

DATA IN OUTPUT

(1) (2)

NOTES:

1. tFWL2 max. (in ns) = 10*Tf + 3*TRCLK

where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.

2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for

PAE

to go HIGH (after one RCLK cycle plus tPAE). If the time between the rising edge of WCLK and the

rising edge of RCLK is less than tSKEW2, then the

PAE

deassertion may be delayed one extra RCLK cycle.

= HIGH,

= LOW

PAE

offset = n,

PAF

offset = m, D = maximum FIFO depth = 8,192 words for the IDT72V255, 16,384 words for the IDT72V265.

Figure 18. Write Timing (First Word Fall Through Mode)

5.04 26

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

WCLK

WEN

D0 - D17

RCLK

REN

Q0 - Q17

PAF

PAE

1212

tENS

W1W1W2W3W[D/2]

Wm+1 W[m+2]

tOHZ

tSKEW1

tENH

tDS tDH

tOE tAtAtA

tPAF

tWFF

tWF

tENS

tSKEW2

W[D+1]

3478 drw 22

tPAE

W[D/2+1] W[D-n+1]

W[D-n]

tAtA

tHF

tREF

WDW[D+1]

W[D-n+2]

W[m+3]

W[D-n+3]

(1) (2)

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that

will go LOW (after one WCLK cycle plus tWFF). If the time between the rising ege of RCLK

and the rising edge of WCLK is less than tSKEW1, then the

assertion may be delayed an extra WCLK cycle.

2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for

PAF

to go HIGH (after one WCLK cycle plus tPAF). If the time between the rising edge of RCLK and the rising

edge of WCLK is less than tSKEW2, then the

PAF

deassertion may be delayed an extra WCLK cycle.

= HIGH

PAE

Offset = n,

PAF

offset = m, D = maximum FIFO depth = 8,192 words for the IDT72V255, 16,384 words for the IDT72V265.

Figure 19. Read Timing (First Word Fall Through Mode)

5.04 27

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

WCLK

WEN

RCLK

REN

D0 - D17

PAF

PAE

Q0 - Q17

(4)

tREF

tRTStENH

tDH

tRTS

W[y+1]

tENS tENH

tRTF1

3478 drw 23

(1,

tENS

tENH

W[x + 1]

tSKEW2

tENS

tDS

tPAF

tHF

tPAE

tENS

tENH

tENS

tDS tDH

tENH

tREF

(3)

NOTES:

1. tRTF2 contribute a variable delay to the overall retransmit time:

tRTF2 max = 14*Tf + 4*TRCLK (in ns)

Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the RCLK period.

2. Retransmit set up is complete after

returns LOW, only then can a read operation begin. Write operations are permitted after one of two conditions

have been met:

is LOW or 14 cycles of the faster clock (RCLK or WCLK) have elapsed since the RCLK rising edge enabled by the

pulse.

3. Following Retransmit Setup, the rising edge of RCLK that accesses the first memory location also initiates the updating of

PAE

, and

PAF

4. No more than D-2 words (D = 8,192 words for the 72V255, 16,384 words for the 72V265) should have been written to the FIFO between Reset (Master

or Partial) and Retransmit Setup. Therefore,

will be LOW throughout the Retransmit Setup procedure.

=LOW

Figure 20. Retransmit Timing (FWFT mode)

5.04 28

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

Figure 21. Block Diagram of Single 8,192x18/16,384x18 Synchronous FIFO

OPERATING CONFIGURATIONS

SINGLE DEVICE CONFIGURATION

A single IDT72V255/72V265 may be used when the appli-

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting to-

gether the control signals of multiple devices. Status flags can

be detected from any one device. The exceptions are the

and

functions in IDT Standard mode and the

and

functions in FWFT mode. Because of variations in skew

between RCLK and WCLK, it is possible for

deassertion

and

assertion to vary by one cycle between FIFOs. In

IDT Standard mode, such problems can be avoided by creat-

ing composite flags, that is, ANDing

of every FIFO, and

separately ANDing

of every FIFO. In FWFT mode, com-

posite flags can be created by ORing

of every FIFO, and

separately ORing

of every FIFO. Figure 22 demonstrates

an 36-word width by using two IDT72V255/72V265s. Any

word width can be attained by adding additional IDT72V255/

72V265s.

DEPTH EXPANSION CONFIGURATION

The IDT72V255/72V265 can easily be adapted to applica-

tions requiring more than 8,192/16,384 words of buffering. In

FWFT mode, the FIFOs can be arranged in series (the data

outputs of one FIFO connected to the data inputs of the next)–

no external logic necessary. The resulting configuration

provides a total depth equivalent to the sum of the depths

associated with each single FIFO. Figure 23 shows a depth

expansion using two IDT72V255/72V265s.

Care should be taken to select FWFT mode during Master

Reset for all FIFOs in the depth expansion configuration. The

first word written to an empty configuration will pass from one

FIFO to the next ("ripple down") until it finally appears at the

outputs of the last FIFO in the chain–no read operation is

necessary. Each time the data word appears at the outputs

of one FIFO, that device's

line goes LOW, enabling a write

to the next FIFO in line.

The

assertion time is variable and is described with the

help of the tFWL2 parameter, which includes including delay

caused by clock skew:

tFWL2 max.= 10*Tf + 3*TRCLK

where TRCLK is the RCLK period and Tf is either the RCLK

or the WCLK period, whichever is shorter.

The maximum amount of time it takes for a word to pass

from the inputs of the first FIFO to the outputs of the last FIFO

in the chain is the sum of the delays for each individual FIFO:

tFWL2(1) + tFWL2(2) + ... + tFWL2(N)+ N*TRCLK

where N is the number of FIFOs in the expansion.

Note that the additional RCLK term accounts for the time it

takes to pass data between FIFOs.

The ripple down delay is only noticeable for the first word

DATA OUT (Q0 - Q17)

DATA IN (D0 - D17)

MASTER RESET (

MRS

)

READ CLOCK (RCLK)

READ ENABLE (

REN

)

OUTPUT ENABLE (

)

EMPTY FLAG/OUTPUT READY (

)

PROGRAMMABLE ALMOST EMPTY (

PAE

)

WRITE CLOCK (WCLK)

WRITE ENABLE (

WEN

)

LOAD (

)

FULL FLAG/INPUT READY (

)

PROGRAMMABLE ALMOST FULL (

PAF

)

IDT

72V255/

72V265

PARTIAL RESET (

PRS

)

FIRST WORD FALL THROUGH/SERIAL INPUT (FWFT/SI) RETRANSMIT (

)

3478 drw 24

HALF FULL FLAG (

)

FREQUENCY SELECT (FS)

SERIAL ENABLE(

SEN

)

cation requirements are for 8,192/16,384 words or less. The

IDT72V255/72V265 can always be used in Single Device

Configuration, whether IDT Standard Mode or FWFT Mode

has been selected. No special set up procedure is necessary.

5.04 29

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18 MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 23. Block Diagram of 16,384x18/32,768x18 Supersync Depth Expansion

NOTE:

1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.

2. Do not connect any output control signals directly together.

Figure 22. Block Diagram of 8,192x36/16,384x36 72V255/72V265 Width Expansion

DATA IN (Dn)

WRITE CLOCK (WCLK)

36 18 18

MASTER RESET (

MRS

)

READ CLOCK (RCLK)

DATA OUT (Qn)

18 36

WRITE ENABLE (

WEN

)

FULL FLAG/INPUT READY (

)

PROGRAMMABLE (

PAF

)

PROGRAMMABLE (

PAE

)

EMPTY FLAG/OUTPUT READY (

) #2

OUTPUT ENABLE (

)

READ ENABLE (

REN

)

LOAD (

)IDT

72V255/

72V265/ EMPTY FLAG/OUTPUT READY (

) #1

PARTIAL RESET (

PRS

)

IDT

72V255/

72V265/

3478 drw 25

FULL FLAG/INPUT READY (

) #2

HALF FULL FLAG (

)

FREQUENCY SELECT (FS)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

RETRANSMIT (

)

GATE

(1)GATE

(1)

•

INPUT READY

WRITE ENABLE

WRITE CLOCK

WEN

WCLK

DATA BUS

RCLK READ CLOCK

RCLK

REN

OUTPUT ENABLE

OUTPUT READY

GND

WEN

WCLK

REN

READ ENABLE

DATA OUT

72V255/

72V265

FS FS

TRANSFER CLOCK

3478 drw 26

18 18

72V255/

72V265

written to an empty depth expansion configuration. There will

be no delay evident for subsequent words written to the

configuration.

The first free location created by reading from a full depth

expansion configuration will "bubble up" from the last FIFO to

the previous one until it finally moves into the first FIFO of the

chain. Each time a free location is created in one FIFO of the

chain, that FIFO's

line goes LOW, enabling the preceding

FIFO to write a word to fill it.

The amount of time it takes for

of the first FIFO in the

chain to assert after a word is read from the last FIFO is the

sum of the delays for each individual FIFO:

N*(3*TWCLK)

where N is the number of FIFOs in the expansion and

TWCLK is the WCLK period. Note that one of the three WCLK

cycle accounts for TSKEW1 delays.

In a Supersync depth expansion, set FS individually for

each FIFO in the chain. The Transfer Clock line should be tied

to either WCLK or RCLK, whichever is faster. Both these

actions result in moving, as quickly as possible, data to the

end of the chain and free locations to the beginning of the

chain.

5.04 30

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72V255/72V265 3.3Volt SyncFIFO

8,192 x 18, 16,384 x 18

ORDERING INFORMATION

Commercial (0°C to +70°C)

Military (–55°C to +125°C)

Compliant to MIL-STD-883, Class B

Pin Grid Array (PGA)

Thin Plastic Quad Flatpack

Slim Thin Quad Flatpack

Low Power

8,192 x 18 3.3V Synchronous FIFO

16,384 x 18 3.3V Synchronous FIFO

BLANK

15 Com'l Only

20 Com'l & Mil.

25 Mil. Only

72V255

72V265

IDT XXXXX

Device Type X

Power XX

Speed X

Package X

Clock Cycle Time (tCLK)

Speed in Nanoseconds

Process /

Temperature

Range

3478 drw 27