LTC4234CWHH#PBF - LINEAR TECHNOLOGY

LTC4234

4234fa

For more information www.linear.com/LTC4234

TYPICAL APPLICATION

FEATURES DESCRIPTION

20A Guaranteed SOA

Hot Swap Controller

The LT C

4234 is an integrated solution for Hot Swap™

applications that allows a board to be safely inserted and

removed from a live backplane. The part integrates a

HotSwap controller, power MOSFET and current sense

resistor in a single package for small form factor applica-

tions. The MOSFET Safe Operating Area is production tested

and guaranteed for the stresses in Hot Swap applications.

The LTC4234 provides separate inrush current control

and an 11% accurate 22.5A current limit with output

dependent foldback. The current limit threshold can be

adjusted dynamically using the ISET pin. Additional features

include a current monitor output that amplifies the sense

resistor voltage for ground referenced current sensing

and a MOSFET temperature monitor output. Thermal limit,

overvoltage, undervoltage and power good monitoring are

also provided. For a 10A compatible version, see LTC4233.

12V, 20A Card Resident Application with Auto-Retry

Power-Up Waveform

APPLICATIONS

n Allows Safe Board Insertion into Live Backplane

n Small Footprint

n 4mΩ MOSFET Including RSENSE

n Safe Operating Area Guaranteed at 81W, 30ms

n Wide Operating Voltage Range: 2.9V to 15V

n Adjustable, 11% Accurate Current Limit

n Current and Temperature Monitor Outputs

n Overtemperature Protection

n Adjustable Current Limit Timer Before Fault

n Power Good and Fault Outputs

n Adjustable Inrush Current Control

n 2.5% Accurate Undervoltage and Overvoltage Protection

n Pin Compatible with LTC4233

n Available in a 38-Pin (5mm × 9mm) QFN Package

n High Availability Servers

n Solid State Drives

n Industrial

n 240W, 12V Systems

L, LT , LT C , LT M , Linear Technology and the Linear logo are registered trademarks and

HotSwap and PowerPath are trademarks of Linear Technology Corporation. All other

trademarks are the property of their respective owners.

12V

VOUT

12V

20A

4234 TA01a

1000µF

10k

VDD

ISET

TIMER

INTVCC

OUT

GND

GATE

IMON

LTC4234

SENSE–

SENSE

F LT

20k

1µF

*TVS: DIODES INC. SMAJ17A

ADC

107k

10k

5.23k

150k

20k

VIN

10V/DIV CONTACT

BOUNCE

VOUT

10V/DIV

20ms/DIV 4234 TA01b

IIN

0.2A/DIV

LTC4234

4234fa

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PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS

Supply Voltage (VDD) ................................. –0.3V to 28V

Input Voltages

FB, OV, UV ..............................................–0.3V to 12V

TIMER ................................................... –0.3V to 3.5V

SENSE−, SENSE .....VDD − 10V or –0.3V to VDD + 0.3V

Output Voltages

ISET, IMON ................................................. –0.3V to 3V

PG, FLT ................................................. –0.3V to 35V

OUT ............................................ –0.3V to VDD + 0.3V

INTVCC .................................................. –0.3V to 3.5V

GATE (Note 3) ........................................ –0.3V to 33V

Operating Ambient Temperature Range

LTC4234C ................................................ 0°C to 70°C

LTC4234I .............................................–40°C to 85°C

LTC4234H .......................................... –40°C to 125°C

Junction Temperature (Notes 4, 5) ........................ 150°C

Storage Temperature Range .................. –65°C to 150°C

(Notes 1, 2)

17 18 19

TOP VIEW

VDD

SENSE

WHH PACKAGE

38-LEAD (5mm × 9mm) PLASTIC QFN

20 21 22

1UV

IMON

TIMER

INTVCC

VDD (DNC)

GND

SENSE (DNC)

OUT

ISET

FLT

SENSE–

VDD (DNC)

GATE

SENSE

OUT

TJMAX = 150°C, θJA = 15°C/W

EXPOSED PADS (PINS 39 and 40) ARE VDD AND SENSE

θJA = 15°C/W SOLDERED, OTHERWISE θJA = 50°C/W

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC4234CWHH#PBF LTC4234CWHH#TRPBF 4234 38-Lead (5mm × 9mm) Plastic QFN 0°C to 70°C

LTC4234IWHH#PBF LTC4234IWHH#TRPBF 4234 38-Lead (5mm × 9mm) Plastic QFN –40°C to 85°C

LTC4234HWHH#PBF LTC4234HWHH#TRPBF 4234 38-Lead (5mm × 9mm) Plastic QFN –40°C to 125°C

Consult LT C Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LT C Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC4234

4234fa

For more information www.linear.com/LTC4234

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Characteristics

VDD Input Supply Range l2.9 15 V

IDD Input Supply Current MOSFET On, No Load l1.6 3 mA

VDD(UVL) Input Supply Undervoltage Lockout VDD Rising l2.63 2.73 2.85 V

IOUT OUT Leakage Current VOUT = VGATE = 0V, VDD = 15V

VOUT = VGATE = 12V

±700

µA

dVGATE/dt OUT Turn-On Ramp Rate GATE Open l0.15 0.35 0.6 V/ms

RON MOSFET + Sense Resistor On-Resistance C-Grade, I-Grade

H-Grade

2.3

4.0

7.2

8.2

mΩ

ILIM(TH) Current Limit Threshold VFB = 1.35V, ISET Open

VFB = 0V, ISET Open

VFB = 1.35V, RSET = 20k

9.4

22.5

5.7

11.1

7.4

12.8

SOA MOSFET Safe Operating Area 13.5V, 6A Folded Back, 200W2s (Note 6)

7.5V, 22A Onset of Foldback, 200W2s (Note 7)

Inputs

IIN OV, UV, FB Input Current V = 1.2V l0 ±1 µA

ISENSE−(IN) SENSE− Input Current VSENSE− = 12V l4 ±10 µA

VTH OV, UV, FB Threshold Voltage VPIN Rising l1.205 1.235 1.265 V

∆VOV(HYST) OV Hysteresis l10 20 30 mV

∆VUV(HYST) UV Hysteresis l50 80 110 mV

VUV(RTH)UV Reset Threshold Voltage VUV Falling l0.55 0.62 0.7 V

∆VFB(HYST) FB Power Good Hysteresis l10 20 30 mV

RISET ISET Internal Resistor l19 20 21 kΩ

Outputs

VINTVCC INTVCC Output Voltage VDD = 5V,15V, ILOAD = 0mA, –10mA l2.8 3.1 3.3 V

VOL PG, F LT Output Low Voltage I = 2mA l0.4 0.8 V

IOH PG , F LT Input Leakage Current V = 30V l0 ±10 µA

VTIMER(H) TIMER High Threshold VTIMER Rising l1.2 1.235 1.28 V

VTIMER(L) TIMER Low Threshold VTIMER Falling l0.1 0.21 0.3 V

ITIMER(UP) TIMER Pull-Up Current VTIMER = 0V l–80 –100 –120 µA

ITIMER(DN) TIMER Pull-Down Current VTIMER = 1.2V l1.4 2 2.6 µA

ITIMER(RATIO) TIMER Current Ratio ITIMER(DN)/ITIMER(UP) l1.6 2 2.7 %

AIMON IMON Current Gain l4.5 5 5.25 µA/A

BWIMON IMON Bandwidth 250 kHz

IOFF(IMON) IMON Offset Current IOUT = 600mA l0 ±9 µA

IGATE(UP) Gate Pull-Up Current Gate Drive On, VGATE = VOUT = 12V l–18 –24 –29 µA

IGATE(DN) Gate Pull-Down Current Gate Drive Off, VGATE = 18V, VOUT = 12V l180 250 500 µA

IGATE(FST) Gate Fast Pull-Down Current Fast Turn Off, VGATE = 18V, VOUT = 12V 140 mA

LTC4234

4234fa

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Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All currents into pins are positive; all voltages are referenced to

GND unless otherwise specified.

Note 3: An internal clamp limits the GATE pin to a maximum of 6.5V

above OUT. Driving this pin to voltages beyond the clamp may damage the

device.

Note 4: This IC includes overtemperature protection that is intended

to protect the device during momentary overload conditions. Junction

temperature will exceed 150°C when overtemperature protection is active.

Continuous operation above the specified maximum operating junction

temperature may impair device reliability.

Note 5: TJ is calculated from the ambient temperature, TA, and power

dissipation, PD, according to the formula:

TJ = TA + (PD • 15°C/W)

Note 6: SOA tested at room temperature. SOA (i.e. P2t), is reduced at

elevated temperatures according to the following formula:

P2t TJ

( )

=200 W2s





•150°C – TJ

150°C – 25°C











Note 7: Guaranteed by design and extrapolated from P2t limit of 200W2s.

ELECTRICAL CHARACTERISTICS

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VDD = 12V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AC Characteristics

tPHL(GATE) Input High (OV), Input Low (UV) to GATE

Low Propagation Delay

VGATE < 17.8V Falling l8 20 µs

tPHL(ILIM) Short Circuit to GATE Low VFB = 0, Step VDD − SENSE− to 50mV, VGATE <

15V Falling

l1 5 µs

tD(ON) Turn-On Delay Step VUV to 2V, VGATE > 13V l24 48 72 ms

tD(FAULT) UV Low to Clear Fault Latch Delay 1 µs

tD(CB) Circuit Breaker Filter Delay Time (Internal) VFB = 0, Step VDD − SENSE− to 50mV l1.2 2 2.7 ms

tD(COOL_DOWN)Cool Down Delay (Internal) l600 900 1200 ms

LTC4234

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TYPICAL PERFORMANCE CHARACTERISTICS

UV Hysteresis vs Temperature

Timer Pull-Up Current

vs Temperature

Current Limit Delay

(tPHL(ILIM) vs Overdrive)

Current Limit Threshold Foldback

Current Limit Adjustment

(IOUT vs RSET) RISET vs Temperature

IDD vs VDD INTVCC Load Regulation

UV Low-High Threshold

vs Temperature

TA = 25°C, VDD = 12V unless otherwise noted.

VDD (V)

1.0

IDD (mA)

1.4

1.8

125°C

25°C

–40°C

2.2

10 205 15 25

4234 G01

ILOAD (mA)

0.5

1.5

1.0

INTVCC (V)

3.5

2.0

2.5

3.0

4234 G02

–14–12–10–8–6–4–2

VDD = 5V

VDD = 3.3V

TEMPERATURE (°C)

–50

1.224

UV LOW-HIGH THRESHOLD (V)

1.228

1.232

1.236

1.240

–25 0 25 50

4234 G03

75 100 125 150

TEMPERATURE (°C)

–50

0.04

UV HYSTERESIS (V)

0.06

0.08

0.10

–25 0 25 50

4234 G04

75 100 125 150

TEMPERATURE (°C)

–50

–90

TIMER PULL-UP CURRENT (µA)

–95

–100

–105

–110

–25 0 25 50

4234 G05

75 100 125 150

OUTPUT CURRENT (A)

CURRENT PROPAGATION DELAY (µs)

100

1000

0 80 120

4234 G06

0.1

4020 10060

FB VOLTAGE (V)

CURRENT LIMIT VALUE (A)

0.2 0.4 0.6 0.8

4234 G07

1.0 1.2

>30ms SOA GUARANTEED

RSET (Ω)

CURRENT LIMIT VALUE (A)

1k 100k 1M 10M

4234 G08

10k

TEMPERATURE (°C)

–50

ISET RESISTOR (kΩ)

–25 0 25 50

4234 G09

75 100 125 150

LTC4234

4234fa

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TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, VDD = 12V unless otherwise noted.

IMON vs Temperature and VDD

GATE Pull-Up Current

vs Temperature

Gate Drive vs GATE Pull-Up

Current Gate Drive vs VDD

SOA Constant vs Junction

Temperature

VISET vs Temperature

RON vs VDD and Temperature Guaranteed MOSFET SOA Curve

PG, F LT VOUT Low vs ILOAD

TEMPERATURE (°C)

–50

RON (mΩ)

–25 0 25 50

4234 G10

75 100 125 150

VDD = 3.3V TO 12V

VDS (V)

0.1

ID (A)

100

1 10 100

4234 G11

3ms

30ms

TA = 25°C

SINGLE PULSE

>30ms SOA

GUARANTEED

CURRENT (mA)

06 10

4234 G12

2 4 8 12

PG, FLT VOL (V)

TEMPERATURE (°C)

–50

IMON (µA)

100

105

25 75 150

4234 G13

–25 0 50 100 125

VDD = 3.3V TO 12V

ILOAD = 20A

TEMPERATURE (°C)

–50

–23.0

IGATE PULL-UP (µA)

–23.5

–24.0

–24.5

–25.0

–25 0 25 50

4234 G14

75 100 125 150

IGATE (µA)

∆VGATE (VGATE – VOUT) (V)

–5 –10 –15 –20

4234 G15

–25 –30

VDD = 12V

VDD = 3.3V

VDD (V)

6.2

6.0

5.8

5.6

5.4

5.2

5 10 15

4234 G16

20 25 30

∆VGATE (VGATE – VOUT) (V)

JUNCTION TEMPERATURE (°C)

NORMALIZED P2t

0.2

0.4

0.6

1.0

25 50 75 100

4234 G17

125 150

0.8

TEMPERATURE (°C)

–50

0.2

VISET (V)

0.4

0.5

0.6

0.7

0 50 100 150

4234 G18

0.8

0.9

–25 25 75 125

LTC4234

4234fa

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PIN FUNCTIONS

DNC: Do Not Connect. Leave open.

FB: Foldback and Power Good Input. Connect this pin to

an external resistive divider from OUT. If the voltage falls

below 0.6V, the current limit is reduced using a foldback

profile (see the Typical Performance Characteristics sec-

tion). If the voltage falls below 1.21V, the PG pin will pull

low to indicate the power is bad

F LT : Overcurrent Fault Indicator. Open-drain output pulls

low when an overcurrent fault has occurred and the circuit

breaker trips. For overcurrent auto-retry tie to UV pin (see

Applications Information section for details).

GATE: Gate Drive for Internal N-Channel MOSFET. An

internal 24µA current source charges the gate of the

N-channel MOSFET. At start-up the GATE pin ramps up

at a 0.35V/ms rate determined by internal circuitry. Dur-

ing an undervoltage or overvoltage condition a 250µA

pull-down current turns the MOSFET off. During a short

circuit or undervoltage lockout condition, a 140mA pull-

down current source between GATE and OUT is activated.

GND: Device Ground.

IMON: Current Monitor Output. The current in the internal

MOSFET switch is divided by 200,000 and sourced from

this pin. Placing a 20k resistor on this pin allows a 0V to

2V voltage swing when current ranges from 0A to 20A.

INTVCC: Internal 3.1V Supply Decoupling Output. This pin

must have a 1.0µF or larger bypass capacitor. Overloading

this pin can disrupt internal operation.

ISET: Current Limit Adjustment Pin. For 22.5A current limit

value, open this pin. This pin is driven by a 20k resistor

in series with a voltage source. The pin voltage is used

to generate the current limit threshold. The internal 20k

resistor (RISET) and an external resistor (RSET) between

ISET and ground create an attenuator that lowers the

current limit value. Due to circuit tolerance RSET should

not be less than 2k. In order to match the temperature

variation of the sense resistor, the voltage on this pin is

made proportional to temperature of the MOSFET switch.

OUT: Output of Internal MOSFET Switch. Connect this pin

directly to the load.

OV: Overvoltage Comparator Input. Connect this pin to an

external resistive divider from VDD. If the voltage at this

pin rises above 1.235V, an overvoltage is detected and

the switch turns off. Tie to GND if unused.

PG: Power Good Indicator. Open-drain output pulls low

when the FB pin drops below 1.21V indicating the power

is bad. If the voltage at FB rises above 1.235V and the

GATE-to-OUT voltage exceeds 4.2V, the open-drain pull-

down releases the PG pin to go high.

SENSE: Current Sense Node and MOSFET Drain. One

exposed pad on the UH package is connected to SENSE

and should be soldered to an electrically isolated printed

circuit board trace to properly transfer the heat out of the

package. Connect the SENSE pin 31 to the SENSE– pin 34.

SENSE−: Current Limit and Current Monitor Amplifier

Input. The current limit circuit controls the GATE pin to

limit the voltage between the VDD and SENSE– pins to

15mV (22.5A) or less depending on the voltage at the FB

pin. This pin must be connected to SENSE pin on the right

side (connect Pin 34 to Pin 31).

TIMER: Current Limit Timer Input. Connect a capacitor

between this pin and ground to set a 12ms/µF duration for

current limit before the switch is turned off. If the UV pin

is toggled low while the MOSFET switch is off, the switch

will turn on again following cool down time of 4.14s/µF

duration. Tie this pin to INTVCC for a fixed 2ms overcurrent

delay and 900ms cool down time.

UV: Undervoltage Comparator Input. Tie high to INTVCC

if unused. Connect this pin to an external resistive divider

from VDD. If the UV pin voltage falls below 1.15V, an un-

dervoltage is detected and the switch turns off. Pulling this

pin below 0.62V resets the overcurrent fault and allows

the switch to turn back on (see Application Information

section for details). If overcurrent auto-retry is desired

then tie this pin to the F LT pin.

VDD: Supply Voltage and Current Sense Input. This ex-

posed pad must be soldered to input power. VDD has an

undervoltage lockout threshold of 2.73V.

LTC4234

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FUNCTIONAL BLOCK DIAGRAM

4234 BD

RISET

20k

VDD

(EXPOSED PAD)

SENSE–

OUT

GND

IMON

INTVCC

100µA

TIMER

F LT

–ISET

GATE

6.1V

SENSE

(EXPOSED PAD)

CLAMP

0.6V POSITIVE

TEMPERATURE

COEFFICIENT

REFERENCE

3.3mΩ

MOSFET

0.7mΩ

SENSE RESISTOR

CHARGE

PUMP

AND GATE

DRIVER

f = 2MHz

3.1V

GEN

LOGIC

INRUSHCS

0.35V/ms

FOLDBACK

0.6V

2.65V

1.235V

+–

–

1.235V

–

0.21V

–

TM1

1.235V –

TM2

0.62V

–

RST

VDD

2.73V +

–

UVLO1

1.235V –

2µA

–

UVLO2

LTC4234

4234fa

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OPERATION

The Functional Diagram displays the main circuits of the

device. The LTC4234 is designed to turn a board’s supply

voltage on and off in a controlled manner allowing the board

to be safely inserted and removed from a live backplane.

The LTC4234 includes a 3.3mΩ MOSFET and a 0.7mΩ

current sense resistor. During normal operation, the charge

pump and gate driver turn on the pass MOSFET’s gate to

provide power to the load. The inrush current control is

accomplished by the INRUSH circuit. This circuit limits

the GATE ramp rate to 0.35V/ms and hence controls the

voltage ramp rate of the output capacitor.

The current sense (CS) amplifier monitors the load current

using the voltage sensed across the current sense resistor.

The CS amplifier limits the current in the load by reduc-

ing the GATE-to-OUT voltage in an active control loop. It

is simple to adjust the current limit threshold using the

current limit adjustment (ISET) pin. This allows a different

threshold during other times such as start-up. Note there

must be a connection between SENSE to SENSE− (Pin 34

to Pin 31) in order to monitor current.

A short circuit on the output to ground causes significant

power dissipation during active current limiting. To limit

this power, the foldback amplifier reduces the current

limit value from 22.5A to 5.7A in a linear manner as the

FB pin drops below 0.6V (see the Typical Performance

Characteristics).

If an overcurrent condition persists, the TIMER pin ramps

up with a 100µA current source until the pin voltage

exceeds 1.235V (comparator TM2). This indicates to the

logic that it is time to turn off the pass MOSFET to prevent

overheating. At this point the TIMER pin ramps down

using the 2µA current source until the voltage drops below

0.21V (Comparator TM1) which completes one timer cycle.

After eight TIMER pin cycles (ramping to 1.235V and then

below 0.21V) the logic starts the internal 48ms timer. At

this point, the pass transistor has cooled and it is safe

to turn it on again. It is suitable in many applications to

use an internal 2ms overcurrent timer with a 900ms cool

down period. Tying the TIMER pin to INTVCC sets this

default timing. Latchoff is the normal operating condition

following overcurrent turnoff. Retry is initiated by pulling

the UV pin low for a minimum of 1µs then high. Auto-retry

is implemented by tying the F LT to the UV pin.

The output voltage is monitored using the FB pin and the

PG comparator to determine if power is available for the

load. The power good condition is signaled by the PG pin

using an open-drain pull-down transistor.

The Functional Diagram shows the monitoring blocks of

the LTC4234. The two comparators on the left side include

the UV and OV comparators. These comparators are used

to determine if the external conditions are valid prior to

turning on the MOSFET. But first the undervoltage lockout

circuits UVLO1 and UVLO2 must validate the input supply

and the internally generated 3.1V supply (INTVCC) and

generate the power up initialization to the logic circuits. If

the external conditions remain valid for 48ms the MOSFET

is allowed to turn on.

Other monitoring features include MOSFET current and

temperature monitoring. The current monitor (CM) outputs

a current proportional to the sense resistor current. This

current can drive an external resistor or other circuits for

monitoring purposes. A voltage proportional to the MOS-

FET temperature is output to the ISET pin. The MOSFET is

protected by a thermal shutdown circuit.

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APPLICATIONS INFORMATION

The typical LTC4234 application is in a high availability

system that uses a positive voltage supply to distribute

power to individual cards. The complete application circuit

is shown in Figure 1. External component selection is

discussed in detail in the following sections.

Turn-On Sequence

Several conditions must be present before the internal

pass MOSFET can be turned on. First the supply VDD must

exceed its undervoltage lockout level. Next the internally

generated supply INTVCC must cross its 2.65V undervolt-

age threshold. This generates a 25µs power-on-reset pulse

which clears the fault register and initializes internal latches.

After the power-on-reset pulse, the UV and OV pins must

indicate that the input voltage is within the acceptable

Figure 1. 10A, 12V Card Resident Application

range. All of these conditions must be satisfied for a du-

ration of 48ms to ensure that any contact bounce during

the insertion has ended.

The MOSFET is turned on by charging up the GATE with a

charge pump generated 24µA current source whose value

is adjusted by shunting a portion of the pull-up current to

ground. The charging current is controlled by the INRUSH

circuit that maintains a constant slope of GATE voltage

versus time (Figure 2). The voltage at the GATE pin rises

with a slope of 0.35[V/ms] and the supply inrush current

is set at:

IINRUSH= CL • 0.35[V/ms]

This gate slope is designed to charge up a 1000µF capaci-

tor to 12V in 34ms, with an inrush current of 350mA. This

t1t2

SLOPE = 0.35[V/ms]

GATE

OUT

VDD + 6.15V

VDD

4234 F02

Figure 2. Supply Turn-On

ADC

226k

1µF

20k

12V

4234 F01

0.1µF

*TVS Z1: DIODES INC. SMAJ17A

680µF

VOUT

12V

10A

VDD

Z1*

OUT

GND

IMON

RSET

20k

RMON

20k

ISET

CGATE

0.1µF

RGATE

100k

GATE

LTC4234

INTVCC

TIMER

SENSE–

SENSE

F LT

140k

20k

CCOMP

3.3nF

10k

UV = 9.88V

OV = 15.2V

PG = 10.5V

20k

150k

LTC4234

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APPLICATIONS INFORMATION

allows the inrush current to stay under the folded back

current limit threshold (5.7A) for capacitors less than 10mF.

Included in the Typical Performance Characteristics section

is a graph of the Safe Operating Area for the MOSFET. It

is evident from this graph that the power dissipation at

12V, 350mA for 34ms is in the safe region.

Adding a capacitor and a 100k series resistor from GATE to

ground will lower the inrush current below the default value

set by the INRUSH circuit. The 3.3nF capacitor, CCOMP, is

necessary to compensate the current limit regulation loop

when the RGATE and CGATE network is on the GATE pin.

The GATE is charged with a 24µA current source (when

the INRUSH circuit is not driving the GATE). The voltage

at the GATE pin rises with a slope equal to 24µA/CGATE

and the supply inrush current is set at:

IINRUSH =

CGATE

•24µA

When the GATE voltage reaches the MOSFET threshold

voltage, the switch begins to turn on and the OUT volt-

age follows the GATE voltage as it increases. Once OUT

reaches VDD, the GATE will ramp up until clamped by the

6.1V Zener between GATE and OUT.

As the OUT voltage rises, so will the FB pin which is moni-

toring it. Once the FB pin crosses its 1.235V threshold

and the GATE to OUT voltage exceeds 4.2V, the PG pin

will cease to pull low and indicate that the power is good.

Parasitic MOSFET Oscillation

When the N-channel MOSFET ramps up the output during

power-up it operates as a source follower. The source fol-

lower configuration may self-oscillate in the range of 25kHz

to 300kHz when the load capacitance is less than 10µF,

especially if the wiring inductance from the supply to VDD

pin is greater than 3µH. The possibility of oscillations will

increase as the load current (during power-up) increases.

There are two ways to prevent this type of oscillation. The

simplest way is to avoid load capacitances below 10µF.

For wiring inductances larger than 20µH, the minimum

load capacitance may extend to 100µF. A second choice

is to connect an external gate capacitor CP > 1.5nF as

shown in Figure 3.

Figure 3. Compensation for Small CLOAD

4234 F03

LTC4234

GATE CP

2.2nF

OPTIONAL

RC TO LOWER

INRUSH CURRENT

Turn-Off Sequence

The switch can be turned off by a variety of conditions. A

normal turn-off is initiated by the UV pin going below its

1.235V threshold. Additionally, several fault conditions

will turn off the switch. These include an input overvolt-

age (OV pin), overcurrent circuit breaker (SENSE– pin) or

overtemperature. Normally the switch is turned off with a

250µA current pulling down the GATE pin to ground. With

the switch turned off, the OUT voltage drops which pulls

the FB pin below its threshold. The PG then pulls low to

indicate output power is no longer good.

If VDD drops below 2.65V for greater than 5µs or INTVCC

drops below 2.5V for greater than 1µs, a fast shut down

of the switch is initiated. The GATE is pulled down with a

140mA current to the OUT pin.

Overcurrent Fault

The LTC4234 features an adjustable current limit with

foldback that protects against short circuits and exces-

sive load current. To protect against excessive power

dissipation in the switch during active current limit, the

available current is reduced as a function of the output

voltage sensed by the FB pin. A graph in the Typical Per-

formance Characteristics curves shows the Current Limit

Threshold Foldback.

An overcurrent fault occurs when the current limit circuitry

has been engaged for longer than the timeout delay set

by the TIMER. Current limiting begins when the MOSFET

current reaches 5.7A to 22.5A (depending on the foldback).

The GATE pin is then brought down with a 140mA GATE-

to-OUT current. The voltage on the GATE is regulated in

order to limit the current to 22.5A. At this point, a circuit

breaker time delay starts by charging the external timing

capacitor with a 100µA pull-up current from the TIMER

LTC4234

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APPLICATIONS INFORMATION

pin. If the TIMER pin reaches its 1.235V threshold, the

internal switch turns off (with a 250µA current from

GATE to ground). Included in the Typical Performance

Characteristics curves is a graph of the Safe Operating

Area for the MOSFET. From this graph one can determine

the MOSFET’s maximum time in current limit for a given

output power.

Tying the TIMER pin to INTVCC will force the part to use

the internally generated (circuit breaker) delay of 2ms.

In either case the F LT pin is pulled low to indicate an

overcurrent fault has turned off the pass MOSFET. For a

given circuit breaker time delay, the equation for setting

the timing capacitor’s value is as follows:

CT = tCB • 0.083[µF/ms]

After the switch is turned off, the TIMER pin begins dis-

charging the timing capacitor with a 2µA pull-down cur-

rent. When the TIMER pin reaches its 0.21V threshold, it

completes one timer cycle. After eight TIMER pin cycles

(ramping to 1.235V and then below 0.21V) plus the 48ms

debounce time, the switch is allowed to turn on again if

the overcurrent fault latch has been cleared. Bringing the

UV pin below 0.6V for a minimum of 1µs and then high

will clear the fault latch. If the TIMER pin is tied to INTVCC

then the switch is allowed to turn on again (after an internal

900ms cool down time plus the 48ms debounce time), if

the overcurrent fault latch is cleared.

Tying the F LT pin to the UV pin allows the part to self-clear

the fault and turn the MOSFET on as soon as TIMER pin

has ramped below 0.21V for the eighth time followed by

the 48ms debounce time. In this auto-retry mode the

LTC4234 repeatedly tries to turn on after an overcurrent

at a period determined by the capacitor on the TIMER pin.

The auto retry mode also functions when the TIMER pin

is tied to INTVCC.

The waveform in Figure 4 shows how the output latches

off following a short-circuit. The current in the MOSFET

is 5.7A as the TIMER pin ramps up.

Current Limit Adjustment

The default value of the active current limit is 22.5A. The

current limit threshold can be adjusted lower by placing

a resistor between the ISET pin and ground. As shown in

the Functional Block Diagram the voltage at the ISET pin

(via the clamp circuit) sets the CS amplifier’s built-in offset

voltage. This offset voltage directly determines the active

current limit value. With the ISET pin open, the voltage

at the ISET pin is determined by a positive temperature

coefficient reference. This voltage is set to 0.618V which

corresponds to a 22.5A current limit at room temperature.

An external resistor RSET placed between the ISET pin and

ground forms a resistive divider with the internal 20k RISET

sourcing resistor. The divider acts to lower the voltage at

the ISET pin and therefore lower the current limit threshold.

The overall current limit threshold precision is reduced to

±15% when using a 20k resistor to halve the threshold.

Using a switch (connected to ground) in series with RSET

allows the active current limit to change only when the

switch is closed. This feature can be used to program a

reduced running current while the maximum available

current limit is used at start-up.

Monitor MOSFET Temperature

The voltage at the ISET pin increases linearly with increas-

ing temperature. The temperature profile of the ISET pin is

shown in the Typical Performance Characteristics section.

Figure 4. Short-Circuit Waveform

∆VGATE

10V/DIV

IOUT

5A/DIV

VOUT

10V/DIV

TIMER

2V/DIV

1ms/DIV 4234 F04

LTC4234

4234fa

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Using a comparator or ADC to measure the ISET voltage

provides an accurate indication of the MOSFET temperature.

The ISET voltage follows the formula:

VISET =

SET

RSET +RISET

•(T +273°C)•2.093[mV/°C]

The MOSFET temperature is calculated using RISET of 20k.

T=RSET +20k

( )

• VISET

RSET •2.093[mV/°C] – 273°C

When RSET is not present, T becomes:

ISET

2.093[mV/°C] – 273°C

There is an overtemperature circuit in the LTC4234 that

monitors an internal voltage similar to the ISET pin voltage.

When the die temperature exceeds 155°C the circuit turns

off the MOSFET until the temperature drops to 135°C.

Monitor MOSFET Current

The current in the MOSFET passes through an internal

0.7mΩ sense resistor. The voltage on the sense resistor is

converted to a current that is sourced out of the IMON pin.

The gain of ISENSE amplifier is 5µA/A referenced from the

MOSFET current. This output current can be converted to

a voltage using an external resistor to drive a comparator

or ADC. The voltage compliance for the IMON pin is from

0V to INTVCC − 0.7V.

A microcontroller with a built-in comparator can build a

simple integrating single-slope ADC by resetting a capaci-

tor that is charged with this current. When the capacitor

voltage trips the comparator and the capacitor is reset, a

timer is started. The time between resets will indicate the

MOSFET current.

Monitor OV and UV Faults

Protecting the load from an overvoltage condition is the

main function of the OV pin. In Figure 1 an external resis-

tive divider (driving the OV pin) connects to a comparator

to turn off the MOSFET when the VDD voltage exceeds

15.2V. If the VDD pin subsequently falls back below 14.9V,

the switch will be allowed to turn on immediately. In the

LTC4234 the OV pin threshold is 1.235V when rising, and

1.215V when falling out of overvoltage.

The UV pin functions as an undervoltage protection pin

or as an “ON” pin. In the Figure 1 application the MOS-

FET turns off when VDD falls below 9.23V. If the VDD pin

subsequently rises above 9.88V for 48ms, the switch will

be allowed to turn on again. The LTC4234 UV turn-on/off

threshold are 1.235V (rising) and 1.155V (falling).

In the case of an undervoltage or overvoltage, the MOSFET

turns off and there is indication on the PG status pin. When

the overvoltage is removed, the MOSFET’s gate ramps up

immediately at the rate determined by the INRUSH circuit.

Power Good Indication

In addition to setting the foldback current limit threshold,

the FB pin is used to determine a power good condition.

The Figure 1 application uses an external resistive divider

on the OUT pin to drive the FB pin. On the LTC4234 the

PG comparator drives high when the FB pin rises above

1.235V and low when it falls below 1.215V.

Once the PG comparator is high the GATE pin voltage is

monitored with respect to the OUT pin. Once the GATE

minus OUT voltage exceeds 4.2V the PG pin goes high.

This indicates to the system that it is safe to load the OUT

pin while the MOSFET is completely turned “on”. The PG

pin goes low when the GATE is commanded off (using

the UV, OV or SENSE– pins) or when the PG comparator

drives low.

Design Example

Consider the following design example (Figure 5):

TA = 60°C, VIN = 12V, IMAX = 20A. IINRUSH = 350mA,

= 1000µF, VUVON

= 9.88V, VOVOFF

= 15.2V, VPGTHRESHOLD

= 10.5V. A current limit fault triggers an automatic restart

of the power-up sequence.

APPLICATIONS INFORMATION

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4234fa

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The inrush current is defined by the current required to

charge the output capacitor using the fixed 0.35V/ms GATE

charge up rate. The inrush current is defined as:

INRUSH =CL•0.35V













=1000µF • 0.35V













=350mA

As mentioned previously the charge-up time is the output

voltage (12V) divided by the output rate of 0.35V/ms

resulting in 34ms. The peak power dissipation of 12V at

350mA (or 4.2W) must not exceed the SOA of the pass

MOSFET for 34ms (see MOSFET SOA graph in the Typical

Performance Characteristics). On the SOA graph the 30ms

line crosses the 10V VDS vertical line at 8A. This verifies

that the 80W for 30ms is safe at room temperature. Each

single point on the 8ms and 30ms lines represent a power

(voltage times current) and time that follow a constant P2t

relationship of 200W2s. This constant P2t number is valid

for power pulses less than 50ms. Beyond 50ms the P2t

number will depend on the thermal characteristics of the

board. If the MOSFET junction temperature is elevated,

then the P2t constant must be derated. At TJ = 60°C the

new constant becomes:

P2t TJ=60°C

( )

=200 W2s





•150°C – 60°C

150°C – 25°C











104 W2s









The maximum power for 34ms can be calculated from

the derated constant:

PMAX =P2t TJ=60°C

( )

τ=104 W2s







34ms =55W

Therefore the power dissipation at charge-up is within

the MOSFET SOA.

Next the power dissipated in the MOSFET during overcur-

rent must be limited. The active current limit uses a timer

to prevent excessive energy dissipation in the MOSFET.

The worst-case power dissipation occurs when the voltage

versus current profile of the foldback current limit is at the

maximum. This occurs when the current is 25A and the

voltage is one-half of the VIN or 6V. See the Current Limit

Threshold Foldback in the Typical Performance Charac-

teristics section to view this profile. In order to survive

150W, the MOSFET SOA dictates a maximum current limit

timeout. If the MOSFET operating temperature is elevated

prior to current limit the SOA constant must be derated

according to the formula:

P2t TJ

( )

=P2t 25°C

( )

•150°C– TJ

150°C – 25°C











TJ is calculated from the ambient temperature, package

thermal impedance (θJA) and the I2R heating:

TJ = (θJA • I2 • RON) + TA = 15°C/W • (20A)2 • 7.2mΩ

+ 60°C = 103˚C

Use the SOA derating formula:

P2t TJ=103°C

( )

=200 W2S







•

150°C–103°C

150°C – 25°C











=28 W2S







So the SOA constant is derated to 28 W2s. The maximum

current limit timeout is calculated from the revised constant

and the 150 W dissipated in current limit:

tMAX =P2t TJ=103°C

( )

P2=28 W2S







150W

( )

2=1.2ms

APPLICATIONS INFORMATION

ADC

226k

1µF

20k

*TVS Z1: DIODES INC. SMAJ17A

12V

4234 F05

68nF

1000µF

OUT

12V

20A

VDD

Z1*

OUT

GND

IMON

RMON

20k

ISET

GATE

LTC4234

INTVCC

TIMER

SENSE–

SENSE

F LT

140k

20k

10k

20k

150k

UV = 9.88V

OV = 15.2V

PG = 10.5V

Figure 5. 20A, 12V Card Resident Application

LTC4234

4234fa

For more information www.linear.com/LTC4234

APPLICATIONS INFORMATION

Therefore it is acceptable to set the current limit timeout

using CT to be 0.8ms:

CT=

0.8ms

12 ms/µF

[ ]

=68nF

To configure the LTC4234 for auto retry after overcurrent

fault, connect the F LT to the UV pin.

After the 0.8ms timeout the F LT pin pulls down on the UV

pin restart the power-up sequence.

The values for overvoltage, undervoltage and power good

thresholds using the resistive dividers on the UV, OV and

FB pins match the requirements of turn-on at 9.88V and

turn-off at 15.2V.

The final schematic in Figure 5 results in very few external

components. The pull-up resistor, R7, connects to the PG

pin while the 20k (RMON) converts the IMON current to a

voltage at a ratio:

VIMON = 5[µA/A] • 20k • IOUT = 0.1[V/A] • IOUT

In addition there is a 1µF bypass (C1) on the INTVCC pin

and note the connection between SENSE to SENSE− (Pin34

to Pin 31).

Layout Considerations

In Hot Swap applications where load currents can be 20A,

narrow PCB tracks exhibit more resistance than wider tracks

and operate at elevated temperatures. The minimum trace

width requirement for 1oz copper foil is 0.02" per amp to

make sure the trace stays at a reasonable temperature.

Using 0.03" per amp or wider is recommended. Note that

1oz copper exhibits a sheet resistance of about 0.5mΩ/

square. Small resistances add up quickly in high current

applications.

The input supply should be tied to VDD exposed pad through

a PCB trace that enters between Pin 1 and Pin 38. The VDD

pad connects to the sense resistor and MOSFET. Globally

there are three DNC pins that are unconnected and left

open (pins 6, 8, 33). Connect the SENSE– pin (pin 34) to

the SENSE pin (pin 31). Figure 6 shows a recommended

layout for the LTC4234.

During normal operation the power dissipated in the

MOSFET could be as high as 2.9W. To remove this heat

solder the SENSE exposed pad to a copper trace that

contains vias underneath the pad. The OUT pins conduct

substantial heat from the MOSFET. Connect all the OUT

pins to a plane of 1oz copper. Since the trace that connects

OUT pins must accommodate high current, this area of

copper is usually present. It is also important to put C1,

the bypass capacitor for the INTVCC pin as close as pos-

sible between INTVCC and GND.

Thermal Considerations

The LTC4234 junction to board temperature rise in still air

when the load current is 10A, 15A and 20A is shown in

curves of Figure 7 and Figure 8. The junction temperature

was measured at the package and the board temperature

was measured at the board edge. This temperature rise

falls as the board area is increases from 6.45cm2 to

103cm2. Tw o different SENSE pad areas are shown as

separate figures.

This thermal test board uses 2oz copper on the top layer

divided equally between VDD and OUT traces similar to

GND

4234 F06

VDD OUT

SENSE

VDD

Figure 6. Recommended Layout

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APPLICATIONS INFORMATION

Figure 6. The second layer is 1oz copper connected to

the vias to the SENSE pad on the top layer. Tw o versions

of the second layer are considered. One uses a minimum

sized SENSE pad that only covers the vias for the top

layer while the remainder of the second layer is empty

(see Figure 7). The other version fills the second layer

with SENSE connected copper (see Figure 8). The third

layer is 1oz copper tied to ground while the bottom layer

is 2oz copper tied to ground except for a few signal traces.

The curves demonstrate that the heat from the MOSFET

can be effectively transferred out of the package through

the OUT pins and only requires a minimum sized SENSE

pad under the package. However for small boards the

larger SENSE area does reduce the junction temperature

when sourcing higher currents.

Additional Applications

The LTC4234 has a wide operating range from 2.9V to 15V.

The UV, OV and PG thresholds are set with few resistors.

All other functions are independent of supply voltage.

In addition to Hot Swap applications, the LTC4234 also

functions as a backplane resident switch for removable

load cards (see Figure 9).

Figure 10 shows a 3.3V application with a UV threshold

of 2.87V, an OV threshold of 3.77V and a PG threshold

of 3.05V.

The last page shows a 40A parallel application where the

two LTC4234 parts each provide 20A to the load. The

PNPs prevent one LTC4234 from faulting off in current

limit until both parts hit the 22.5A limit. The PNPs are

disconnected when power good is false via the series

MOSFETs M1 and M2

Figure 7. Temperature Rise for Small SENSE Pad Figure 8. Temperature Rise for Large SENSE Pad

∆TJB

AB (cm

)

100

120

10A 15A 20A

20 40 60 80

4234 F07

100

4234 F07

SMALL SENSE PAD (2ND LAYER)

∆TJB

AB (cm

)

100

120

10A 15A

20 40 60 80

100

20A

4234 F08

LARGE SENSE PAD (2ND LAYER)

LTC4234

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For more information www.linear.com/LTC4234

APPLICATIONS INFORMATION

14.7k

10k

17.4k

ADC

3.16k

1µF

10k

3.3V

RMON

20k

4234 F10

1000µF

VDD

Z1*

OUT

GND

IMON

LTC4234

SENSE–

SENSE

INTVCC

*TVS Z1: DIODES INC. SMAJ17A

TIMER

F LT

OUT

3.3V

10k

ISET

GATE

UV = 2.87V

OV = 3.77V

PG = 3.05V

Figure 10. 3.3V, 20A Card Resident Application with Auto-Retry

150k

20k

ADC

1µF

*TVS Z1: DIODES INC. SMAJ17A

RMON

20k

4234 F09

VDD

OUT

GND

IMON

ISET

GATE

LTC4234

SENSE–

SENSE

INTVCC

TIMER

F LT

OUT

12V

20A

UV = 9.88V

OV = 15.2V

PG = 10.5V

12V

10k

226k

Z1*

20k

12V

20k R3

140k

LOAD

Figure 9. 12V, 20A Backplane Resident Application with Insertion Activated Turn-On

LTC4234

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PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

5.00 ±0.10

(2 SIDES)

PIN 1

TOP MARK

(SEE NOTE 6) 1

BOTTOM VIEW—EXPOSED PAD

3.59 ±0.10

3.59 ±0.05

4.14 ±0.10

2.93 ±0.10

4.14 ±0.05

2.93 ±0.05

9.00 ±0.10

(2 SIDES)

3.59 ±0.05

5.5 ±0.05

4.1 ±0.05

2.7 ±0.05

3.59 ±0.10

(WHH36MA) QFN 1212 REV Ø

7.50

REF

0.40 ±0.10

0.5 BSC

0.25 ±0.05

0.50 REF

1.22

REF

0.72

REF

0.203 REF

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.350 REF

0.00 – 0.05

SEATING PLANE

0.90 ±0.10

0.70 ±0.05

0.35 REF

0.5 BSC

0.7

BSC

0.9 ±0.10

7.5 REF (2 SIDES)

0.25 ±0.05

PACKAGE

OUTLINE

PIN 1 NOTCH

R = 0.30

WHH Package

Variation: WHH38MA

38-Lead Plastic QFN (5mm × 9mm)

(Reference LTC DWG # 05-08-1934 Rev Ø)

0.7 BSC

2.7 REF

NOTE:

1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

0.5 REF

1.22 REF

0.72 REF

LTC4234

4234fa

For more information www.linear.com/LTC4234

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 10/15 Changed input clamp to SMAJ17A in application circuit.

Updated SOA specification; added BWIMON and tD(FAULT) specifications.

Added SOA Constant vs Junction Temperature curve; updated MOSFET SOA curve.

Updated INTVCC, SENSE and VDD pin functions.

Clarified latchoff and auto-retry behavior.

Added equations to calculate MOSFET temperature from VISET.

Updated sections: Design Example, Layout Considerations, Typical Application.

1, 10, 17

3, 4

14, 15, 20

LTC4234

4234fa

For more information www.linear.com/LTC4234

 LINEAR TECHNOLOGY CORPORATION 2015

LT 1015 REV A • PRINTED IN USA

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTC4234

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

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12V, 40A Parallel Application

4234 TA02

VN2222LLG

2N5087

VN2222LLG

150k

20k

107k

Z1*

5.23k

10k

1µF

12V

0.1µF

2200µF

VDD

OUT

GND

IMON

LTC4234

SENSE–

SENSE

INTVCC

TIMER

F LT

OUT

12V

40A

100k

ISET

150k

20k

107k

5.23k

10k

1µF

*TVS Z1, Z2: DIODES INC: SMBJ8V5(C)A

VDD

OUT

GND

IMON

LTC4234

SENSE–

SENSE

INTVCC

TIMER

F LT

GATE

ISET

GATE