– 1 –
CXK581000ATM/AYM/AM/AP
E92756D53-PP
131072-word ×8-bit High Speed CMOS Static RAM
Description
The CXK581000ATM/AYM/AM/AP is a high speed
CMOS static RAM organized as 131072-words by
8 bits.
A polysilicon TFT cell technology realized extremely low
stand- by current and higher data retention stability.
Special feature are low power consumption, high
speed and broad package line-up.
The CXK581000ATM/AYM/AM/AP ia a suitable
RAM for portable equipment with battery back up.
Features
•Fast access time:
CXK581000ATM/AYM/AM/AP (Access time)
-55LL/55SL 55ns (Max.)
-70LL/70SL 70ns (Max.)
-10LL/10SL 100ns (Max.)
•Low standby current:
CXK581000ATM/AYM/AM/AP
-55LL/70LL/10LL 20µA (Max.)
-55SL/70SL/10SL 12µA (Max.)
•Low data retention current
CXK581000ATM/AYM/AM/AP
-55LL/70LL/10LL 12µA (Max.)
-55SL/70SL/10SL 4µA (Max.)
•Single +5V supply: +5V ±10%
•Low voltage data retention: 2.0V (Min.)
•Broad package line-up
•CXK581000ATM/AYM
8mm ×20mm 32 pin TSOP package
•CXK581000AM 525mil 32 pin SOP package
•CXK581000AP 600mil 32 pin DIP package
Functions
131072-word ×8-bit static RAM
Structure
Silicon gate CMOS IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
Block Diagram
VCC
GND
OE
WE
CE1
CE2
A10
A11
A9
A8
A13
A15
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
Buffer Row
Decoder Memory
Matrix
1024 × 1024
I/O Gate
Column
Decoder
I/O Buffer
Buffer
Buffer
I/O 1 I/O 8
CXK581000ATM
32 pin TSOP (Plastic) CXK581000AYM
32 pin TSOP (Plastic)
CXK581000AM
32 pin SOP (Plastic) CXK581000AP
32 pin DIP (Plastic)
-55LL/70LL/10LL
-55SL/70SL/10SL
For the availability of this product, please contact the sales office.
– 2 –
CXK581000ATM/AYM/AM/AP
Pin Configuration (Top View)
A11
A9
A8
A13
WE
CE2
A15
VCC
NC
A16
A14
A12
A7
A6
A5
A4
A4
A5
A6
A7
A12
A14
A16
NC
VCC
A15
CE2
WE
A13
A8
A9
A11
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
I/O4
I/O5
I/O6
I/O7
I/O8
CE1
A10
OE
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
A3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CXK581000AYM
(Mirror Image Pinout)
CXK581000ATM
(Standard Pinout)
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Pin Description
A0 to A16
I/O1 to I/O8
CE1, CE2
WE
OE
Vcc
GND
NC
Address input
Data input output
Chip enable 1, 2 input
Write enable input
Output enable input
Power supply
Ground
No connection
Symbol Description
Absolute Maximum Ratings (Ta = 25°C, GND = 0V)
Item Symbol Rating Unit
Supply voltage
Input voltage
Input and output voltage
Allowable power dissipation
Operating temperature
Storage temperature
Soldering temperature
VCC
VIN
VI/O
PD
Topr
Tstg
Tsolder
–0.5 to +7.0
–0.5∗to VCC +0.5
–0.5∗to VCC +0.5
1.0
0.7
0 to +70
–55 to +150
260 • 10
235 • 10
V
W
°C
°C • s
CXK581000AP
CXK581000ATM/AYM/AM
∗VIN,VI/O = –3.0V Min. for pulse width less than 50ns.
CE1 CE2 OE WE Mode I/O pin VCC Current
H
×
L
L
L
×
L
H
H
H
×
×
H
L
×
×
×
H
H
L
Not selected
Not selected
Output disable
Read
Write
High Z
High Z
High Z
Data out
Data in
Truth Table
×: "H" or "L"
DC Recommended Operating Conditions (Ta = 0 to +70°C, GND = 0V)
Supply voltage
Input high voltage
Input low voltage
VCC
VIH
VIL
4.5
2.2
–0.3∗
5.0
—
—
5.5
VCC +0.3
0.8 V
Item Symbol Min. Typ. Max. Unit
∗VIL = –3.0V Min. for pulse width less than 50ns.
CXK581000AM
CXK581000AP
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O8
I/O7
I/O6
I/O5
I/O4
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CXK581000AP
CXK581000ATM/AYM/AM
ISB1, ISB2
ISB1, ISB2
ICC1, ICC2, ICC3
ICC1, ICC2, ICC3
ICC1, ICC2, ICC3
– 3 –
CXK581000ATM/AYM/AM/AP
Electrical Characteristics
• DC Characteristics (VCC = 5V ±10%, GND = 0V, Ta = 0 to = +70°C)
Item Symbol Test conditions Min. Typ.∗1Max. Unit
Input leakage current
Output leakage current
Operating power
supply current
Average operating
current
Standby current
Output high
voltage
Output low
voltage
ILI
ILO
ICC1
ICC2
ICC3
ISB1
ISB2
VOH
VOL
VIN = GND to VCC
CE1 = VIH or CE2 = VIL or OE = VIH
or WE = VIL, VI/O = GND to VCC
CE1 = VIL, CE2 = VIH
VIN = VIH or VIL
IOUT = 0mA
Min. cycle 55LL/55SL
Duty = 100% 70LL/70SL
IOUT = 0mA 10LL/10SL
Cycle time 1µs
duty = 100%
IOUT = 0mA
CE1 ≤0.2V
CE2 ≥VCC – 0.2V
VIL ≤0.2V
VIH ≥VCC – 0.2V
CE2 ≤0.2V
or CE1 ≥VCC – 0.2V
{
CE2 ≥VCC – 0.2V
CE1 = VIH or CE2 = VIL
IOH = –1.0mA
IOL = 2.1mA
–1
–1
—
—
—
—
—
—
—
—
—
—
—
—
2.4
—
1
1
15
90
70
60
20
20
4
2
12
2.4
1
3
—
0.4
—
—
7
45
40
35
10
—
—
0.7
—
—
0.3
0.6
—
—
µA
mA
µA
mA
V
0 to +70°C
LL∗20 to +40°C
+25°C
0 to +70°C
SL∗30 to +40°C
+25°C
∗1VCC = 5V, Ta = 25°C
∗2 For -55LL/70LL/10LL
∗3 For -55SL/70SL/10SL
– 4 –
CXK581000ATM/AYM/AM/AP
I/O Capacitance (Ta = 25°C, f = 1MHz)
Input capacitance
I/O capacitance
Item Symbol Test conditions Min. Typ. Max. Unit
CIN
CI/O
VIN = 0V
VI/O = 0V —
——
—7
8pF
Note) This parameter is sampled and is not 100% tested.
Input pulse high level
Input pulse low level
input rise time
input fall time
Input and output reference level
-55LL/55SL
Output load conditions -70LL/70SL
-10LL/10SL
VIH = 2.2V
VIL = 0.8V
tr = 5ns
tf = 5ns
1.5V
CL∗= 30pF, 1TTL
CL∗= 100pF, 1TTL
Item Conditions
AC Characteristics
• AC test conditions (VCC = 5V±10%, Ta = 0 to +70°C)
∗CLincludes scope and jig capacitances.
TTL
CL
• Test circuit
– 5 –
CXK581000ATM/AYM/AM/AP
—
55
55
55
30
—
—
—
25
25
• Read cycle (WE = "H")
Read cycle time
Address access time
Chip enable access time (CE1)
Chip enable access time (CE2)
Output enable to output valid
Output hold from address change
Chip enable to output in low Z (CE1, CE2)
Output enable to output in low Z (OE)
Chip disable to output in high Z (CE1, CE2)
Output disable to output in high Z (OE)
Item Symbol -55LL/55SL -70LL/70SL -10LL/10SL Unit
Min. Max. Min. Max. Min. Max.
Item Symbol -55LL/55SL -70LL/70SL -10LL/10SL Unit
Min. Max. Min. Max. Min. Max.
tRC
tAA
tCO1
tCO2
tOE
tOH
tLZ1, tLZ2
tOLZ
tHZ1, tHZ2∗
tOHZ∗
55
—
—
—
—
15
10
5
—
—
70
—
—
—
—
15
10
5
—
—
—
70
70
70
40
—
—
—
25
25
—
100
100
100
50
—
—
—
35
35
100
—
—
—
—
15
10
5
—
—
ns
∗tHZ1, tHZ2 and tOHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
Write cycle time
Address valid to end of write
Chip enable to end of write
Data to write time overlap
Data hold from write time
Write pulse width
Address setup time
Write recovery time (WE)
Write recovery time (CE1, CE2)
Output active from end of write
Write to output in high Z
tWC
tAW
tCW
tDW
tDH
tWP
tAS
tWR
tWR1
tOW
tWHZ∗
55
50
50
25
0
40
0
0
0
10
—
—
—
—
—
—
—
—
—
—
—
25
70
60
60
30
0
50
0
0
0
10
—
—
—
—
—
—
—
—
—
—
—
25
—
—
—
—
—
—
—
—
—
—
30
100
70
70
40
0
70
0
0
0
10
—
ns
∗tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage level.
– 6 –
CXK581000ATM/AYM/AM/AP
Timing Waveform
• Read cycle (1) : CE1 = OE = VIL, CE2 = VIH, WE = VIH
• Read cycle (2) : WE = VIH
• Write cycle (1) : WE control
tWC
tCW
tAW
tCW
tWPtAS
tDHtDW
tOW
tWHZ
tWR
Data valid
High impedance
Address
OE
CE1
CE2
WE
Data in
Data out
(∗1)
(∗2) (∗2)
tOLZ
Data valid
High impedance
Address
CE1
CE2
OE
Data out
tRC
tAA
tCO1
tLZ1
tLZ2
tCO2
tHZ1
tHZ2
tOHZtOE
Address
Data out Previous data valid Data valid
tRC
tAA
tOH
– 7 –
CXK581000ATM/AYM/AM/AP
• Write cycle (2) : CE1 control
• Write cycle (3) : CE2 control
∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously.
∗2 Do not apply the data input voltage of the opposite phase to the output while the I/O pin is in output condition.
∗3tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until
the end of the write cycle.
tWC
tOW
tAW
tWP
tAS
tDHtDW
Data valid
High impedance
Address
OE
CE1
CE2
WE
Data in
Data out
tCW
tAS
tCW
tWR1 (∗3)
tWC
tCW
tAW
tCW
tWP
tAS
tDHtDW
tWR1
Data valid
High impedance
Address
OE
CE1
CE2
WE
Data in
Data out
(∗3)
– 8 –
CXK581000ATM/AYM/AM/AP
Data Retention Waveform
•Low supply voltage data retention waveform (1) : CE1 control
•Low supply voltage data retention waveform (2) : CE2 control
Data Retention Characteristics (Ta = 0 to +70°C)
Item Symbol Test conditions Min. Typ. Max. Unit
Data retention voltage
Data retention current
Data retention setup
time
Recovery time
VDR
ICCDR1
ICCDR2
tCDRS
tR
∗1
VCC = 3.0V∗1
2.0
—
—
—
—
—
—
—
—
0
5
5.5
12
2.4
1.2
4
0.8
0.3
20
12
—
—
—
—
—
0.4
—
—
0.15
0.7
0.3
—
—
V
µA
ns
ms
0 to +70°C
LL∗20 to +40°C
+25°C
0 to +70°C
SL∗30 to +40°C
+25°C
Note)
∗1 CE1 ≥VCC – 0.2V, CE2 ≥VCC – 0.2V [CE1 Control] or CE2 ≤0.2V [CE2 Control]
∗2 For -55LL/70LL/10LL
∗3 For -55SL/70SL/10SL
Data retention mode
tCDRS tR
CE2 ≤ 0.2V
VCC
4.5V
CE2
VDR
0.4V
GND
Data retention modetCDRS tR
CE1 ≥ VCC – 0.2V
VCC
4.5V
2.2V
VDR
CE1
GND
VCC = 2.0V to 5.5V∗1LL∗2
SL∗3
Chip disable to data retention mode
– 9 –
CXK581000ATM/AYM/AM/AP
Example of Representative Characteristics
1.5
1.25
1.0
0.75
0.54.5 4.75 55.25 5.5
Ta = 25°C
ICC1
ICC2
Supply current vs. Supply voltage
VCC — Supply voltage (V)
I
CC1
, I
CC2
— Supply current (Relative Value)
1.2
1.1
1.0
0.9
0.8020 40 60 80
VCC = 5.0V
ICC1
ICC2 (Write)
Supply current vs. Ambient temperature
Ta — Ambient temperature (°C)
l
CC1
, I
CC2
— Supply current (Relative Value)
ICC2 (Read)
1.0
0.8
0.6
0.4
0.2
00412 16 20
Write
Supply current vs. Frequency
Frequency (1/tRC, 1/tWC) (MHz)
I
CC2
— Supply current (Relative Value)
Read
100ns 70ns 55ns
8
VCC = 5.0V
Ta = 25°C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6 0 100 200 300 400
VCC = 5.0V
Ta = 25°C
TAA, TCO1, TCO2
TOE
Access time vs. Load capacitance
CL — Load capacity (pF)
T
AA
, T
CO1
, T
CO2
, T
OE
— Access time (Relative Value)
1.4
1.2
1.0
0.8
0.64.5 4.75 5 5.25 5.5
Ta = 25°C
TAA, TCO1, TCO2
TOE
Access time vs. Supply voltage
VCC — Supply voltage (V)
T
AA
, T
CO1
, T
CO2
, T
OE
— Access time (Relative Value)
1.4
1.2
1.0
0.8
0.6 020 40 60 80
VCC = 5.0V
TCO1, TCO2, TAA
TOE
Access time vs. Ambient temperature
Ta — Ambient temperature (°C)
T
AA
, T
CO1
, T
CO2
, T
OE
— Access time (Relative Value)
– 10 –
CXK581000ATM/AYM/AM/AP
2.0
1.5
1.0
0.5
02.0 3.0 4.0 5.0 6.0
Ta = 25°C
ISB2
ISB1
Standby current vs. Supply voltage
VCC — Supply voltage (V)
I
SB1
, I
SB2
— Standby current (Relative value)
20
10
5
2
1
0.5
0.2 020 40 60 80
VCC = 5.0V
Standby current vs. Ambient temperature
Ta — Ambient temperature (°C)
I
SB1
— Standby current (Relative value)
1.2
1.1
1.0
0.9
0.84.5 4.75 55.25 5.5
Ta = 25°C
VIL, VIH
Input voltage level vs. Supply voltage
VCC — Supply voltage (V)
V
IL
, V
IH
— Input voltage (Relative value)
1.4
1.2
1.0
0.8
0.6 02040
60 80
Standby current vs. Ambient temperature
Ta — Ambient temperature (°C)
I
SB2
— Standby current (Relative value)
VCC = 5.0V
1.4
1.2
1.0
0.8
0.6 12345
Output high current vs. Output high voltage
VOH — Output high voltage (V)
I
OH
— Output high current (Relative value)
VCC = 5.0V
Ta = 25°C
1.8
1.4
1.0
0.6
00.2 0.4 0.6 0.8
Output low current vs. Output low voltage
VOL — Output low voltage (V)
I
OL
— Output low current (Relative value)
VCC = 5.0V
Ta = 25°C
– 11 –
CXK581000ATM/AYM/AM/AP
Package Outline Unit: mm
CXK581000ATM
CXK581000AYM
SONY CODE
EIAJ CODE
JEDEC CODE
TSOP (I) -32P-L01
TSOP (I) 032-P-0820-A
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
42 ALLOY
SOLDER PLATING
EPOXY / PHENOL RESIN
0° to 10°
32PIN TSOP (I) (PLASTIC)
8.0 ± 0.2
32 17
0.2 – 0.03
+ 0.08
0.5
116
A
0.127 – 0.02
+ 0.05
0.1 ± 0.1
0.5 ± 0.1
1.07 – 0.1
+ 0.2
∗18.4 ± 0.2
20.0 ± 0.2
DETAIL A
0.1
0.08 M
NOTE: Dimension “∗” does not include mold protrusion.
SONY CODE
EIAJ CODE
JEDEC CODE
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
EPOXY RESIN
SOLDER PLATING
42 ALLOY
TSOP-32P-L01R
TSOP032-P-0820-B
32PIN TSOP (PLASTIC)
M
0.08 0.5
0.2 – 0.03
+ 0.08
16 1
17 32
8.0 ± 0.2
∗18.4 ± 0.2
20.0 ± 0.2
1.07 – 0.1
+ 0.2
0.127 – 0.02
+ 0.05
0.1 ± 0.1
0.5 ± 0.1
0° to 10°
A
0.1
DETAIL A
0.3g
NOTE: Dimension “∗” does not include mold protrusion.
– 12 –
CXK581000ATM/AYM/AM/AP
CXK581000AM
CXK581000AP
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
SONY CODE
EIAJ CODE
JEDEC CODE
SOP-32P-L02
∗SOP032-P-0525-A
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
32PIN SOP (PLASTIC) 525mil
20.5 – 0.1
+ 0.4
32 17
10.4 ± 0.1 1.27 16
+ 0.3
11.2 – 0.1
14.0 ± 0.4
2.9 – 0.25
+ 0.15
11.9
A
0.15 – 0.05
+ 0.1
0.2 ± 0.1
0.8 ± 0.2
0° to 10°
DETAIL A
0.1
0.12 M
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE WEIGHT
SONY CODE
EIAJ CODE
JEDEC CODE
DIP-32P-01
∗DIP32-P-0600-A
EPOXY / PHENOL RESIN
SOLDER PLATING
42 ALLOY
4.5g
32PIN DIP (PLASTIC) 600mil
40.2 – 0.1
+ 0.4
32 17
1
2.54
16
15.24
0.5 ± 0.1
1.2 ± 0.15
3.0 MIN 0.5 MIN
0° to 15°
4.6 – 0.1
+ 0.4
13.5 – 0.1
+ 0.3
0.25 – 0.05
+ 0.1
