© 2006 Microchip Technology Inc. DS22004B-page 1
MCP6G01/1R/1U/2/3/4
Features
• 3 Gain Selections:
- +1, +10, +50 V/V
• One Gain Select Input per Amplifier
• Rail-to-Rail Input and Output
• Low Gain Error: ±1% (max.)
• High Bandwidth: 250 kHz to 900 kHz (typ.)
• Low Supply Current: 110 µA (typ.)
• Single Supply: 1.8V to 5.5V
• Extended Temperature Range: -40°C to +125°C
Typical Applications
• A/D Converter Driver
• Industrial Instrumentation
• Bar Code Readers
• Metering
• Digital Cameras
Block Diagram
Description
The Microchip Technology Inc. MCP6G01/1R/1U/2/3/4
are analog Selectable Gain Amplifiers (SGA). They can
be configured for gains of +1 V/V, +10 V/V, and
+50 V/V through the Gain Select input pin(s). The Chip
Select pin on the MCP6G03 can put it into shutdown to
conserve power. These SGAs are optimized for single
supply applications requiring reasonable quiescent
current and speed.
The single amplifiers MCP6G01, MCP6G01R,
MCP6G01U, and MCP6G03, are available in 5-pin
SOT-23 package and the dual amplifier MCP6G02, are
available in 8-pin SOIC and MSOP packages. The
quad amplifier MCP6G04 is available in 14-pin SOIC
and TSSOP packages. All parts are fully specified from
-40°C to +125°C.
Package Types
VOUT
VDD
GSEL
VIN
VSS
3
RF
RG
Gain Select
Logic
Gain
Switches
Resistor Ladder
(RLAD)
Gain
(V/V)
GSEL Voltage (Typ.)
(V)
1V
DD/2 (or open)
10 0
50 VDD
Note: VSS is assumed to be 0V
CS
(MCP6G03
only)
5MΩ
VIN
GSEL
VSS
VOUT
VDD
1
2
3
4
8
7
6
5
NC
NC
NC
GSELA
VOUTA
VINA
GSELC
VINC
1
2
3
4
14
13
12
11 VSS
VOUTC
GSELD
5
6
7
10
9
8
VDD
GSELB
VOUTD
VOUTB
VIND
VINB
MCP6G01
SOIC, MSOP
VINA
GSELA
VSS
GSELB
VOUTB
1
2
3
4
8
7
6
5
VDD
VINB
VOUTA
MCP6G02
SOIC, MSOP
MCP6G04
SOIC, TSSOP
VIN
GSEL
VSS
VOUT
VDD
1
2
3
4
8
7
6
5
CS
NC
NC
MCP6G03
SOIC, MSOP
VDD
1
2
3
5
4
VSS
VOUT
VIN GSEL
MCP6G01R
SOT-23-5
VSS
1
2
3
5
4
VDD
VIN
GSEL VOUT
MCP6G01U
SOT-23-5
VSS
1
2
3
5
4
VDD
VOUT
VIN GSEL
MCP6G01
SOT-23-5
110 µA Selectable Gain Amplifier
MCP6G01/1R/1U/2/3/4
DS22004B-page 2 © 2006 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Analog Input Pin (VIN)......................................±2mA
Analog Input (VIN) †† ..................... VSS –1.0VtoV
DD +1.0V
All other Inputs and Outputs........... VSS –0.3VtoV
DD +0.3V
Output Short Circuit Current...................................continuous
Current at Output and Supply Pins ................................ ±30 mA
Storage Temperature.....................................-65°C to +150°C
Junction Temperature.................................................. +150°C
ESD protection on all pins (HBM; MM) ................ ≥ 4 kV; 200V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.4 “Input Voltage and Current Limits”.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
VIN = (0.3V)/G, RL= 100 kΩ to VDD/2, GSEL = VDD/2, and CS is tied low.
Parameters Sym Min Typ Max Units Conditions
Amplifier Inputs (VIN)
Input Offset Voltage VOS –4.5 ±1.0 +4.5 mV G = +1
— ±1.0 — mV G = +10, +50
Input Offset Voltage Drift ΔVOS/ΔTA— ±2 — µV/°C G = +1, TA = -40°C to +125°C
Power Supply Rejection Ratio PSRR 65 80 — dB G = +1 (Note 1)
Input Bias Current IB—1— pA
Input Bias Current at IB—30— pAT
A = +85°C
Temperature IB— 1000 5000 pA TA = +125°C
Input Impedance ZIN —10
13||6 — Ω||pF
Amplifier Gain
Nominal Gains G — 1 to 50 — V/V +1, +10 or +50
DC Gain Error G = +1 gE–0.3 — +0.3 % VOUT ≈ 0.3V to VDD −0.3V
G ≥ +10 gE–1.0 — +1.0 % VOUT ≈ 0.3V to VDD −0.3V
DC Gain Drift G = +1 ΔG/ΔTA—±1—ppm/°CT
A = -40°C to +125°C
G ≥ +10 ΔG/ΔTA—±4—ppm/°CT
A = -40°C to +125°C
Ladder Resistance (Note 1)
Ladder Resistance RLAD 200 350 500 kΩ
Ladder Resistance
across Temperature
ΔRLAD/ΔTA— –1800 — ppm/°C TA = -40°C to +125°C
Amplifier Output
DC Output Non-linearity G = +1 VONL –0.2 — +0.2 % of FSR VOUT = 0.3V to VDD –0.3V,
VDD =1.8V
VONL –0.1 — +0.1 % of FSR VOUT = 0.3V to VDD –0.3V,
VDD =5.5V
DC Output Non-linearity, G = +10, +50 VONL –0.05 — +0.05 % of FSR VOUT = 0.3V to VDD –0.3V
Maximum Output Voltage Swing VOH, VOL VSS+10 — VDD–10 mV G = +1; 0.3V output overdrive
VOH, VOL VSS+10 — VDD–10 mV G ≥ +10; 0.5V output overdrive
Short Circuit Current ISC —±7— mAV
DD = 1.8V
ISC —±20— mAV
DD = 5.5V
Note 1: RLAD (RF+RG in Figure 4-1) connects VSS, VOUT
, and the inverting input of the internal amplifier. Thus, VSS is coupled
to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the VSS pin be tied directly
to ground to avoid noise problems.
2: IQ includes current in RLAD (typically 0.6 µA at VOUT = 0.3V), and excludes digital switching currents.
© 2006 Microchip Technology Inc. DS22004B-page 3
MCP6G01/1R/1U/2/3/4
Power Supply
Supply Voltage VDD 1.8 — 5.5 V
Quiescent Current per Amplifier IQ60 110 170 µA IO = 0 (Note 2)
DC ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
VIN = (0.3V)/G, RL= 100 kΩ to VDD/2, GSEL = VDD/2, and CS is tied low.
Parameters Sym Min Typ Max Units Conditions
Note 1: RLAD (RF+RG in Figure 4-1) connects VSS, VOUT
, and the inverting input of the internal amplifier. Thus, VSS is coupled
to the internal amplifier and the PSRR spec describes PSRR+ only. It is recommended that the VSS pin be tied directly
to ground to avoid noise problems.
2: IQ includes current in RLAD (typically 0.6 µA at VOUT = 0.3V), and excludes digital switching currents.
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA= +25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V,
VIN = (0.3V)/G, RL= 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters Sym Min Typ Max Units Conditions
Frequency Response
-3dB Bandwidth BW — 900 — kHz G = +1, VOUT < 100 mVP-P (Note 1)
BW — 350 — kHz G = +10, VOUT < 100 mVP-P (Note 1)
BW — 250 — kHz G = +50, VOUT < 100 mVP-P (Note 1)
Gain Peaking GPK — 0.3 — dB G = +1; VOUT < 100 mVP-P
GPK — 0 — dB G = +10, VOUT < 100 mVP-P
GPK — 0.7 — dB G = +50; VOUT < 100 mVP-P
Total Harmonic Distortion plus Noise
f = 1 kHz, G = +1 V/V THD+N — 0.0029 — % VOUT = 1.75V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
f = 1 kHz, G = +10 V/V THD+N — 0.18 — % VOUT = 2.5V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
f = 1 kHz, G = +50 V/V THD+N — 1.3 — % VOUT = 2.5V ± 1.4VPK, VDD = 5.0V,
BW = 80 kHz
Step Response
Slew Rate SR — 0.50 — V/µs G = 1
SR — 2.3 — V/µs G = 10
SR — 4.5 — V/µs G = 50
Noise
Input Noise Voltage Eni —9—µV
P-P f = 0.1 Hz to 10 Hz (Note 2)
Eni —50—µV
P-P f = 0.1 Hz to 30 kHz (Note 2)
Input Noise Voltage Density eni —38—nV/√Hz G = +1 V/V, f = 10 kHz (Note 2)
eni —46—nV/√Hz G = +10 V/V, f = 10 kHz (Note 2)
eni —41—nV/√Hz G = +50 V/V, f = 10 kHz (Note 2)
Input Noise Current Density ini —4—fA/√Hz f = 10 kHz
Note 1: See Table 4-1 for a list of typical numbers and Figure 2-31 for the frequency response versus gain.
2: Eni and eni include ladder resistance thermal noise.
MCP6G01/1R/1U/2/3/4
DS22004B-page 4 © 2006 Microchip Technology Inc.
DIGITAL ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA= 25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL= 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VCSL 0 — 0.2VDD VCS = 0V
CS Input Current, Low ICSL —30—pACS = 0V
CS High Specifications
CS Logic Threshold, High VCSH 0.8VDD —V
DD VCS = VDD
CS Input Current, High ICSH —0.8—µACS = VDD = 5.5V
Quiescent Current per Amplifier,
Shutdown Mode (IDD)
IDD_SHDN — 120 — pA CS = VDD, MCP6G03
Quiescent Current per Amplifier,
Shutdown Mode (ISS) (Note 3)
ISS_SHDN — –2.4 — µA CS = VDD = 1.8V, MCP6G03
ISS_SHDN — –7.2 — µA CS = VDD = 5.5V, MCP6G03
CS Dynamic Specifications
Input Capacitance CCS —10—pF
Input Rise/Fall Times tCSRF —— 2µs (Note 2)
CS Low to Amplifier Output High
Turn-on Time
tCSON — 40 — µs G = +1 V/V, VDD = 1.8V, VIN = 0.9VDD
CS = 0.2VDD to VOUT = 0.8VDD
tCSON — 7 — µs G = +1 V/V, VDD = 5.5V, VIN = 0.9VDD
CS = 0.2VDD to VOUT = 0.8VDD
CS High to Amplifier Output High-Z
Turn-off Time
tCSOFF —30 —µs
G = +1 V/V, VIN = VDD/2,
CS = 0.8VDD to VOUT = 0.1VDD/2
Hysteresis VCSHY —0.40— VV
DD = 1.8V
VCSHY —0.55— VV
DD = 5.5V
GSEL Specifications (Note 1)
GSEL Logic Threshold, Low VGSL 0.15VDD — 0.35VDD V Gain changes between 1 and 10,
IGSEL = 0
GSEL Logic Threshold, High VGSH 0.65VDD — 0.85VDD V Gain changes between 1 and 50,
IGSEL = 0
GSEL Input Current, Low IGSL –10 — –1.5 µA GSEL voltage = 0.3VDD
GSEL Input Current, High IGSH +1.5 — +10 µA GSEL voltage = 0.7VDD
GSEL Dynamic Specifications (Note 1)
Input Capacitance CGSEL —8—pF
Input Rise/Fall Times tGSRF ——10 µs (Note 2)
Hysteresis VGSHY —45—mVV
DD = 1.8V
VGSHY —95—mVV
DD = 5.5V
GSEL Low to Valid Output Time,
G = +1 to +10 Select
tGSL1 —10 —µs
VIN = 150 mV,
GSEL = 0.25VDD to VOUT = 1.37V
GSEL Middle to Valid Output Time,
G = +10 to +1 Select
tGSM10 —12 —µs
VIN = 150 mV,
GSEL = 0.25VDD to VOUT = 0.28V
GSEL High to Valid Output Time,
G = +1 to +50 Select
tGSH1 —9—µs
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 1.35V
GSEL Middle to Valid Output Time,
G = +50 to +1 Select
tGSM50 —8—µs
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 0.18V
Note 1: GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high.
2: Not tested in production. Set by design and characterization.
3: ISS_SHDN includes the current through the CS pin, RL and RLAD, and excludes digital switching currents. The block dia-
gram on the from page shows these current paths (through VSS).
© 2006 Microchip Technology Inc. DS22004B-page 5
MCP6G01/1R/1U/2/3/4
FIGURE 1-1: Gain Select Timing Diagram.
GSEL High to Valid Output Time,
G = +10 to +50 Select
tGSH10 —12 —µs
VIN = 30 mV,
GSEL = 0.75VDD to VOUT = 1.38V
GSEL Low to Valid Output Time,
G = +50 to +10 Select
tGSL50 —9—µs
VIN = 30 mV,
GSEL = 0.25VDD to VOUT = 0.42V
DIGITAL ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, TA= 25°C, VDD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL= 100 kΩ to VDD/2, CL = 60 pF, GSEL = VDD/2, and CS is tied low.
Parameters Sym Min Typ Max Units Conditions
Note 1: GSEL is a tri-level input pin. The gain is 10 when its voltage is low, 1 when it is at mid-suppy, and 50 when it is high.
2: Not tested in production. Set by design and characterization.
3: ISS_SHDN includes the current through the CS pin, RL and RLAD, and excludes digital switching currents. The block dia-
gram on the from page shows these current paths (through VSS).
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.8V to +5.5V, and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA–40 — +125 °C
Operating Temperature Range TA–40 — +125 °C (Note 1)
Storage Temperature Range TA–65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W
Thermal Resistance, 8L-SOIC θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 14L-SOIC θJA — 120 — °C/W
Thermal Resistance, 14L-TSSOP θJA — 100 — °C/W
Note 1: The MCP6G01/1R/1U/2/3/4 family of SGAs operates over this temperature range, but operation must not cause TJ to
exceed Maximum Junction Temperature (+150°C).
GSEL
VOUT
tGSL1
0.15V
1.50V
VIN 0.150V 0.030V
0.15V
tGSM10
0.03V
1.50V
tGSH1
0.03V
tGSM50
0.30V
1.50V
tGSH10
0.30V
tGSL50
MCP6G01/1R/1U/2/3/4
DS22004B-page 6 © 2006 Microchip Technology Inc.
FIGURE 1-2: SGA Chip Select Timing Diagram.
CS
tCSOFF
VOUT
tCSON
High-Z High-Z
IDD 120 pA (typ.)
110 µA (typ.)
0.9VDD
ISS
–VDD / 7 MΩ(typ.)
–110 µA (typ.)
ICS 30 pA (typ.)
VDD / 7 MΩ(typ.)
© 2006 Microchip Technology Inc. DS22004B-page 7
MCP6G01/1R/1U/2/3/4
1.1 DC Output Voltage Specs / Model
1.1.1 IDEAL MODEL
The ideal SGA output voltage (VOUT) is (see Figure 1-3):
EQUATION 1-1:
This equation holds when there are no gain or offset
errors.
1.1.2 LINEAR MODEL
The SGA’s linear region of operation is modeled by the
line VO_LIN shown in Figure 1-3. VO_LIN includes offset
and gain errors, but does not include non-linear effects.
EQUATION 1-2:
This line’s endpoints are 0.3V from the supply rails
(VO_ID = 0.3V and VDD – 0.3V). The gain error and
input offset voltage specifications (in the electrical
specifications) relate to Figure 1-3 as follows:
EQUATION 1-3:
The input offset specification describes VOS at
G=+1V/V.
The DC Gain Drift (ΔG/ΔTA) can be calculated from the
change in gE across temperature. This is shown in the
following equation:
EQUATION 1-4:
FIGURE 1-3: Output Voltage Model.
1.1.3 OUTPUT NON-LINEARITY
Figure 1-4 shows the Integral Non-Linearity (INL) of the
output voltage. INL is the output non-linearity error not
explained by VO_LIN:
EQUATION 1-5:
The output non-linearity specification (in the Electrical
Specifications, with units of % of FSR) is related to
Figure 1-4 by:
EQUATION 1-6:
Note that the Full Scale Range (FSR) is VDD –0.6V
(0.3V to VDD –0.3V).
Where:
G is the nominal gain
VO_ID GVIN
=
VREF VSS 0V==
VO_LIN G1gE
+()VIN
0.3V
G
------------VOS
+–
⎝⎠
⎛⎞
0.3V+=
VREF VSS 0V==
Where:
G is the nominal gain
gE is the gain error
VOS is the input offset voltage
gE100% V2V1
–
VDD 0.6V–
-----------------------------
⋅=
VOS
V1
G1gE
+()
-------------------------,= G+1=
Where:
V1VOUT VO_ID,–= VO_ID 0.3V=
V2VOUT VO_ID,–= VO_ID VDD 0.3V–=
GΔTA
Δ⁄ GgE
Δ
TA
Δ
----------,⋅=in units of V/V/°C
GΔTA
Δ⁄ 100% gE
Δ
TA
Δ
----------,⋅=in units of %/°C
0
0
0.3
VDD-0.3
VDD
VOUT
VOUT (V)
VIN (V)
0.3 VDD-0.3 VDD
GGG
V1
VO_ID
VO_LIN
V2
INL VOUT VO_LIN
–=
VONL 100% max V3V4
,()
VDD 0.6V–
-------------------------------
⋅=
V3max INL–()=
Where:
V4max INL()=
MCP6G01/1R/1U/2/3/4
DS22004B-page 8 © 2006 Microchip Technology Inc.
FIGURE 1-4: Output Voltage INL.
0
INL (V)
VIN (V)
0.3 VDD-0.3 VDD
GGG
0
V3
V4
© 2006 Microchip Technology Inc. DS22004B-page 9
MCP6G01/1R/1U/2/3/4
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-1: DC Gain Error, G = +1.
FIGURE 2-2: DC Gain Error, G ≥+10.
FIGURE 2-3: Input Offset Voltage.
FIGURE 2-4: DC Gain Drift, G = +1.
FIGURE 2-5: DC Gain Drift, G ≥+10.
FIGURE 2-6: Input Offset Voltage Drift.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
5%
10%
15%
20%
25%
30%
-0.28
-0.24
-0.20
-0.16
-0.12
-0.08
-0.04
0.00
0.04
0.08
0.12
0.16
0.20
0.24
0.28
DC Gain Error (%)
Percentage of Occurrences
2460 Samples
G = +1
0%
2%
4%
6%
8%
10%
12%
14%
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
DC Gain Error (%)
Percentage of Occurrences
4916 Samples
G ≥ +10
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
-4.5
-3.5
-2.5
-1.5
-0.5
0.5
1.5
2.5
3.5
4.5
Input Offset Voltage (mV)
Percentage of Occurrences
2460 Samples
G = +50
G = +10
G = +1
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
-5
-4
-3
-2
-1
0
1
2
3
4
5
DC Gain Drift (ppm/°C)
Percentage of Occurrences
2459 Samples
G = +1
TA = -40 to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
DC Gain Drift (ppm/°C)
Percentage of Occurrences
4912 Samples
G ≥ +10
TA = -40 to +125°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
1612 Samples
G = +1, +10, +50
TA = -40 to +125°C
MCP6G01/1R/1U/2/3/4
DS22004B-page 10 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-7: The MCP6G01/1R/1U/2/3/4
family shows no phase reversal under overdrive.
FIGURE 2-8: PSRR vs. Temperature.
FIGURE 2-9: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-10: Crosstalk vs. Frequency,
with G = 50 (circuit in Figure 4-7).
FIGURE 2-11: PSRR vs. Frequency.
FIGURE 2-12: Quiescent Current vs.
Supply Voltage.
-1
0
1
2
3
4
5
6
0.0E+00 1.0E-03 2.0E-03 3.0E-03 4.0E-03 5.0E-03 6.0E-03 7.0E-03 8.0E-03 9.0E-03 1.0E-02
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +1 V/V
VIN
VOUT
70
80
90
100
110
120
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR (dB)
10
100
1000
10000
0.1 1 10 100 1000 10000 10000
0Frequency (Hz)
Input Noise Voltage Density
(nV/
Hz)
1k 10k 100k1 10 1000.1
G = +1
= +10
= +50
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1.E+03 1.E+04 1.E+05
Frequency (Hz)
Crosstalk, Input Referred
(dB)
1k 100k10k
VDD = 5.0V
G = 50 V/V
RS = 0 Ω
RS= 1 MΩ
RS= 100 kΩ
RS= 10 kΩ
20
30
40
50
60
70
80
90
100 1000 10000 100000
Frequency (Hz)
Power Supply Rejection Ratio
(dB)
Input Referred
G = 1
G = 10
G = 50
VDD = 1.8V
VDD = 5.5V
100 1k 10k 100k
0
20
40
60
80
100
120
140
160
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Quiescent Current (mA)
TA = +25°C
TA = –40°C
TA = +125°C
TA = +85°C
© 2006 Microchip Technology Inc. DS22004B-page 11
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-13: Quiescent Current (ISS) in
Shutdown Mode vs. Supply Voltage.
FIGURE 2-14: Input Bias Current vs.
Temperature.
FIGURE 2-15: Input Bias Current vs. Input
Voltage.
FIGURE 2-16: Quiescent Current (ISS) in
Shutdown Mode vs. Temperature.
FIGURE 2-17: Input Bias Current vs. Input
Voltage.
FIGURE 2-18: Output Short Circuit Current
vs. Supply Voltage.
-8
-7
-6
-5
-4
-3
-2
-1
0
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Quiescent Current in
Shutdown (µA)
In Shutdown Mode
VIN = VDD/2
CS = VDD
ISS_SHDN
1
10
100
1,000
55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias Current (pA)
VDD = 5.5V
VIN = VDD
1
10
100
1,000
10,000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Input Voltage (V)
Input Bias Current (pA)
TA = +85°C
VDD = 5.5V
TA = +125°C
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Quiescent Current in
Shutdown (µA)
In Shutdown Mode
VIN = VDD/2
VDD = 5.5V
VDD = 1.8V
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Output Short Circuit Current
Magnitude (mA)
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
MCP6G01/1R/1U/2/3/4
DS22004B-page 12 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-19: Output Voltage Error vs.
Ideal Output Voltage, with VDD =1.8V.
FIGURE 2-20: Output Voltage Headroom
vs. Output plus Ladder Current (circuit in
Figure 4-4).
FIGURE 2-21: Output Impedance vs.
Frequency.
FIGURE 2-22: Output Voltage Error vs.
Ideal Output Voltage, with VDD =5.5V.
FIGURE 2-23: Output Voltage Headroom
vs. Temperature.
FIGURE 2-24: Ladder Resistance Drift.
-3
-2
-1
0
1
2
3
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Ideal Output Voltage; GVIN (V)
Output Error, Input Referred;
VOUT/G – VIN (mV)
VDD = +1.8V
Representative Part
G = +1
G = +10
G = +50
1
10
100
1000
0.01 0.1 1 10
Output Current Magnitude (mA)
Output Voltage Headroom;
VDD – VOH and VOL – VSS (mV)
VDD = +5.5V
VDD – VOH
VDD = +1.8V
VOL – VSS
1.E+02
1.E+03
1.E+04
1.E+05
1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Output Impedance Magnitude
(ȍ)
G = 50
= 10
= 1
100
1k
100k
10k
1M100k10k 10M
-3
-2
-1
0
1
2
3
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Ideal Output Voltage; GVIN (V)
Output Error, Input Referred;
VOUT/G – VIN (mV)
VDD = +5.5V
Representative Part
G = +1
G = +10
G = +50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Output Voltage Headroom;
VDD–VOH and VOL–VSS (mV)
VDD = 5.5V: VDD–VOH
VOL–VSS
VDD = 1.8V: VOL–VSS
VDD–VOH
0%
2%
4%
6%
8%
10%
12%
14%
-2000
-1900
-1800
-1700
-1600
-1500
Ladder Resistance Drift (ppm/°C)
Percentage of Occurrences
1228 Samples
TA = -40 to +125°C
© 2006 Microchip Technology Inc. DS22004B-page 13
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-25: Slew Rate vs. Temperature,
with G = +1.
FIGURE 2-26: Slew Rate vs. Temperature,
with G = +10.
FIGURE 2-27: Bandwidth vs. Resistive
Load.
FIGURE 2-28: Output Voltage Swing vs.
Frequency.
FIGURE 2-29: Slew Rate vs. Temperature,
with G = +50.
FIGURE 2-30: Bandwidth vs. Capacitive
Load.
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
G = +1 V/V
Falling Edge
Rising Edge
VDD = 1.8V
VDD = 5.5V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
G = +10 V/V
Falling Edge
Rising Edge
VDD = 5.5V
1.E+04
1.E+05
1.E+06
1.E+02 1.E+03 1.E+04 1.E+05
Resistive Load (ȍ)
Bandwidth (Hz)
G = +1
G = +10
G = +50
10k
1M
100k
10k 100k100 1k
0.1
1
10
1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Output Voltage Swing (V P-P)
VDD = 1.8V
VDD = 5.5V
G = +1
G = +10
G = +50
1k 100k 1M10k
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
G = +50 V/V
Falling Edge
Rising Edge
VDD = 5.5V
1.E+05
1.E+06
10 100 1000
Capacitive Load (pF)
Bandwidth (Hz)
100k
1M
G = +10
G = +50
G = +1
MCP6G01/1R/1U/2/3/4
DS22004B-page 14 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-31: Gain vs. Frequency.
FIGURE 2-32: Small Signal Pulse
Response.
FIGURE 2-33: THD plus Noise vs.
Frequency, VOUT = 2.8 VP-P
.
FIGURE 2-34: Gain Peaking vs. Capacitive
Load.
FIGURE 2-35: Large Signal Pulse
Response.
FIGURE 2-36: THD plus Noise vs.
Frequency, VOUT = 4.0 VP-P
.
-40
-30
-20
-10
0
10
20
30
40
1.E+04 1.E+05 1.E+06 1.E+07
Frequency (Hz)
Gain (dB)
G = +1
100k 1M 10M10k
G = +50
G = +10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00
Time (5 µs/div)
Output Voltage
(20 mV/div)
0
0
0
1
1
1
1
1
Normalized Input
Voltage (100 mV/div)
VDD = +5.0V
VOUT
G = +50
G = +10
G = +1
GVIN
0.001
0.01
0.1
1
10
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
THD + Noise (%)
Measurement BW = 80 kHz
100 1k 100k10k
G = +10
G = +1
G = +50
VOUT = 2.8VP-P
VDD = 5.0V
0
1
2
3
4
5
6
7
10 100 1000
Capacitive Load (pF)
Gain Peaking (dB)
G = +1
G = +10
G = +50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00
Time (5 µs/div)
Normalized Input Voltage,
Output Voltage (V)
VDD = +5.0V
GVI
VOUT
G = +1
G = +10
G = +50
0.001
0.01
0.1
1
10
1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
THD + Noise (%)
VOUT = 4 VP-P
VDD = 5.0V
100 1k 100k10k
G = +10
G = +1
G = +50
Measurement BW = 80 kHz
© 2006 Microchip Technology Inc. DS22004B-page 15
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-37: THD plus Noise vs. Supply
Voltage.
FIGURE 2-38: THD plus Noise vs. Output
Swing.
FIGURE 2-39: Gain Select Timing, with
Gain = 1 and 10.
FIGURE 2-40: THD plus Noise vs. Load
Resistance.
FIGURE 2-41: Gain Select Timing, with
Gain = 1 and 50.
FIGURE 2-42: Gain Select Timing, with
Gain = 1 and 10.
0.001
0.01
0.1
1
10
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
THD + Noise (%)
G = +1
G = +10
G = +50
VOUT = 0.8VDD
f = 1 kHz
Measurement BW = 80 kHz
0.001
0.01
0.1
1
10
110
Output Swing (VP-P)
THD + Noise (%)
G = +1
G = +10
G = +50
Measurement BW = 80 kHz
VDD = 5.0V
f = 1 kHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 102030405060708090100
Time (10 µs/div)
Output Voltage (V)
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
Gain Select Voltage (V)
0
GSEL
(G = +1)
(G = +10) (G = +10)
5
VDD = 5.0V
VIN = 0.15V
VOUT
0.001
0.01
0.1
1
10
1.E+03 1.E+04 1.E+05 1.E+06
Load Resistance (Ω)
THD + Noise (%)
G = +1
G = +10
G = +50
f = 1 kHz
VDD = 5.0V
1k 10k 100k 1M
Measurement BW = 80 kHz
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 102030405060708090100
Time (10 µs/div)
Output Voltage (V)
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
Gain Select Voltage (V)
0GSEL
(G = +1)
(G = +50)
(G = +1)
5
VDD = 5.0V
VIN = 0.030V
VOUT
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0 102030405060708090100
Time (10 µs/div)
Output Voltage (V)
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
Gain Select Voltage (V)
0
GSEL
(G = +10)
(G = +50)
(G = +10)
5
VDD = 5.0V
VIN = 0.030V
VOUT
MCP6G01/1R/1U/2/3/4
DS22004B-page 16 © 2006 Microchip Technology Inc.
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-43: Output Voltage vs. Chip
Select, with VDD =1.8V.
FIGURE 2-44: GSEL Pin Current vs. GSEL
Voltage, with VDD =1.8V.
FIGURE 2-45: GSEL Current, with GSEL
Voltage of 0.3VDD.
FIGURE 2-46: Output Voltage vs. Chip
Select, with VDD =5.0V.
FIGURE 2-47: GSEL Pin Current vs. GSEL
Voltage, with VDD =5.5V.
FIGURE 2-48: GSEL Current, with GSEL
Voltage of 0.7VDD.
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Time (20 µs/div)
Output Voltage (mV)
Chip Select Voltage (V)
1.8
0
VOUT is "ON"
CS
VDD = 1.8V
VIN = 0.9VDD
Shutdown
G = 1
G = 10
G = 50
-10
-8
-6
-4
-2
0
2
4
6
8
10
0.00.20.40.60.81.01.21.41.61.8
GSEL Voltage (V)
GSEL Current (µA)
TA = +25°C
= +85°C
= +125°C
VDD = 1.8V
TA = +125°C
= +85°C
= +25°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
22%
-7.0
-6.6
-6.2
-5.8
-5.4
-5.0
-4.6
-4.2
-3.8
-3.4
-3.0
GSEL Current (µA)
Percentage of Occurrences
1228 Samples
GSEL = 0.3VDD
VDD = 1.8V
VDD = 5.5V
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Time (20 µs/div)
Output Voltage (mV)
Chip Select Voltage (V)
5
0
VOUT is "ON"
CS
VDD = 5.0V
VIN = 0.9VDD
Shutdown
G = 1
G = 10
G = 50
-10
-8
-6
-4
-2
0
2
4
6
8
10
0.00.51.01.52.02.53.03.54.04.55.05.5
GSEL Voltage (V)
GSEL Current (µA)
VDD = 5.5V
TA= +25°C
= +85°C
= +125°C
TA = +125°C
= +85°C
= +25°C
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
3.0
3.4
3.8
4.2
4.6
5.0
5.4
5.8
6.2
6.6
7.0
GSEL Current (µA)
Percentage of Occurrences
1228 Samples
GSEL = 0.7VDD
VDD = 5.5VVDD = 1.8V
© 2006 Microchip Technology Inc. DS22004B-page 17
MCP6G01/1R/1U/2/3/4
Note: Unless otherwise indicated, TA=+25°C, V
DD = +1.8V to +5.5V, VSS = GND, G = +1 V/V, VIN = (0.3V)/G,
RL=100kΩ to VDD/2, CL= 60 pF, GSEL = VDD/2, and CS is tied low.
FIGURE 2-49: GSEL Trip Point between
G = +1 and G = +10.
FIGURE 2-50: GSEL Trip Point between
G = +1 and G = +50.
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0.213
0.218
0.222
0.227
0.231
0.236
0.241
0.245
0.250
0.255
0.259
Normalized GSEL Trip Point; VGSEL/VDD
Percentage of Occurrences
1227 Samples
G = +1 to +10
VDD = 1.8V VDD = 5.5V
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
0.736
0.741
0.745
0.750
0.755
0.759
0.764
0.768
0.773
Normalized GSEL Trip Point; VGSEL/VDD
Percentage of Occurrences
1228 Samples
G = +1 to +50
VDD = 1.8VVDD = 5.5V
MCP6G01/1R/1U/2/3/4
DS22004B-page 18 © 2006 Microchip Technology Inc.
3.0 PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
3.1 Analog Output
The output pin (VOUT) is a low impedance voltage
source. The selected gain (G) and input voltage (VIN)
determine its value.
3.2 Analog Input
The analog inputs (VIN) are high impedance CMOS
inputs with low bias currents. Only three fixed, non-
inverting gains are available through these inputs.
3.3 Power Supply (VSS and VDD)
The Positive Power Supply Pin (VDD) is 1.8V to 5.5V
higher than the Negative Power Supply Pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground, and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These parts need
to use a bulk capacitor (typically 1.0 µF to 10 µF) within
100 mm of the VDD pin; it can be shared with nearby
analog parts.
3.4 Digital Inputs
The Chip Select (CS) input is a Schmitt-triggered,
CMOS logic input.
The Gain Select (GSEL) inputs are tri-level digital
inputs. They function similar to normal logic inputs at
low (G = +10) and high voltages (G = +50). The pin can
also be set to mid-supply (G = +1) by a low impedance
source, or by leaving this pin open.
MCP6G01
(SOIC,
MSOP)
MCP6G01
(SOT-23-5)
MCP6G01R
(SOT-23-5)
MCP6G01U
(SOT-23-5) MCP6G03 Symbol Description
61 1 46 V
OUT Analog Output
2 4 4 3 2 GSEL Gain Select Input
33 3 13 V
IN Analog Input
75 2 57 V
DD Positive Power Supply
42 5 24 V
SS Negative Power Supply
—— — —8 CS
Chip Select
1,5,8 — — — 1,5 NC No Internal Connection
MCP6G02 MCP6G04 Symbol Description
11V
OUTA Analog Output A
2 2 GSELAGain Select Input (SGA A)
33 V
INA Analog Input A
84 V
DD Positive Power Supply
55 V
INB Analog Input B
6 6 GSELBGain Select Input (SGA B)
77V
OUTB Analog Output B
—8V
OUTC Analog Output C
— 9 GSELCGain Select Input (SGA C)
—10 V
INC Analog Input C
411 V
SS Negative Power Supply
—12 V
IND Analog Input D
— 13 GSELDGain Select Input (SGA D)
—14V
OUTD Analog Output D
© 2006 Microchip Technology Inc. DS22004B-page 19
MCP6G01/1R/1U/2/3/4
4.0 APPLICATIONS INFORMATION
The MCP6G01/1R/1U/2/3/4 family of Selectable Gain
Amplifiers (SGA) is based on simple analog building
blocks (see Figure 4-1). Each of these blocks will be
explained in more detail in the following subsections.
FIGURE 4-1: SGA Block Diagram.
4.1 Internal Op Amp
The internal op amp gives the right combination of
bandwidth, accuracy, and flexibility.
4.1.1 COMPENSATION CAPACITORS
The internal op amp has three compensation
capacitors (comp. caps.) connected to a switching
network. They are selected to give good small signal
bandwidth at high gains, and good slew rate (full power
bandwidth) at low gains. The change in bandwidth as
gain changes is between 250 and 900 kHz. Refer to
Table 4-1 for more information.
TABLE 4-1: GAIN VS. INTERNAL
COMPENSATION
CAPACITOR
4.1.2 RAIL-TO-RAIL INPUTS
The input stage of the internal op amp uses two
differential input stages in parallel; one operates at low
VIN (input voltage), while the other operates at high VIN.
With this topology, the internal inputs can operate to
0.3V past either supply rail, although the output will clip
the signal before that happens.
The inputs need to be kept within a smaller range to
prevent output clipping. The input offset voltage also
reduces the range; most designs will need the following
for normal operation:
EQUATION 4-1:
The transition between the two input stage occurs
when VIN ≈VDD – 1.1V (see Figure 2-19 and Figure 2-
22). For the best distortion and gain linearity, avoid this
region of operation.
4.1.3 PHASE REVERSAL
The MCP6G01/1R/1U/2/3/4 amplifier family is
designed with CMOS input devices. It is designed to
not exhibit phase inversion when the input pins exceed
the supply voltages. Figure 2-7 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
Gain
(V/V)
GSEL Voltage (Typ.)
(V)
1V
DD/2 (or open)
10 0
50 VDD
Note: VSS is assumed to be 0V
VOUT
VDD
GSEL
VIN
VSS
3
RF
RG
Gain Select
Logic
Gain
Switches
Resistor Ladder
(RLAD)
CS
(MCP6G03
only)
5MΩ
Gain
(V/V)
Internal
Comp.
Cap.
G x BW
(MHz)
Typ.
SR
(V/µs)
Typ.
FPBW
(kHz)
Typ.
BW
(kHz)
Typ.
1 Large 0.90 0.50 29 900
10 Medium 3.5 2.3 133 350
50 Small 12.5 4.5 260 250
Note 1: Changing the compensation capacitor does not
change the DC performance (e.g., VOS).
2: G x BW is approximately the Gain Bandwidth
Product of the internal op amp.
3: FPBW is the Full Power Bandwidth at
VDD = 5.5V, which is based on slew rate (SR).
4: BW is the closed-loop, small signal –3 dB
bandwidth.
VOL
G
----------VOS VIN
VOH
G
-----------VOS
–<<+
MCP6G01/1R/1U/2/3/4
DS22004B-page 20 © 2006 Microchip Technology Inc.
4.1.4 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specified limits.
FIGURE 4-2: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN pins (see Section
“Absolute Maximum Ratings †” at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN) from going too far below ground, and the resistor
R1 limits the possible current drawn out of the input pin.
Diode D1 prevents the input pin (VIN) from going too far
above VDD. When implemented as shown, resistor R1
also limits the current through D1.
FIGURE 4-3: Protecting the Analog
Inputs.
It is also possible to connect the diode to the left of the
resistor R1. In this case, the current through the diode
D1 needs to be limited by some other mechanism. The
resistor then serves as in-rush current limiter; the DC
current into the input pin (VIN) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-17. Applications that are
high impedance may need to limit the useable voltage
range.
4.1.5 RAIL-TO-RAIL OUTPUT
The maximum output voltage swing is the maximum
swing possible under a particular amplifier load current.
The amplifier load current is the sum of the external
load current (IOUT) and the current through the ladder
resistance (ILAD); see Figure 4-4.
EQUATION 4-2:
FIGURE 4-4: Amplifier Load Current.
See Figure 2-20 for the typical output headroom
(VDD – VOH or VOL – VSS) as a function of amplifier
load current.The specification table states the output
can reach within 10 mV of either supply rail when
RL= 100 kΩ.
4.2 Resistor Ladder
The resistor ladder shown in Figure 4-1
(RLAD =R
F+R
G) sets the gain. Placing the gain
switches in series with the inverting input reduces the
parasitic capacitance, distortion, and gain mismatch.
RLAD is an additional load on the output of the SGA and
causes additional current draw from the supplies.
When CS is high, the SGA is shut down (low power).
RLAD is still attached to the VOUT and VSS pins. Thus,
these pins and the internal amplifier’s inverting input
are all connected through RLAD and the output is not
high-Z (unlike the internal op amp).
RLAD contributes to the output noise; see Figure 2-9.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN
VSS
to the rest of
Input
Stage the amplifier
V1MCP6G0X
R1
VDD
D1
R1≥VSS – (minimum expected V1)
2mA
VOUT
VIN
Where:
Amplifier Load Current IOUT ILAD
+=
ILAD
VOUT VSS
–()
RLAD
---------------------------------=
VOUT
VSS
RLAD
IOUT
ILAD
MCP6G0X
VIN
© 2006 Microchip Technology Inc. DS22004B-page 21
MCP6G01/1R/1U/2/3/4
RLAD is intended to be driven at the VSS pin by a low
impedance voltage source. The power supply driving
the VSS pin should have an output impedance less than
0.1Ω to maintain reasonable gain accuracy.
4.3 MCP6G03 Chip Select (CS)
The MCP6G03 is a single amplifier with chip select
(CS). When CS is high, the internal op amp is shut
down and its output placed in a high-Z state. The
resistive ladder is always connected between VSS and
VOUT
; even in shutdown. This means that the output
resistance will be 350 kΩ (typ.), with a path for output
signals to appear at the input. The supply current at
VSS includes the current through the load resistor and
ladder resistors; it also includes current from the CS pin
to VSS. When CS is low, the amplifier is enabled. If CS
is left floating, the amplifier may not operate properly.
Figure 1-2 and Figure 2-43 show how the output
voltage and supply current response to a CS pulse.
4.4 Gain Select (GSEL)
The amplifier can be set to the gains +1 V/V, +10 V/V,
and +50 V/V using one input pin (GSEL). At the same
time, different compensation capacitors are selected to
optimize the bandwidth vs. slew rate trade-off (see
Tabl e 4 - 1 ). Ta bl e 4- 2 shows how to change the gain
using a GPIO pin on a microcontroller and Tab l e 4 - 3
shows how to hard wire the gain (i.e., using PCB
wiring).
TABLE 4-2: MCU DRIVEN GAIN
SELECTION
TABLE 4-3: HARD WIRED GAIN
SELECTION
4.5 Capacitive Load and Stability
Large capacitive loads can cause stability problems
and reduced bandwidth for the MCP6G01/1R/1U/2/3/4
family of SGAs (Figure 2-30 and Figure 2-34). As the
load capacitance increases, there is a corresponding
increase in frequency response peaking and step
response overshoot and ringing. This happens
because a large load capacitance decreases the
internal amplifier’s phase margin and bandwidth.
When driving large capacitive loads with these SGAs
(i.e., > 60 pF), a small series resistor at the output
(RISO in Figure 4-5) improves the internal amplifier’s
stability by making the load resistive at higher
frequencies. The bandwidth will be generally lower
than the bandwidth with no capacitive load.
FIGURE 4-5: SGA Circuit for Large
Capacitive Loads.
Figure 4-6 gives recommended RISO values for
different capacitive loads. After selecting RISO for your
circuit, double check the resulting frequency response
peaking and step response overshoot on the bench.
Modify RISO’s value until the response is reasonable at
all gains.
Gain MCU Pin’s State
+1 V/V Output PIC’s VREF at VDD/2
Digital Output High-Z (Notes 1)
Output VDD/2 PWM signal (Notes 2)
+10 V/V Digital Output driven Low
+50 V/V Digital Output driven High
Note 1: See Section 4.8.1 “Driving the Gain
Select Pin with a Microcontroller GPIO
Pin”.
2: See Section 4.8.2 “Driving the Gain
Select Pin with a PWM Signal”
Selected Gain Possible GSEL Drivers
+1 V/V Open Circuit (Note 1)
Low impedance source at VDD/2
+10 V/V Tied to GND (0V)
+50 V/V Tied to VDD
Note 1: The GSEL pin floats to mid-supply
(VDD/2); a bypass capacitor may be
needed.
VIN VOUT
MCP6G0X
RISO
CL
MCP6G01/1R/1U/2/3/4
DS22004B-page 22 © 2006 Microchip Technology Inc.
FIGURE 4-6: Recommended RISO.
4.6 Layout Considerations
Good PC board layout techniques will help achieve the
performance shown in Section 1.0 “Electrical
Characteristics” and Section 2.0 “Typical
Performance Curves”. It will also help minimize
Electromagnetic Compatibility (EMC) issues.
Because the MCP6G01/1R/1U/2/3/4 SGAs’ frequency
response reaches unity gain at 10 MHz when G = 50, it
is important to use good PCB layout techniques. Any
parasitic coupling at high frequency might cause
undesired peaking. Filtering high frequency signals
(i.e., fast edge rates) can help.
4.6.1 COMPONENT PLACEMENT
Separate different circuit functions: digital from analog,
low speed from high speed, and low power from high
power. This will reduce crosstalk.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high frequency (low rise time)
signals.
4.6.2 SUPPLY BYPASS
Use a local bypass capacitor (0.01 µF to 0.1 µF) within
2 mm of the VDD pin for good, high frequency
performance. It must connect directly to ground.
Use a bulk bypass capacitor (i.e., 1.0 µF to 10 µF)
within 100 mm of the VDD pin. It needs to connect to
ground, and provides large, slow currents. This
capacitor may be shared with other nearby analog
parts.
Ground plane is important, and power plane(s) can
also be of great help. High frequency (e.g., multi-layer
ceramic capacitors), surface mount components
improve the supply’s performance.
4.6.3 INPUT SOURCE IMPEDANCE
The sources driving the inputs of the SGAs need to
have reasonably low source impedance at higher
frequencies. Figure 4-7 shows how the external source
resistance (RS), SGA package pin capacitance (CP1),
and SGA package pin-to-pin capacitance (CP2) form a
positive feedback voltage divider network. Feedback
may cause frequency response peaking and step
response overshoot and ringing.
FIGURE 4-7: Positive Feedback Path.
Figure 2-10 shows the crosstalk (referred to input) that
results when a hostile signal is connected to the other
inputs (e.g., VINB through VIND), and the input of
interest (e.g., VINA) has RS connected to GND. A gain
of +50 was chosen for this plot because it
demonstrates the worst-case behavior. Increasing RS
increases the crosstalk as expected. At a source
impedance of 10 MΩ, there is noticeable change in
behavior.
Most designs should use a source resistance (RS) no
larger than 10 MΩ. Careful attention to layout parasitics
and proper component selection will help minimize this
effect. When a source impedance larger than 10 MΩ
must be used, place a capacitor in parallel to CP1 to
reduce the positive feedback. This capacitor needs to
be large enough to overcome gain (or crosstalk)
peaking, yet small enough to allow a reasonable signal
bandwidth.
4.6.4 SIGNAL COUPLING
The input pins of the MCP6G01/1R/1U/2/3/4 family of
SGAs are high impedance. This makes them especially
susceptible to capacitively coupled noise. Using a
ground plane helps reduce this problem.
When noise is capacitively coupled, the ground plane
provides additional shunt capacitance to ground. When
noise is magnetically coupled, the ground plane
reduces the mutual inductance between traces.
Increasing the separation between traces makes a
significant difference.
Changing the direction of one of the traces can also
reduce magnetic coupling. It may help to locate guard
traces next to the victim trace. They should be on both
sides of, and as close as possible to, the victim trace.
Connect the guard traces to the ground plane at both
ends. Also connect long guard traces to the ground
plane in the middle.
10
100
1,000
10 100 1,000 10,000 100,000
Load Capacitance (F)
Recommended RISO (
:
)
10p 100p 1n 100n
For all gains
10n
VSMCP6G0X VOUT
RS
CP1
CP2
© 2006 Microchip Technology Inc. DS22004B-page 23
MCP6G01/1R/1U/2/3/4
4.7 Unused Amplifiers
An unused amplifier in a quad package (MCP6G04)
should be configured as shown in Figure 4-8. This
circuit prevents the output from toggling and causing
crosstalk. Because the VIN pin looks like an open
circuit, the GSEL voltage is automatically set at VDD/2,
and the gain is 1 V/V. The output pin provides a
buffered VDD/2 voltage and minimizes the supply
current draw of the unused amplifier.
FIGURE 4-8: Unused Amplifiers.
4.8 Typical Applications
4.8.1 DRIVING THE GAIN SELECT PIN
WITH A MICROCONTROLLER GPIO
PIN
The circuit in Figure 4-9 uses a microcontroller GPIO
pin to drive the Gain Select input (GSEL). Setting the
GPIO pin to logic low, high-Z or logic high gives a GSEL
voltage of 0V, VDD/2 or VDD, respectively (G = 10, 1 or
50).
FIGURE 4-9: Driving the GSEL Pin.
The microcontroller’s GPIO pin cannot produce a
leakage current of more than ±1 µA for this circuit to
function properly. In noisy environments, a capacitor
may need to be added to the GPIO pin.
4.8.2 DRIVING THE GAIN SELECT PIN
WITH A PWM SIGNAL
The circuit in Figure 4-10 uses a PWM output on a PIC
microcontroller (100 kHz clock rate) to drive the Gain
Select input (GSEL). Setting the PWM duty cycle to
0%, 50% or 100% gives a GSEL voltage of 0V, VDD/2
or VDD, respectively (G = 10, 1 or 50).
FIGURE 4-10: Driving the GSEL Pin.
The PWM clock rate needs to be fast so it is easily
filtered and does not interfere with the desired signal,
and it needs to be slow enough for good accuracy and
low crosstalk. This filter reduces the ripple at the GSEL
pin to about 7 mVP-P at VDD = 5.0V. The 10% settling
time is about 200 µs; the filter limits how quickly the
gain can be changed. Scale the resistors and/or
capacitors for other clock rates, or for different ripple.
4.8.3 GAIN RANGING
Figure 4-11 shows a circuit that measures the current
IX. The circuit’s performance benefits from changing
the gain on the SGA. Just as a hand-held multimeter
uses different measurement ranges to obtain the best
results, this circuit makes it easy to set a high gain for
small signals and a low gain for large signals. As a
result, the required dynamic range at the SGA’s output
is less than at its input (by up to 34 dB).
FIGURE 4-11: Wide Dynamic Range
Current Measurement Circuit.
¼ MCP6G04
VOUT
MCP6G0X
VIN
GSEL
VDD
VOUT
MCP6G0XVIN
GSEL
MCU
GPIO
Pin
VDD
VDD
VOUT
MCP6G0XVIN
GSEL
PIC MCU
PWM
Output
4.7 nF
VDD
VDD
10 kΩ
4.7 nF
10 kΩ
IX
VOUT
MCP6G0X
RS
MCP6G01/1R/1U/2/3/4
DS22004B-page 24 © 2006 Microchip Technology Inc.
4.8.4 SHIFTED GAIN RANGE SGA
Figure 4-12 shows a circuit using a MCP6271 at a gain
of +10 in front of a MCP6G01. This shifts the overall
gain range to +10 V/V to +500 V/V (from +1 V/V to
+50 V/V).
FIGURE 4-12: SGA with Higher Gain
Range.
It is also easy to shift the gain range to lower gains (see
Figure 4-13). The MCP6001 acts as a unity gain buffer,
and the resistive voltage divider shifts the gain range
down to +0.1 V/V to +5.0 V/V (from +1 V/V to +50 V/V).
FIGURE 4-13: SGA with Lower Gain
Range.
4.8.5 ADC DRIVER
This family of SGAs is well suited for driving Analog-to-
Digital Converters (ADC). The gains (1, 10, and 50)
effectively increase the ADC’s input resolution by a
factor of as large as 50 (i.e., by 5.6 bits). This works
well for applications needing relative accuracy more
than absolute accuracy (e.g., power monitoring); see
Figure 4-14.
FIGURE 4-14: SGA as an ADC Driver.
The low-pass filter in the block diagram reduces the
integrated noise at the MCP6G01’s output and serves
as an anti-aliasing filter. This filter may be designed
using Microchip’s FilterLab® software, available at
www.microchip.com.
VIN
VOUT
MCP6271 MCP6G01
1.11 kΩ
10.0 kΩ
VIN
MCP6001
1.11 kΩ
10.0 kΩ
VOUT
MCP6G01
OUT
MCP3001
10-bit
ADC
3
MCP6G01VIN
Low-pass
Filter
© 2006 Microchip Technology Inc. DS22004B-page 25
MCP6G01/1R/1U/2/3/4
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
8-Lead SOIC (150 mil) (MCP6G01, MCP6G02, MCP6G03)Example:
XXXXXXXX
XXXXYYWW
NNN
8-Lead MSOP (MCP6G01, MCP6G02, MCP6G03)Example:
XXXXXX
YWWNNN
6G01E
634256
MCP6G01E
SN^^0634
256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
5-Lead SOT-23 (MCP6G01, MCP6G01R, MCP6G01U)
XXNN CK25
Device Code
MCP6G01 CKNN
MCP6G01R CLNN
MCP6G01U CMNN
Note: Applies to 5-Lead SOT-23
MCP6G01/1R/1U/2/3/4
DS22004B-page 26 © 2006 Microchip Technology Inc.
Package Marking Information (Continued)
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
14-Lead SOIC (150 mil) (MCP6S24)Example:
XXXXXXXXXXX
YYWWNNN
XXXXXXXXXXX
XXXXXXXX
NNN
YYWW
14-Lead TSSOP (4.4mm) (MCP6S24)Example:
6G04E/ST
256
0609
MCP6G04
0609256
E/SL^^
3
e
© 2006 Microchip Technology Inc. DS22004B-page 27
MCP6G01/1R/1U/2/3/4
5-Lead Plastic Small Outline Transistor (OT) (SOT-23)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1
p
D
B
n
E
E1
L
c
β
φ
α
A2
A
A1
p1
10501050
b
Mold Draft Angle Bottom
10501050
a
Mold Draft Angle Top
0.500.430.35.020.017.014BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
10501050
f
Foot Angle
0.550.450.35.022.018.014LFoot Length
3.102.952.80.122.116.110DOverall Length
1.751.631.50.069.064.059E1Molded Package Width
3.002.802.60.118.110.102EOverall Width
0.150.080.00.006.003.000A1Standoff
1.301.100.90.051.043.035A2Molded Package Thickness
1.451.180.90.057.046.035AOverall Height
1.90.075
p1
Outside lead pitch (basic)
0.95.038
p
Pitch
55
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES
*
Units
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
Notes:
EIAJ Equivalent: SC-74A
Drawing No. C04-091
*
Controlling Parameter
Revised 09-12-05
MCP6G01/1R/1U/2/3/4
DS22004B-page 28 © 2006 Microchip Technology Inc.
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
L
L1
ϕ
c
A2
A1
A
b
2
1
NOTE 1
e
E
E1
D
N
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
Footprint
Foot Angle
Lead Thickness
Lead Width
Units
Dimension Limits
N
e
A
A2
A1
E
E1
D
L
L1
ϕ
c
b
—
0.75
0.00
0.40
0°
0.08
0.22
8
0.65 BSC
—
0.85
—
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
—
—
—
1.10
0.95
0.15
0.80
8°
0.23
0.40
MIN NOM MAX
MILLIMETERS
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions
shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing No. C04–111, Sept. 8, 2006
© 2006 Microchip Technology Inc. DS22004B-page 29
MCP6G01/1R/1U/2/3/4
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.33.020.017.013BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length
0.510.380.25.020.015.010hChamfer Distance
5.004.904.80.197.193.189DOverall Length
3.993.913.71.157.154.146
E1
Molded Package Width
6.206.025.79.244.237.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052A2Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27.050
p
Pitch
88
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
MCP6G01/1R/1U/2/3/4
DS22004B-page 30 © 2006 Microchip Technology Inc.
14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Foot Angle φ048048
1512015120
β
Mold Draft Angle Bottom
1512015120
α
Mold Draft Angle Top
0.510.420.36.020.017.014BLead Width
0.250.230.20.010.009.008
c
Lead Thickness
1.270.840.41.050.033.016LFoot Length
0.510.380.25.020.015.010hChamfer Distance
8.818.698.56.347.342.337DOverall Length
3.993.903.81.157.154.150E1Molded Package Width
6.205.995.79.244.236.228EOverall Width
0.250.180.10.010.007.004A1Standoff §
1.551.421.32.061.056.052
A2
Molded Package Thickness
1.751.551.35.069.061.053AOverall Height
1.27
.050
p
Pitch
1414
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERSINCHES*Units
2
1
D
p
n
B
E
E1
h
L
c
β
45°
φ
α
A2
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-065 Revised 7-20-06
§ Significant Characteristic
© 2006 Microchip Technology Inc. DS22004B-page 31
MCP6G01/1R/1U/2/3/4
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
L
β
c
φ
2
1
D
n
B
p
E1
E
α
A2A1
A
8°4°0°8°4°
0°
φ
Foot Angle
β
Mold Draft Angle Bottom
12° REF
α
Mold Draft Angle Top
0.300.250.19.012.010.007BLead Width
0.200.150.09.008.006.004
c
Lead Thickness
0.700.600.50.028.024.020LFoot Length
5.105.004.90.201.197.193DMolded Package Length
4.504.404.30.177.173.169E1Molded Package Width
6.506.386.25.256.251.246EOverall Width
0.150.100.05.006.004.002A1Standoff
0.950.900.85.037.035.033A2Molded Package Thickness
1.101.051.00.043.041.039AOverall Height
0.65 BSC.026 BSC
p
Pitch
1414
n
Number of Pins
MAXNOMMINMAXNOMMINDimension Limits
MILLIMETERS
*
INCHESUnits
Dimensions D and E1 do not include mold fla sh or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.
Notes:
JEDEC Equivalent: MO-153 AB-1
Revised: 08-17-05
*
Controlling Parameter
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tole rance, for information purposes only.
See ASME Y14.5M
See ASME Y14.5M
Drawing No. C04-087
12° REF
12° REF
12° REF
MCP6G01/1R/1U/2/3/4
DS22004B-page 32 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS22004B-page 33
MCP6G01/1R/1U/2/3/4
APPENDIX A: REVISION HISTORY
Revision B (December 2006)
The following is the list of modifications:
• Added SOT-23-5 package option for the single
gain blocks MCP6G01, MCP6G01R, and
MCP6G01U.
• Added a discussion on VIN range vs. G.
Revision A (September 2006)
• Original Release of this Document.
MCP6G01/1R/1U/2/3/4
DS22004B-page 34 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS22004B-page 35
MCP6G01/1R/1U/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6G01: Single SGA
MCP6G01T: Single SGA
(Tape and Reel for MSOP and SOIC)
MCP6G01RT: Single SGA
(Tape and Reel for SOT-23-5)
MCP6G01UT: Single SGA
(Tape and Reel for SOT-23-5)
MCP6G02: Dual SGA
MCP6G02T: Dual SGA
(Tape and Reel for MSOP and SOIC)
MCP6G03: Single SGA
MCP6G03T: Single SGA
(Tape and Reel for MSOP and SOIC)
MCP6G04: Quad SGA
MCP6G04T: Quad SGA
(Tape and Reel for SOIC and TSSOP)
Temperature Range: E = -40°C to +125°C
Package: MS = Plastic MSOP, 8-lead
OT = Plastic Small Outline Transistor (SOT-23-5), 5-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead (MCP6G04)
ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6G04)
PART NO. –X /XX
PackageTemperature
Range
Device
Examples:
a) MCP6G01-E/MS: Extended Temperature,
8LD MSOP.
b) MCP6G01T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
c) MCP6G01T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
d) MCP6G01RT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
e) MCP6G01UT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23-5.
a) MCP6G02-E/MS: Extended Temperature,
8LD MSOP.
b) MCP6G02T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
a) MCP6G03-E/MS: Extended Temperature,
8LD MSOP.
b) MCP6G03T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC.
c) MCP6G03-E/SN: Extended Temperature,
8LD SOIC.
a) MCP6G04T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC.
b) MCP6G04T-E/ST: Tape and Reel,
Extended Temperature,
14LD TSSOP.
c) MCP6G04-E/ST: Extended Temperature,
14LD TSSOP.
MCP6G01/1R/1U/2/3/4
DS22004B-page 36 © 2006 Microchip Technology Inc.
NOTES:
© 2006 Microchip Technology Inc. DS22004B-page 37
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
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OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
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FITNESS FOR PURPOSE. Microchip disclaims all liability
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intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active
Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
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SQTP is a service mark of Microchip Technology Incorporated
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All other trademarks mentioned herein are property of their
respective companies.
© 2006, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC®
8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs,
microperipherals, nonvolatile memory and analog products. In addition,
Microchip’s quality system for the design and manufacture of
development systems is ISO 9001:2000 certified.
DS22004B-page 38 © 2006 Microchip Technology Inc.
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