LP3923TLX/NOPB - NATIONAL SEMICONDUCTOR

LP3923

LP3923 Cellular Phone Power Management Unit

Literature Number: SNVS567A

LP3923

October 4, 2011

Cellular Phone Power Management Unit

General Description

The LP3923 is a fully Integrated Power Management Unit

(PMU) designed for CDMA cellular phones.

The LP3923 PMU contains a fully integrated Li-Ion battery

charger with power FET and over-voltage-protection (OVP),

one Buck regulator, 8 low-noise low-dropout (LDO) voltage

regulators, and a high-speed serial interface to program on/

off conditions and output voltages of individual regulators, and

to read status information of the PMU. Two LILO (low-input,

low-output) type LDOs with separate power input provide an

application option for pre-regulated high efficient power man-

agement for longer battery life.

The Li-Ion charger can safely charge and maintain a single

cell Li-Ion battery operating from an AC adapter. The charger

integrates a power FET, a reverse current blocking diode, a

sense resistor with current monitor output, and requires only

a few external components. Charging is thermally regulated

to obtain the most efficient charging rate for a given ambient

temperature.

A built-in Over-Voltage Protection (OVP) circuit at the charger

inputs protects the PMU from input voltages up to +28V, elim-

inating the need for any external protection circuitry.

Buck regulator has an automatic switch to PFM mode at low

load conditions providing very good efficiency at low output

currents. An external divider circuitry provides user defined

buck output voltage.

A-type LDO regulators provide excellent PSRR and very low

noise, 10 µV typ., ideally suited for supplying voltage to RF

and other analog sections.

Features

■Integrated Li-Ion battery charger with power FET, thermal

regulation and 28V OVP

■Six Low-Noise LDOs, two LILO LDOs

3 x 300 mA

4 x 150 mA

1 x 80 mA

■One high efficiency Synchronous Magnetic Buck

Regulators, IOUT 700 mA

High efficiency PFM mode @low IOUT

Auto Mode PFM/PWM switch

Low inductance 2.2 µH @ 2 MHz clock

■I2C-compatible interface for controlling LDO outputs and

charger operation

■Thermal Shutdown with Early Warning Alarm

■Under-Voltage Lockout

■30-bump 3.0 x 2.5 mm micro SMD package

Key Specifications

■50 mA to 1200 mA Charging Current

■3.0V to 5.5V Input Voltage Range

■135 mV typ. Dropout Voltage @ 300 mA LDOs

2% (typ.) Output Voltage accuracy on LDOs

■700 mA (typ.) buck regulator

Applications

■Cellular Handsets

System Diagram

30058601

LP3923 Cellular Phone Power Management Unit

Typical Application Diagram

30058639

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LP3923

Device Pin Diagram

30058603

Package Marking Information

30058604

Ordering Information

Order Number PWR_ON

HF_PWR

Pin in

Standby

VFULL_

RATE

Default

Charging

Current

Charger

LDO

Mode

PS_HOLD

Startup

LDO 1 and

LDO2 Startup

condition with

SEL=GND

Product

ID Supplied as

LP3923TL Level

Sensitive

Level

Sensitive 2.8V 400mA Disabled No On by default

3.0V 3923 250 Tape &

Reel

LP3923TLX Level

Sensitive

Level

Sensitive 2.8V 400mA Disabled No On by default

3.0V 3923 3000 Tape &

Reel

LP3923TL-VI Level

Sensitive

Level

Sensitive

2.8V 100mA Disabled Yes On by defaul

3.0V V017 250 Tape &

Reel

LP3923TLX-VI Level

Sensitive

Level

Sensitive

2.8V 100mA Disabled Yes On by default

3.0V V017 3000 Tape &

Reel

LP3923TL-VB Level

Sensitive

Level

Sensitive

2.8V 100mA Disabled Yes Off by default

3.0V V020 250 Tape &

Reel

LP3923TLX-VB Level

Sensitive

Level

Sensitive

2.8V 100mA Disabled Yes Off by default

3.0V V020 3000 Tape &

Reel

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LP3923

Order Number PWR_ON

HF_PWR

Pin in

Standby

VFULL_

RATE

Default

Charging

Current

Charger

LDO

Mode

PS_HOLD

Startup

LDO 1 and

LDO2 Startup

condition with

SEL=GND

Product

ID Supplied as

LP3923TL-VC Level

Sensitive

Level

Sensitive

3.0V 100mA Disabled Yes Off by default

3.0V V026 250 Tape &

Reel

LP3923TLX-VC Level

Sensitive

Level

Sensitive

3.0V 100mA Disabled Yes Off by default

3.0V V026 3000 Tape &

Reel

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LP3923

LP3923 Pin Descriptions

Pin Number Name Type Description

A1 LDO4 A LDO4 Output

A2 LDO5 A LDO5 Output

A3 LDO6 A LDO6 Output

A4 VIN2 P Input for LDO3 -LDO8

A5 LDO7 A LDO7 Output

B1 LDO2 A LDO2 Output

B2 TCXO_EN DI Enable control input for LDO4. HIGH = Enable, LOW = Disable (SLEEP

Mode).

B3 RX_EN DI Enable control input for LDO5. HIGH = Enable, LOW = Disable.

B4 TX_EN DI Enable control input for LDO6. HIGH = Enable, LOW = Disable.

B5 LDO3 A LDO3 Output

C1 VIN1 P Input for LDO1 and LDO2

C2 PS_HOLD DI Power Supply Hold Input

C3 RESET_N DO Reset Output. Pin stays LOW during power up sequence

C4 IMON A

Charging current monitor output. This pin presents an analog voltage

representation of the charging current.

C5 LDO8 A LDO8 Output

D1 LDO1 A LDO1 Output

D2 SEL DI LDO1 and LDO2 default voltage selection.

D3 PON_N DO State of PWR_ON inverted. Digital output referred to LDO3.

D4 SDA DI/O Serial Interface, Data Input/Output

Open Drain output, external pull up resistor is needed, typ. 1.5 kΩ.

D5 GND G IC Ground pin

E1 SW A Buck Output

E2 HF_PWR DI Power up sequence starts when this pin is set HIGH. Internal 500 kΩ pull-

down resistor.

E3 PWR_ON DI Power up sequence starts when this pin is set HIGH.

Internal 500 kΩ pull-down resistor.

E4 SCL DI Serial Interface Clock input.

External pull up resistor is needed, typ. 1.5 kΩ.

E5 BATT P Main battery connection. Used both as a power connection for current

delivery to the battery and as a voltage sense connection to monitor the

battery charge level.

F1 VINB P Input for Buck

F2 GNDB G Power Ground for Buck

F3 FB A Buck Feedback pin

F4 ACOK_N DO AC Adapter indicator, LOW when VCHG_IN is above its trip point

F5 CHG_IN P DC power input to charger block from AC adapter or USB

A: Analog Pin

D: Digital Pin

I: Input Pin

DI/O Digital Input/Output Pin

G: Ground

O: Output Pin

P: Power Connection

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LP3923

Device Description

The LP3923 Charge Management and Regulator Unit is de-

signed to supply charger and voltage output capabilities for

mobile systems, e.g. CDMA handsets. The device provides a

Li-Ion charging function and 8 or 9 regulated outputs. Com-

munication with the device is via an I2C compatible serial

interface that allows function control and status read-back.

The battery charge management section provides a pro-

grammable CC/CV linear charge capability and end of charg-

ing current threshold. Following a normal charge cycle a

maintenance mode utilizing programmable restart voltage

levels enables the battery voltage to be maintained at the

correct level. Power dissipation is thermally regulated to ob-

tain optimum charge levels over the ambient temperature

range.

CHARGER FEATURES

•Pre-charge, CC, CV and Maintenance modes

•Integrated FET

•Integrated Reverse Current Blocking Diode

•Integrated Sense Resistor

•Thermal Regulation

•Charging Current Monitor Output

•Programmable charging current 50 mA - 1200 mA with 50

mA steps

•Default CC mode current 400 mA

•Pre-charging current fixed 50 mA

•Termination voltage 4.1V, 4.2V (default), 4.3V and 4.4V

•Restart level 50 mV, 100 mV (default), 150 mV and 200

mV below Termination voltage

•End of Charge 0,05C, 0.1C, 0.15C (default) and 0.2C

•Input voltage operating range 4.5 - 6.8V

REGULATORS

Eight low dropout linear regulators provide programmable

voltage outputs with current capabilities of 80 mA, 150 mA,

and 300 mA as given in the table below. LDO1 and LDO2 are

supplied either by the VBATT (SEL=GND) or by buck

regulator’s output (SEL=VBATT). If the supply voltage is low

(supply from buck), then LDO1 and LDO2 are going to be low-

input low-output (LILO) LDOs.

Buck regulator can provide 700 mA (typ.) of current. If the

buck is used for supplying LDO1 and LDO2 it won’t be able

to supply external devices. If LDO1 and LDO2 are supplied

by VBATT, then buck can be used as an output power channel

for digital loading with the default output voltage value of 1.8V

Under voltage lockout oversees device start up with a preset

level of 3.0V( typ.).

LDOs and Buck Default Voltages (for options LP3923TL/X and LP3923TL/X-VI)

Device Type Current

(mA)

Enable

control

Input Output(V) Startup

default

Input Output(V) Startup

default

SEL=BATT SEL=GND

Buck 700 SI VINB=BATT 2.0* ON VINB=BATT 1.8* ON

LDO1 LILO 300 SI VIN1=VBUCK 1.8 ON VIN1=BATT 3 ON

LDO2 LILO 300 SI VIN1=VBUCK 1.8 ON VIN1=BATT 3 ON

LDO3 D 300 - VIN2=BATT 3 ON VIN2=BATT 3 ON

LDO4 A 80 TCXO_EN VIN2=BATT 3 OFF VIN2=BATT 3 OFF

LDO5 A 150 RX_EN VIN2=BATT 3 OFF VIN2=BATT 3 OFF

LDO6 A 150 TX_EN VIN2=BATT 3 OFF VIN2=BATT 3 OFF

LDO7 A 150 SI VIN2=BATT 3 ON VIN2=BATT 3 ON

LDO8 D 150 SI VIN2=BATT 3 OFF VIN2=BATT 3 OFF

* Voltage is set by the external resistors.

LDOs and Buck Default Voltages (for option LP3923TL/X-VB)

Device Type Current

(mA)

Enable

control

Input Output(V) Startup

default

Input Output(V) Startup

default

SEL=BATT SEL=GND

Buck 700 SI VINB=BATT 2.0* ON VINB=BATT 1.8* ON

LDO1 LILO 300 SI VIN1=VBUCK 1.8 ON VIN1=BATT 3 OFF

LDO2 LILO 300 SI VIN1=VBUCK 1.8 ON VIN1=BATT 3 OFF

LDO3 D 300 - VIN2=BATT 3 ON VIN2=BATT 3 ON

LDO4 A 80 TCXO_EN VIN2=BATT 3 OFF VIN2=BATT 3 OFF

LDO5 A 150 RX_EN VIN2=BATT 3 OFF VIN2=BATT 3 OFF

LDO6 A 150 TX_EN VIN2=BATT 3 OFF VIN2=BATT 3 OFF

LDO7 A 150 SI VIN2=BATT 3 ON VIN2=BATT 3 ON

LDO8 D 150 SI VIN2=BATT 3 OFF VIN2=BATT 3 OFF

* Voltage is set by the external resistors.

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LP3923

Absolute Maximum Ratings (Note 1, Note

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

CHG_IN (VBATT=2.8-5.5V) −0.3V to +28V

VBATT=VIN1-2, BATT, HF_PWR,

VINB −0.3V to +6.0V

All other inputs −0.3V to VBATT+0.3V,

max 6.0V

Junction Temperature (TJ-MAX) 150°C

Storage Temperature −40°C to +150°C

Max Continuous Power Dissipation

PD-MAX (Note 3)

Internally Limited

ESD (Note 4)

BATT, VIN1, VIN2, HF_PWR,

CHG_IN, PWR_ON, VINB

8 kV HBM

Operating Ratings (Note 1, Note 2)

CHG_IN (Note 10) 4.5 to 6.8V

VBATT = VIN1-2, BATT, VINB 3.0V to 5.5V

HF_PWR, PWR_ON 0V to 5.5V

ACOK_N, SDA, SCL, RX_EN,

TX_EN, TCXO_EN, PS_HOLD,

RESET_N 0V to (VLDO + 0.3V)

All other pins 0V to VBATT + 0.3V)

Junction Temperature (TJ)−40°C to +125°C

Ambient Temperature (TA) (Note 6)−40°C to +85°C

Thermal Properties (Note 9)

Junction-to-Ambient Thermal

Resistance (θJA)

(Jedec Standard Thermal PCB)

Micro SMD 30 39°C/W

General Electrical Characteristics

Unless otherwise noted, VIN (= VIN1 = VIN2 = VINB = BATT) = 3.6V, GND = 0V, CVIN1–2 = CVINB = 10 µF, CLDOx = 1 µF. Typical

values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction

temperature range for operation, TA = TJ = −40°C to +125°C. (Note 6)

Symbol Parameter Conditions Typ Limit Units

Min Max

IQ(STANDBY) Standby Supply

Current

VIN = 3.6V, UVLO on, internal logic circuit

on, all other circuits off. 2 10 µA

IQ(SLEEP) Sleep Mode Current

@ 0 load

Buck, LDO1, LDO2, LDO3 and LDO7 enabled 130 400 µA

POWER MONITOR FUNCTIONS

Battery Under-Voltage Lockout

VUVLO-R Under Voltage Lock-

out Rising

VIN Rising 3.00 2.85 3.15

VUVLO-F Under Voltage Lock-

out Falling

VIN Falling (LP3923-VC) 2.80 2.65 2.95

THERMAL SHUTDOWN

Higher Threshold (Note 7) 160 °C

LOGIC AND CONTROL INPUTS

VIL Input Low Level PS_HOLD, SDA, SCL, RX_EN, TCXO_EN, TX_EN 0.25*

VLDO3

PWR_ON, HF_PWR, SEL 0.25*

VBATT

VIH Input High Level PS_HOLD, SDA, SCL, RX_EN, TCXO_EN, TX_EN 0.75*

VLDO3

PWR_ON, HF_PWR, SEL 0.75*

VBATT

IIL Logic Input Current All logic inputs except PWR_ON, HF_PWR.

0V ≤ VINPUT ≤ VBATT

–5 +5 µA

RIN Input Resistance PWR_ON and HF_PWR Pull-Down resistance to GND

(Note 7)500 kΩ

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LP3923

Symbol Parameter Conditions Typ Limit Units

Min Max

LOGIC AND CONTROL OUTPUTS

VOL Output Low Level PON_N, RESET_N, SDA, ACOK_N

IOUT = 2 mA 0.25*

VLDO3

VOH Output High Level PON_N, RESET_N, ACOK_N

IOUT = −2 mA

(Not applicable to Open Drain Output SDA)

0.75*

VLDO3

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LP3923

LDO1, LDO2 (LILO) Electrical Characteristics

Unless otherwise noted, if SEL=GND, then VIN=VIN1=BATT=3.6V, if SEL=BATT, then VIN=VIN1=VBUCK, GND = 0V, CV!N1-2 =

10 µF, CLDOx= 1 µF. Note VINMIN is the greater of 3.0V or VOUT +0.5V. Typical values and limits appearing in normal type apply for

TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = −40°C to

+125°C.(Note 6)

Symbol Parameter Conditions Typical Limit Units

Min Max

VOUT Output Voltage

Accuracy

IOUT = 1 mA, VOUT = 3.0V −2 +2 %

−3 +3

Default Output

Voltage

SEL = GND 3.0 V

SEL = BATT 1.8

IOUT Output Current VINMIN ≤ VIN ≤ 5.5V 300 mA

Output Current Limit VOUT = 0V 600

VDO Dropout Voltage IOUT =300 mA

(Note 7, Note 8)135 180 mV

ΔVOUT Line Regulation VINMIN ≤ VIN ≤ 5.5V

IOUT = 1 mA 2 mV

Load Regulation 1 mA ≤ IOUT ≤ 300 mA 5

PSRR Power Supply Ripple

Rejection Ratio

F = 10 kHz, COUT = 1 µF,

VOUT = 3.0V, IOUT = 20 mA (Note 7)60 dB

tSTART-UP Start-Up Time from

Shut-down

COUT = 1 µF, IOUT = 300 mA

(Note 7)35 µs

TTransient Start-Up Transient

Overshoot

COUT = 1 µF, IOUT = 300 mA

(Note 7) 30 mV

LDO3 (D-Type) Electrical Characteristics

Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF. Note VINMIN is the greater of 3.0V or

VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over

the entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (Note 6)

Symbol Parameter Conditions Typical Limit Units

Min Max

VOUT Output Voltage

Accuracy

IOUT = 1 mA, VOUT = 3.0V −2 +2 %

−3 +3

Default Output Voltage 3.0 V

IOUT Output Current VINMIN ≤ VIN ≤ 5.5V 300 mA

Output Current Limit VOUT = 0V 600

VDO Dropout Voltage IOUT = 300 mA

(Note 7, Note 8)135 250 mV

ΔVOUT Line Regulation VINMIN ≤ VIN ≤ 5.5V

IOUT = 1 mA 2 mV

Load Regulation 1 mA ≤ IOUT ≤ 300 mA 5

eNOutput Noise Voltage 10 Hz ≤ f ≤ 100 kHz,

COUT = 1 µF (Note 7)35 µVRMS

PSRR Power Supply Ripple

Rejection Ratio

F = 10 kHz,

COUT = 1 µF,

IOUT = 20 mA (Note 7)

60 dB

tSTART-UP Start-Up Time from

Shut-down

COUT = 1 µF, IOUT = 300 mA

(Note 7)35 µs

TTransient Start-Up Transient

Overshoot

COUT = 1 µF, IOUT = 300 mA

(Note 7) 30 mV

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LP3923

LDO4 (A-Type) Electrical Characteristics

Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF, TCXO_EN high. Note VINMIN is the

greater of 3.0V or VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in bold-

face type apply over the entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (Note 6)

Symbol Parameter Conditions Typical Limit Units

Min Max

VOUT Output Voltage

Accuracy

IOUT = 1 mA, VOUT = 3.0V −2 +2 %

−3 +3

Default Output Voltage 3.0 V

IOUT Output Current VINMIN ≤ VIN ≤ 5.5V 80 mA

Output Current Limit VOUT = 0V 400

VDO Dropout Voltage IOUT =80 mA

(Note 7, Note 8)60 85 mV

ΔVOUT Line Regulation VINMIN + ≤ VIN ≤ 5.5V, IOUT = 1 mA 1 mV

Load Regulation 1 mA ≤ IOUT ≤ 80 mA 5

eNOutput Noise Voltage 10 Hz ≤ f ≤ 100 kHz,

COUT = 1 µF (Note 7)10 µVRMS

PSRR Power Supply Ripple

Rejection Ratio

F = 10 kHz,

COUT = 1 µF, IOUT = 20 mA (Note 7)75 dB

tSTART-UP Start-Up Time from

Shut-down

COUT = 1 µF, IOUT = 80 mA (Note 7)35 µs

TTransient Start-Up Transient

Overshoot

COUT = 1 µF, IOUT = 80 mA (Note 7) 30 mV

LDO5, LDO6, LDO7 (A-Type) Electrical Characteristics

Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF, RX_EN, TX_EN high. Note VINMIN is the

greater of 3.0V or VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in bold-

face type apply over the entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (Note 6)

Symbol Parameter Conditions Typical Limit Units

Min Max

VOUT Output Voltage

Accuracy

IOUT = 1 mA, VOUT = 3.0V −2 +2 %

−3 +3

Default Output Voltage 3.0 V

IOUT Output Current VINMIN ≤ VIN ≤ 5.5V 150 mA

Output Current Limit VOUT = 0V 400

VDO Dropout Voltage IOUT = 150 mA (Note 7, Note 8)100 150 mV

ΔVOUT Line Regulation VINMIN ≤ VIN ≤ 5.5V

IOUT = 1 mA 1 mV

Load Regulation 1 mA ≤ IOUT ≤ 150 mA 5

eNOutput Noise Voltage 10 Hz ≤ f ≤ 100 kHz,

COUT = 1 µF (Note 7)10 µVRMS

PSRR Power Supply Ripple

Rejection Ratio

F = 10 kHz, COUT = 1 µF, IOUT = 20 mA (Note 7)75 dB

tSTART-UP Start-Up Time from

Shut-down

COUT = 1 µF, IOUT = 150 mA (Note 7)35 µs

TTransient Start-Up Transient

Overshoot

COUT = 1 µF, IOUT = 150 mA (Note 7) 30 mV

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LP3923

LDO8 (D-Type) Electrical Characteristics

Unless otherwise noted, VIN=VIN2=BATT=3.6V, GND = 0V, CV!N1-2 = 10 µF, CLDOx= 1 µF. Note VINMIN is the greater of 3.0V or

VOUT +0.5V. Typical values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over

the entire junction temperature range for operation, TA = TJ = −40°C to +125°C. (Note 6)

Symbol Parameter Conditions Typical Limit Units

Min Max

VOUT Output Voltage

Accuracy

IOUT = 1 mA, VOUT = 3.0V −2 +2

%−3 +3

Default Output Voltage 3.0

IOUT Output Current VINMIN ≤ VIN ≤ 5.5V 150 mA

Output Current Limit VOUT = 0V 400

VDO Dropout Voltage IOUT = 150 mA (Note 7, Note 8)125 140 mV

ΔVOUT Line Regulation VINMIN ≤ VIN ≤ 5.5V, IOUT = 1 mA 2 mV

Load Regulation 1 mA ≤ IOUT ≤ 150 mA 5

eNOutput Noise Voltage 10 Hz ≤ f ≤ 100 kHz, COUT = 1 µF (Note 7)35 µVRMS

PSRR Power Supply Ripple

Rejection Ratio

F = 10 kHz, COUT = 1 µF, IOUT = 20 mA (Note 7)60 dB

tSTART-UP Start-Up Time from

Shut-down

COUT = 1 µF, IOUT = 150 mA (Note 7)35 µs

TTransient Start-Up Transient

Overshoot

COUT = 1 µF, IOUT = 150 mA (Note 7) 30 mV

Buck Converter Electrical Characteristics

Unless otherwise noted, VIN = VINB = 3.6V, GND = 0V, CVINB = 10 µF. Typical values and limits appearing in normal type apply

for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, TA = TJ = −40°C

to +125°C. (Note 6, Note 11)

Symbol Parameter Conditions Typ Limit Units

Min Max

VFB Feedback Voltage (BUCK) 3.0V ≤VIN≤ 5.5V 0.5 0.485 0.515 V

VOUT,PWM Output Voltage 3.0V ≤VIN≤ 5.5V, IOUT = 150mA

External resistor divider accuracy

not considered.

RFB1=390kΩ RFB2=150kΩ (Note 7)

1.8 1.746 1.854 V

VOUT,PFM Output Voltage regulation in

PFM mode relative to regulation

in PWM mode

(Note 7)

1.5 %

VOUT

Line Regulation 3.0V ≤ VIN ≤ 5.5V, IOUT = 10 mA 0.14 %/V

Load Regulation 100 mA ≤ IOUT ≤ 300 mA 0.0013 %/mA

ILIM_PWM Switch Peak Current Limit PWM Mode 1150 800 1500 mA

RDSON(P) P Channel FET on Resistance VIN = 3.6V

IDS = 100 mA

310 mΩ

RDSON(N) N Channel FET on Resistance 160 mΩ

fOSC Internal Oscillator Frequency PWM Mode 2 1.9 2.1 MHz

Efficiency IOUT = 5 mA, PFM Mode

VOUT = 1.8V (Note 7)88

IOUT = 300 mA, PWM Mode

VOUT = 1.8V (Note 7)90

TSTUP Start Up Time IOUT = 0 (Note 7), VOUT = 1.8V 140 µs

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LP3923

Charger Electrical Characteristics

Unless otherwise noted, VCHG_IN = 5V, VIN= BATT = 3.6V, CCHG_IN = 1 μF, VBATT = 30 µF. Typical values and limits appearing in

normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation,

TA = TJ = −25°C to +85°C. (Note 6, Note 9)

Symbol Parameter Conditions Typical Limit Units

Min Max

VCHG_IN AC wall adapter input

voltage operating range

4.5 6.8 V

VOK_CHG

CHG_IN OK trip-point. VCHG_IN - VBATT (Rising) 150 mV

VCHG_IN - VBATT (Falling) 40

VTERM

Battery charging

termination voltage

tolerance

VTERM = 4.2V, ICHG = 50 mA

VTERM is measured at 10% of the programmed

ICHG current

-0.35 +0.35

-1 +1

ICHG CHG_IN programmable

full-rate charging current

6.8V ≥ VCHG_IN ≥ 4.5V

VBATT < VCHG_IN − VOK_CHG

VFULL_RATE < VBATT < VTERM (Note 10)

50 1200 mA

Full rate charging current

tolerance

ICHG = 400 mA −10 +10 %

IPREEQUAL Pre-charging current 2.2V < VBATT < VFULL_RATE 50 30 70 mA

VFULL_RATE Full-rate qualification

threshold

VBATT rising, transition from pre-charging to full-

rate charging

2.8 2.7 2.9

VBATT rising, transition from pre-charging to full-

rate charging (LP3923-VC)

3.0 2.9 3.1

IEOC End-of-charging current,

% of full-rate current

0.1C option selected 10 %

VRESTART Restart threshold voltage From VTERM voltage (4.2V, −100 mV options

selected)

−100 −70 −130 mV

IMON IMON Voltage 1 ICHG = 100 mA 0.247 V

IMON Voltage 2 ICHG = 400 mA 0.988 0.840 1.127

CBATT Capacitance on BATT (Note 7) 30 1000 µF

TREG Regulated junction

temperature

(Note 7) 115 °C

Detection and Timing (one combined timer)

TPOK Power OK deglitch time VCHG > VBATT + VOK_CHG 30 ms

TPC_FULL Deglitch time From pre-charging to full-rate charging 210 ms

TCHG Charge timer Pre-charge mode 1

Hrs

CC mode/CV mode (combined timer)

disabled

TEOC Deglitch time for end- of-

charge transition

210 ms

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LP3923

Serial Interface

Unless otherwise noted, VIN = BATT = 3.6V, GND = 0V, CVIN1–2 = 10 µF CLDOx = 1 µF and VLDO3 = 3.0V. Typical values and limits

appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature range

for operation, TA = TJ = −40°C to +125°C. (Note 6, Note 7)

Symbol Parameter Conditions Typ Limit Units

Min Max

fCLK Clock Frequency 400 kHz

tBF Bus-Free Time between START

and STOP

1.3 µs

tHOLD Hold Time Repeated START

Condition

0.6 µs

tCLK-LP CLK Low Period 1.3 µs

tCLK-HP CLK High Period 0.6 µs

tSU Set-Up Time Repeated START

Condition

0.6 µs

tDATA-HOLD Data Hold Time 50 ns

tDATA-SU Data Set-Up Time 100 ns

tSU Set-Up Time for STOP Condition 0.6 µs

tTRANS Maximum Pulse Width of Spikes

that Must Be Suppressed by the

Input Filter of Both DATA & CLK

Signals

50 ns

Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the

device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the

Electrical Characteristics tables.

Note 2: All voltages are with respect to the potential at the GND pin.

Note 3: Internal Thermal Shutdown circuitry protects the device from permanent damage.

Note 4: The human-body model is 100 pF discharged through 1.5 kΩ. The machine model is a 200 pF capacitor discharged directly into each pin, MIL-STD-883

3015.7.

Note 5: Care must be exercised where high power dissipation is likely. The maximum ambient temperature may have to be derated. Maximum ambient

temperature (TA-MAX) is dependant on the maximum operating junction temperature (TJ-MAX-OP), the maximum power dissipation of the device in the application

(PD-MAX), and the junction to ambient thermal resistance of the package in the application (θJA). This relationship is given by the following equation:

TA-MAX = TJ-MAX-OP - (θJA x PD-MAX)

Note 6: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production with TJ = 25°C. All hot and cold limits

are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

Note 7: Guaranteed by design.

Note 8: Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value. This specification does not apply

in cases it implies operation with an input voltage below the 2.5V minimum appearing under Operating Ratings. For example, this specification does not apply

for devices having 1.5V outputs because the specification would imply operation with an input voltage at or about 1.5V.

Note 9: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,

special care must be paid to thermal dissipation issues in board design.

Note 10: Full charging current is guaranteed for CHG_IN = 4.5 to 6.8V, but particularly at higher input voltages. Increased power dissipation may cause the

thermal regulation to limit the current to a safe level, resulting in longer charging time.

Note 11: Buck output voltage accuracy depends on the accuracy of the external feedback resistors. Resistor values should be chosen for the divider network to

ensure that at the desired output voltage the FB pin is at the specified value of 0.5V. See Buck Converter Application Information.

13 www.national.com

LP3923

Power Up and Power Down Sequences

30058638

Note 1: CHG_IN is edge sensitive and HF_PWR is level sensitive at startup in STANDBY mode and level sensitive in POWER-ON-RESET mode.

Note 2: PWR_ON is level sensitive at startup. PS_HOLD must be asserted before PWR_ON goes LOW to keep PMU powered. PWR_ON input is not monitored

after PMU is powered up (PS_HOLD asserted).

Note 3: PON_N is a direct inversion of PWR_ON input when LDO3 is powered up (no power-on switch debouncing on PON_N output).

Note 4: The input signal which activates Power Up sequence (either PWR_ON or CHG_IN or HF_PWR) must be on when PS_HOLD is asserted.

Note 5: Time delay between the PS_HOLD going low and the start of Power Down sequence depends on PS_HOLD_DELAY setting (0=35ms, 1=350ms) (typ.).

FIGURE 1. Power Up and Power Down Timing Diagram

www.national.com 14

LP3923

LP3923 Serial Port Communication: Slave Address Code: 7h'7E

Control Registers

Addr Register

(Default value)* D7 D6 D5 D4 D3 D2 D1 D0

8h'00 OP_EN1

(01000111)

BUCK_

PWM

EN_

BUCK X X EN_LDO8 EN_LDO7 EN_LDO2 EN_LDO1

8h'01

LDO1PGM O/P

SEL=BATT

(00001100)

SEL=GND

(00011011)

X X X LDO1_

V1_OP[4]

LDO1_

V1_OP[3]

LDO1_

V1_OP[2]

LDO1_

V1_OP[1]

LDO1_

V1_OP[0]

8h'02

LDO2 Program O/P

SEL=BATT

(00001100)

SEL=GND

(00011011)

X X X LDO2_

V2_OP[4]

LDO2_

V2_OP[3]

LDO2_

V2_OP[2]

LDO2_

V2_OP[1]

LDO2_

V2_OP[0]

8h'03 LDO3 PGM O/P

(00011011) X X X LDO3_

V3_OP[4]

LDO3_

V3_OP[3]

LDO3_

V3_OP[2]

LDO3_

V3_OP[1]

LDO3_

V3_OP[0]

8h'04 LDO4 PGM O/P

(00011011) X X X LDO4_

V4_OP[4]

LDO4_

V4_OP[3]

LDO4_

V4_OP[2]

LDO4_

V4_OP[1]

LDO4_

V4_OP[0]

8h'05 LDO5 PGM O/P

(00011011) X X X LDO5_

V5_OP[4]

LDO5_

V5_OP[3]

LDO5_

V5_OP[2]

LDO5_

V5_OP[1]

LDO5_

V5_OP[0]

8h'06 LDO6 PGM O/P

(00011011) X X X LDO6_

V6_OP[4]

LDO6_

V6_OP[3]

LDO6_

V6_OP[2]

LDO6_

V6_OP[1]

LDO6_

V6_OP[0]

8h'07 LDO7 PGM O/P

(00011011) X X X LDO7_

V7_OP[4]

LDO7_

V7_OP[3]

LDO7_

V7_OP[2]

LDO7_

V7_OP[1]

LDO7_

V7_OP[0]

8h'08 LDO8 PGM O/P

(00011011) X X X LDO8_

V8_OP[4]

LDO8_

V8_OP[3]

LDO8_

V8_OP[2]

LDO8_

V8_OP[1]

LDO8_

V8_OP[0]

8h'0C

Status1

Trig.-PWR_ON

(10000010)

Trig.-HF_PWR

(01000010)

Trig.-CHG_IN

(00100010)

PWR_ON

TRIG

HF_PWR

TRIG

CHG_IN

TRIG X TSD_H TSD_L FF X

8h'10 CHARGER Control 1

(00010 001) X X Force_

EOC

PROG_

CHGTIME

[1]

PROG_

CHGTIME

[0]

EN_EOC X EN_CHG

8h'11 CHARGER Control 2

(00000111) X X X PROG_

ICHG[4]

PROG_

ICHG[3]

PROG_

ICHG[2]

PROG_

ICHG[1]

PROG_

ICHG[0]

8h'12 CHARGER Control 3

(00011001) X X VTERM

[1] VTERM[0] PROG_

EOC[1]

PROG_

EOC[0]

PROG_

VSTRT[1]

PROG_

VSTART[0]

8h'13 CHARGER Status 1

(0000 0000)

BATT_

OVER_OUT

CHGIN_

OK_OUT EOC TOUT_

FULLRATE

TOUT_

PRECHG X FULLRATE PRECHG

8h'14 CHARGER Status 2

(00000000) X X X X X X TOUT_

CONSTV BAD_BATT

8h'1C MISC Control1

(00000000) X X X X X X EN_

APU_TSD

PS_HOLD_

DELAY

X — Not used.

BOLD locations are Read Only type.

NOTE: All Control registers apart from Charger Control registers (h'10 — h'12) are reset to default at the end of every Power Down sequence.

15 www.national.com

LP3923

BUCK_PWM 0 - Auto mode PFM/PWM

1 - Buck forced PWM mode

EN_BUCK 0 - disable Buck

1 - enable Buck

EN_LDO8 0 - disable LDO8

1 - enable LDO8

EN_LDO7 0 - disable LDO7

1 - enable LDO7

EN_LDO2 0 - disable LDO2 on LP3923TL/X and -VI; enable on LP3923TL/X-VB

1 - enable LDO2 on LP3923TL/X and -VI; disable on LP3923TL/X-VB

EN_LDO1 0 - disable LDO1 on LP3923TL/X and -VI; enable on LP3923TL/X-VB

1 - enable LDO1 on LP3923TL/X and -VI; disable on LP3923TL/X-VB

PWR_ON_TRIG 0 - system was not powered on by PWR_ON input

1 - system was powered on by PWR_ON input

HF_PWR_TRIG 0 - system was not powered on by HF_PWR input

1 - system was powered on by HF_PWR input

CHG_IN_TRIG 0 - system was not powered on by connecting AC adapter

1 - system was powered on by connecting AC adapter

TSD_H 0 - Thermal Shutdown threshold not exceeded

1 - Thermal Shutdown threshold exceeded (cause Power Down sequence)

TSD_L 0 - chip temperature has not been over TSD early warning threshold

1 - chip temperature has been over TSD early warning threshold

FF 0 - Buck output voltage out of range

1 - Buck output voltage within range

BATT_OVER_OUT 0 - battery voltage is in normal range

1- battery voltage is over critical limit

CHGIN_OK_OUT 0 - voltage is not connected to AC adapter input

1 - voltage is connected to AC adapter input

EOC 0 - charging current is above EOC current level

1 - charging current is below EOC current level

TOUT_FULLRATE 0 - no time out occurred in Constant Current mode

1 - time out occurred in Constant Current mode

TOUT_PRECHG 0 - no time out occurred in pre-charge mode

1 - time out occurred in pre-charge mode

FULLRATE 0 - charger is not in CC or CV mode

1 - charger is in CC or CV mode

PRECHG 0 - charger is not in pre-charge mode

1 - charger is in pre-charge mode

TOUT_CONSTV 0 - no time out occurred in Constant Voltage mode

1 - time out occurred in Constant Voltage mode

BAD_BATT 0 - charger has not detected a bad battery

1 - charger has detected a bad battery

www.national.com 16

LP3923

EN_APU_TSD 0 - do not start PMU automatically after TSD event

1 - start PMU automatically after TSD event

PS_HOLD_DELAY 0 - PMU powerdown after PS_HOLD has been low for 35 ms

1 - PMU powerdown after PS_HOLD has been low for 350 ms

LDO OUTPUT VOLTAGE PROGRAMMING

The following table summarizes the supported output voltages for LP3923. Default voltages after start-up sequences have been

highlighted in bold.

Data Code LDO_Vx_OP[x] LDOx [V] Data Code LDO_Vx_OP[x] LDOx [V]

8h'00 1.20 8h'10 2.20

8h'01 1.25 8h'11 2.40

8h'02 1.30 8h'12 2.50

8h'03 1.35 8h'13 2.60

8h'04 1.40 8h'14 2.65

8h'05 1.45 8h'15 2.70

8h'06 1.50 8h'16 2.75

8h'07 1.55 8h'17 2.80

8h08 1.60 8h'18 2.85

8h'09 1.65 8h'19 2.90

8h'0A 1.70 8h'1A 2.95

8h'0B 1.75 8h'1B 3.00*

8h'0C 1.80* 8h'1C 3.05

8h'0D 1.85 8h'1D 3.10

8h'0E 1.90 8h'1E 3.20

8h'0F 2.00 8h'1F 3.3

* See table on page 5.

CHARGING CURRENT PROGRAMMING

The following table summarizes the supported currents for LP3923.

PROG_ ICHG[4] PROG_ ICHG[3] PROG_ ICHG[2] PROG_ ICHG[1] PROG_ ICHG[0] ICHG (mA)

0000050

0 0 0 0 1 100

0 0 0 1 0 150

0 0 0 1 1 200

0 0 1 0 0 250

0 0 1 0 1 300

0 0 1 1 0 350

00111400 (Default)

0 1 0 0 0 450

0 1 0 0 1 500

0 1 0 1 0 550

0 1 0 1 1 600

0 1 1 0 0 650

0 1 1 0 1 700

0 1 1 1 0 750

0 1 1 1 1 800

1 0 0 0 0 850

1 0 0 0 1 900

17 www.national.com

LP3923

PROG_ ICHG[4] PROG_ ICHG[3] PROG_ ICHG[2] PROG_ ICHG[1] PROG_ ICHG[0] ICHG (mA)

1 0 0 1 0 950

1 0 0 1 1 1000

1 0 1 0 0 1050

1 0 1 0 1 1100

1 0 1 1 0 1150

1 0 1 1 1 1200

Charging Termination Voltage Programming

VTERM[1] VTERM[0] VTERM

0 0 4.1

0 1 4.2 (Default)

1 0 4.3

1 1 4.4

End of Charging Current Programming

PROG_EOC[1] PROG_EOC[0] IEOC

0 0 0.05C

0 1 0.1C

1 0 0.15C (Default)

1 1 0.2C

Note: “C” is the programmed charging current.

Charging Restart Voltage Programming

PROG_VRSTRT[1] PROG_VRSTRT[0] Restart Voltage (V)

0 0 VTERM −50 mV

0 1 VTERM −100 mV (Default)

1 0 VTERM −150 mV

1 1 VTERM −200 mV

Charge Timer Programming

PROG_CHGTIME[1] PROG_CHGTIME[0] Charging Timer (Hrs)

0 0 Disabled

0 1 2

1 0 5 (Default)

1 1 8

www.national.com 18

LP3923

BATTERY CHARGE MANAGEMENT

A charge management system allowing safe charge and

maintenance of a Li-Ion battery is implemented on the

LP3923. It has a CC/CV linear charge capability with pro-

grammable battery regulation voltage and end of charging

current threshold. A maintenance mode utilizing pro-

grammable restart voltage levels enables the battery voltage

to be maintained at the correct level. The charging current in

the constant voltage mode is programmable from 50 mA to

1.2A in 50 mA steps.

If PMU is started without a battery, and the battery is attached

later, the charging current should be programmed once more;

otherwise, the charging current will be the same as without a

battery.

If the battery is deeply depleted and the overdischarge pro-

tection circuit is active, during startup the charger may detect

that the battery is not present. This can cause the charger to

select a non-default charging current (LDO mode default

charging current).

CHARGER FUNCTION

Following the correct detection of an input voltage at the

charger pin the charger enters a pre-charge mode. In this

mode a constant current of 50 mA is available to charge the

battery to 2.8V. At this voltage level the charge management

applies the full rate constant current to raise the battery volt-

age to the termination voltage level (default 4.2V). The full-

rate charging current may be programmed to a different level

at this stage. When termination voltage (VTERM) is reached,

the charger is in constant voltage mode and a constant volt-

age of 4.2V is maintained. This mode is complete when the

end of charging current (default 0.15C) is detected and the

charge management enters the maintenance mode. In main-

tenance mode the battery voltage is monitored for the restart

level (default VTERM - 100 mV) and the charge cycle is re-

initiated to re-establish the termination voltage level.

THERMAL SHUTDOWN

The Thermal Shutdown (TSD) function monitors the chip tem-

perature to protect the chip from temperature damage

caused, for example, by excessive power dissipation. If the

temperature exceeds a higher threshold value of +160°C, the

TSD_H bit in the Register 0x0C is set, and the chip will auto-

matically run the Power Down sequence.

The restart operation after Thermal Shutdown can be initiated

only after the chip has cooled down to the +90°C threshold.

The APU_TSD_EN bit in the Register 0x1C is controlling the

restart. If this bit is cleared (default) then a Power On se-

quence is initiated normally through PWR_ON, CHG_IN or

VBUS. If APU_TSD_EN is written to logic 1 then an automatic

Power Up sequence is initiated. All register settings pre-

served in such case. Power On can be activated only if the

junction temperature is less than the early warning lower

threshold +90°C.

The temperature monitoring function has two charger thresh-

old values that result in protective actions. When a lower

threshold of +105°C is exceeded, the TSD_L bit in Register

0x0C will be set, bit will reset it if the temperature has de-

creased to lower than 15°C below the threshold.

When a upper charger threshold of +115°C is exceeded, the

charger will reduce charging current to protect the chip.

Parameter Typ Unit

Higher Threshold

160 °C

Charger Early

Warning *)

105 °C

Early Warning

Hysteresis *)

15 °C

Charger Thermal

Regulation

115 °C

*) Guaranteed by design.

TERMINATION AND RESTART

The termination and restart voltage levels are determined by

the data in the VTERM[1:0] and PROG_VSTRT[1:0] bits in

the control register. The restart voltage is programmed rela-

tive to the selected termination voltage.

19 www.national.com

LP3923

30058634

Simplified Charger Functional State Diagram (when EOC is enabled)

30058607

Charging Cycle Diagram

www.national.com 20

LP3923

IMON CHARGING CURRENT MONITOR

Charging current is monitored within the charger section and

a proportional voltage representation of the charging current

is presented at the IMON output pin. The output voltage re-

lationship to the actual charging current is represented in the

following graph and by the equation:

VIMON(mV) = (2.47 x ICHG(mA))

30058606

Note that this function is not available if there is no input at

CHG_IN or if the charger is off due to the input at CHG_IN

being less than the compliance voltage.

21 www.national.com

LP3923

Buck Converter Application

Information

BUCK OUTPUT VOLTAGE SELECTION

Buck output voltage can be programmed via the selection of

the external feedback resistor network forming the output

feedback between the output voltage side of the inductor and

the FB pin and the FB pin and GND.

30058618

Buck Converter Components

VOUT will be adjusted to make the voltage at FB equal to 0.5V.

The resistor from FB to ground (RFB2) should be around 200

kΩ to keep the current drawn through the resistor network to

a minimum but large enough that it is not susceptible to noise.

If R2 is 200 kΩ and with VFB at 0.5V, the current through the

resistor feedback network will be 2.5 µA.

The formula for output voltage selection is

VOUT - output voltage (V)

VFB - feedback voltage (0.5V)

RFB1 - feedback resistor from VOUT to FB

RFB2 - feedback resistor from FB to GND

The recommended value for C1 is 2.2 pF to 5.1 pF, and for

C2 is 15 pF.

Component Configurations for Various Output Voltage Values

VOUT [V] RFB1 [kΩ] RFB2 [kΩ] C1 [pF] C2 [pF] L [µH] COUT [µF]

1.4 360 200 2.2 to 5.1 15 2.2 10

1.6 390 178 2.2 to 5.1 15 2.2 10

1.8 390 150 2.2 to 5.1 15 2.2 10

2.0 453 150 2.2 to 5.1 15 2.2 10

INDUCTOR SELECTION

There are two main considerations when choosing an induc-

tor; the inductor should not saturate, and the inductor current

ripple is small enough to achieve the desired output voltage

ripple. Different saturation current rating specs are followed

by different manufacturers so attention must be given to de-

tails. Saturation current ratings are typically given at 25°C so

ratings at the application maximum ambient temperature

should be requested from the manufacturer.

There are two methods to choose the inductor saturation cur-

rent rating.

Method 1

The total current is the sum of the load and the inductor ripple

current. This can be written as:

ILOAD = load current

IRIPPLE = average to peak inductor current

VIN = input voltage

L= inductor inductance

f= switching frequency

Method 2

A more conservative approach is to choose an inductor that

can handle the maximum current limit of 1500 mA. Given a

peak-to-peak current ripple (IPP) the inductor needs to be at

least:

A 2.2 µH inductor with a saturation current rating of at least

1500 mA is recommended for most applications. The

inductor’s resistance should be less than 0.3Ω for good effi-

ciency. The below table suggests inductors and suppliers.

For low-cost applications, an unshielded bobbin inductor is

suggested. For noise critical applications, a toroidal or shield-

ed-bobbin inductor should be used. A good practice is to lay

out the board with overlapping footprints of both types for de-

sign flexibility. This allows substitution of a low-noise toroidal

inductor, in the event that noise from low-cost bobbin models

is unacceptable.

www.national.com 22

LP3923

Suggested Inductors and Their Suppliers (Preliminary and Untested)

Model Vendor Dimensions (mm) DC R(max)

DO3314-222MXC Coilcraft 3.3 x 3.3 x 1.4 200 mΩ

LPO3310-222MX Coilcraft 3.3 x 3.3 x 1.0 150 mΩ

ELL5GM2R2N Panasonic 5.2 x 5.2 x x 1.5 53 mΩ

CDRH2D142R2 Sumida 3.2 x 3.2 x 1.55 94 mΩ

INPUT CAPACITOR SELECTION

A ceramic input capacitor of 10 µF is sufficient for most ap-

plications. A larger value may be used for improved input

voltage filtering. Use X7R or X5R type capacitors, do not use

Y5V. The DC bias characteristics of ceramic capacitors must

be considered when selecting case sizes of 0805 or smaller

for use in the application. Smaller case sizes in many cases

exhibit a large drop in capacitance value as the DC bias in-

creases.

The input filter capacitor supplies current to the PFET switch

of the converter in the first half of each cycle and reduces

voltage ripple imposed on the input power source. A ceramic

capacitor’s low ESR provides the best noise filtering of the

input voltage spikes due to this rapidly changing current. Se-

lect an input filter capacitor with a surge current rating suffi-

cient for the power-up surge from the input power source. The

power-up surge current is approximately the capacitor’s value

(µF) times the voltage rise rate (V/µs).

The input current ripple can be calculated as:

The worst case IRMS is:

OUTPUT CAPACITOR SELECTION

A 10 µF capacitor is recommended for use at the output of the

buck converter. Use X7R or X5R type capacitors; do not use

Y5V. The DC bias characteristics of ceramic capacitors must

be considered when selecting case sizes of 0805 or smaller

for use in the application. Smaller case sizes in many cases

exhibit a large drop in capacitance value as the DC bias in-

creases. DC bias characteristics vary from manufacturer to

manufacturer and dc bias curves should be requested from

them as part of the capacitor selection process.

The output filter capacitor smooths out current flow from the

inductor to the load, helps maintain a steady output voltage

during transient load changes and reduces output voltage

ripple. These capacitors must be selected with sufficient ca-

pacitance and sufficiently low ESR to perform these functions.

The output voltage ripple is caused by the charging and dis-

charging of the output capacitor and also due to its ESR. It

can be calculated as:

Voltage peak to peak ripple due to capacitance =

Voltage peak to peak ripple due to ESR =

VPP-ESR = IPP*RESR

Voltage peak to peak ripple, root mean squared =

Note that the output ripple is dependent on the inductor cur-

rent ripple and the equivalent series resistance of the output

capacitor (RESR). Because these two components are out of

phase the rms value is used. The RESR is frequency depen-

dent (as well as temperature dependent); make sure the

frequency of the RESR given is the same order of magnitude

as the switching frequency.

Suggested Capacitors And Their Suppliers

Model Type Vendor Voltage Rating Case Size

10 µF (CIN and COUT)

GRM21BR60J106k Ceramic, X5R MURATA 6.3V 0805

JMK212BJ106K Ceramic, X5R TAIYO YUDEN 6.3V 0805

C2012X5R0J106K Ceramic, X5R TDK 6.3V 0805

23 www.national.com

LP3923

LDO Information

OPERATIONAL INFORMATION

The LP3923 has eight LDOs of which 4 are enabled by default

and powered up during the power up sequence, LDOs 1, 2,

3 and 7 are powered up during the power up sequence. LDOs

4, 5, and 6 are separately externally enabled and will follow

LDO3 in start up if their respective enable pin is pulled high.

LDO1, LDO2, LDO7 and LDO8 can be enabled/disabled via

the Serial Interface

LDO3 must remain in regulation otherwise the device will

power down.

The LILO-type LDO is optimized for low output voltage and

for good dynamic performance to supply different fast charg-

ing (digital) pads.

INPUT VOLTAGES

There are two input voltage pins used to power the eight LDOs

on the LP3923. VIN1 is the supply for LDO1 and LDO2. VIN2

is the supply for LDO3, LDO4, LDO5, LDO6, LDO7, and

LDO8.

EXTERNAL CAPACITORS

The Low Drop Out Linear Voltage regulators on the LP3923

require external capacitors to ensure stable outputs. The

LDOs on the LP3923 are specifically designed to use small

surface mount ceramic capacitors which require minimum

board space. These capacitors must be correctly selected for

good performance.

INPUT CAPACITOR

Input capacitors are required for correct operation. It is rec-

ommended that a 10 µF capacitor be connected between

each of the voltage input pins and ground (this capacitance

value may be increased without limit).

This capacitor must be located a distance of not more than 1

cm from the input pin and returned to a clean analogue

ground. A ceramic capacitor is recommended although a

good quality tantalum or film capacitor may be used at the

input.

Important: Tantalum capacitors can suffer catastrophic fail-

ures due to surge current when connected to a low-

impedance source of power (like a battery or a very large

capacitor). If a tantalum capacitor is used at the input, it must

be guaranteed by the manufacturer to have a surge current

rating sufficient for the application.

There are no requirements for the ESR (Equivalent Series

Resistance) on the input capacitor, but tolerance and tem-

perature coefficient must be considered when selecting the

capacitor to ensure the capacitance will remain within its op-

erational range over the entire operating temperature range

and conditions.

OUTPUT CAPACITOR

Correct selection of the output capacitor is critical to ensure

stable operation in the intended application.

The output capacitor must meet all the requirements specified

in the recommended capacitor table over all conditions in the

application. These conditions include DC-bias, frequency and

temperature. Unstable operation will result if the capacitance

drops below the minimum specified value.

The LP3923 is designed specifically to work with very small

ceramic output capacitors. The LDOs on the LP3923 are

specifically designed to be used with X7R and X5R type ca-

pacitors. With these capacitors, selection of the capacitor for

the application is dependant on the range of operating con-

ditions and temperature range for that application. (See sec-

tion on Capacitor Characteristics).

It is also recommended that the output capacitor be placed

within 1 cm from the output pin and returned to a clean ground

line.

CAPACITOR CHARACTERISTICS

The LDOs on the LP3923 are designed to work with ceramic

capacitors on the input and output to take advantage of the

benefits they offer. For capacitance values around 1µF, ce-

ramic capacitors give the circuit designer the best design

options in terms of low cost and minimal area.

For both input and output capacitors careful interpretation of

the capacitor specification is required to ensure correct device

operation. The capacitor value can change greatly dependant

on the conditions of operation and capacitor type.

In particular, to ensure stability, the output capacitor selection

should take account of all the capacitor parameters to ensure

that the specification is met within the application. Capaci-

tance value can vary with DC bias conditions as well as

temperature and frequency of operation. Capacitor values will

also show some decrease over time due to aging. The ca-

pacitor parameters are also dependant on the particular case

size with smaller sizes giving poorer performance figures in

general.

As an example shows a typical graph showing a comparison

of capacitor case sizes in a Capacitance vs. DC Bias plot. As

shown in the graph, as a result of the DC Bias condition the

capacitance value may drop below the minimum capacitance

value given in the recommended capacitor table (0.7 µF in

this case). Note that the graph shows the capacitance out of

spec for the 0402 case size capacitor at higher bias voltages.

It is therefore recommended that the capacitor manufacturers'

specifications for the nominal value capacitor are consulted

for all conditions as some capacitor sizes (e.g. 0402) may not

be suitable in the actual application.

30058616

FIGURE 2. Graph Showing A Typical Variation in

Capacitance vs DC Bias

Ceramic capacitors have the lowest ESR values, thus making

them best for eliminating high frequency noise. The ESR of a

typical 1 µF ceramic capacitor is in the range of 10 mΩ to

40 mΩ, and also meets the ESR requirement for stability.

The temperature performance of ceramic capacitors varies by

type. Capacitor type X7R is specified with a tolerance of ±15%

www.national.com 24

LP3923

over the temperature range –55°C to +125°C. The X5R has

a similar tolerance over the reduced temperature range of –

55°C to +85°C. Most large value ceramic capacitors (≥ 2.2

µF) are manufactured with Z5U or Y5V temperature charac-

teristics, which results in the capacitance dropping by more

than 50% as the temperature goes from +25°C to +85°C.

Therefore X7R is recommended over these other capacitor

types in applications where the temperature will change sig-

nificantly above or below +25°C.

No-Load Stability

The LDOs on the LP3923 will remain stable and in regulation

with no external load.

LDO Output Capacitors, Recommended Specification

Symbol Parameter Type Typ Min Max Units

CO(LDO1) Capacitance X5R, X7R 1.0 0.7 2.2 µF

CO(LDO2) Capacitance X5R, X7R 1.0 0.7 2.2 µF

CO(LDO3) Capacitance X5R, X7R 1.0 0.7 2.2 µF

CO(LDO4) Capacitance X5R, X7R 1.0 0.7 2.2 µF

CO(LDO5) Capacitance X5R, X7R 1.0 0.7 2.2 µF

CO(LDO6) Capacitance X5R, X7R 1.0 0.7 2.2 µF

CO(LDO7) Capacitance X5R, X7R 1.0 0.7 2.2 µF

CO(LDO8) Capacitance X5R, X7R 1.0 0.7 2.2 µF

Note: Note: The capacitor tolerance should be 30% or better over the full temperature range. X7R, or X5R capacitors should be used. These specifications are

given to ensure stability of the supply outputs and care must be taken to ensure that the capacitance remains within these values over all conditions within

the application. See Capacitor Characteristics section in Application Information.

25 www.national.com

LP3923

30058602

FIGURE 3. Typical Application Circuit

(Buck Output used as input for LILOs)

www.national.com 26

LP3923

I2C Compatible Serial Bus Interface

INTERFACE BUS OVERVIEW

The I2C compatible synchronous serial interface provides ac-

cess to the programmable functions and registers on the

device.

This protocol uses a two-wire interface for bi-directional com-

munications between the IC’s connected to the bus. The two

interface lines are the Serial Data Line (SDA), and the Serial

Clock Line (SCL). These lines should be connected to a pos-

itive supply, via a pull-up resistor of 1.5 kΩ, and remain HIGH

even when the bus is idle.

Every device on the bus is assigned a unique address and

acts as either a Master or a Slave depending on whether it

generates or receives the serial clock (SCL).

DATA TRANSACTIONS

One data bit is transferred during each clock pulse. Data is

sampled during the high state of the serial clock (SCL). Con-

sequently, throughout the clock’s high period, the data should

remain stable. Any changes on the SDA line during the high

state of the SCL and in the middle of a transaction, aborts the

current transaction. New data should be sent during the low

SCL state. This protocol permits a single data line to transfer

both command/control information and data using the syn-

chronous serial clock.

30058627

FIGURE 4. Bit Transfer

Each data transaction is composed of a Start Condition, a

number of byte transfers (set by the software) and a Stop

Condition to terminate the transaction. Every byte written to

the SDA bus must be 8 bits long and is transferred with the

most significant bit first. After each byte, an Acknowledge sig-

nal must follow. The following sections provide further details

of this process.

START AND STOP

The Master device on the bus always generates the Start and

Stop Conditions (control codes). After a Start Condition is

generated, the bus is considered busy and it retains this sta-

tus until a certain time after a Stop Condition is generated. A

high-to-low transition of the data line (SDA) while the clock

(SCL) is high indicates a Start Condition. A low-to-high tran-

sition of the SDA line while the SCL is high indicates a Stop

Condition.

30058610

FIGURE 5. Start and Stop Conditions

In addition to the first Start Condition, a repeated Start Con-

dition can be generated in the middle of a transaction. This

allows another device to be accessed, or a register read cycle.

ACKNOWLEDGE CYCLE

The Acknowledge Cycle consists of two signals: the acknowl-

edge clock pulse the master sends with each byte transferred,

and the acknowledge signal sent by the receiving device.

The master generates the acknowledge clock pulse on the

ninth clock pulse of the byte transfer. The transmitter releases

the SDA line (permits it to go high) to allow the receiver to

send the acknowledge signal. The receiver must pull down

the SDA line during the acknowledge clock pulse and ensure

that SDA remains low during the high period of the clock

pulse, thus signaling the correct reception of the last data byte

and its readiness to receive the next byte.

30058628

FIGURE 6. Bus Acknowledge Cycle

27 www.national.com

LP3923

”ACKNOWLEDGE AFTER EVERY BYTE” RULE

The master generates an acknowledge clock pulse after each

byte transfer. The receiver sends an acknowledge signal after

every byte received.

There is one exception to the “acknowledge after every byte”

rule.

When the master is the receiver, it must indicate to the trans-

mitter an end of data by not-acknowledging (“negative ac-

knowledge”) the last byte clocked out of the slave. This

“negative acknowledge” still includes the acknowledge clock

pulse (generated by the master), but the SDA line is not pulled

down.

ADDRESSING TRANSFER FORMATS

Each device on the bus has a unique slave address. The

LP3923 operates as a slave device with the address 7h’7E

(binary nnnnnnnn). Before any data is transmitted, the master

transmits the address of the slave being addressed. The slave

device should send an acknowledge signal on the SDA line,

once it recognizes its address.

The slave address is the first seven bits after a Start Condi-

tion. The direction of the data transfer (R/W) depends on the

bit sent after the slave address — the eighth bit.

When the slave address is sent, each device in the system

compares this slave address with its own. If there is a match,

the device considers itself addressed and sends an acknowl-

edge signal. Depending upon the state of the R/W bit (1:read,

0:write), the device acts as a transmitter or a receiver.

CONTROL REGISTER WRITE CYCLE

•Master device generates start condition.

•Master device sends slave address (7 bits) and the data

direction bit (r/w = '0').

•Slave device sends acknowledge signal if the slave

address is correct.

•Master sends control register address (8 bits).

•Slave sends acknowledge signal.

•Master sends data byte to be written to the addressed

•Slave sends acknowledge signal.

•If master will send further data bytes the control register

address will be incremented by one after acknowledge

signal.

•Write cycle ends when the master creates stop condition.

CONTROL REGISTER READ CYCLE

•Master device generates a start condition.

•Master device sends slave address (7 bits) and the data

direction bit (r/w = '0').

•Slave device sends acknowledge signal if the slave

address is correct.

•Master sends control register address (8 bits).

•Slave sends acknowledge signal.

•Master device generates repeated start condition.

•Master sends the slave address (7 bits) and the data

direction bit (r/w = “1”).

•Slave sends acknowledge signal if the slave address is

correct.

•Slave sends data byte from addressed register.

•If the master device sends acknowledge signal, the control

sends data byte from addressed register.

•Read cycle ends when the master does not generate

acknowledge signal after data byte and generates stop

condition.

Address Mode

Data Read <Start Condition>

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Slave Address><r/w = ‘1’>[Ack]

[Register Data]<Ack or NAck>

… additional reads from subsequent register

address possible

Data Write <Start Condition>

<Slave Address><r/w = ‘0’>[Ack]

<Register Addr.>[Ack]

<Register Data>[Ack]

… additional writes to subsequent register

address possible

< > Data from master [ ] Data from slave

www.national.com 28

LP3923

30058629

FIGURE 7. Register Write Format

30058630

FIGURE 8. Register Read Format

29 www.national.com

LP3923

Physical Dimensions inches (millimeters) unless otherwise noted

Thin Micro SMD 30Package

NS Package Number MKT-TLA3011A

X1 = 2.466 mm ±0.030 mm

X2 = 2.974 mm ±0.030 mm

X3 = 0.600 mm ±0.075 mm

www.national.com 30

LP3923

Notes

31 www.national.com

LP3923

Notes

LP3923 Cellular Phone Power Management Unit

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