SCOPE: CMOS HIGHSPEED 8-BIT A/D CONVERTER WI TH TRACK AND HOLD
Device Type Generic Number
01 MX7824T(x)/883B
02 MX7824U(x)/883B
Case Outline(s). The case outlines shall be designated in Mil-Std-1835 and as follows:
Outline Letter Mil-Std-1835 Case Outline Package Code
MAXIM SMD
Q L GDIP1-T24 or CDIP2-T24 24 LEAD CERDIP J24
A bsolu te Maximum Ratings
Supply Voltage to GND ................................................................................….. 0V, +7V
Digital Input Voltage ...............................................................................…... -0.3V, VDD
Digital Output Voltage ................................................................................... -0.3V, VDD
Positive Reference Voltage ...................................................................... VREF- to VDD
Negative Reference Voltage ..................................................................... 0V to VREF+
Input Voltage (VIN) ..................................................................................... -0.3V to VDD
Lead Temperature (soldering, 10 seconds) ............................................................... +300°C
Storage Temperature .................................................................................. -65°C to +150 °C
Continuous Power Dissipation ............................................................................ TA=+70°C
24 pin CERDIP(derate 12.5mW/°C above +70°C) ................................................ 1000mW
Junct ion Temper atur e TJ ........................................................................................ +150°C
Thermal Resista nce, J unction to Case, ΘJC
24 pin CERDIP.................................................................................................... 40°C/W
Thermal Resistance, Junction to Ambient, ΘJA:
24 pin CERDIP................................................................................................... 80°C/W
Recommended Operating Co ndit ions
Ambient Operating Range (TA) ......................................................….... -55°C to +125°C
Supply Voltage Range (VDD) ............................................................…... +4.75V to 5.25V
Positive Reference Voltage (VREF+) ................................................................…... +5.0V
Negative Reference Voltage (VREF-) ....................................................................….... 0V
Ground Potential (GND) .......................................................................................……. 0V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those indicated in the operational section s of the sp ecifica tions is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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TABLE 1. ELECTRICAL TE STS:
TEST Symbol
CONDITIONS
-55 °C TA +125°C 1/ 2/
Unless otherwise specified Group A
Subgroup Device
type Limits
Min Limits
Max Units
Resolution RES Guaranteed but not tested 1,2,3 All 8LSB
Total Unadjusted Error
NOTE 3 TUE 1,2,3 01
02
±1.0
±0.5 LSB
Analog Input Voltage
Range VIN 1All
VREF- VREF+ V
Analog Input Leakage
Current IIN 1,2,3 All -3.0 +3.0 µA
Analog Input Capacitance CIN1 0V, 5V, NOTE 4 4 All 45 pF
Reference Input Resistance RIN NOTE 4 1,2,3 All 1.0 4.0 k
Digital Input High Level
Voltage VIH ___ __
A0, A1, RD, CS 1,2,3 All 2.4 V
Digital Input Low Level
Voltage VIL ___ __
A0, A1, RD, CS 1,2,3 All 0.8 V
Digital Input High Current IIH ___ __
A0, A1, RD, CS 1,2,3 All 1.0 µA
Digital Input Low Current IIL ___ __
A0, A1, RD, CS 1,2,3 All -1.0 µA
Digital Input Capacitance CIN2 ___ __ NOTE 4
A0, A1, RD, CS 4All 8.0 pF
Digital O utput High Level
Voltage VOH ___
DB0-DB7, INT, ISOURCE=360µA1,2,3 All 4.0 V
Digital Output Low Level
Voltage VOL ___
DB0-DB7, INT, ISINK=1.6mA
RDY, ISINK=2.6mA, NOTE 5 1,2,3 All
0.4
0.4 V
Floating State Leakage
Current IOUT DB0-DB7 only 1,2,3 All ±3.0 µA
Slew Rate, Tracking
Capacitance NOTE 4 4All 0.157 V/µs
Digital Output Capacitance COUT NOTE 4 4 All 8.0 pF
Supply Current IDD __ ___
CS=RD=2.4V 1,2,3 All 20.0 mA
Power Supply Sensitivity PSS VDD=5.0V±5% 1,2,3 All ±0.25 LSB
__ __
CS to RD Setup Time tCSS Figure 3 9,10,11 All 0ns
__ __
CS to RD Hold Time tCSH Figure 3 9,10,11 All 0ns
__
CS to RDY delay tRDY Pull-up resistor=5k, CL=50pF,
Figure 3 9
10,11 All 40
60 ns
Conversion Time, Mode 0 tCRD See Figure 3. NOTE 7 9
10,11 All 2.0
2.8 µs
Data Access Time __
After RD,
Mode 1
tACC1 NOTE 6 and 7
Figure 3 and 5 9
10,11 All 85
120 ns
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TEST Symbol
CONDITIONS
-55 °C TA +125°C 1/ 2/
Unless otherwise specified Group A
Subgroup Device
type Limits
Min Limits
Max Units
__ ___
RD to INT Delay, NOTE 5 tINTH CL=50pF 9
10,11 All 75
100 ns
Data Hold Time tDH NOTE 8, Figure 3,4 9
10,11 All 60
70 ns
Delay Time Between
Conversion tPFigure 3 9
10,11 All 500
600 ns
Read Pulse Width, Mode 1 tRD Figure 3 9
10,11 All 60
80 600
400 ns
Data Access Time After
___
INT, Mode 0
tACC2 NOTE 6, 7, Figure 3,5 9
10,11 All 50
70 ns
Multiplexer Address Setup
Time tAS Figure 3 9,10,11 All 0ns
Multiplexer Address Hold
Time tAH Figure 3 9
10,11 All 30
40 ns
NOTE 1: VDD=+5V, VREF(+)=+5V; VREF(-)=GND=0V, unless otherwise specified.
Specifications apply for mode 0. All input control signals are specified with tr=tf=20ns
(10 percent to 90 percent of +5.0V) and timed from a voltage level of 1.6V.
NOTE 2: Subgroups 10 and 1 1, if not tested, shall be guara nteed to the li mits specified in Table 1 .
NOTE 3: Total unadjusted error includes offset, full-scale, and linearity errors.
NOTE 4: The (CIN1, C IN2, RIN, COUT, and SR measurements) are measured initially and after any process
or design changes which may affect these tests.
NOTE 5: RDY is an open-drain output.
NOTE 6: Measured with load circuits of Figure 5 and defined as the time
required for an output to cross 0.8V or 2.4V.
NOTE 7: If not tested, it shall be guaranteed to the limits specified in Table 1.
NOTE 8: Defined as the time required for the data lines to change 0.5V when loaded with the circuits of
Figure 4 and is measured only for the initial test and after process or design change which may affect tDH.
TERMINAL CONNECTIONS
J24 J24
1AIN4 13VREF-
2AIN3 14VREF+
3AIN2 15RDY
4AIN1 16__
CS
5NC 17DB4
6DB0 18DB5
7DB1 19DB6
8DB2 20DB7
9DB3 21A1
10 __
RD 22 A0
11 ___
INT 23 NC
12 GND 24 VDD
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Package ORDERING INFORMATION: SMD NUMBER
01 24 pin CERDIP MX7824TQ/883B 5962-8876401LA
02 24 pin CERDIP MX7824UQ/883B 5962-8876402LA
MODE SELEC TION TAB LE
CHANNEL A1 A0
AIN1 0 0
AIN2 0 1
AIN3 1 0
AIN4 1 1
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QUALITY ASSURAN CE
Sampling and inspection procedures shall be in accordance with MIL-Prf-38535, Appendix A as specified in Mil-
Std-883.
Screening shall be in accordance wit h Method 5004 of Mil-Std-883. Burn-in test Method 1015:
1. Test Condition, A, B, C, or D.
2. TA = +125°C minimum.
3. Interim and final electrical test requirements shall be specified in Table 2.
Quality conformance inspection shall be in accordance with Method 5005 of Mil-Std-883, including Groups A, B,
C, and D inspection.
Group A inspection:
1. Tests as specified in Table 2.
2. Selected subgroups in Table 1, Method 5005 of Mil-Std-883 shall be omitted.
Group C and D inspections:
a. End-point electrical parameters shall be specified in Table 1.
b. Steady-state life te st, Method 1005 of Mil-Std -883:
1. Test condition A, B, C, D.
2. TA = +125°C, minimum.
3. Test duration, 1000 hours, except as permitted by Method 1005 of Mil-Std-883.
TABLE 2. ELECTRICAL TEST REQUIR EMENTS
Mil-Std-883 Test Requirements Subgroups
per Method 5005, Table 1
Interim Electric Parameters
Method 5004 1
Final Electrical Parameters
Method 5005 1*, 2, 3, 4**, 9, 10, 11***
Group A Test Requirements
Method 5005 1, 2, 3, 4**, 9, 10, 11***
Group C and D End-Point Electrical Parameters
Method 5005 1
* PDA applies to Subgroup 1 only.
** Subgroup 4, Capacitance tests are performed at initial qual and upon redesign.
Sample size will be 116 units.
*** Subgroups 10 and 11 if not tested, are guaranteed to the limits specified in Table 1.
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