VIPer100B022Y - STMicroelectronics

VIPer100B

VIPer100BSP

SMPS PRIMARY I.C.

February 2001

BLOCK DIAGRAM

TYPE VDSS InRDS(on)

VIPer100B/BSP 400V 6 A 1.1 Ω

FEATURE

■ADJUSTABLESWITCHING FREQUENCYUP

TO200KHZ

■CURRENT MODE CONTROL

■SOFTSTARTAND SHUTDOWNCONTROL

■AUTOMATIC BURST MODEOPERATION IN

STAND-BYCONDITION ABLETO MEET

”BLUEANGEL”NORM (<1W TOTAL POWER

CONSUMPTION)

■INTERNALLY TRIMMED ZENER

REFERENCE

■UNDERVOLTAGELOCK-OUTWITH

HYSTERESIS

■INTEGRATED START-UPSUPPLY

■AVALANCHERUGGED

■OVERTEMPERATUREPROTECTION

■LOWSTAND-BY CURRENT

■ADJUSTABLECURRENT LIMITATION

DESCRIPTION

VIPer100B/100BSP, made using VIPower M0

Technology,combines on the same silicon chip a

state-of-the-art PWM circuit together with an

optimized high voltage avalanche rugged Vertical

Power MOSFET (400 V / 6 A). Typical

applications cover off line power supplies with

a secondary power capability of 100 W in a US

mains lines configuration. It is compatible from

both primary or secondaryregulation loop despite

using around 50% less components when

compared with a discrete solution. Burst mode

operation is an additional feature of this device,

offering the possibility to operate in stand-by

modewithoutextra components.

PowerSO-10

PENTAWATT HV PENTAWATT HV

(022Y)

FC00231

VDD

OSC

COMP

DRAIN

SOURCE

13 V

UVLO

LOGIC

SECURITY

LATCH PWM

LATCH

R/S SQS

R2 R3Q

OSCILLATOR

OVERTEMP.

DETECTOR

ERROR

AMPLIFIER_

0.5 V +

_1.7

µs

DELAY 250 ns

BLANKING CURRENT

AMPLIFIER

ON/OFF

0.5V

0.5V/A

4.5 V



1/22

ABSOLUTE MAXIMUM RATING

Symbol Parameter Value Unit

VDS Continuous Drain-Source Voltage (Tj = 25 to 125oC)

for VIPer100B/BSP -0.3 to 400 V

IDMaximum Current Internally Limited A

VDD Supply Voltage 0 to 15 V

VOSC Voltage Range Input 0 to VDD V

VCOMP Voltage Range Input 0 to 5 V

ICOMP Maximum Continuous Current ±2mA

esd Electrostatic discharge (R = 1.5 KΩC = 100pF) 4000 V

ID(AR) Avalanche Drain-Source Current, Repetitive or Not-Repetitive

(TC = 100 oC, Pulse Width Limited by TJmax, δ <1%)

for VIPer100B/BSP TBD A

Ptot Power Dissipation at Tc = 25oC82W

Junction Operating Temperature Internally Limited oC

Tstg Storage Temperature -65 to 150 oC

THERMALDATA

PENTAWATT-HV PowerSO-10(*)

Rthj-case Thermal Resistance Junction-case Max 1.4 1.4 oC/W

Rthj-amb. Thermal Resistance Ambient-case Max 60 50 oC/W

(*) When mounted using the minimum recommended pad size on FR-4 board.

CURRENT AND VOLTAGE CONVENTIONS

13V

OSC

COMP SOURCE

DRAINVDD

VCOMP

VOSC

VDD VDS

ICOMP

IOSC

IDD ID

FC00020

CONNECTIONDIAGRAMS (Top View)

PENTAWATT HV PENTAWATTHV (022Y) PowerSO-10

VIPer100B/BSP

2/22

PINSFUNCTIONAL DESCRIPTION

DRAIN PIN:

Integrated power MOSFET drain pin. It provides

internal bias current during start-up via an

integrated high voltage current source which is

switched off during normal operation. The device

is able to handle an unclamped current during its

normal operation,assuring self protection against

voltage surges, PCB stray inductance, and

allowing a snubberless operation for low output

power.

SOURCEPIN:

Power MOSFET source pin. Primary side circuit

commonground connection.

VDD PIN:

This pin providestwo functions:

-It corresponds to the low voltage supply of the

control part of the circuit. If VDD goesbelow 8V,

the start-up current source is activated and the

output power MOSFET is switched off until the

VDD voltage reaches 11V. During this phase,

the internal current consumption is reduced,

the VDD pin is sourcing a current of about 2mA

and the COMP pin is shorted to ground. After

that, the current source is shut down, and the

devicetries to start up by switchingagain.

-This pin is also connectedto the error amplifier,

in order to allow primary as well as secondary

regulation configurations. In case of primary

regulation, an internal 13V trimmed reference

voltage is used to maintain VDD at 13V. For

secondary regulation, a voltage between 8.5V

and 12.5V will be puton VDD pin by transformer

design, in order to stuck the output of the

transconductance amplifier to the high state.

The COMP pin behaves as a constant current

source, and can easily be connected to the

output of an optocoupler. Note that any

overvoltagedue to regulation loop failure is still

detected by the error amplifier through the VDD

voltage, which cannot overpass 13V. The

output voltage will be somewhat higher than

the nominal one, but still under control.

COMPPIN :

This pin providestwo functions:

-It is the output of the error transconductance

amplifier, and allows for the connection of a

compensation network to provide the desired

transfer function of the regulation loop. Its

bandwidth can be easily adjusted to the

needed value with usual componentsvalue. As

stated above, secondary regulation

configurations are also implemented through

the COMPpin.

-When the COMP voltage is going below 0.5V,

the shut-down of the circuit occurs, with a zero

duty cycle for the power MOSFET. This feature

can be used to switch off the converter,and is

automatically activated by the regulation loop

(whatever is the configuration) to provide a

burst mode operation in case of negligible

outputpower or open load condition.

OSC PIN :

An RT-CTnetworkmust be connectedon that pin

to define the switching frequency. Note that

despitethe connectionof RTto VDD, no significant

frequencychangeoccurs for VDD varyingfrom 8V

to 15V. It provides also a synchronisation

capability, when connected to an external

frequencysource.

ORDERINGNUMBERS

PENTAWATT HV PENTAWATT HV (022Y) PowerSO-10

VIPer100B VIPer100B (022Y) VIPer100BSP

VIPer100B/BSP

3/22

AVALANCHE CHARACTERISTICS

Symbol Parameter Max Value Unit

ID(ar) Avalanche Current, Repetitive or Not-Repetitive

(pulse width limited by Tjmax, δ <1%)

for VIPer100B/BSP TBD

TBD A

E(ar) Single Pulse Avalanche Energy

(starting Tj=25o

C, ID=I

D(ar))(seefig.12) TBD mJ

ELECTRICAL CHARACTERISTICS (TJ=25o

C, VDD = 13 V,unless otherwisespecified)

POWERSECTION

Symbol Parameter Test Conditions Min. Typ. Max. Unit

BVDSS Drain-Source Voltage ID=1mA V

COMP = 0 V 400 V

IDSS Off-State Drain Current VCOMP =0V T

= 125 oC

VDS =400V 1 mA

DS(on) Static Drain Source on

Resistance ID=4A

D=4A T

J=100o

C0.9 1.1

2Ω

Ω

tfFall Time ID = 0.2 A Vin = 300 V (1)

(see fig.3) 100 ns

trRise Time ID=4A V

in = 300 V (1)

(see fig. 3) 50 ns

COSS Output Capacitance VDS = 25 V 180 pF

(1) On InductiveLoad, Clamped.

SUPPLYSECTION

Symbol Parameter Test Conditions Min. Typ. Max. Unit

IDDch Start-up Charging

Current VDD =5V V

DS =70V

(see fig. 2 and fig. 15) -2 mA

IDD0 Operating Supply Current VDD =12V, F

SW =0KHz

(see fig. 2) 12 16 mA

IDD1 Operating Supply Current VDD =12V, F

SW = 100 KHz 15.5 mA

IDD2 Operating Supply Current VDD =12V, F

SW =200KHz 19 mA

DDoff Undervoltage Shutdown (see fig. 2) 8 9 V

VDDon Undervoltage Reset (see fig. 2) 11 12 V

VDDhyst Hysteresis Start-up (see fig. 2) 2.4 3 V

VIPer100B/BSP

4/22

ELECTRICAL CHARACTERISTICS (continued)

OSCILLATORSECTION

Symbol Parameter Test Conditions Min. Typ. Max. Unit

FSW Oscillator Frequency

Total Variation RT=8.2K

Ω

CT=2.4 nF

VDD =9to15V

with RT± 1% CT ± 5%

(see fig. 6 and fig. 9)

90 100 110 KHz

VOSCih Oscillator Peak Voltage 7.1 V

VOSCil Oscillator Valley Voltage 3.7 V

ERRORAMPLIFIER SECTION

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VDDreg Vg Regulation Point ICOMP = 0 mA (see fig.1) 12.6 13 13.4 V

∆VDDreg Total Variation TJ=0to100o

C2%

BW Unity Gain Bandwidth From Input = VDD to Output = VCOMP

COMP pin is open (see fig. 10) 150 KHz

AVOL Open Loop Voltage

Gain COMP pin is open (see fig. 10) 45 52 dB

GmDC Transconductance VCOMP = 2.5 V (see fig. 1) 1.1 1.5 1.9 mA/V

VCOMPLO Output Low Level ICOMP = -400 µAV

DD =14V 0.2 V

VCOMPHI Output High Level ICOMP = 400 µAV

DD =12V 4.5 V

ICOMPLO Output Low Current

Capability VCOMP =2.5V V

DD =14V -600 µ

COMPHI Output High Current

Capability VCOMP =2.5V V

DD = 12 V 600 µA

PWM COMPARATORSECTION

Symbol Parameter Test Conditions Min. Typ. Max. Unit

HID ∆VCOMP/∆IDpeak VCOMP = 1 to 3 V 0.35 0.5 0.65 V/A

VCOMPoff VCOMP offset IDpeak =10mA 0.5 V

Dpeak Peak Current Limitation VDD =12V COMPpinopen 6 8 11 A

dCurrent Sense Delay

to turn-off ID= 1 A 250 ns

tbBlanking Time 250 360 ns

ton(min) Minimum on Time 350 ns

SHUTDOWNAND OVERTEMPERATURESECTION

Symbol Parameter Test Conditions Min. Typ. Max. Unit

VCOMPth Restart threshold (see fig. 4) 0.5 V

tDISsu Disable Set Up Time (see fig. 4) 1.7 5 µs

Ttsd Thermal Shutdown

Temperature (see fig. 8) 140 170 oC

Thyst Thermal Shutdown

Hysteresis (see fig. 8) 40 oC

VIPer100B/BSP

5/22

Figure 1:V

DD RegulationPoint

ICOMP

ICOMPHI

ICOMPLO VDDreg

0VDD

Slope =

Gm inmA/V

FC00150

Figure 3: TransitionTime

VDS

tf tr

10%Ipeak

10%VD

90%VD

FC00160

Figure 2: UndervoltageLockout

VDDon

IDDch

IDD0

VDD

VDDoff

VDS =70V

Fsw = 0

IDD

VDDhyst

FC00170

Figure 4: Shut Down Action

VCOMP

VOS C

tDIS s u

ENABLE DIS ABLEENABLE

VCOMPth

F C00060

Figure5: BreakdownVoltagevs Temperature Figure 6: TypicalFrequencyVariation

Temper atur e ( °C)

FC00180

0 20 40 60 80 100 120

0.95

1.05

1.1

1.15

DS S

(Normalized)

Temperatur e (°C)

0 20 40 60 80 100 120 140

-5

-4

-3

-2

-1

1F C00190

(%)

VIPer100B/BSP

6/22

Figure 8: OvertemperatureProtection

Vdd

Vcomp

Ttsd

Ttsd-Thyst

Vddon

Vddoff

S C10191

Figure 7: Start-up Waveforms

VIPer100B/BSP

7/22

Figure 9: Oscillator

1 2 3 5 10 20 30 50

100

200

300

500

1,000

Rt (kΩ)

Frequency (kHz)

Oscillator frequency vs Rt and Ct

Ct = 1.5nF

Ct = 2.7nF

Ct= 4.7nF

Ct = 10nF

FC00030FC00030

1 2 3 5 10 20 30 50

0.5

0.6

0.7

0.8

0.9

Rt (kΩ)

Dmax

Maximum duty cycle vs Rt FC00040

OSC

VDD

~360Ω

CLK

FC00050

For RT> 1.2 KΩ:

FSW =2.3

RTCTDMAX

DMAX =1−550

RT−150

RecommendedDMAX values:

100KHz:> 80%

200KHz:> 70%

VIPer100B/BSP

8/22

Figure 10: ErrorAmplifier FrequencyResponse

0.001 0.01 0.1 1 10 100 1,000

(20)

Frequency (kHz)

VoltageGain (dB)

RCOMP= +∞

RCOMP= 270k

RCOMP = 82k

RCOMP= 27k

RCOMP= 12k

FC00200

Figure 11: ErrorAmplifier PhaseResponse

0.001 0.01 0.1 1 10 100 1,000

(50)

100

150

200

Frequency (kHz)

Phase (°)

RCOMP= +∞

RCOMP= 270k

RCOMP= 82k

RCOMP= 27k

RCOMP= 12k

FC00210

VIPer100B/BSP

9/22

Figure 12: AvalancheTest Circuit

F C00195B

VIPer100B

13V

OSC

COMP SOURCE

DRAINVDD

100

BT2

12V

47uF

16V

2 x STHV102FIin parallel

1mH

GENERATOR INPUT

500us PULSE

BT1

0 to 20V

VIPer100B/BSP

10/22

Figure 13: Off Line Power Supply With Auxiliary Supply Feedback

ACIN +Vcc

GND

BR1

TR2

C10

TR1

C9C7

VIPer100B

13V

OSC

COMP SOURCE

DRAINVDD

C11

FC00081B

Figure 14: Off Line Power Supply With OptocouplerFeedback

AC IN

BR1

TR2

C10

TR1

L2 +Vcc

GND

VIPer100B

ISO1 R6

13V

OSC

COMP SOURCE

DRAINVDD

C11

FC00091B

VIPer100B/BSP

11/22

OPERATION DESCRIPTION:

CURRENT MODE TOPOLOGY:

The current mode control method, like the one

integratedin the VIPer100B/BSPuses two control

loops - an inner current control loop and an outer

loop for voltage control. When the Power

MOSFET output transistor is on, the inductor

current (primary side of the transformer) is

monitored with a SenseFET technique and

converted into a voltage VSproportional to this

current. When VSreaches VCOMP (the amplified

output voltage error) the power switch is switched

off. Thus, the outer voltage control loop defines

the level at which the inner loop regulates peak

current through the power switch and the primary

winding of the transformer.

Excellent open loop D.C. and dynamic line

regulation is ensured due to the inherent input

voltage feedforward characteristic of the current

mode control. This results in an improved line

regulation, instantaneous correction to line

changes and better stability for the voltage

regulationloop.

Current mode topology also ensures good

limitation in the case of short circuit. During a first

phase the output current increases slowly

following the dynamic of the regulation loop. Then

it reaches the maximum limitation current

internally set and finally stops because the power

supply on VDD is no longer correct. For specific

applications the maximum peak current internally

set can be overridden by externally limiting the

voltage excursion on the COMP pin. An

integrated blanking filter inhibits the PWM

comparator output for a short time after the

integrated Power MOSFET is switched on. This

function prevents anomalous or premature

termination of the switching pulse in the case of

current spikes caused by primary side

capacitance or secondary side rectifier reverse

recoverytime.

STAND-BY MODE

Stand-by operation in nearly open load condition

automatically leads to a burst mode operation

allowingvoltageregulationon the secondaryside.

The transition from normal operation to burst

mode operationhappens for a power PSTBY given

by :

PSTBY =1

2LPISTBY

2FSW

Where:

LPis the primary inductanceof thetransformer.

FSW isthe normalswitchingfrequency.

ISTBY is the minimum controllable current,

corresponding to the minimum on time that the

device is able to providein normal operation.This

currentcan be computedas :

ISTBY =(tb+td)VIN

tb+t

dis the sum of the blanking time and of the

propagationtime of the internal current sense and

comparator, and represents roughly the minimum

on time of the device. Note that PSTBY may be

affected by the efficiency of the converter at low

load, and must include the power drawn on the

primaryauxiliary voltage.

As soon as the power goes below this limit, the

auxiliary secondary voltage starts to increase

above the 13V regulation level forcing the output

voltage of the transconductance amplifier to low

state (VCOMP <V

COMPth). This situation leads to

the shutdown mode where the power switch is

maintained in the off state, resulting in missing

cycles and zero duty cycle. As soon as VDD gets

back to the regulation level and the VCOMPth

threshold is reached, the device operates again.

The above cycle repeats indefinitely, providing a

burst mode of which the effective duty cycle is

much lower than the minimum one when in

normal operation. The equivalent switching

frequency is also lower than the normal one,

leading to a reduced consumption on the input

mains lines. This mode of operation allows the

VIPer100B/BSP to meet the new German ”Blue

Angel” Norm with less than 1W total power

consumption for the system when working in

stand-by. The output voltage remains regulated

around the normal level, with a low frequency

ripple corresponding to the burst mode. The

amplitude of this ripple is low, because of the

output capacitors and of the low output current

drawn in such conditions.The normal operation

resumes automatically when the power get back

to higherlevels than PSTBY.

HIGH VOLTAGE START-UP CURRENT

SOURCE

An integrated high voltage current source

providesa bias currentfromthe DRAIN pin during

the start-up phase. This current is partially

absorbed by internal control circuits which are

VIPer100B/BSP

12/22

placed into a standby mode with reduced

consumption and also provided to the external

capacitor connected to the VDD pin. As soon as

the voltage on this pin reaches the high voltage

threshold VDDon of the UVLO logic, the device

turns into active mode and starts switching. The

start up current generatoris switched off, and the

converter should normally provide the needed

current on the VDD pin through the auxiliary

winding of the transformer, as shown on figure

15.

In case of abnormal condition where the auxiliary

winding is unable to provide the low voltage

supply current to the VDD pin (i.e. short circuit on

the output of the converter),the externalcapacitor

discharges itself down to the low threshold

voltage VDDoff of the UVLO logic, and the device

get back to the inactive state where the internal

circuits are in standby mode and the start up

current source is activated. The converter enters

a endless start up cycle, witha start-upduty cycle

defined by the ratio of charging current towards

discharging when the VIPer100B/BSP tries to

start.Thisratio is fixed by design to 2 to 15, which

gives a 12% start up duty cycle while the power

dissipation at start up is approximately 0.6 W, for

a 230 Vrms input voltage. This low value of

start-up duty cycle prevents the stress of the

output rectifiers and of the transformer when in

shortcircuit.

The external capacitor CVDD on the VDD pin must

be sized according to the time needed by the

converter to start up, when the device starts

switching. This time tSS depends on many

parameters, among which transformer design,

output capacitors, soft start feature and

compensation network implemented on the

COMPpin. The following formula can be used for

definingthe minimum capacitorneeded:

CVDD >IDD tSS

VDDhyst

where:

IDD is the consumption current on the VDD pin

when switching. Refer to specified IDD1 and IDD2

values.

tSS is the start up time of the converter when the

device begins to switch. Worst case is generally

at full load.

VDDhyst is the voltage hysteresis of the UVLO

logic. Referto the minimumspecifiedvalue.

Soft start feature can be implemented on the

COMP pin through a simple capacitor which will

be also used as the compensation network. In

this case, the regulation loop bandwidth is rather

low, because of the large value of this capacitor.

In case a large regulation loop bandwidth is

mandatory, the schematics of figure 16 can be

Figure 15: Behaviourof thehigh voltage currentsource at start-up

F C00100B

Ref.

UNDE R VOL T AGE

L OCK OUT L OGIC

15 mA1mA

3mA

2mA

15 mA

VDD DR AIN

SOURCE

VIPer100B

Auxiliary primary

winding

VDD

VDDoff

VDDon

S tart upduty cycle~ 10%

CVDD

VIPer100B/BSP

13/22

used. It mixes a high performance compensation

network together with a separate high value soft

start capacitor. Both soft start time and regulation

loop bandwidthcan be adjustedseparately.

If the device is intentionally shut down by putting

the COMP pin to ground, the device is also

performing start-up cycles, and the VDD voltageis

oscillatingbetweenVDDon and VDDoff. This voltage

can be used for supplying external functions,

provided that their consumption doesn’t exceed

0.5mA. Figure 17 shows a typical application of

this function, with a latched shut down. Once the

”Shutdown”signal has been activated,the device

remains in the off state until the input voltage is

removed.

TRANSCONDUCTANCE ERROR AMPLIFIER

The VIPer100B/BSPincludesa transconductance

error amplifier. Transconductance Gm is the

change in output current(ICOMP) versus changein

input voltage (VDD). Thus:

Gm=∂ICOMP

∂VDD

The output impedance ZCOMP at the outputof this

amplifier(COMP pin) can be defined as:

ZCOMP =∂VCOMP

∂ICOMP =1

Gmx∂VCOMP

∂VDD

This last equation shows that the open loop gain

AVOL can be relatedto Gmand ZCOMP:

AVOL =G

mxZCOMP

where Gmvalue for VIPer100B/BSP is 1.5 mA/V

typically.

Gmis well defined by specification, but ZCOMP and

thereforeAVOL are subject to large tolerances.An

impedance Z can be connected between the

COMP pin and ground in order to define more

accurately the transfer function F of the error

amplifier, according to the following equation,

very similarto the one above:

F(S) = Gmx Z(S)

The error amplifier frequency response is

reported in figure 10 for different values of a

simple resistance connected on the COMP pin.

The unloaded transconductance error amplifier

shows an internal ZCOMP of about 330 KΩ. More

complex impedance can be connected on the

COMP pin to achieve different compensation

laws. A capacitor will provide an integrator

function, thus eliminating the DC static error, and

a resistancein series leads to a flat gain at higher

frequency, insuring a correct phase margin. This

configurationis illustrated on figure18.

As shown in figure 18 an additionalnoise filtering

capacitor of 2.2 nF is generally needed to avoid

anyhigh frequencyinterference.

It can be also interesting to implement a slope

compensation when working in continuous mode

with duty cycle higher than 50%. Figure 19 shows

such a configuration. Note that R1 and C2 build

the classical compensation network, and Q1 is

injecting the slope compensation with the correct

polarityfrom the oscillator sawtooth.

EXTERNALCLOCK SYNCHRONIZATION:

The OSC pin provides a synchronisation

capability, when connected to an external

Figure 17: Latched Shut Down

13V

OSC

COMP SOURCE

DRAINVDD

VIPer100B

Shutdown Q1

R2R3

R4 D1

F C00110B

Figure 16: Mixed SoftStartand Compensation

13V

OSC

COMP SOURCE

DRAINVDD

VIPer100B

C1 +C2

+C3

AUXILIARY

WINDING

F C00131B

VIPer100B/BSP

14/22

frequency source. Figure 20 shows one possible

schematic to be adapted depending the specific

needs. If the proposed schematic is used, the

pulse durationmust be kept at a low value (500ns

is sufficient) for minimizing consumption. The

optocoupler must be able to provide 20mA

throughthe optotransistor.

PRIMARYPEAK CURRENT LIMITATION

The primary IDPEAK current and, as resulting

effect, the output power can be limited using the

simple circuit shown in figure 21. The circuit

based on Q1, R1and R2clamps the voltage on

the COMP pin in order to limit the primary peak

currentof the deviceto a value:

IDPEAK =VCOMP−0.5

HID

where:

VCOMP =0.6xR1+R2

The suggestedvalue for R1+R2is in the range of

220KΩ.

OVER-TEMPERATURE PROTECTION:

Over-temperature protection is based on chip

temperature sensing. The minimum junction

temperature at which over-temperature cut-out

occurs is 140oC while the typical value is 170oC.

The device is automatically restarted when the

junction temperature decreases to the restart

temperaturethresholdthat is typically40oC below

Figure 19: Slope Compensation

13V

OSC

COMP SOURCE

DRAINVDD

VIPer100B

R1R2

C1 R3

F C00141B

+13V

OSC

COMP SOURCE

DRAINVDD

VIPer100B

F C00121B

Figure 18: TypicalCompensation Network

13V

OSC

COMP SOURCE

DRAINVDD

VIPer100B

10 kΩ

FC00220B

Figure 20:ExternalClock Synchronization Figure 21:CurrentLimitationCircuit Example

13V

OSC

COMP SOURCE

DRAINVDD

VIPer100B

FC00240B

VIPer100B/BSP

15/22

VIPer100B

13V

OSC

COMP SOURCE

DRAINVDD

ISO1

Frominput

diodes bridge

T osecondary

filteringandload

FC00500B

Figure 22: Recommendedlayout

LAYOUTCONSIDERATIONS

Some simple rules insure a correct running of

switching power supplies. They may be classified

into twocategories:

-To minimise power loops: the way the switched

power current must be carefully analysed and

the corresponding paths must present the

smallest inner loop area as possible. This

avoids radiated EMC noises, conducted EMC

noises by magnetic coupling, and provides a

better efficiency by eliminating parasitic

inductances,especially on secondaryside.

-To use different tracks for low level signals and

power ones. The interferencesdue to a mixing

of signal and power may result in instabilities

and/or anomalous behaviour of the device in

case of violent power surge (Input

overvoltages,outputshort circuits...).

In case of VIPer, these rules apply as shown on

figure 22. The loops C1-T1-U1, C5-D2-T1,

C7-D1-T1 must be minimised. C6 must be as

close as possible from T1. The signal

components C2, ISO1, C3 and C4 are using a

dedicated track to be connected directly to the

sourceof the device.

VIPer100B/BSP

16/22