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Security and Surveillance Cameras
PC Multimedia
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Applications
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3.75 µm x 3.75 µm pixel
1280 x 720 at 60 fps @ 10-bit,
45 fps @ 12-bit
programmable controls for frame rate,
mirror and flip, cropping, and windowing
supports image sizes:
720p (1280x720), VGA (640x480),
and more
ultra low power mode (ULPM)
support for output formats:
10/12-bit RGB RAW
two-wire serial bus control (SCCB)
MIPI serial output interface (1-lane)/
DVP interface
image quality control:
defect pixel correction and
automatic black level calibration
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Product Features ¬OV09755-H55A
(color, lead-free, 55-pin CSP5)
Ordering Information
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active array size: 1280 x 720
power supply:
- core: 1.14 to 1.26V (1.2V nominal)
- analog: 3.15 to 3.45V (3.3V nominal)
- I/O: 1.7 to 1.9V (1.8V nominal)
power requirements:
- active: 100 mW
- standby: 500 µW
- XSHUTDN: 25 µW
temperature range:
- operating: -30°C to +85°C junction
temperature
- stable image: 0°C to +60°C junction
temperature
output interface: 1-lane MIPI serial
output/DVP parallel output
output formats: 10/12-bit RGB RAW
lens size: 1/3"
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lens chief ray angle: 9° linear
input clock frequency: 6 ~ 74.5 MHz
maximum image transfer rate:
- 720p (1280x720): 60 fps
- VGA (640x480): 90 fps
sensitivity: 43Ke-/lux-sec
max S/N ratio: 42.6 dB
dynamic range: 73.04 dB @ 16x gain
pixel size: 3.75 µm x 3.75 µm
dark current: 30 e-/sec
@ 60°C junction temperature
image area: 4852.20 µm x 2756 µm
package dimensions:
6429 µm x 3864 µm
Product Specifications
Version 1.1, October, 2016
OmniVision reserves the right to make changes to their products or to discontinue any product or
service without further notice. OmniVision, the OmniVision logo and OmniPixel are registered
trademarks of OmniVision Technologies, Inc. OmniPixel3-HS is a trademark of OmniVision
Technologies, Inc. All other trademarks are the property of their respective owners.
4275 Burton Drive
Santa Clara, CA 95054
USA
Tel: + 1 408 567 3000
Fax: + 1 408 567 3001
www.ovt.com
OV9755
Functional Block Diagram
OV9755
image sensor core image
sensor
processor
image output
interface
column
sample/hold
row select
PLLs
control register bank
SCCB slave interface
timing generator and system control logic
gain control
PLL
XVCLK
TM
PWDNB
XSHUTDN
HREF
FSIN/VSYNC
ULPM
STROBE
SCL
SID
SDA
MCP/N
MDP/N
PCLK
D[11:0]
image
array AMP
ISP
12-bit
ADC
FIFO
output