. Preliminary IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Features * 512K x 36 or 1M x 18 organization * Common I/O * CMOS technology * Asynchronous output enable and sleep mode inputs * Synchronous pipeline mode of operation with self-timed late write * Single differential HSTL clock * HSTL input and output levels * +2.5V power supply * Registered addresses, write enables, synchronous select, and data-ins * Boundary scan using a limited set of JTAG 1149.1 functions * Byte write capability and global write enable * 7 x 17 bump ball grid array (BGA) package with SRAM JEDEC standard pinout and boundary scan order * Programmable impedance output drivers Description The IBM0418166XLAC and IBM0436166XLAC 16Mb SRAMS are synchronous pipeline mode, highperformance CMOS static random-access memories that have wide I/O and achieve 2-ns cycle times. Single differential K clocks are used to initiate the read/write operation, and all internal operations are self-timed. At the rising edge of the K clock, all addresses, write enables, synchronous selects, and XLACds.fm.00 November 24, 2003 data-ins are registered internally. Data-outs are updated from output registers off the next rising edge of the K clock. An internal write buffer allows write data to follow one cycle after addresses and controls. The chip is operated with a single +2.5V power supply and is compatible with HSTL I/O interfaces. Page 1 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary x36 BGA Bump Layout (Top View) 1 2 3 4 5 6 7 A VDDQ SA14 SA11 NC SA10 SA7 VDDQ B NC SA18 SA13 NC SA9 SA6 NC C NC SA15 SA12 VDD SA8 SA5 NC D DQ21 DQ20 VSS ZQ VSS DQ15 DQ14 E DQ24 DQ22 VSS SS VSS DQ13 DQ11 F VDDQ DQ23 VSS G VSS DQ12 VDDQ G DQ19 DQ18 SBWc NC SBWb DQ17 DQ16 H DQ25 DQ26 VSS NC VSS DQ9 DQ10 J VDDQ VDD VREF VDD VREF VDD VDDQ K VSS DQ8 DQ7 K SBWa DQ0 DQ1 K DQ28 DQ27 VSS L DQ34 DQ35 SBWd M VDDQ DQ30 VSS SW VSS DQ5 VDDQ N DQ29 DQ31 VSS SA1 VSS DQ4 DQ6 P DQ32 DQ33 VSS SA0 VSS DQ2 DQ3 1 1 R NC SA16 M1 VDD M2 SA4 NC T NC NC SA17 SA2 SA3 NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ 1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD, respectively. x18 BGA Bump Layout (Top View) 1 2 3 4 5 6 7 A VDDQ SA14 SA11 NC SA10 SA7 VDDQ B NC SA18 SA13 NC SA9 SA6 NC C NC SA15 SA12 VDD SA8 SA5 NC D DQ10 NC VSS ZQ VSS DQ7 NC E NC DQ11 VSS SS VSS NC DQ6 F VDDQ NC VSS G VSS DQ5 VDDQ G NC DQ9 SBWc NC NC NC DQ8 H DQ12 NC VSS NC VSS DQ4 NC J VDDQ VDD VREF VDD VREF VDD VDDQ K NC DQ13 VSS K VSS NC DQ3 L DQ17 NC NC K SBWa DQ0 NC M VDDQ DQ14 VSS SW VSS NC VDDQ N DQ15 NC VSS SA1 VSS DQ2 NC P NC DQ16 VSS SA0 VSS NC DQ1 1 VDD M21 R NC SA16 M1 SA4 NC T NC SA19 SA17 NC SA3 SA2 ZZ U VDDQ TMS TDI TCK TDO NC VDDQ 1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively. Page 2 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Pin Description SA0-SA19 Address Input G Asynchronous Output Enable DQ0-DQ35 Data I/O SS Synchronous Select Clock Mode Inputs. For this application, M1 and M2 need to connect to VSS and VDD, respectively. K, K Differential Input Register Clocks SW Write Enable, Global VREF HSTL Input Reference Voltage SBWa Write Enable, Byte a (DQ0-DQ8) VDD Power Supply (+2.5V) SBWb Write Enable, Byte b (DQ9-DQ17) VSS Ground SBWc Write Enable, Byte c (DQ18-DQ26) VDDQ SBWd Write Enable, Byte d (DQ27-DQ35) ZZ Asynchronous Sleep Mode ZQ Output Driver Impedance Control NC No Connect TMS, TDI, TCK IEEE 1149.1 Test Inputs (LVTTL levels) TDO IEEE 1149.1 Test Output (LVTTL level) M1, M2 Output Power Supply Ordering Information Part Number Organization IBM0418166XLAC-30 IBM0418166XLAC-40 Speed (Cycle Time) (ns) 3.0 1M x 18 4.0 IBM0418166XLAC-50 5.0 IBM0436166XLAC-30 3.0 IBM0436166XLAC-40 IBM0436166XLAC-50 XLACds.fm.00 November 24, 2003 Leads 512K x 36 7 x 17 BGA 4.0 5.0 Page 3 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary SS RD Add Register WR Add Register 2:1 MUX SA0-SA19 K Latch ZZ SW SW Register SW Register SBW Register SBW Register Row Decoder Block Diagram 512K x 36 or 1M x 18 Array Column Decoder Latch Match Read/Write Amp SBW 2:1 MUX SS Register SS Register Write Buffer Data Out Register G DQ0-DQ35 or DQ0-DQ17 SRAM Features Late Write The late-write function allows write data to be registered one cycle after addresses and controls. This feature eliminates one of two bus-turnaround cycles normally required when going from a read to a write operation. Late write is accomplished by buffering write addresses and data. The SRAM array update occurs during the third write cycle. Read-cycle addresses are monitored to determine if the SRAM array or the write buffer will supply read data. During a write, the byte writes control which byte of data will be written for a given address (see the Clock Truth Table on page 6). Page 4 of 25 XLACds.fm.00 November 24, 2003 Preliminary IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Mode Control Mode control pins M1 and M2 are used to select four different read protocols: * Single clock, flow-through (M1 = VSS, M2 = VSS) * Pipeline (M1 = VSS, M2 = VDD) * Register-latch (M1 = VDD, M2 = VSS) * Dual clock, flow-through (M1 = VDD, M2 = VDD) This datasheet only describes pipeline functionality. Mode control inputs must be set at power-up, and must not change during SRAM operation. Sleep Mode Sleep mode is enabled by switching the asynchronous signal, ZZ, to high. When the SRAM is in sleep mode, the outputs go to a High-Z state, and the SRAM draws standby current. SRAM data is preserved, and a recovery time (tZZR) is required before the SRAM resumes normal operation. Programmable Impedance/Power Up Requirements An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be five times the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of 15% is between 175 and 350. Periodic readjustment of the output driver impedance is necessary because the impedance is affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock cycles, and each evaluation may move the output driver impedance level, one step at a time, towards the optimum level. The output driver has 64 discrete binary weighted steps. Impedance updates for zeros occur whenever the SRAM is driving ones for the same DQs; impedance updates for ones occur whenever SRAM is driving zeros for the same DQs. Updates of both zeros and ones occur when the SRAM is in a High-Z state. The SRAM requires 4s of power-up time after VDD reaches its operating range. Furthermore, to guarantee the output driver impedance, the SRAM requires 2048 clock cycles and a Read '0' and Read '1' or a Read '1' and a Read '0' across all outputs. The RC time constant of the loaded RQ trace must be less than 3ns. Power-Up/Power-Down Sequence The power supplies need to be powered up in the following sequence: VDD, VDDQ, VREF, followed by inputs. The power down sequence must be the reverse. VDDQ must not exceed VDD. XLACds.fm.00 November 24, 2003 Page 5 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Clock Truth Table K ZZ SS SW SBWa SBWb SBWc SBWd DQ (n) DQ (n + 1) MODE LH L L H X X X X X DOUT 0-35 Read Cycle, All Bytes LH L L L L H H H X DIN 0-8 Write Cycle, First Byte LH L L L H L H H X DIN 9-17 Write Cycle, Second Byte LH L L L H H L H X DIN 18-26 Write Cycle, Third Byte LH L L L H H H L X DIN 27-35 Write Cycle, Fourth Byte LH L L L L L L L X DIN 0-35 Write Cycle, All Bytes LH L L L H H H H X High-Z Abort Write Cycle LH L H X X X X X X High-Z Deselect Cycle X H X X X X X X High-Z High-Z Sleep Mode X = Not applicable; L= Low; H = High Output Enable Truth Table Operation (n) G (n, n + 1) DQ (n) DQ (n + 1) Read L X DOUT 0-35 Read H High-Z High-Z Sleep (ZZ = H) X High-Z High-Z Write (SW = L) L X High-Z Deselect (SS = H) L X High-Z Symbol Rating Units Notes Power Supply Voltage VDD -0.5 to 2.825 V 1 Input Voltage VIN -0.5 to 2.4 V 1 VOUT -0.5 to 2.825 V 1 TJ 0 to +110 C 1 Storage Temperature TSTG -55 to +125 C 1 Short Circuit Output Current IOUT 25 mA 1 X = Not applicable; L= Low; H = High Absolute Maximum Ratings Item Output Voltage Operating Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Page 6 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Recommended DC Operating Conditions (TA = 0 to 85C) Parameter Symbol Min. Typ. Max. Units Notes VDD 2.375 2.5 2.625 V 1 VDDQ 1.4 1.5 1.6 V 1 Input High Voltage VIH VREF +0.1 -- VDDQ + 0.3 V 1, 2 Input Low Voltage VIL -0.3 -- VREF - 0.1 V 1, 3 VREF 0.7 0.75 0.8 V 1 Clocks Signal Voltage VIN - CLK -0.3 -- VDDQ + 0.3 V 1, 4 Differential Clocks Signal Voltage VDIF - CLK 0.1 -- VDDQ + 0.6 V 1, 5 Clocks Common Mode Voltage VCM - CLK 0.7 -- 0.8 V 1 Supply Voltage Output Driver Supply Voltage Input Reference Voltage 1. 2. 3. 4. All voltages referenced to VSS. All VDD, VDDQ, and VSS pins must be connected. VIH(Max)DC = VDDQ + 0.3V, VIH(Max)AC = 2.6V (2.1V for DQs) (pulse width 20% of cycle time). VIL(Min)DC = -0.3V, VIL(Min)AC = -1.0V (-0.5V for DQs) (pulse width 20% of cycle time). VIN-CLK specifies the maximum allowable DC excursions of each differential clock (K, K, C, C). 5. VDIF-CLK specifies the minimum clock differential voltage required for switching. XLACds.fm.00 November 24, 2003 Page 7 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary DC Electrical Characteristics (TA = 0 to +85C, VDD = 2.5V 5%) Symbol Parameter Min. x36 IDD Average Power Supply Operating Current (IOUT = 0, VIN = VIH or VIL, ZZ and SS = VIL) x18 -30 580 -40 410 -50 330 -30 460 -50 330 -40 265 Units Notes mA 1 mA 1 ISBSS Power Supply Standby Current (SS = VIH, ZZ = VIH, All other inputs = VIH or VIH, IIH = 0) 150 mA 1 ISBZZ Power Supply Sleep Current (ZZ = VIH, All other inputs = VIH or VIL, IOUT = 0) 100 mA 1 ILI Input Leakage Current Any input (except JTAG) (VIN = VSS or VDDQ) -2 +2 A ILO Output Leakage Current (VOUT = VSS or VDDQ, DQ in High-Z) -5 +5 A VOH Output High Level Voltage (IOH = -8mA) VDDQ -.4 VDDQ V 2, 3 VOL Output Low Level Voltage (IOL = +8mA) VSS VSS + .4 V 2, 3 JTAG Leakage Current (VIN = VSS or VDD) -70 +10 A 4 ILIJTAG 1. 2. 3. 4. Max. IOUT = Chip Output Current Minimum Impedance Output Driver JEDEC Standard JESD8-6 Class 1 Compatible For JTAG inputs only. Page 8 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Programmable Impedance Output Driver DC Electrical Characteristics (TA = 0 to +85C, VDD = 2.5V 5%) Parameter Symbol Min. Max. Units Notes Output High Voltage VOH VDDQ / 2 VDDQ V 1, 2, 4 Output Low Voltage VOL VSS VDDQ / 2 V 3, 4 1. 2. 3. 4. IOH = (VDDQ / 2) / (RQ / 5) 15% @ VOH = VDDQ / 2 (for: 175 RQ 250). IOH = (VDDQ / 2) / (RQ / 5) 15%, + 20% @ VOH = VDDQ / 2 (for: 250 RQ 350). IOL = (VDDQ / 2) / (RQ / 5) 15% @ VOL = VDDQ / 2 (for: 175 RQ 350). Parameter tested with RQ = 250 and VDDQ = 1.5V. PBGA Thermal Characteristics Item Thermal Resistance Junction to Case Capacitance Symbol Rating Units RJC 1 C/W (TA = 0 to +85C, VDD = 2.5V 5%, f = 1MHz) Parameter Input Capacitance Data I/O Capacitance (DQ0-DQ35) AC Input Characteristics Symbol Test Condition Max. Units CIN VIN = 0V 4 pF COUT VOUT = 0V 5 pF (TA = 0 to +85C, VDD = 2.5V 5%) Item Symbol Min. AC Input Logic High VIH (AC) VREF + 400 AC Input Logic Low VIL (AC) Clock Input Differential Voltage VDIF (AC) VREF Peak-to-Peak AC Voltage VREF (AC) Max. VREF - 400 800 5% VREF (DC) Units Notes mV 3, 4 mV 3, 4 mV 2, 3 mV 1 1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF. 2. SRAM performance is a function of clock input differential voltage (VDIF). 3. To guarantee AC characteristics, VIH, VIL, Trise, and Tfall of inputs and clocks must be within 20% of each other. If these conditions are not met then: - Setup time is measured from clock crossing to inputs at their switched VIHAC, VILAC levels. - Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels. 4. See AC Input Definition on page 10. XLACds.fm.00 November 24, 2003 Page 9 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary AC Input Definition VIH (ac) VREF VDIF VIL (ac) AC Test Conditions (TA = 0 to +85C, VDD = 2.5V 5%, VDDQ = 1.5V) Parameter Symbol Conditions Units Input High Level VIH 1.25 V Input Low Level VIL 0.25 V Input Reference Voltage VREF 0.75 V Differential Clocks Voltage VDIF-CLK 1.0 V Clocks Common Mode Voltage VCM-CLK 0.75 V Input Rise Time Trise 0.5 ns Input Fall Time Tfall 0.5 ns 0.75 V Differential Cross Point V I/O Signals Reference Level (except K and C clocks) Clocks Reference Level Output Load Conditions Notes 1 1. See AC Test Loading on page 11. Page 10 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary AC Test Loading 50 0.75V 50 5pF 25 DQ 50 0.75V 50 5pF 0.75V XLACds.fm.00 November 24, 2003 Page 11 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM AC Characteristics Preliminary (TA = 0 to +85C, VDD = 2.5V 5%) 30 Symbol 40 50 Parameter Units Min. Max. Min. Max. Min. tKHKH Cycle Time 3.0 4.0 5.0 ns tKHKL Clock High Pulse Width 1.2 1.5 1.5 ns tKLKH Clock Low Pulse Width 1.2 1.5 1.5 ns tKHQV Clock to Output Valid tAVKH Address Setup Time 0.5 0.5 tKHAX Address Hold Time 0.5 tSVKH Sync Select Setup Time tKHSX ns 1, 3 0.5 ns 2 0.5 0.5 ns 2 0.5 0.5 0.5 ns 2 Sync Select Hold Time 0.5 0.5 0.5 ns 2 tWVKH Write Enables Setup Time 0.5 0.5 0.5 ns 2 tKHWX Write Enables Hold Time 0.5 0.5 0.5 ns 2 tDVKH Data In Setup Time 0.5 0.5 0.5 ns 2 tKHDX Data In Hold Time 0.5 0.5 0.5 ns 2 tKHQX Data Out Hold Time 0.5 0.5 0.5 ns 1 tKHQZ Clock High to Output High-Z ns 1, 3 tKHQX4 Clock High to Output Active ns 1, 3 tGHQZ Output Enable to High-Z ns 1, 3 tGLQX Output Enable to Low-Z ns 1 tGLQV Output Enable to Output Valid 2.0 2.0 2.0 ns 1 tZZR Sleep Mode Recovery TIme 200 200 200 ns tZZE Sleep Mode Enable TIme 6 8 8 ns tSSZZ Sync to Sleep Time 1.5 2.0 Notes Max. 2.25 0.5 2.25 0.5 2.0 0.5 2 2.25 2.25 0.5 2.0 0.5 2 2.0 0.5 2 ns 1. See AC Test Loading on page 11. 2. To guarantee AC characteristics, VIH, VIL, Trise, and Tfall of inputs and clocks must be within 20% of each other. If these conditions are not met: - Setup time is measured from clock crossing to inputs at their switched VIHAC,VILAC levels. - Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels. 3. Verified by design and tested without guardbands. Page 12 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Timing Diagram (Read and Deselect Cycles) tKLKH tKHKL tKHKH K tAVKH SA A2 A1 A3 A3 A4 tKHSX tKHAX SS tWVKH tSVKH SW tGLQV tKHWX G tKHQX tGHQZ DQ Q1 tGLQX XLACds.fm.00 November 24, 2003 tKHQZ tKHQV Q4 Q3 Q2 tKHQX4 tKHQV Page 13 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Timing Diagram (Read, Write Cycles) tKLKH tKHKL tKHKH K tAVKH SA A2 A1 A3 A2 A4 tKHAX tSVKH SS tKHSX tKHWX tKHWX SW tWVKH tWVKH tKHWX tKHWX SBW tWVKH tWVKH G tGHQZ tKHQV tKHQZ tKHDX Q1 DQ Q3 D2 tKHQV tKHQX4 tDVKH Q2 D4 tDVKH tKHDX Notes: 1. D2 is the input data written in memory location A2. 2. Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address. Page 14 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Timing Diagram (Asynchronous Sleep Mode) tKHKH K tKHSX tSSZZ ZZ tSSZZ tZZE tSVKH tSVKH SS tKHQV tZZR Q1 DQ ADDR A1 tAVKH tKHAX XLACds.fm.00 November 24, 2003 Page 15 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary IEEE 1149.1 TAP and Boundary Scan The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core. In conformance with IEEE standard 1149.1, the SRAM contains a test access port (TAP) controller, Instruction register, Boundary Scan register, Bypass register, and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, a TRST signal is not required. The following signals are supported: * * * * TCK: TMS: TDI: TDO: Test Clock Test Mode Select Test Data In Test Data Out JTAG Recommended DC Operating Conditions Symbol Parameter (TA = 0 to 85C) Min. Typ. Max. Units Notes VIH1 JTAG Input High Voltage 1.7 -- 2.8 V VIL1 JTAG Input Low Voltage -0.3 -- 0.8 V VOH1 JTAG Output High Level 2.1 -- -- V 2 VOL1 JTAG Output Low Level -- -- 0.2 V 1 Conditions Units Notes 1. OH1 = -2mA at 2.1V. 2. OL1 = +2mA at 0.2V. JTAG AC Test Conditions (TA = 0 to +85C, VDD = 2.5V 5%) Symbol Parameter VIH1 Input Pulse High Level 2.0 V VIL1 Input Pulse Low Level 0.0 V TR1 Input Rise Time 2.0 ns TF1 Input Fall Time 2.0 ns Input and Output Timing Reference Level 1.5 V 1 1. See AC Test Loading on page 11. Page 16 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary JTAG AC Characteristics (TA = 0 to +85C, VDD = 2.5V 5%) Parameter Symbol Min. Max. Units TCK Cycle Time tTHTH 20 -- ns TCK High Pulse Width tTHTL 7 -- ns TCK Low Pulse Width tTLTH 7 -- ns TMS Setup tMVTH 4 -- ns TMS Hold tTHMX 4 -- ns TDI Setup tDVTH 4 -- ns TDI Hold tTHDX 4 -- ns TCK Low to Valid Data tTLOV -- 7 ns Notes 1 1. See AC Test Loading on page 11. JTAG Timing Diagram tTHTL tTLTH tTHTH TCK tTHMX TMS tTHDX tMVTH TDI tDVTH TDO tTLOV XLACds.fm.00 November 24, 2003 Page 17 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Scan Register Definition Register Name Bit Size x18 Bit Size x36 Instruction 3 3 Bypass 1 1 32 32 51 70 ID 1, 2 Boundary Scan 1. The boundary-scan chain consists of the following bits: * 36 or 18 bits for data inputs, depending on x36 or x18 configuration * 19 bits for SA0-SA18 in x36; 20 bits for SA0-SA19 in x18 * 4 bits for SBWa-SBWd in x36; 2 bits for SBWa and SBWb in x18 * 9 bits for K, K, ZQ, SS, G, SW, ZZ, M1, and M2 * 2 bits for place holders 2. K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are used for boundary-scan sampling. ID Register Definition Field Bit Number and Description Revision Number (31:28) IBM internal use Device Density and Configuration (27:19) Vendor Definition (18:12) Manufacture JEDEC Code (11:1) Start Bit (0) 1M x 18 XXXX 011100001 0110001 00010100100 1 512K x 36 XXXX 011011110 0110001 00010100100 1 Part Page 18 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Instruction Set Code Instruction Notes 000 SAMPLE-Z 1, 5 001 IDCODE 2 010 SAMPLE-Z 1, 5 011 PRIVATE 6 100 SAMPLE 4, 5 101 PRIVATE 6 110 PRIVATE 6 111 BYPASS 3 1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs. 2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data. 3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the Shift DR state. 4. SAMPLE instruction does not place DQs in High-Z. 5. SRAM must not be in Sleep mode (ZZ = H) when SAMPLE-Z or SAMPLE instructions are invoked. 6. PRIVATE is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality. This part has not been designed to comply with the following sections of IEEE 1149.1: * * * * 7.2.1.b, e 7.7.1.a-f 10.1.1.b, e 10.7.1.a-d XLACds.fm.00 November 24, 2003 Page 19 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Boundary Scan Order (x36) Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 25 DQ12 6F 49 DQ26 2H 2 SA0 4P 26 DQ11 7E 50 DQ25 1H 3 SA2 4T 27 DQ13 6E 51 SBWc 3G 4 SA4 6R 28 DQ14 7D 52 ZQ 4D 5 SA3 5T 29 DQ15 6D 53 SS 4E 6 ZZ 7T 30 SA7 6A 54 PH1 4G 7 DQ2 6P 31 SA5 6C 55 PH2 4H 8 DQ3 7P 32 SA8 5C 56 SW 4M 9 DQ4 6N 33 SA10 5A 57 SBWd 3L 10 DQ6 7N 34 SA6 6B 58 DQ28 1K 11 DQ5 6M 35 SA9 5B 59 DQ27 2K 12 DQ0 6L 36 SA13 3B 60 DQ34 1L 13 DQ1 7L 37 SA18 2B 61 DQ35 2L 14 DQ7 6K 38 SA11 3A 62 DQ30 2M 15 DQ8 7K 39 SA12 3C 63 DQ29 1N 16 SBWa 5L 40 SA15 2C 64 DQ31 2N 17 K 4L 41 SA14 2A 65 DQ32 1P 18 K 4K 42 DQ20 2D 66 DQ33 2P 19 G 4F 43 DQ21 1D 67 SA17 3T 20 SBWb 5G 44 DQ22 2E 68 SA16 2R 21 DQ10 7H 45 DQ24 1E 69 SA1 4N 22 DQ9 6H 46 DQ23 2F 70 M1 3R 23 DQ16 7G 47 DQ18 2G 24 DQ17 6G 48 DQ19 1G 1. The input of the PH signal is connected to VSS. 2. The input of the PH signal is connected to VDD. Page 20 of 25 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Boundary Scan Order (x18) Exit Order Signal Bump # Exit Order Signal Bump # 1 M2 5R 27 SA18 2B 2 SA2 6T 28 SA11 3A 3 SA0 4P 29 SA12 3C 4 SA4 6R 30 SA15 2C 5 SA3 5T 31 SA14 2A 6 ZZ 7T 32 DQ10 1D 7 DQ1 7P 33 DQ11 2E 8 DQ2 6N 34 DQ9 2G 9 DQ0 6L 35 DQ12 1H 10 DQ3 7K 36 SBWb 3G 11 SBWa 5L 37 ZQ 4D 12 K 4L 38 SS 4E 13 K 4K 39 PH1 4G 14 G 4F 40 PH2 4H 15 DQ4 6H 41 SW 4M 16 DQ8 7G 42 DQ13 2K 17 DQ5 6F 43 DQ17 1L 18 DQ6 7E 44 DQ14 2M 19 DQ7 6D 45 DQ15 1N 20 SA7 6A 46 DQ16 2P 21 SA5 6C 47 SA17 3T 22 SA8 5C 48 SA16 2R 23 SA10 5A 49 SA1 4N 24 SA6 6B 50 SA19 2T 25 SA9 5B 51 M1 3R 26 SA13 3B 1. The input of the PH signal is connected to VSS. 2. The input of the PH signal is connected to VDD. XLACds.fm.00 November 24, 2003 Page 21 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary TAP Controller State Machine 1 Test Logic Reset 0 0 Run Test Idle 1 1 Select DR 0 0 1 1 Select IR 1 Capture IR Capture DR 0 0 0 Shift IR 0 Shift DR 1 1 1 1 Exit1 IR Exit1 DR 0 0 0 0 Pause DR Pause IR 1 1 Exit2 DR 0 Exit2 IR 0 1 1 Update DR 0 Page 22 of 25 1 Update IR 1 0 XLACds.fm.00 November 24, 2003 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary 7 x 17 BGA Dimensions 0.84 Solder Ball 0.889 0.04 diameter 20.32 1 2 3 4 5 7.62 12.294 6 7 1.27 3.19 A B C D E F G H J K L M N P R T U 22.00 19.968 16.764 14 11.968 Flush to 1.4 Max 12.7 Indicates A1 Location Chip 2.618 0.254 Under fill Plate 0.725 0.2 0.0826 0.0254 0.701 0.099 0.1778 Plate Under fill 2.549 0.13 0.71 0.05 Note: All dimensions in millimeters XLACds.fm.00 November 24, 2003 Page 23 of 25 IBM0436166XLAC IBM0418166XLAC 16Mb (512K x 36 & 1M x 18) SRAM Preliminary Revision Log Rev November 24, 2003 Revision Log Page 24 of 25 Contents of Modification Initial release (00). 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