IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 1 of 25
Features
• 512K × 36 or 1M × 18 organization
•CMOS technology
• Synchronous pipeline mode of operation with
self-timed late write
• Single differential HSTL clock
• HSTL input and output levels
• +2.5V power supply
• Registered addresses, write enables, synchro-
nous select, and data-ins
• Common I/O
• Asynchronous output enable and sleep mode
inputs
• Boundary scan using a limited set of JTAG
1149.1 functions
• Byte write capability and global write enable
•7 × 17 bump ball grid array (BGA) package with
SRAM JEDEC standard pinout and boundary
scan order
• Programmable impedance output drivers
Description
The IBM0418166XLAC and IBM0436166XLAC
16Mb SRAMS are synchronous pipeline mode, high-
performance CMOS static random-access memo-
ries that have wide I/O and achieve 2-ns cycle times.
Single differential K clocks are used to initiate the
read/write operation, and all internal operations are
self-timed. At the rising edge of the K clock, all
addresses, write enables, synchronous selects, and
data-ins are registered internally. Data-outs are
updated from output registers off the next rising
edge of the K clock. An internal write buffer allows
write data to follow one cycle after addresses and
controls. The chip is operated with a single +2.5V
power supply and is compatible with HSTL I/O inter-
faces.
.
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 2 of 25
XLACds.fm.00
November 24, 2003
x36 BGA Bump Layout (Top View)
1234567
AVDDQ SA14 SA11 NC SA10 SA7 VDDQ
BNC SA18 SA13 NC SA9 SA6 NC
CNC SA15 SA12 VDD SA8 SA5 NC
DDQ21 DQ20 VSS ZQ VSS DQ15 DQ14
EDQ24 DQ22 VSS SS VSS DQ13 DQ11
FVDDQ DQ23 VSS GVSS DQ12 VDDQ
GDQ19 DQ18 SBWc NC SBWb DQ17 DQ16
HDQ25 DQ26 VSS NC VSS DQ9 DQ10
JVDDQ VDD VREF VDD VREF VDD VDDQ
KDQ28 DQ27 VSS KVSS DQ8 DQ7
LDQ34 DQ35 SBWd KSBWa DQ0 DQ1
MVDDQ DQ30 VSS SW VSS DQ5 VDDQ
NDQ29 DQ31 VSS SA1 VSS DQ4 DQ6
PDQ32 DQ33 VSS SA0 VSS DQ2 DQ3
RNC SA16 M11VDD M21SA4 NC
TNC NC SA17 SA2 SA3 NC ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD, respectively.
x18 BGA Bump Layout (Top View)
1234567
AVDDQ SA14 SA11 NC SA10 SA7 VDDQ
BNC SA18 SA13 NC SA9 SA6 NC
CNC SA15 SA12 VDD SA8 SA5 NC
DDQ10 NC VSS ZQ VSS DQ7 NC
ENC DQ11 VSS SS VSS NC DQ6
FVDDQ NC VSS GVSS DQ5 VDDQ
GNC DQ9 SBWc NC NC NC DQ8
HDQ12 NC VSS NC VSS DQ4 NC
JVDDQ VDD VREF VDD VREF VDD VDDQ
KNC DQ13 VSS KVSS NC DQ3
LDQ17 NC NC K SBWa DQ0 NC
MVDDQ DQ14 VSS SW VSS NC VDDQ
NDQ15 NC VSS SA1 VSS DQ2 NC
PNC DQ16 VSS SA0 VSS NC DQ1
RNC SA16 M11VDD M21SA4 NC
TNC SA19 SA17 NC SA3 SA2 ZZ
UVDDQ TMS TDI TCK TDO NC VDDQ
1. M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively.
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 3 of 25
Pin Description
SA0–SA19 Address Input G Asynchronous Output Enable
DQ0–DQ35 Data I/O SS Synchronous Select
K, K Differential Input Register Clocks M1, M2 Clock Mode Inputs. For this application, M1 and
M2 need to connect to VSS and VDD, respectively.
SW Write Enable, Global VREF HSTL Input Reference Voltage
SBWaWrite Enable, Byte a (DQ0–DQ8) VDD Power Supply (+2.5V)
SBWbWrite Enable, Byte b (DQ9–DQ17) VSS Ground
SBWc Write Enable, Byte c (DQ18–DQ26) VDDQ Output Power Supply
SBWd Write Enable, Byte d (DQ27–DQ35) ZZ Asynchronous Sleep Mode
TMS, TDI, TCK IEEE 1149.1 Test Inputs (LVTTL levels) ZQ Output Driver Impedance Control
TDO IEEE 1149.1 Test Output (LVTTL level) NC No Connect
Ordering Information
Part Number Organization Speed (Cycle Time) (ns) Leads
IBM0418166XLAC-30
1M × 18
3.0
7 × 17 BGA
IBM0418166XLAC-40 4.0
IBM0418166XLAC-50 5.0
IBM0436166XLAC-30
512K × 36
3.0
IBM0436166XLAC-40 4.0
IBM0436166XLAC-50 5.0
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 4 of 25
XLACds.fm.00
November 24, 2003
SRAM Features
Late Write
The late-write function allows write data to be registered one cycle after addresses and controls. This feature
eliminates one of two bus-turnaround cycles normally required when going from a read to a write operation.
Late write is accomplished by buffering write addresses and data. The SRAM array update occurs during the
third write cycle. Read-cycle addresses are monitored to determine if the SRAM array or the write buffer will
supply read data.
During a write, the byte writes control which byte of data will be written for a given address (see the Clock
Truth Table on page 6).
Block Diagram
512K ×36
or
1M ×18
Buffer
Write
Column Decoder
Read/Write Amp
Row Decoder
2:1 MUX
2:1 MUX
Data Out
Register
DQ0–DQ35 or DQ0–DQ17
WR Add
Register
RD Add
Register
Match
Latch
Latch
K
ZZ
SA0–SA19
SW
SBW SBW SBW
SW
G
SS
SS
SS
SW
Array
Register Register
Register Register
Register
Register
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 5 of 25
Mode Control
Mode control pins M1 and M2 are used to select four different read protocols:
• Single clock, flow-through (M1 = VSS, M2 = VSS)
• Pipeline (M1 = VSS, M2 = VDD)
• Register-latch (M1 = VDD, M2 = VSS)
• Dual clock, flow-through (M1 = VDD, M2 = VDD)
This datasheet only describes pipeline functionality. Mode control inputs must be set at power-up, and must
not change during SRAM operation.
Sleep Mode
Sleep mode is enabled by switching the asynchronous signal, ZZ, to high. When the SRAM is in sleep mode,
the outputs go to a High-Z state, and the SRAM draws standby current. SRAM data is preserved, and a
recovery time (tZZR) is required before the SRAM resumes normal operation.
Programmable Impedance/Power Up Requirements
An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to
adjust its output driver impedance. The value of RQ must be five times the value of the intended line imped-
ance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of
15% is between 175Ω and 350Ω. Periodic readjustment of the output driver impedance is necessary because
the impedance is affected by drifts in supply voltage and temperature. One evaluation occurs every 64 clock
cycles, and each evaluation may move the output driver impedance level, one step at a time, towards the
optimum level. The output driver has 64 discrete binary weighted steps. Impedance updates for zeros occur
whenever the SRAM is driving ones for the same DQs; impedance updates for ones occur whenever SRAM
is driving zeros for the same DQs. Updates of both zeros and ones occur when the SRAM is in a High-Z
state. The SRAM requires 4µs of power-up time after VDD reaches its operating range. Furthermore, to guar-
antee the output driver impedance, the SRAM requires 2048 clock cycles and a Read '0' and Read '1' or a
Read '1' and a Read '0' across all outputs. The RC time constant of the loaded RQ trace must be less than
3ns.
Power-Up/Power-Down Sequence
The power supplies need to be powered up in the following sequence: VDD, VDDQ, VREF, followed by inputs.
The power down sequence must be the reverse. VDDQ must not exceed VDD.
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 6 of 25
XLACds.fm.00
November 24, 2003
Clock Truth Table
KZZ SS SW SBWa SBWb SBWc SBWd DQ (n) DQ (n + 1) MODE
L→HLLHXXXXX
DOUT 0-35 Read Cycle, All Bytes
L→HLLLLHHHX
DIN 0-8 Write Cycle, First Byte
L→HLLLHLHHX
DIN 9-17 Write Cycle, Second Byte
L→HLLLHHLHX
DIN 18-26 Write Cycle, Third Byte
L→HLLLHHHLX
DIN 27-35 Write Cycle, Fourth Byte
L→HLLLLLLLX
DIN 0-35 Write Cycle, All Bytes
L→HL L LHHHHXHigh-Z Abort Write Cycle
L→HLHXXXXXXHigh-Z Deselect Cycle
X H X X X X X X High-Z High-Z Sleep Mode
X = Not applicable; L= Low; H = High
Output Enable Truth Table
Operation (n) G (n, n + 1) DQ (n) DQ (n + 1)
Read L X DOUT 0-35
Read H High-Z High-Z
Sleep (ZZ = H) X High-Z High-Z
Write (SW = L) L X High-Z
Deselect (SS = H) L X High-Z
X = Not applicable; L= Low; H = High
Absolute Maximum Ratings
Item Symbol Rating Units
Notes
Power Supply Voltage VDD -0.5 to 2.825 V 1
Input Voltage VIN -0.5 to 2.4 V 1
Output Voltage VOUT -0.5 to 2.825 V 1
Operating Temperature TJ0 to +110 °C1
Storage Temperature TSTG -55 to +125 °C1
Short Circuit Output Current IOUT 25 mA 1
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli-
ability.
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 7 of 25
Recommended DC Operating Conditions (TA= 0 to 85
°
C)
Parameter Symbol Min. Typ. Max. Units Notes
Supply Voltage VDD 2.375 2.5 2.625 V 1
Output Driver Supply Voltage VDDQ 1.4 1.5 1.6 V 1
Input High Voltage VIH VREF +0.1 —VDDQ + 0.3 V1, 2
Input Low Voltage VIL -0.3 — VREF - 0.1 V1, 3
Input Reference Voltage VREF 0.70.750.8 V1
Clocks Signal Voltage VIN - CLK -0.3 — VDDQ + 0.3 V1, 4
Differential Clocks Signal Voltage VDIF - CLK 0.1 — VDDQ + 0.6 V1, 5
Clocks Common Mode Voltage VCM - CLK 0.7 — 0.8 V 1
1. All voltages referenced to VSS. All VDD, VDDQ, and VSS pins must be connected.
2. VIH(Max)DC = VDDQ + 0.3V, VIH(Max)AC = 2.6V (2.1V for DQs) (pulse width ≤ 20% of cycle time).
3. VIL(Min)DC = -0.3V, VIL(Min)AC = -1.0V (-0.5V for DQs) (pulse width ≤ 20% of cycle time).
4. VIN-CLK specifies the maximum allowable DC excursions of each differential clock (K, K, C, C).
5. VDIF-CLK specifies the minimum clock differential voltage required for switching.
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 8 of 25
XLACds.fm.00
November 24, 2003
DC Electrical Characteristics (TA = 0 to +85°C, VDD = 2.5V ±5%)
Symbol Parameter Min. Max. Units Notes
IDD
Average Power Supply Operating
Current
(IOUT = 0, VIN = VIH or VIL,
ZZ and SS = VIL)
x36
-30 580
mA 1-40 410
-50 330
x18
-30 460
mA 1-50 330
-40 265
ISBSS
Power Supply Standby Current
(SS = VIH, ZZ = VIH,
All other inputs = VIH or VIH, IIH = 0)
150 mA 1
ISBZZ
Power Supply Sleep Current
(ZZ = VIH,
All other inputs = VIH or VIL,
IOUT = 0)
100 mA 1
ILI
Input Leakage Current
Any input (except JTAG)
(VIN = VSS or VDDQ)
-2 +2 µA
ILO
Output Leakage Current
(VOUT = VSS or VDDQ,
DQ in High-Z)
-5 +5 µA
VOH Output High Level Voltage
(IOH = -8mA) VDDQ -.4 VDDQ V2, 3
VOL
Output Low Level Voltage
(IOL = +8mA) VSS VSS + .4 V2, 3
ILIJTAG JTAG Leakage Current
(VIN = VSS or VDD)-70 +10 µA4
1. IOUT = Chip Output Current
2. Minimum Impedance Output Driver
3. JEDEC Standard JESD8-6 Class 1 Compatible
4. For JTAG inputs only.
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 9 of 25
Programmable Impedance Output Driver DC Electrical Characteristics
(TA = 0 to +85°C, VDD =2.5V ±5%)
Parameter Symbol Min. Max. Units Notes
Output High Voltage VOH VDDQ / 2 VDDQ V 1, 2, 4
Output Low Voltage VOL VSS VDDQ / 2 V3, 4
1. IOH = (VDDQ / 2) / (RQ / 5) ± 15% @ VOH = VDDQ / 2 (for: 175Ω ≤ RQ ≤ 250Ω).
2. IOH = (VDDQ / 2) / (RQ / 5) ± 15%, + 20% @ VOH = VDDQ / 2 (for: 250Ω ≤ RQ ≤ 350Ω).
3. IOL = (VDDQ / 2) / (RQ / 5) ± 15% @ VOL = VDDQ / 2 (for: 175Ω ≤ RQ ≤ 350Ω).
4. Parameter tested with RQ = 250Ω and VDDQ = 1.5V.
PBGA Thermal Characteristics
Item Symbol Rating Units
Thermal Resistance Junction to Case RΘJC 1°C/W
Capacitance (TA = 0 to +85
°
C, VDD =2.5V ±5%, f = 1MHz)
Parameter Symbol Te st
Condition Max. Units
Input Capacitance CIN VIN = 0V 4pF
Data I/O Capacitance (DQ0–DQ35) COUT VOUT = 0V 5pF
AC Input Characteristics (TA= 0 to +85
°
C, VDD =2.5V ± 5%)
Item Symbol Min. Max. Units Notes
AC Input Logic High VIH (AC) VREF + 400 mV 3, 4
AC Input Logic Low VIL (AC) VREF - 400 mV 3, 4
Clock Input Differential Voltage VDIF (AC) 800 mV 2, 3
VREF Peak-to-Peak AC Voltage VREF (AC) 5% VREF (DC) mV 1
1. The peak-to-peak AC component superimposed on VREF may not exceed 5% of the DC component of VREF.
2. SRAM performance is a function of clock input differential voltage (VDIF).
3. To guarantee AC characteristics, VIH, VIL, Trise, and Tfall of inputs and clocks must be within 20% of each other. If these condi-
tions are not met then:
– Setup time is measured from clock crossing to inputs at their switched VIHAC, VILAC levels.
– Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels.
4. See AC Input Definition on page 10.
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 10 of 25
XLACds.fm.00
November 24, 2003
AC Input Definition
AC Test Conditions (TA= 0 to +85
°
C, VDD =2.5V ±
5%, VDDQ =1.5V)
Parameter Symbol Conditions Units Notes
Input High Level VIH 1.25 V
Input Low Level VIL 0.25 V
Input Reference Voltage VREF 0.75 V
Differential Clocks Voltage VDIF-CLK 1.0 V
Clocks Common Mode Voltage VCM-CLK 0.75 V
Input Rise Time Trise 0.5 ns
Input Fall Time Tfall 0.5 ns
I/O Signals Reference Level (except K and C clocks) 0.75 V
Clocks Reference Level Differential
Cross Point V
Output Load Conditions 1
1. See AC Test Loading on page 11.
VIH (ac)
VREF
VIL (ac)
VDIF
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 11 of 25
AC Test Loading
DQ
0.75V
50Ω
50Ω
25Ω 5pF
0.75V
50Ω
50Ω
5pF
0.75V
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 12 of 25
XLACds.fm.00
November 24, 2003
AC Characteristics (TA= 0 to +85°C, VDD =2.5V ±
5%)
Symbol Parameter
30 40 50
Units Notes
Min. Max. Min. Max. Min. Max.
tKHKH Cycle Time 3.0 4.0 5.0 ns
tKHKL Clock High Pulse Width 1.2 1.5 1.5 ns
tKLKH Clock Low Pulse Width 1.2 1.5 1.5 ns
tKHQV Clock to Output Valid 1.5 2.0 2.25 ns 1, 3
tAVKH Address Setup Time 0.5 0.5 0.5 ns 2
tKHAX Address Hold Time 0.5 0.5 0.5 ns 2
tSVKH Sync Select Setup Time 0.5 0.5 0.5 ns 2
tKHSX Sync Select Hold Time 0.5 0.5 0.5 ns 2
tWVKH Write Enables Setup Time 0.5 0.5 0.5 ns 2
tKHWX Write Enables Hold Time 0.5 0.5 0.5 ns 2
tDVKH Data In Setup Time 0.5 0.5 0.5 ns 2
tKHDX Data In Hold Time 0.5 0.5 0.5 ns 2
tKHQX Data Out Hold Time 0.5 0.5 0.5 ns 1
tKHQZ Clock High to Output High-Z 2.25 2.25 2.25 ns 1, 3
tKHQX4 Clock High to Output Active 0.5 0.5 0.5 ns 1, 3
tGHQZ Output Enable to High-Z 2.0 2.0 2.0 ns 1, 3
tGLQX Output Enable to Low-Z 0.5 0.5 0.5 ns 1
tGLQV Output Enable to Output Valid 2.0 2.0 2.0 ns 1
tZZR Sleep Mode Recovery TIme 200 200 200 ns
tZZE Sleep Mode Enable TIme 6 8 8 ns
tSSZZ Sync to Sleep Time 2 2 2 ns
1. See AC Test Loading on page 11.
2. To guarantee AC characteristics, VIH, VIL, Trise, and Tfall of inputs and clocks must be within 20% of each other. If these condi-
tions are not met:
– Setup time is measured from clock crossing to inputs at their switched VIHAC,VILAC levels.
– Hold time is measured from clock crossing to inputs switching out of their valid VIHAC, VILAC levels.
3. Verified by design and tested without guardbands.
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 13 of 25
Timing Diagram (Read and Deselect Cycles)
K
SS
SW
G
DQ
SA
tKHKH
A3 A3
Q1 Q2 Q3 Q4
tKHKL
tKHQX
tKHQV
tAVKH
tKHAX
tSVKH
tKHSX
tKHWX
tWVKH
tKHQZ
tKHQX4 tKHQV
tGHQZ
tGLQX
tGLQV
A2
A1
tKLKH
A4
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 14 of 25
XLACds.fm.00
November 24, 2003
Timing Diagram (Read, Write Cycles)
K
SS
SW
G
DQ
SA
tKHKH
A3
D2 Q3 D4
tKLKH
tKHKL
tKHQV
tAVKH
tKHAX
tSVKH
tKHWX
tWVKH
tKHQZ
tKHQX4
tGHQZ
SBW
tDVKH
tKHDX
tKHQV
Q2
A1 A2 A2 A4
Q1
Notes:
1. D2 is the input data written in memory location A2.
2. Q2 is output data read from the write buffer, as a result of address A2 being a match from the last write cycle address.
tKHWX
tWVKH tWVKH
tKHWX
tKHWX
tWVKH
tDVKH
tKHDX
tKHSX
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 15 of 25
Timing Diagram (Asynchronous Sleep Mode)
tAVKH
K
ZZ
tKHKH
tSSZZ
SS
tZZR
tZZE tSVKH
ADDR
DQ
tSVKH
tKHSX
tKHAX
tKHQV
A1
Q1
tSSZZ
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 16 of 25
XLACds.fm.00
November 24, 2003
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions intended to test the interconnection between SRAM I/Os
and printed circuit board traces or other components. There is no multiplexer in the path from I/O pins to the
RAM core.
In conformance with IEEE standard 1149.1, the SRAM contains a test access port (TAP) controller, Instruc-
tion register, Boundary Scan register, Bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally upon power-up; therefore, a TRST
signal is not required. The following signals are supported:
• TCK: Test Clock
• TMS: Test Mode Select
• TDI: Test Data In
• TDO: Test Data Out
JTAG Recommended DC Operating Conditions (TA= 0 to 85
°
C)
Symbol Parameter Min. Typ. Max. Units Notes
VIH1 JTAG Input High Voltage 1.7 — 2.8 V
VIL1 JTAG Input Low Voltage -0.3 — 0.8 V
VOH1 JTAG Output High Level 2.1 — — V 2
VOL1 JTAG Output Low Level — — 0.2 V 1
1. OH1 = -2mA at 2.1V.
2. OL1 = +2mA at 0.2V.
JTAG AC Test Conditions (TA= 0 to +85
°
C, VDD =2.5V ±5%)
Symbol Parameter Conditions Units
Notes
VIH1 Input Pulse High Level 2.0 V
VIL1 Input Pulse Low Level 0.0 V
TR1 Input Rise Time 2.0 ns
TF1 Input Fall Time 2.0 ns
Input and Output Timing Reference Level 1.5 V 1
1. See AC Test Loading on page 11.
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 17 of 25
JTAG AC Characteristics (TA=0 to +85
°
C, VDD =2.5V ±5%)
Parameter Symbol Min. Max. Units Notes
TCK Cycle Time tTHTH 20 — ns
TCK High Pulse Width tTHTL 7— ns
TCK Low Pulse Width tTLTH 7— ns
TMS Setup tMVTH 4— ns
TMS Hold tTHMX 4— ns
TDI Setup tDVTH 4— ns
TDI Hold tTHDX 4— ns
TCK Low to Valid Data tTLOV — 7 ns 1
1. See AC Test Loading on page 11.
JTAG Timing Diagram
TCK
TMS
TDI
TDO
tTHTL tTLTH tTHTH
tTHMX
tMVTH
tDVTH
tTHDX
tTLOV
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 18 of 25
XLACds.fm.00
November 24, 2003
Scan Register Definition
Register Name Bit Size x18 Bit Size x36
Instruction 3 3
Bypass 1 1
ID 32 32
Boundary Scan1, 2 51 70
1. The boundary-scan chain consists of the following bits:
• 36 or 18 bits for data inputs, depending on x36 or x18 configuration
• 19 bits for SA0–SA18 in x36; 20 bits for SA0–SA19 in x18
• 4 bits for SBWa–SBWd in x36; 2 bits for SBWa and SBWb in x18
• 9 bits for K, K, ZQ, SS, G, SW, ZZ, M1, and M2
• 2 bits for place holders
2. K and K clocks connect to a differential receiver that generates a single-ended clock signal. This signal and its inverted value are
used for boundary-scan sampling.
ID Register Definition
Part
Field Bit Number and Description
Revision Number
(31:28)
IBM internal use
Device Density and
Configuration (27:19)
Vendor Definition
(18:12)
Manufacture JEDEC
Code (11:1)
Start
Bit (0)
1M x 18 XXXX 011100001 0110001 00010100100 1
512K x 36 XXXX 011011110 0110001 00010100100 1
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 19 of 25
This part has not been designed to comply with the following sections of IEEE 1149.1:
• 7.2.1.b, e
• 7.7.1.a–f
• 10.1.1.b, e
• 10.7.1.a–d
Instruction Set
Code Instruction Notes
000 SAMPLE-Z 1, 5
001 IDCODE 2
010 SAMPLE-Z 1, 5
011 PRIVATE 6
100 SAMPLE 4, 5
101 PRIVATE 6
110 PRIVATE 6
111 BYPASS 3
1. Places DQs in High-Z in order to sample all input data regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded
TDI when exiting the Shift DR state.
4. SAMPLE instruction does not place DQs in High-Z.
5. SRAM must not be in Sleep mode (ZZ = H) when SAMPLE-Z or SAMPLE instructions are invoked.
6. PRIVATE is reserved for the exclusive use of IBM. Invoking this instruction will cause improper SRAM functionality.
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 20 of 25
XLACds.fm.00
November 24, 2003
Boundary Scan Order (x36)
Exit Order Signal Bump # Exit Order Signal Bump # Exit Order Signal Bump #
1M2 5R 25 DQ12 6F 49 DQ26 2H
2SA0 4P 26 DQ11 7E 50 DQ25 1H
3SA2 4T 27 DQ13 6E 51 SBWc 3G
4SA4 6R 28 DQ14 7D 52 ZQ 4D
5SA3 5T 29 DQ15 6D 53 SS 4E
6ZZ 7T 30 SA7 6A 54 PH14G
7DQ2 6P 31 SA5 6C 55 PH24H
8DQ3 7P 32 SA8 5C 56 SW 4M
9DQ4 6N 33 SA10 5A 57 SBWd 3L
10 DQ6 7N 34 SA6 6B 58 DQ28 1K
11 DQ5 6M 35 SA9 5B 59 DQ27 2K
12 DQ0 6L 36 SA13 3B 60 DQ34 1L
13 DQ1 7L 37 SA18 2B 61 DQ35 2L
14 DQ7 6K 38 SA11 3A 62 DQ30 2M
15 DQ8 7K 39 SA12 3C 63 DQ29 1N
16 SBWa 5L 40 SA15 2C 64 DQ31 2N
17 K4L 41 SA14 2A 65 DQ32 1P
18 K4K
42 DQ20 2D 66 DQ33 2P
19 G4F 43 DQ21 1D 67 SA17 3T
20 SBWb 5G 44 DQ22 2E 68 SA16 2R
21 DQ10 7H 45 DQ24 1E 69 SA1 4N
22 DQ9 6H 46 DQ23 2F 70 M1 3R
23 DQ16 7G 47 DQ18 2G
24 DQ17 6G 48 DQ19 1G
1. The input of the PH signal is connected to VSS.
2. The input of the PH signal is connected to VDD.
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 21 of 25
Boundary Scan Order (x18)
Exit Order Signal Bump # Exit Order Signal Bump #
1M2 5R 27 SA18 2B
2SA2 6T 28 SA11 3A
3SA0 4P 29 SA12 3C
4SA4 6R 30 SA15 2C
5SA3 5T 31 SA14 2A
6ZZ 7T 32 DQ10 1D
7DQ1 7P 33 DQ11 2E
8DQ2 6N 34 DQ9 2G
9DQ0 6L 35 DQ12 1H
10 DQ3 7K 36 SBWb 3G
11 SBWa 5L 37 ZQ 4D
12 K4L 38 SS 4E
13 K4K39
PH14G
14 G4F 40 PH24H
15 DQ4 6H 41 SW 4M
16 DQ8 7G 42 DQ13 2K
17 DQ5 6F 43DQ171L
18 DQ6 7E 44 DQ14 2M
19 DQ7 6D 45 DQ15 1N
20 SA7 6A 46 DQ16 2P
21 SA5 6C 47 SA17 3T
22 SA8 5C 48 SA16 2R
23 SA10 5A 49 SA1 4N
24 SA6 6B 50 SA19 2T
25 SA9 5B 51 M1 3R
26 SA13 3B
1. The input of the PH signal is connected to VSS.
2. The input of the PH signal is connected to VDD.
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Page 22 of 25
XLACds.fm.00
November 24, 2003
TAP Controller State Machine
Test Logic Reset
Run Test Idle Select DR
Capture DR
Shift DR
Exit1 DR
Pause DR
Exit2 DR
Update DR
Select IR
Capture IR
Shift IR
Exit1 IR
Pause IR
Exit2 IR
Update IR
1
1
1
0
0
0
0
1
0
1
1
0
1
1
1
0
01
1
1
0
1
0
0
0
1
1
0
0
0
0
1
IBM0436166XLAC
IBM0418166XLAC
Preliminary 16Mb (512K x 36 & 1M x 18) SRAM
XLACds.fm.00
November 24, 2003
Page 23 of 25
7 x 17 BGA Dimensions
Note: All dimensions in millimeters
Plate
0.71 ± 0.05
0.701 ± 0.099
Under fill
0.0826 ± 0.0254
0.725 ± 0.2
Indicates A1
Location
Plate
Chip
12.7
22.00
19.968
2.549 ± 0.13
0.1778
Under fill
14
11.968
16.764
2.618 ± 0.254
Flush to 1.4 Max
1
2
3
4
5
6
7
1.27
UTRPNMLKJHFGEDCBA
0.84
20.32
3.19
7.62
Solder Ball 0.889 ± 0.04 diameter
12.294
IBM0436166XLAC
IBM0418166XLAC
16Mb (512K x 36 & 1M x 18) SRAM Preliminary
Revision Log
Page 24 of 25
XLACds.fm.00
November 24, 2003
Revision Log
Rev Contents of Modification
November 24, 2003 Initial release (00).
C0pyright and Disclaimer
© Copyright International Business Machines Corporation 2003
All Rights Reserved
Printed in the United States of America November 2003.
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or
both.
IBM IBM Logo
IEEE is a registered trademark in the United States of the Institute of Electrical and Electronics Engineers.
Other company, product, and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document
are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction
could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not
affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied
license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this docu-
ment was obtained in specific environments, and is presented as an illustration. The results obtained in other operating
environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN “AS IS” BASIS. In no event will IBM be
liable for damages arising directly or indirectly from any use of the information contained in this document.
IBM Microelectronics Division
2070 Route 52, Bldg. 330
Hopewell Junction, NY 12533-6351
The IBM home page can be found at ibm.com
The IBM Microelectronics Division home page can be found at ibm.com/chips
XLACds.fm.00
November 24, 2003
Note: This document contains information on products in the sampling and/or initial production phases of
development. This information is subject to change without notice. Verify with your IBM field applications
engineer that you have the latest version of this document before finalizing a design.
While the information contained herein is believed to be accurate, such information is preliminary, and should not be
relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made.
