38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
1
DESCRIPTION
The 38B7 group is the 8-bit microcomputer based on the 740 family
core technology.
The 38B7 group has six 8-bit timers, one 16-bit timer, a fluorescent
display automatic display circuit, 16-channel 10-bit A-D converter, a
serial I/O with automatic transfer function, which are available for
controlling musical instruments and household appliances.
The 38B7 group has variations of internal memory type. For details,
refer to the section on part numbering.
For details on availability of microcomputers in the 38B7 group, refer
to the section on group expansion.
Built-in pull-down resistors connected to high-breakdown voltage ports
are available by specifying with the mask option in the mask ROM
version. For the details, refer to the section on the mask option of
pull-down resistor.
FEATURES
<Microcomputer mode>
•Basic machine-language instructions....................................... 71
•The minimum instruction execution time .......................... 0.48 µs
(at 4.19 MHz oscillation frequency)
•Memory sizeROM ........................................................ 60K bytes
RAM .......................................................2048 bytes
•Programmable input/output ports ............................................. 75
•High-breakdown-voltage output ports ...................................... 52
•Software pull-up resistors. (Ports P64 to P67, P7, P80 to P83, P9,
PA, PB)
•Interrupts .................................................. 22 sources, 16 vectors
•Timers ...........................................................8-bit ✕ 6, 16-bit ✕ 1
•Serial I/O1 (Clock-synchronized) ................................... 8-bit ✕ 1
(max. 256-byte automatic transfer function)
•Serial I/O2 (UART or Clock-synchronized) .................... 8-bit ✕ 1
•Serial I/O3 (Clock-synchronized) ................................... 8-bit ✕ 1
•PWM ............................................................................ 14-bit ✕ 1
8-bit ✕ 1 (also functions as timer 6)
•A-D converter .............................................. 10-bit ✕ 16 channels
•D-A converter ................................................................1 channel
•Fluorescent display function......................... Total 56 control pins
•Interrupt interval determination function ..................................... 1
(Serviceable even in low-speed mode)
•Watchdog timer ............................................................ 16-bit ✕ 1
•Buzzer output ............................................................................. 1
•Two clock generating circuits
Main clock (XIN–XOUT).......................... Internal feedback resistor
Sub-clock (XCIN–XCOUT) ..........Without internal feedback resistor
(connect to external ceramic resonator or quartz-crystal oscillator)
•Power source voltage
In high-speed mode ...................................................4.0 to 5.5 V
(at 4.19 MHz oscillation frequency and high-speed selected)
In middle-speed mode........................................... 2.7 to 5.5 V (*)
(at 4.19 MHz oscillation frequency and middle-speed selected)
In low-speed mode ................................................ 2.7 to 5.5 V (*)
(at 32 kHz oscillation frequency)
(*: 4.0 to 5.5 V for Flash memory version)
•Power dissipation
In high-speed mode ..........................................................35 mW
(at 4.19 MHz oscillation frequency)
In low-speed mode .............................................................60 µW
(at 32 kHz oscillation frequency, at 3 V power source voltage)
•Operating temperature range ................................... –20 to 85 °C
<Flash memory mode>
●Supply voltage ................................................. V CC = 5 V ± 10 %
●Program/Erase voltage ............................... VPP = 11.7 to 12.6 V
●Programming method...................... Programming in unit of byte
●Erasing method
Batch erasing ........................................ Parallel/Serial I/O mode
Block erasing .................................... CPU reprogramming mode
●Program/Erase control by software command
●Number of times for programming/erasing ............................ 100
●Operating temperature range (at programming/erasing)
..................................................................... Normal temperature
■Notes
1. The flash memory version cannot be used for application em-
bedded in the MCU card.
2. Power source voltage Vcc of the flash memory version is 4.0
to 5.5 V.
APPLICATION
Musical instruments, VCR, household appliances, etc.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
2
Fig. 1 Pin configuration of M38B79MFH-XXXXFP
PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
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2
5
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7
2
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6
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3
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6
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7
4
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10
0
M
3
8
B
7
9
M
F
H
-
X
X
X
X
F
P
*
P
4
7
/
F
L
D
3
9
*
P
0
0
/
F
L
D
8
*
P
0
3
/
F
L
D
1
1
*
P
0
4
/
F
L
D
1
2
*
P
0
5
/
F
L
D
1
3
*
P
0
6
/
F
L
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1
4
*
P
0
7
/
F
L
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1
5
*
P
1
1
/
F
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1
7
*
P
1
2
/
F
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1
8
*
P
1
3
/
F
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1
9
*
P
1
4
/
F
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2
0
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P
1
5
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F
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2
1
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1
6
/
F
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2
2
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1
7
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F
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3
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F
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6
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9
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V
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4
6
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F
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3
8
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4
3
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F
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3
5
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4
2
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F
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3
4
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4
1
/
F
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3
3
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P
4
0
/
F
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3
2
*
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3
7
/
F
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3
1
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3
6
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F
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3
0
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3
5
/
F
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2
9
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P
3
4
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F
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2
8
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3
3
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F
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2
7
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3
2
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F
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2
6
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P
3
1
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F
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2
5
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3
0
/
F
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2
4
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P
4
5
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F
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3
7
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4
4
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F
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3
6
P
B
5
/
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1
P
B
4
/
S
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L
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1
1
P
B
3
/
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1
P
A
6
/
A
N
6
P
A
7
/
A
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7
V
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F
A
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S
S
P
9
0
/
S
I
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3
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A
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8
P
9
1
/
S
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3
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A
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9
P
9
2
/
S
C
L
K
3
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A
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1
0
P
9
4
/
R
T
P
1
/
A
N
1
2
P
9
5
/
R
T
P
0
/
A
N
1
3
P
9
6
/
P
W
M
0
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A
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1
4
P
9
7
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B
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0
2
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A
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1
5
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B
2
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1
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A
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5
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6
/
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6
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2
7
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7
P
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6
/
S
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1
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P
5
1
/
F
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4
1
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P
5
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F
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0
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P
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3
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F
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3
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2
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7
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5
6
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F
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6
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6
1
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F
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9
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6
0
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F
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8
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6
3
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1
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P
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2
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5
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3
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C
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:
1
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6
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2
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
3
Fig. 2 Functional block diagram
FUNCTIONAL BLOCK DIAGRAM
P
o
r
t
P
0
(8
)
8
P
o
r
t
P
1
(
8
)
8
P
o
r
t
P
2
(
8
)
8
P
o
r
t
P
3
(
8
)
8
P
o
r
t
P
4
(
8
)
8
P
o
r
t
P
6
(
8
)
8
P
o
r
t
P
7
(
8
)
8
P
o
r
t
P
8
(
4
)
4
P
o
r
t
P
9
(
8
)
8
P
o
r
t
P
A
(
8
)
8
S
y
s
t
e
m
c
l
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c
k
g
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n
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r
a
t
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XI
N-
XO
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T
(
m
a
i
n
-
c
l
o
c
k
)
XC
I
N-
XC
O
U
T
(
s
u
b
-
c
l
o
c
k
)
T
i
m
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r
s
T
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m
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r
X
(
1
6
-
b
i
t
)
T
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m
e
r
1
(
8
-
b
i
t
)
T
i
m
e
r
2
(
8
-
b
i
t
)
T
i
m
e
r
3
(
8
-
b
i
t
)
T
i
m
e
r
4
(
8
-
b
i
t
)
T
i
m
e
r
5
(
8
-
b
i
t
)
T
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6
(
8
-
b
i
t
)
A
-
D
c
o
n
v
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r
(
1
0
-
b
i
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✕
1
2
c
h
a
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n
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l
)
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P
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M
e
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I
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p
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P
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(
1
4
-
b
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P
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1
(
8
-
b
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)
S
e
r
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C
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)
(
2
5
6
b
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a
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r
a
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s
f
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S
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I
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O
2
(
C
l
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c
k
-
s
y
n
c
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d
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A
R
T
)
F
L
D
d
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p
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a
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f
u
n
c
t
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n
5
6
c
o
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t
r
o
l
p
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n
s
(
5
2
h
i
g
h
-
b
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a
k
d
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w
n
v
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t
a
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p
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)
I
n
t
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r
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p
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v
a
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d
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f
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n
B
u
z
z
e
r
o
u
t
p
u
t
P
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r
t
P
5
(
8
)
8
S
e
r
i
a
l
I
/
O
3(
C
l
o
c
k
-
s
y
n
c
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r
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n
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d
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P
o
r
t
P
B
(
7
)
7
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
4
Table 1 Pin description (1)
Pin Name Function
VCC, VSS Power source • Apply voltage of 4.0–5.5 V to VCC, and 0 V to VSS.
CNVSS CNVSS • Connect to VSS.
• VPP power input pin in flash memory mode.
VEE Pull-down • Apply voltage supplied to pull-down resistors of ports P0, P1, P2 and P3.
power source
VREF Reference voltage • Reference voltage input pin for A-D converter.
AVSS Analog power • Analog power source input pin for A-D converter.
source • Connect to VSS.
______
RESET Reset input • Reset input pin for active “L”.
XIN Clock input • Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set the
XOUT Clock output oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• The clock is used as the oscillating source of system clock.
P00/FLD8–Output port P0 • 8-bit output port. • FLD automatic display
P07/FLD15 • High-breakdown-voltage P-channel open-drain output structure. pins
• A pull-down resistor is built in between port P0 and the VEE pin.
• At reset, this port is set to VEE level.
P10/FLD16–I/O port P1 • 8-bit I/O port. • FLD automatic display
P17/FLD23 • I/O direction register allows each pin to be individually programmed as either pins
input or output.
• At reset, this port is set to input mode.
• Low-voltage input level.
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P1 and the VEE pin.
• At reset, this port is set to VEE level.
P20/FLD0–Output port P2 • 8-bit output port with the same function as port P0. • FLD automatic display
P27/FLD7• High-breakdown-voltage P-channel open-drain output structure. pins
• A pull-down resistor is built in between port P2 and the VEE pin.
• At reset, this port is set to VEE level.
P30/FLD24– I/O port P3 • 8-bit I/O port with the same function as port P1. • FLD automatic display
P37/FLD31 • Low-voltage input level. pins
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is built in between port P3 and the VEE pin.
• At reset, this port is set to VEE level.
P40/FLD32–I/O port P4 • 8-bit I/O port with the same function as port P1. • FLD automatic display
P47/FLD39 • Low-voltage input level. pins
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P4 and the VEE pin.
P50/FLD40–I/O port P5 • 8-bit I/O port with the same function as port P1. • FLD automatic display
P57/FLD47 • Low-voltage input level. pins
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P5 and the VEE pin.
P60/FLD48–I/O port P6 • 4-bit I/O port with the same function as port P1. • FLD automatic display
P63/FLD51 • Low-voltage input level. pins
• High-breakdown-voltage P-channel open-drain output structure.
• A pull-down resistor is not built in between port P6 and the VEE pin.
Function except a port function
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
5
Table 2 Pin description (2)
Function except a port function
Pin Name Function
P64/RXD/FLD52, I/O port P6 • 4-bit I/O port . • FLD automatic display
P65/TXD/FLD53,• Low-voltage input level for input ports. pins
P66/SCLK21/FLD54,• CMOS compatible input level for RxD, SCLK21, SCLK22.• Serial I/O2 function pins
P67/SRDY2/SCLK22/• CMOS 3-state output structure.
FLD55,
P70/INT0, I/O port P7 • 8-bit I/O port. • Interrupt input pins
P71/INT1,• CMOS compatible input level.
P72/INT2,• CMOS 3-state output structure.
P73/INT3/DIMOUT,• Interrupt input pin
• Dimmer signal output pin
P74/PWM1• PWM output pin
P75/T1OUT,• Timer output pins
P76/T3OUT,
P77/INT4/BUZ01 • Interrupt input pin
• Buzzer output pin
P80/XCIN, I/O port P8 • 4-bit I/O port with the same function as port P7. •
I/O pins for sub-clock generating
P81/XCOUT • CMOS compatible input level.
circuit (connect a ceramic resonator
• CMOS 3-state output structure.
or a quarts-crystal oscillator)
P82/CNTR1,• Timer input pin
P8
3
/CNTR
0
/CNTR
2
• Timer I/O pin
P90/SIN3/AN8,
I
/O port P9 • 8-bit I/O port with the same function as port P7. • Serial I/O3 function pins
P91/SOUT3/AN9,• CMOS compatible input level. • A-D converter input pins
P92/SCLK3/AN10,• CMOS 3-state output structure.
P93/SRDY3/AN11,
P94/RTP1/AN12,• Real time port output pins
P95/RTP0/AN13 • A-D converter input pins
P96/PWM0/AN14 • 14-bit PWM output pin
• A-D converter input pin
P97/BUZ02/AN15 • Buzzer output pin
• A-D converter input pin
PA
0
/AN
0
–PA
7
/AN
7
I
/O port PA • 8-bit I/O port with the same function as port P7. • A-D converter input pin
• CMOS compatible input level.
• CMOS 3-state output structure.
PB0/SCLK12/DA
I
/O port PB • 7-bit I/O port with the same function as port P7. • Serial I/O1 function pin
• CMOS compatible input level. • D-A converter output pin
• CMOS 3-state output structure.
PB1/SRDY1,• Serial I/O1 function pins
PB2/SBUSY1,
PB3/SSTB1,
PB4/SCLK11,
PB5/SOUT1,
PB6/SIN1
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
6
Fig. 3 Part numbering
M
3
8
B
7
9
M
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.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
7
GROUP EXPANSION
Mitsubishi plans to expand the 38B7 group as follows.
Memory Type
Support for Mask ROM and Flash memory versions.
Memory Size
Flash memory size ........................................................... 60K bytes
Mask ROM size................................................................ 60K bytes
RAM size .........................................................................2048 bytes
Package
100P6S-A.................................. 0.65 mm-pitch plastic molded QFP
Fig. 4 Memory expansion plan
Currently supported products are listed below.
Table 3 List of supported products
Note : Products under development: the development schedule and specifications may be revised without notice.
As of Mar. 2000
Product
M38B79MFH-XXXXFP
M38B79FFFP
ROM size (bytes)
ROM size for User ( )
61440
(61310)
RAM size (bytes)
2048
Package
100P6S-A
Remarks
Mask ROM version
Flash memory version
6
0
K
5
6
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5
2
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4
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4
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
8
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 38B7 group uses the standard 740 Family instruction set. Re-
fer to the table of 740 Series addressing modes and machine
instructions or the 740 Series Software Manual for details on the
instruction set.
Machine-resident 740 Series instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
[Index Register X (X)]
The index register X is an 8-bit register. In the index addressing
modes, the value of the OPERAND is added to the contents of
register X and specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In par tial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the
contents of the stack pointer. The high-order 8 bits of the stack ad-
dress are determined by the stack page selection bit. If the stack
page selection bit is “0” , the high-order 8 bits becomes “0016”. If
the stack page selection bit is “1”, the high-order 8 bits becomes
“0116”.
The operations of pushing register contents onto the stack and
popping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with pro-
gram when the user needs them during interrupts or subroutine
calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit
registers PC H and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 5 740 Family CPU register structure
A Accumulator
b7
b7
b7
b7 b0
b7b15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PC
L
Program counterPC
H
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
9
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 6 Register push and pop at interrupt generation and subroutine call
N
o
t
e:
C
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(
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)
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P
CL)
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)
(
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(
S
)
(
S
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+
1
(
S
)
(
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)
+
1
(
P
CH)M
(
S
)
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(
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(
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(
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(
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–
1
(
P
CL)M
(
S
)
(
S
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(
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p
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u
e
s
t
(
N
o
t
e
)
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d
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s
a
b
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f
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s
“
0
”
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
10
[Processor status register (PS)]
The processor status register is an 8-bit register consisting of 5
flags which indicate the status of the processor after an arithmetic
operation and 3 flags which decide MCU operation. Branch opera-
tions can be performed by testing the Carry (C) flag , Zero (Z) flag,
Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z,
V, N flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt
generated by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are
executed in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was
generated by the BRK instruction. The BRK flag in the processor
status register is always “0”. When the BRK instruction is used to
generate an interrupt, the processor status register is pushed
onto the stack with the break flag set to “1”.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed
between accumulator and memory. When the T flag is “1”, direct
arithmetic operations and direct data transfers are enabled
between memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location
operated on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of eac h bit of processor status register
Set instruction
Clear instruction
C flag Z flag I flag D flag B flag T flag V flag N flag
SEC
CLC
_
_SEI
CLI SED
CLD
_
_SET
CLT CLV
__
_
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
11
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the internal system clock selection bit etc.
The CPU mode register is allocated at address 003B16.
Fig. 7 Structure of CPU mode register
C
P
U
m
o
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(
C
P
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:
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3
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:
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n
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h
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)
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
12
MEMORY
Special Function Register (SFR) Area
The special function register (SFR) area contains control registers
for I/O ports, timers and other functions.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing, and the other areas are user areas for storing pro-
grams.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
The zero page addressing mode can be used to specify memory and
register addresses in the zero page area. Access to this area with
only 2 bytes is possible in the zero page addressing mode.
Special Page
The special page addressing mode can be used to specify memory
addresses in the special page area. Access to this area with only 2
bytes is possible in the special page addressing mode.
Fig. 8 Memory map diagram
0100
16
0000
16
0040
16
0440
16
FF00
16
FFDC
16
FFFE
16
FFFF
16
192
256
384
512
640
768
896
1024
1536
2048
XXXX
16
00FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
063F
16
083F
16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F000
16
E000
16
D000
16
C000
16
B000
16
A000
16
9000
16
8000
16
7000
16
6000
16
5000
16
4000
16
3000
16
2000
16
1000
16
F080
16
E080
16
D080
16
C080
16
B080
16
A080
16
9080
16
8080
16
7080
16
6080
16
5080
16
4080
16
3080
16
2080
16
1080
16
YYYY
16
ZZZZ
16
RAM
ROM
0EE0
16
0F00
16
0EFF
16
0FFF
16
0EDF
16
0E00
16
Reserved area
SFR area 1
Not used (Note)
Interrupt vector area
ROM area
Reserved ROM area
(common ROM area,128 bytes)
Zero page
Special page
RAM area
RAM size
(byte) Address
XXXX
16
ROM size
(byte) Address
YYYY
16
Reserved ROM area
Address
ZZZZ
16
SFR area 2
RAM area for Serial I/O
automatic transfer
Note: When 1024 bytes or more are used as RAM area, this area can be used.
RAM area for FLD automatic display
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
13
Fig. 9 Memory map of special function register (SFR)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001E16
001F16
Serial I/O2 transmit/receive buffer register (TB/RB)
Port P0 (P0)
Port P1 (P1)
Port P2 (P2)
Port P3 direction register (P3D)
Port P3 (P3)
Port P4 (P4)
Port P4 direction register (P4D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P6 (P6)
Port P6 direction register (P6D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Serial I/O1 automatic transfer data pointer (SIO1DP)
Serial I/O1 control register 1 (SIO1CON1)
Serial I/O1 control register 2 (SIO1CON2)
Serial I/O1 register/Transfer counter (SIO1)
Serial I/O1 control register 3 (SIO1CON3)
Serial I/O2 control register (SIO2CON)
Serial I/O2 status register (SIO2STS)
Port P9 (P9)
Port P9 direction register (P9D)
0EF016
0EF116
0EF216
0EF316
0EF416
0EF516
0EF616
0EF716 Toff2 time set register (TOFF2)
Pull-up control register 1 (PULL1)
Pull-up control register 2 (PULL2)
FLDC mode register (FLDM)
Tdisp time set register (TDISP)
Toff1 time set register (TOFF1)
002016
002116
002216
002316
002416
002516
002616
002716
002816
002916
002A16
002B16
002C16
002D16
002E16
002F16
003016
003116
003216
003316
003416
003516
003616
003716
003816
003916
003A16
003B16
003C16
003D16
003E16
003F16
Timer X mode register 1 (TXM1)
Interrupt control register 2(ICON2)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 4 (T4)
Timer 5 (T5)
Timer 6 (T6)
PWM control register (PWMCON)
Timer 6 PWM register (T6PWM)
Timer 12 mode register (T12M)
Timer 34 mode register (T34M)
Timer 56 mode register (T56M)
Timer X (low-order) (TXL)
Timer X (high-order) (TXH)
Timer X mode register 2 (TXM2)
Interrupt interval determination register (IID)
Interrupt interval determination control register (IIDCON)
AD/DA control register (ADCON)
A-D conversion register (low-order) (ADL)
A-D conversion register (high-order) (ADH)
Interrupt source switch register (IFR)
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1(IREQ1)
Interrupt request register 2(IREQ2)
Interrupt control register 1(ICON1)
0EF816
0EF916
0EFA16
0EFB16
0EFC16
0EFD16
0EFE16
0EFF16
FLD data pointer (FLDDP)
Port P4 FLD/Port switch register (P4FPR)
Port P5 FLD/Port switch register (P5FPR)
Port P6 FLD/Port switch register (P6FPR)
FLD output control register (FLDCON)
Buzzer output control register (BUZCON)
Port P1 direction register (P1D)
PWM register (high-order) (PWMH)
PWM register (low-order) (PWML)
Baud rate generator (BRG)
UART control register (UARTCON)
Port PA (PA)
Port PA direction register (PAD)
Port PB (PB)
Port PB direction register (PBD)
0EEC16
0EED16
Serial I/O3 control register (SIO3CON)
Serial I/O3 register (SIO3)
0EEE16 Watchdog timer control register (WDTCON)
0EEF16 Pull-up control register 3 (PULL3)
Port P0 digit output set switch register
(P0DOR)
Port P2 digit output set switch register
(P2DOR)
Flash memory control register (FCON)
Flash command register (FCMD) (Note)
(Note)
Note: Flash memory version only.
D-A conversion register (DA)
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
14
I/O PORTS
[Direction Registers] PiD
The 38B7 group has 75 programmable I/O pins arranged in ten in-
dividual I/O ports (P1, P3, P4, P5, P6, P7, P8, P9, PA and PB).
The I/O ports have direction registers which determine the input/
output direction of each individual pin. Each bit in a direction reg-
ister corresponds to one pin, and each pin can be set to be input
port or output port. When “0” is written to the bit corresponding to
a pin, that pin becomes an input pin. When “1” is written to that
pin, that pin becomes an output pin. If data is read from a pin set
to output, the value of the port output latch is read, not the value of
the pin itself. Pins set to input (the bit corresponding to that pin
must be set to “0”) are floating and the value of that pin can be
read. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
Fig. 10 Structure of pull-up control registers
(PULL1, PULL2 and PULL3)
[High-Breakdown-Voltage Output Ports]
The 38B7 group has seven ports with high-breakdown-voltage
pins (ports P0 to P5 and P60–P63). The high-breakdown-v oltage
ports have P-channel open-drain output with Vcc – 45 V of break-
down voltage. Each pin in ports P0 to P3 has an internal pull-down
resistor connected to V EE. At reset, the P-channel output transis-
tor of each por t latch is turned off, so that it goes to VEE level (“L”)
by the pull-down resistor.
Wr iting “1” (weak drivability) to bit 7 of the FLDC mode register
(address 0EF4 16) shows the rising transition of the output transis-
tors for reducing transient noise. At reset, bit 7 of the FLDC mode
register is set to “0” (strong drivability).
[Pull-up Control Register] PULL
Ports P64–P67, P7, P80–P83, P9, PA and PB have built-in pro-
grammable pull-up resistors. The pull-up resistors are valid only in
the case that the each control bit is set to “1” and the correspond-
ing port direction registers are set to input mode.
0: No pull-up
1: Pull-up
Pull-up control register 3
(PULL3 : address 0EEF16)
PA0, PA1 pull-up control bit
PA2, PA3 pull-up control bit
PA4, PA5 pull-up control bit
PA6, PA7 pull-up control bit
PB0, PB1 pull-up control bit
PB2, PB3 pull-up control bit
PB4, PB5 pull-up control bit
PB6 pull-up control bit
b7 b0
0: No pull-up
1: Pull-up
Pull-up control register 1
(PULL1 : address 0EF016)
P64, P65 pull-up control bit
P66, P67 pull-up control bit
P70, P71 pull-up control bit
P72, P73 pull-up control bit
P74, P75 pull-up control bit
P76, P77 pull-up control bit
Not used (returns “0” when read)
(Do not write “1”.)
b7 b0
Pull-up control register 2
(PULL2 : address 0EF116)
P80, P81 pull-up control bit
P82, P83 pull-up control bit
P90, P91 pull-up control bit
P92, P93 pull-up control bit
P94, P95 pull-up control bit
P96, P97 pull-up control bit
Not used (returns “0” when read)
(Do not write “1”.)
b7 b0
Not used (returns “0” when read)
(Do not write “1”.)
0: No pull-up
1: Pull-up
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
15
Table 6 List of I/O port functions (1)
Pin
P00/FLD8–
P07/FLD15
Nama
Port P0 Input/Output
Output I/O Format
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output with pull-down
resistor
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
High-breakdown voltage
P-channel open-drain
output
Low-voltage input level
(port input)
CMOS compatible input
level (RxD, S CLK21,
SCLK22)
CMOS 3-state output
Non-Port Function
FLD automatic display
function
Related SFRs
FLDC mode register
P0 digit output set switch
register
Ref.No.
(1)
(2)FLDC mode register
FLD automatic display
function
Serial I/O2 function I/O
P10/FLD16–
P17/FLD23 Port P1 Input/output,
individual
bits
FLDC mode register
P2 digit output set switch
register
(1)P20/FLD0–
P27/FLD7Port P2 Output
P30/FLD24–
P37/FLD31 Port P3 Input/output,
individual
bits
FLDC mode register (2)
FLDC mode register
Port P4 FLD/Port switch
register
(2)P40/FLD32–
P47/FLD39 Port P4 Input/output,
individual
bits
Input/output,
individual
bits
P50/FLD40–
P57/FLD47 Port P5 FLDC mode register
Port P5 FLD/Port switch
register
(2)
FLDC mode register
Port P6 FLD/Port switch
register
(2)Input/output,
individual
bits
Port P6P60/FLD48–
P63/FLD51
P64/RxD/
FLD52
P65/TxD/
FLD53,
P66/SCLK21/
FLD54
P67/SRDY2/
SCLK22/
FLD55
P70/INT0,
P71/INT1
P72/INT2
CMOS compatible input
level
CMOS 3-state output
FLDC mode register
Serial I/O2 control
register
UART control register
Interrupt edge selection
register
(3)
(4)
(5)
(6)Port P7 Input/output,
individual
bits
External interrput input
Interrupt edge selection
register
Interrupt interval determi-
nation control register
Interrupt edge selection
register
FLD output control register
Timer 56 mode register
Timer 12 mode register
Timer 34 mode register
Buzzer output control
register
Interrupt edge selection
register
CPU mode register
(7)P73/INT3/
DIMOUT External interrput input
Dimmer signal output
(8)P74/PWM1
P75/T1OUT
P76/T3OUT
P77/INT4/
BUZ01
CMOS compatible input
level
CMOS 3-state output
PWM output
Timer output
Timer output
Buzzer output
External interrput input (9)
Sub-clock generating
circuit I/O
External count input
P80/XCIN
P81/XCOUT
P82/CNTR1
P83/CNTR0/
CNTR2
Port P8 Input/output,
individual
bits
(10)
(11)
(6)
(12)
Interrupt edge selection
register
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
16
Notes 1 : How to use double-function ports as function I/O ports, refer to the applicable sections.
2 : Make sure that the input level at each pin is either 0 V or Vcc during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from Vcc to Vss through the input-stage gate.
Table 7 List of I/O port functions (2)
Pin
P90/SIN3/
AN8
P91/SOUT3/
AN9,
P92/SCLK3/
AN10
P93/SRDY3/
AN11
P94/RTP1/
AN12,
P95/RTP0/
AN13
P96/PWM0/
AN14
P97/BUZ02/
AN15
PA0/AN0–
PA7/AN7
Nama
Port P9 Input/Output
Input/output,
individual
bits
Non-Port Function
Serial I/O3 function I/O
A-D conversion input
Related SFRs
Serial I/O3 control
register
AD/DA control register
Ref.No.
(6)
I/O Format
CMOS compatible input
level
CMOS 3-state output
Po rt PA CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
(13)
(14)
(15)Real time port output
A-D conversion input Timer X mode register 2
AD/DA control register
PWM output
A-D conversion input
Buzzer output
A-D conversion input
A-D conversion input
PWM control register
AD/DA control register
Buzzer output control register
AD/DA control register
AD/DA control register
(16)
(16)
(17)
PB0/SCLK12/
DA
PB1/SRDY1
PB2/SBUSY1
PB3/SSTB1
PB4/SCLK11
PB5/SOUT1
PB6/SIN1
(18)Serial I/O1 control
registers 1, 2
AD/DA control register
Serial I/O1 control
registers 1, 2 (19)
(18)
(20)
(21)
(6)
Serial I/O1 function I/O
D-A conversion output
Port PB
Input/output,
individual
bits
Input/output,
individual
bits
Serial I/O1 function I/O
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
17
Fig. 11 Port block diagram (1)
(
6
)
P
o
r
t
s
P
7
0
t
o
P
7
2
,
P
8
2
,
P
9
0
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P
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6
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7
(
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P
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P
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(
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P
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
18
Fig. 12 Port block diagram (2)
(
8
)
P
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t
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7
4
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s
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
19
Fig. 13 Port block diagram (3)
(
1
5
)
P
o
r
t
s
P
9
4
,
P
9
5
R
T
P
o
u
t
p
u
t
(
1
6
)
P
o
r
t
s
P
9
6
,
P
9
7
(20) Port PB
3
S
STB1
output
(
1
8
)
P
o
r
t
s
P
B
0
,
P
B
2
Serial clock input
S
BUSY1
input
S
CLK12
output
S
BUSY1
out
p
ut
P
B
0
(
1
7
)
P
o
r
t
P
A
(19) Port PB
1
(
2
1
)
P
o
r
t
s
P
B
4
,
P
B
5
S
O
U
T
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r
S
C
L
K
P
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4
D
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n
b
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s
D
a
t
a
b
u
s
Port latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
PWM output se lec tion bit
Buzzer control signal
P
u
l
l
-
u
p
c
o
n
t
r
o
l
A-D conversion input
Analog input pin selection bits
PWM output
Buzzer sig nal output
D
a
t
a
b
u
s
Port latch
Direction register
P
u
l
l
-
u
p
c
o
n
t
r
o
l
A
-
D
c
o
n
v
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r
s
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n
p
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t
A
n
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p
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p
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s
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e
c
t
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n
b
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s
S
e
r
i
a
l
I
/
O
1
s
e
l
e
c
t
i
o
n
s
i
g
n
a
l
P
B
1
/
S
R
D
Y
1
•
P
B
2
/
S
B
U
S
Y
1
p
i
n
c
o
n
t
r
o
l
b
i
t
D
-
A
c
o
n
v
e
r
t
e
r
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t
p
u
t
D
-
A
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
Data bus
Port latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
P
u
l
l
-
u
p
c
o
n
t
r
o
l
PB
1
/S
RDY1
•PB
2
/S
BUSY1
pin
control bit
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Serial ready output Serial ready input
PB
3
/S
STB1
pin control bit
D
a
t
a
b
u
s
P
o
r
t
l
a
t
c
h
Direction register
Pull-up control
D
a
t
a
b
u
s
Port latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
P-channel output di s able signal (PB
5
)
Output OFF control signal
Serial I/O1 selection signal
S
e
r
i
a
l
c
l
o
c
k
i
n
p
u
t
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
20
INTERRUPTS
Interrupts occur by twenty two sources: five external, sixteen inter-
nal, and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an inter-
rupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0.” Interrupt enable bits can be set or cleared by software. Interrupt
request bits can be cleared by software, but cannot be set by soft-
ware. The BRK instruction interrupt and reset cannot be disabled
with any flag or bit. The I flag disables all interrupts except the BRK
instruction interrupt and reset. If several interrupts requests occur at
the same time, the interrupt with highest priority is accepted first.
Interrupt Operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The contents of the program counter and processor status
register are automatically pushed onto the stack.
2. The interrupt disable flag is set and the corresponding
interrupt request bit is cleared.
3. The interrupt jump destination address is read from the vector
table into the program counter.
Interrupt Source Selection
Any of the following interrupt sources can be selected by the inter-
rupt source switch register (address 003916).
1. INT1 or Serial I/O3
2. INT3 or Serial I/O2 transmit
3. INT4 or A-D conversion
■Note
When the active edge of an external interrupt (INT0–INT4) is set or
when switching interrupt sources in the same vector address, the
corresponding interrupt request bit may also be set. Therefore, please
take following sequence:
(1) Disable the external interrupt which is selected.
(2) Change the active edge in interrupt edge selection register
(3) Clear the set interrupt request bit to “0.”
(4) Enable the external interrupt which is selected.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
21
Vector Addresses (Note 1) Interrupt Request
Interrupt Source Priority Remarks
High Low Generating Conditions
Reset (Note 2) 1 FFFD16 FFFC16 At reset Non-maskable
INT02 FFFB16 FFFA16 At detection of either rising or falling edge of External interrupt
INT0 input (active edge selectable)
INT13 FFF916 FFF816 At detection of either rising or falling edge of External interrupt
INT1 input (active edge selectable)
Valid when INT1 interrupt is selected
Serial I/O3 At completion of data transfer Valid when serial I/O3 is selected
INT24 FFF716 FFF616 At detection of either rising or falling edge of External interrupt
INT2 input (active edge selectable)
Remote control/ At 8-bit counter overflow Valid when interrupt interval
counter overflow determination is operating
Serial I/O1 5 FFF516 FFF416 At completion of data transfer Valid when serial I/O ordinary
mode is selected
Serial I/O auto- At completion of the last data transfer Valid when serial I/O automatic
matic transfer transfer mode is selected
Timer X 6 FFF316 FFF216 At timer X underflow
Timer 1 7 FFF116 FFF016 At timer 1 underflow
Timer 2 8 FFEF16 FFEE16 At timer 2 underflow STP release timer underflow
Timer 3 9 FFED16 FFEC16 At timer 3 underflow
Timer 4 10 FFEB16 FFEA16 At timer 4 underflow
Timer 5 11 FFE916 FFE816 At timer 5 underflow
Timer 6 12 FFE716 FFE616 At timer 6 underflow
Serial I/O2 receive
13 FFE516 FFE416 At completion of serial I/O2 data receive
INT314 FFE316 FFE216 At detection of either rising or falling edge of External interrupt
INT3 input (active edge selectable)
Valid when INT3 interrupt is selected
Serial I/O2 transmit
At completion of serial I/O2 data transmit
INT415 FFE116 FFE016 At detection of either rising or falling edge of External interrupt
INT4 input (active edge selectable)
Valid when INT4 interrupt is selected
A-D conversion At completion of A-D conversion
Valid when A-D conversion is selected
FLD blanking 16 FFDF16 FFDE16 At falling edge of the last timing immediately Valid when FLD blanking
before blanking period starts interrupt is selected
FLD digit At rising edge of digit (each timing)
Valid when FLD digit interrupt is selected
BRK instruction 17 FFDD16 FFDC16 At BRK instruction execution Non-maskable software interrupt
Table 8 Interrupt vector addresses and priority
Notes 1 : Vector addresses contain interrupt jump destination addresses.
2 : Reset function in the same way as an interrupt with the highest priority.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
22
Fig. 15 Structure of interrupt related registers
Fig. 14 Interrupt control
b
7
b
7
b
7
b
7
b
7
b
7b
0
b
0
b
0
b
0
b
0
b
0
I
N
T
0
i
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
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N
T1
i
n
t
e
r
r
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p
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n
a
b
l
e
b
i
t
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e
r
i
a
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I
/
O
3
i
n
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e
r
r
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1
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Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
23
TIMERS
8-Bit Timer
The 38B7 group has six built-in 8-bit timers : Timer 1, Timer 2, Timer
3, Timer 4, Timer 5, and Timer 6.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016”, an underflow occurs with the next
count pulse. Then the contents of the timer latch is reloaded into the
timer and the timer continues down-counting. When a timer
underflows, the interrupt request bit corresponding to that timer is set
to “1”.
The count can be stopped by setting the stop bit of each timer to “1”.
The internal system clock can be set to either the high-speed mode
or low-speed mode with the CPU mode register. At the same time,
the timer internal count source is switched to either f(XIN) or f(XCIN).
●Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register. A rectangular waveform of timer 1 under-
flow signal divided by 2 can be output from the P75/T1OUT pin. The
active edge of the external clock CNTR0 can be switched with the bit
6 of the interrupt edge selection register.
At reset or when executing the STP instruction, all bits of the timer 12
mode register are cleared to “0”, timer 1 is set to “FF16”, and timer 2
is set to “0116”.
●Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register. A rectangular waveform of timer 3 under-
flow signal divided by 2 can be output from the P76/T3OUT pin. The
active edge of the external clock CNTR1 can be switched with the bit
7 of the interrupt edge selection register.
●Timer 5, Timer 6
The count sources of timer 5 and timer 6 can be selected by setting
the timer 56 mode register. A rectangular waveform of timer 6 under-
flow signal divided by 2 can be output from the P74/PWM1 pin.
●Timer 6 PWM1 Mode
Timer 6 can output a PWM rectangular waveform with “H” duty cycle
n/(n+m) from the P74/PWM1 pin by setting the timer 56 mode regis-
ter (refer to Figure 18). The n is the value set in timer 6 latch (address
002516) and m is the value in the timer 6 PWM register (address
002716). If n is “0,” the PWM output is “L”, if m is “0”, the PWM output
is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur
at the rising edge of the PWM output.
Fig. 16 Structure of timer related registers
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b
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
24
Fig. 17 Block diagram of timer
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2
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
25
Fig. 18 Timing chart of timer 6 PWM1 mode
t
s
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
26
16-Bit Timer
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode registers 1, 2 and can be controlled for the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the low-
order byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
●Timer X
Timer X is a down-counter. When the timer reaches “000016”, an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues down-
counting. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR2 pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR2 pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR2 pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR2 pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR2 active edge switch bit is “0”, the timer counts while the input
signal of the CNTR2 pin is at “H”. When it is “1”, the timer counts
while the input signal of the CNTR2 pin is at “L”. When using a timer
in this mode, set the port shared with the CNTR2 pin to input.
■ Note
•Timer X Write Control
If the timer X write control bit is “0”, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is “1”, when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
•Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P94 and P9 5 each time the timer X underflows.
(However, if the real time port control bit is changed from “0” to “1”,
data are output independent of the timer X.) When the data for the
real time port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction regis-
ters to output mode.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
27
Fig. 20 Structure of timer X related registers
Fig. 19 Block diagram of timer X
b
7b
6b
5b
4b
3
b
2b
1b
0
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o
r
t
f
u
n
c
t
i
o
n
i
s
v
a
l
i
d
P
9
4
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
P
9
5
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
1
(
T
X
M
1
:
a
d
d
r
e
s
s
0
0
2
E
1
6
)
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
0
:
W
r
i
t
e
d
a
t
a
t
o
b
o
t
h
t
i
m
e
r
l
a
t
c
h
a
n
d
t
i
m
e
r
1
:
W
r
i
t
e
d
a
t
a
t
o
t
i
m
e
r
l
a
t
c
h
o
n
l
y
T
i
m
e
r
X
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
s
b
2
b
1
00
:
f
(
X
I
N
)
/
2
o
r
f
(
X
C
I
N
)
/
4
01
:
f
(
X
I
N
)
/
8
o
r
f
(
X
C
I
N
)
/
1
6
10
:
f
(
X
I
N
)
/
6
4
o
r
f
(
X
C
I
N
)
/
1
2
8
11
:
N
o
t
a
v
a
i
l
a
b
l
e
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
b
5
b
4
00
:
T
i
m
e
r
m
o
d
e
01
:
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
10
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
11
:
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R
2
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:•
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
;
c
o
u
n
t
s
r
i
s
i
n
g
e
d
g
e
s
•
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
;
o
u
t
p
u
t
s
t
a
r
t
s
w
i
t
h
“
H
”
l
e
v
e
l
•
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
;
m
e
a
s
u
r
e
s
“
H
”
p
e
r
i
o
d
s
1
:•
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
;
c
o
u
n
t
s
f
a
l
l
i
n
g
e
d
g
e
s
•
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
;
o
u
t
p
u
t
s
t
a
r
t
s
w
i
t
h
“
L
”
l
e
v
e
l
•
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
;
m
e
a
s
u
r
e
s
“
L
”
p
e
r
i
o
d
s
T
i
m
e
r
X
s
t
o
p
c
o
n
t
r
o
l
b
i
t
0
:
C
o
u
n
t
o
p
e
r
a
t
i
n
g
1
:
C
o
u
n
t
s
t
o
p
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
2
(
T
X
M
2
:
a
d
d
r
e
s
s
0
0
2
F
1
6
)
b
7b
6b
5b
4b
3
b
2b
1
b
0
C
N
T
R
2
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
C
N
T
R
2
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
S
“
0
”
“1”
“
0
”
“
1
”“
1
0
”
“
0
0
”
,
“
0
1
”
,
“
1
1
”
Q
QT
P83/CNTR0/CNTR2
CNTR0
“
1
”
“
0
”
“
1
”
“
0
”
“1”
“
0
”
Q
D
Q
D
P94
P95
“1”
“
0
”
XI
N
XC
I
N
“
1
”
“
0
”
1
/
2
1
/
2
1
/
8
1
/
6
4
P
8
3
l
a
t
c
h
Timer X
(
low-order
)
(
8
)
Timer X
(
hi
g
h-order
)
(
8
)
T
i
m
e
r
X
l
a
t
c
h
(
h
i
g
h
-
o
r
d
e
r
)
(
8
)
T
i
m
e
r
X
l
a
t
c
h
(
l
o
w
-
o
r
d
e
r
)
(
8
)
Data bus
P
u
l
s
e
o
u
t
p
u
t
m
o
d
e
P
8
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pulse width
measur em ent mode
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
Timer X stop
control bit
Pulse output mod e
C
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
I
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
D
i
v
i
d
e
r
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Timer X mode register
write signal
P
9
5
l
a
t
c
h
P
9
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
9
4
l
a
t
c
h
P
9
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rLatch
L
a
t
c
h
P
9
4
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
(
P
9
4
)
P9
5
data for r eal time port
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
(
P
9
5
)
T
i
m
e
r
X
m
o
d
e
r
e
g
i
s
t
e
r
w
r
i
t
e
s
i
g
n
a
l
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
28
SERIAL I/O
Serial I/O1
Serial I/O1 is used as the clock synchronous serial I/O and has an
ordinary mode and an automatic transfer mode. In the automatic
transfer mode, serial transfer is performed through the serial I/O
automatic transfer RAM which has up to 256 bytes (addresses
Fig. 21 Block diagram of serial I/O1
0F0016 to 0FFF16).
The PB1/SRDY1, PB2/SBUSY1, and PB3/SSTB1 pins each have a
handshake I/O signal function and can select either “H” active or
“L” active for active logic.
Main
data bus
S
er
i
a
l
I
/
O
1
automatic transfer
controller
L
o
c
a
l
d
a
t
a
b
u
s
Serial I/O automa tic
tran s fe r RAM
(0F00
16
to 0FFF
16
)
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
3
X
C
I
N
X
I
N
Internal system
clock selection bit
S
er
i
a
l
I
/
O
1
automatic transfer
data
p
ointer
Address decoder
M
a
i
n
a
d
d
r
e
s
s
b
u
sLocal address
bus
“
1
”
“0”1/8
1/16
1/32
1
/
6
4
1
/
1
2
8
S
e
r
i
a
l
I
/
O
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
PB
2
latch
Serial I/O1 counter
S
y
n
c
h
r
o
n
o
u
s
c
i
r
c
u
i
t
S
e
r
i
a
l
I
/
O
1
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
“
1
”
P
B
1
l
a
t
c
h
P
B
4
/
S
C
L
K
1
1
“0”
“
1
”
S
C
L
K
1
“0”
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
1/256
PB
3
latch
P
B
2
/
S
B
U
S
Y
1
P
B
3
/
S
S
T
B
1
(
P
B
3
/
S
S
T
B
1
p
i
n
c
o
n
t
r
o
l
b
i
t
)
S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
t
a
t
u
s
f
l
a
g
“
0
”
“1”
“
0
”
“
1
”
P
B
1
/
S
R
D
Y
1
“0”
“
1
”
P
B
4
l
a
t
c
h
PB
5
/S
OUT1
P
B
6
/
S
I
N
1
PB
5
latch
Serial I/O1 re
g
ister ( 8)
“
0
”
“
1
”S
e
r
i
a
l
t
r
a
n
s
f
e
r
s
e
l
e
c
t
i
o
n
b
i
t
s
1
/
2
D
i
v
i
d
e
r
1
/
4
Serial I/O1 clock
p
in selection bit
P
B
0
/
S
C
L
K
1
2
“
1
”
“
0
”
PB
0
latch
“
0
”
“
1
”
“
0
”“1”
S
e
r
i
a
l
I
/
O
1
c
l
o
c
k
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
P
B
1
/
S
R
D
Y
1
•
P
B
2
/
S
B
U
S
Y
1
p
i
n
c
o
n
t
r
o
l
b
i
t
PB
1
/S
RDY1
•PB
2
/S
BUSY1
pin cont r ol bit
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
29
Fig. 22 Structure of serial I/O1 control registers 1, 2
b
7b
6b
5b
4b
3b
2b
1b
0
b
7b
6b
5b
4b
3b
2b
1b
0
P
B1/
SR
D
Y
1
•
P
B2/
SB
U
S
Y
1
p
i
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
b
1
b
0
0
0
0
0
:
P
i
n
s
P
B1
a
n
d
P
B2
a
r
e
I
/
O
p
o
r
t
s
0
0
0
1
:
N
o
t
u
s
e
d
0
0
1
0
:
P
B1
p
i
n
i
s
a
n
SR
D
Y
1
o
u
t
p
u
t
,
P
B2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
0
0
1
1
:
P
B1
p
i
n
i
s
a
n
SR
D
Y
1
o
u
t
p
u
t
,
P
B2
p
i
n
i
s
a
n
I
/
O
p
o
r
t
.
0
1
0
0
:
P
B1
p
i
n
i
s
a
n
I
/
O
p
o
r
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
i
n
p
u
t
.
0
1
0
1
:
P
B1
p
i
n
i
s
a
n
I
/
O
p
o
r
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
i
n
p
u
t
.
0
1
1
0
:
P
B1
p
i
n
i
s
a
n
I
/
O
p
o
r
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
o
u
t
p
u
t
.
0
1
1
1
:
P
B1
p
i
n
i
s
a
n
I
/
O
p
o
r
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
o
u
t
p
u
t
.
1
0
0
0
:
P
B1
p
i
n
i
s
a
n
SR
D
Y
1
i
n
p
u
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
o
u
t
p
u
t
.
1
0
0
1
:
P
B1
p
i
n
i
s
a
n
SR
D
Y
1
i
n
p
u
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
o
u
t
p
u
t
.
1
0
1
0
:
P
B1
p
i
n
i
s
a
n
SR
D
Y
1
i
n
p
u
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
o
u
t
p
u
t
.
1
0
1
1
:
P
B1
p
i
n
i
s
a
n
SR
D
Y
1
i
n
p
u
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
o
u
t
p
u
t
.
1
1
0
0
:
P
B1
p
i
n
i
s
a
n
SR
D
Y
1
o
u
t
p
u
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
i
n
p
u
t
.
1
1
0
1
:
P
B1
p
i
n
i
s
a
n
SR
D
Y
1
o
u
t
p
u
t
,
P
B2
p
i
n
i
s
a
n
SB
U
S
Y
1
i
n
p
u
t
.
1
1
1
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
30
(1) Serial I/O1 operation
Either the internal synchronous clock or external synchronous
clock can be selected by the serial I/O1 synchronous clock selec-
tion bits (b2 and b3 of address 001916) of serial I/O1 control
register 1 as synchronous clock for serial transfer.
The internal synchronous clock has a built-in dedicated divider
where 7 different clocks are selected by the internal synchronous
clock selection bits (b5, b6 and b7 of address 001C16) of serial
I/O1 control register 3.
The PB1/SRDY1, PB2/SBUSY1, and PB3/SSTB1 pins each select ei-
ther I/O port or handshake I/O signal by the serial I/O1
synchronous clock selection bits (b2 and b3 of address 001916) of
serial I/O1 control register 1 as well as the PB1/SRDY1 • PB2/
SBUSY1 pin control bits (b0 to b3 of address 001A16) of serial
I/O1 control register 2.
For the SOUT1 being used as an output pin, either CMOS output
or N-channel open-drain output is selected by the PB5/SOUT1 P-
channel output disable bit (b7 of address 001A16) of serial I/O1
control register 2.
Either output active or high-impedance can be selected as a
SOUT1 pin state at serial non-transfer by the SOUT1 pin control bit
(b6 of address 001A16) of serial I/O1 control register 2. However,
when the external synchronous clock is selected, perform the fol-
lowing setup to put the SOUT1 pin into a high-impedance state:
When the SCLK1 input is “H” after completion of transfer, set the
SOUT1 pin control bit to “1”.
When the SCLK1 input goes to “L” after the start of the next serial
transfer, the SOUT1 pin control bit is automatically reset to “0” and
put into an output active state.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the trans-
mit-only mode are available for serial transfer, one of which is
selected by the transfer mode selection bit (b5 of address 001916)
of serial I/O1 control register 1.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6
of address 001916) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or auto-
matic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 001916) of serial I/O1 control register 1, after
completion of the above bit setup. Next, set the serial I/O initializa-
tion bit (b4 of address 001916) of serial I/O1 control register 1 to
“1” (Serial I/O enable) .
When stopping serial transfer while data is being transferred, re-
gardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to “0”.
Fig. 23 Structure of serial I/O1 control register 3
b
7b
6
b
5
b
4b
3b
2b
1b
0
S
e
r
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a
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3
(
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(
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b
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0
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f
(
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2
5
6
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(
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/
5
1
2
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
31
(2) 8-bit serial I/O mode
Address 001B 16 is assigned to the serial I/O1 register.
When the internal synchronous clock is selected, a serial transfer
of the 8-bit serial I/O is started by a write signal to the serial I/O1
register (address 001B 16).
The serial transfer status flag (b5 of address 001A16) of serial I/O1
control register 2 indicates the shift register status of serial I/O1,
and is set to “1” by wr iting into the serial I/O1 register, which be-
comes a transfer start trigger and reset to “0” after completion of
8-bit tr ansfer. At the same time, a ser ial I/O1 interrupt request oc-
curs.
When the external synchronous clock is selected, the contents of
the serial I/O1 register are continuously shifted while transfer
clocks are input to SCLK1. Therefore, the clock needs to be con-
trolled externally.
(3) Automatic transfer serial I/O mode
The serial I/O1 automatic transfer controller controls the write and
read operations of the serial I/O1 register, so that the function of
address 001B16 is used as a transfer counter (1-byte unit).
When performing serial transfer through the serial I/O automatic
transfer RAM (addresses 0F0016 to 0FFF16), it is necessary to set
the serial I/O1 automatic transfer data pointer (address 001816)
beforehand.
Input the low-order 8 bits of the first data store address to be seri-
ally transferred to the automatic transfer data pointer set bits.
When the internal synchronous clock is selected, the transfer in-
terval for each 1-byte data can be set by the automatic transfer
interval set bits (b0 to b4 of address 001C 16) of serial I/O1 control
register 3 in the following cases:
1. When using no handshake signal
2. When using the SRDY1 output, SBUSY1 output, and SSTB1 output
of the handshake signal independently
3. When using a combination of SRDY1 output and SSTB1 output or
a combination of SBUSY1 output and SSTB1 output of the hand-
shake signal.
It is possib le to select one of 32 different values, namely 2 to 33
cycles of the transfer clock, as a setting value.
When using the S BUSY1 output and selecting the SBUSY1 output •
SSTB1 output function selection bit (b4 of address 001A16) of serial
I/O1 control register 2 as the signal for all transfer data, provided
that the automatic transfer interval setting is valid, a transfer inter-
val is placed before the start of transmission/reception of the first
data and after the end of transmission/reception of the last data.
For SSTB1 output, regardless of the contents of the SBUSY1 output
• SSTB1 output function selection bit (b4), the transfer interval for
each 1-byte data is longer than the set value by 2 cycles.
Furthermore, when using a combination of SBUSY1 output and
SSTB1 output as a signal for all transfer data, the transfer interval
after the end of transmission/reception of the last data is longer
than the set value by 2 cycles.
When the external synchronous clock is selected, automatic trans-
fer interval setting is disabled.
After completion of the above bit setup, if the internal synchronous
clock is selected, automatic serial transfer is started by writing the
value of “number of transfer bytes – 1” into the transfer counter
(address 001B16).
When the external synchronous clock is selected, write the value
of “number of transfer bytes – 1” into the transfer counter and
keep an internal system clock interval of 5 cycles or more. After
that, input transfer clock to SCLK1.
As a transfer inter val for each 1-byte data transfer, keep an inter-
nal system clock interval of 5 cycles or more from the clock rise
time of the last bit.
Regardless of whether the internal or external synchronous clock
is selected, the automatic transfer data pointer and the transfer
counter are decremented after each 1-byte data is received and
then written into the automatic transfer RAM. The ser ial transf er
status flag (b5 of address 001A16) is set to “1” by writing data into
the transfer counter. Wr iting data becomes a transfer start trigger,
and the serial transfer status flag is reset to “0” after the last data
is written into the automatic transfer RAM. At the same time , a se-
rial I/O1 interrupt request occurs.
The values written in the automatic transfer data pointer set bits
(b0 to b7 of address 001816) and the automatic transfer interval
set bits (b0 to b4 of address 001C16) are held in the latch.
When data is written into the transfer counter, the values latched
in the automatic transfer data pointer set bits (b0 to b7) and the
automatic transfer interval set bits (b0 to b4) are transferred to the
decrement counter.
Fig. 24 Structure of serial I/O1 automatic transfer data pointer
b
7b
0S
e
r
i
a
l
I
/
O
1
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81
6)
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
32
Fig. 25 Automatic transfer serial I/O operation
F
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
33
Fig. 27 SBUSY1 input operation (internal synchronous clock)
Fig. 28 SBUSY1 input operation (external synchronous clock)
(4) Handshake signal
1. SSTB1 output signal
The S STB1 output is a signal to inform an end of transmission/re-
ception to the ser ial transfer destination . The SSTB1 output signal
can be used only when the internal synchronous clock is selected.
In the initial status, namely, in the status in which the serial I/O ini-
tialization bit (b4) is reset to “0”, the S STB1 output goes to “L”, or
the SSTB1 output goes to “H”.
At the end of transmit/receive operation, when the data of the se-
rial I/O1 register is all output from S OUT1, pulses are output in the
period of 1 cycle of the transfer clock so as to cause the S STB1
output to go “H” or the SSTB1 output to go “L”. After that, each
pulse is returned to the initial status in which SSTB1 output goes to
“L” or the SSTB1 output goes to “H”.
Furthermore, after 1 cycle, the serial transfer status flag (b5) is re-
set to “0”.
In the automatic transfer serial I/O mode, whether the SSTB1 out-
put is to be active at an end of each 1-byte data or after
completion of transfer of all data can be selected by the S BUSY1
output • SSTB1 output function selection bit (b4 of address 001A16)
of serial I/O1 control register 2.
2. SBUSY1 input signal
The SBUSY1 input is a signal which receives a request for a stop of
transmission/reception from the serial transfer destination.
When the internal synchronous clock is selected, input an “H”
level signal into the S BUSY1 input and an “L” level signal into the
SBUSY1 input in the initial status in which transfer is stopped.
When starting a transmit/receive operation, input an “L” level sig-
nal into the SBUSY1 input and an “H” level signal into the SBUSY1
input in the period of 1.5 cycles or more of the transfer clock.
Then, transfer clocks are output from the SCLK1 output.
When an “H” level signal is input into the SBUSY1 input and an “L”
level signal into the SBUSY1 input after a transmit/receive opera-
tion is started, this transmit/receive operation are not stopped
immediately and the transfer clocks from the S CLK1 output is not
stopped until the specified number of bits are transmitted and re-
ceived.
The handshake unit of the 8-bit serial I/O is 8 bits and that of the
automatic transfer serial I/O is 8 bits.
When the external synchronous clock is selected, input an “H”
level signal into the S BUSY1 input and an “L” level signal into the
SBUSY1 input in the initial status in which transfer is stopped. At
this time, the transfer clocks to be input in SCLK1 become invalid.
During serial transfer, the transfer clocks to be input in SCLK1 be-
come valid, enabling a transmit/receive operation, while an “L”
level signal is input into the SBUSY1 input and an “H” level signal is
input into the SBUSY1 input.
When changing the input values in the SBUSY1 input and the
SBUSY1 input at these operations, change them when the SCLK1
input is in a high state.
When the high impedance of the SOUT1 output is selected by the
SOUT1 pin control bit (b6), the SOUT1 output becomes active, en-
abling serial transfer by inputting a transfer clock to SCLK1, while
an “L” level signal is input into the S BUSY1 input and an “H” level
signal is input into the SBUSY1 input.
Fig. 26 SSTB1 output operation
SSTB1
SCLK1
SOUT1
Serial transfer
status flag
SBUSY1
SCLK1
SOUT1
SBUSY1
SCLK1
SOUT1
Invalid
(Output high-impedance)
3. SBUSY1 output signal
The SBUSY1 output is a signal which requests a stop of transmis-
sion/reception to the serial transfer destination. In the automatic
transfer serial I/O mode, regardless of the internal or external syn-
chronous clock, whether the SBUSY1 output is to be active at
transfer of each 1-byte data or during transfer of all data can be
selected by the SBUSY1 output • SSTB1 output function selection bit
(b4).
In the initial status, the status in which the serial I/O initialization
bit (b4) is reset to “0”, the SBUSY1 output goes to “H” and the
SBUSY1 output goes to “L”.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
34
When the internal synchronous clock is selected, in the 8-bit serial
I/O mode and the automatic transfer serial I/O mode (SBUSY1 out-
put function outputs in 1-byte units), the SBUSY1 output goes to “L”
and the SBUSY1 output goes to “H” before 0.5 cycle (transfer clock)
of the timing at which the transfer clock from the SCLK1 output
goes to “L” at a start of transmit/receive operation.
In the automatic transfer serial I/O mode (the SBUSY1 output func-
tion outputs all transfer data), the SBUSY1 output goes to “L” and
the SBUSY1 output goes to “H” when the first transmit data is writ-
ten into the serial I/O1 register (address 001B16).
When the external synchronous clock is selected, the SBUSY1 out-
put goes to “L” and the SBUSY1 output goes to “H” when transmit
data is written into the serial I/O1 register to start a transmit opera-
tion, regardless of the serial I/O transfer mode.
At termination of transmit/receive operation, the SBUSY1 output re-
turns to “H” and the SBUSY1 output returns to “L”, the initial status,
when the serial transfer status flag is set to “0”, regardless of
whether the internal or external synchronous clock is selected.
Furthermore, in the automatic transfer serial I/O mode (SBUSY1
output function outputs in 1-byte units), the S BUSY1 output goes to
“H” and the SBUSY1 output goes to “L” each time 1-byte of receive
data is written into the automatic transfer RAM.
Fig. 29 SBUSY1 output operation
(internal synchronous clock, 8-bit serial I/O) Fig. 30 SBUSY1 output operation
(external synchronous clock, 8-bit serial I/O)
Fig. 31 SBUSY1 output operation in automatic transfer serial I/O mode
(internal synchronous clock, SBUSY1 output function outputs each 1-byte)
SBUSY1
SCLK1
SOUT1
Serial transfer
status flag Serial transfer
status flag
SBUSY1
SCLK1
Write to Serial
I/O1 register
SCLK1
SBUSY1
SOUT1
Automatic transfer
interval
Serial transfer
status flag
Automatic transfer RAM
→Serial I/O1 register
Serial I/O1 register
→Automatic transfer RAM
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
35
4. SRDY1 output signal
The SRDY1 output is a transmit/receive enable signal which in-
forms the serial transfer destination that transmit/receive is ready.
In the initial status, when the serial I/O initialization bit (b4) is reset
to “0”, the SRDY1 output goes to “L” and the SRDY1 output goes to
“H”. After transmitted data is stored in the serial I/O1 register (ad-
dress 001B 16) and a transmit/receive operation becomes ready,
the SRDY1 output goes to “H” and the SRDY1 output goes to “L”.
When a transmit/receive operation is started and the transfer clock
goes to “L”, the S RDY1 output goes to “L” and the SRDY1 output
goes to “H”.
5. SRDY1 input signal
The SRDY1 input signal becomes valid only when the SRDY1 input
and the S BUSY1 output are used. The SRDY1 input is a signal for
receiving a transmit/receive ready completion signal from the se-
rial transfer destination.
When the internal synchronous clock is selected, input a low level
signal into the S RDY1 input and a high level signal into the SRDY1
input in the initial status in which the transfer is stopped.
When an “H” level signal is input into the S RDY1 input and an “L”
level signal is input into the SRDY1 input for a period of 1.5 cycles
or more of transfer clock, transfer clocks are output from the
SCLK1 output and a transmit/receive operation is started.
After the transmit/receive operation is started and an “L” level sig-
nal is input into the SRDY1 input and an “H” level signal into the
SRDY1 input, this operation cannot be immediately stopped.
After the specified number of bits are transmitted and received,
the transfer clocks from the SCLK1 output is stopped. The hand-
shake unit of the 8-bit serial I/O and that of the automatic transfer
serial I/O are of 8 bits.
When the external synchronous clock is selected, the SRDY1 input
becomes one of the triggers to output the SBUSY1 signal.
To star t a transmit/receive operation (S BUSY1 output: “L”, S BUSY1
output: “H”), input an “H” level signal into the SRDY1 input and an
“L” level signal into the SRDY1 input, and also write transmit data
into the serial I/O1 register.
Fig. 32 SRDY1 output operation
Fig. 33 SRDY1 input operation (internal synchronous clock)
SRDY1
SCLK1
Write to serial
I/O1 register
SRDY1
SCLK1
SOUT1
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
36
Fig. 34 Handshake operation at serial I/O1 mutual connecting (1)
Fig. 35 Handshake operation at serial I/O1 mutual connecting (2)
A: B:
SCLK1
SRDY1
SBUSY1 SBUSY1
SRDY1
SCLK1
A:
B: Write to serial
I/O1 register
SCLK1
SRDY1
SBUSY1
Internal synchronous
clock selection External synchronous
clock selection
Write to serial
I/O1 register
A: B:
SCLK1
SRDY1
SBUSY1 SBUSY1
SRDY1
SCLK1
A:
B: Write to serial
I/O1 register
SCLK1
SRDY1
SBUSY1
Internal synchronous
clock selection External synchronous
clock selection
Write to serial
I/O1 register
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
37
Serial I/O2
Serial I/O2 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during serial I/O2 opera-
tion.
(1) Clock synchronous serial I/O mode
The clock synchronous serial I/O mode can be selected by setting
the serial I/O2 mode selection bit (b6) of the serial I/O2 control
Fig. 37 Operation of clock synchronous serial I/O2 function
Fig. 36 Block diagram of clock synchronous serial I/O2
register (address 001D16) to “1”. For clock synchronous serial I/O,
the transmitter and the receiver must use the same clock for serial
I/O2 operation. If an internal clock is used, transmit/receive is
started by a write signal to the ser ial I/O2 transmit/receive buffer
register (TB/RB) (address 001F16).
When P67 (SCLK22) is selected as a clock I/O pin, S RDY2 output
function is invalid, and P66 (SCLK21) is used as an I/O port.
1
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D7
D7
D0D1D2D3D4D5D6
D0D1D2D3D4D5D6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transmit/Receive shift clock
(1/2 to 1/2048 of internal
clock or external clock)
Serial I/O2 output TxD
Serial I/O2 input RxD
Write-in signal to serial I/O2 transmit/receive
buffer register (address 001F16)
Overrun error (OE)
detection
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O2
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1”.
Receive enable signal SRDY2
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
38
(2) Asynchronous serial I/O (UART) mode
The asynchronous serial I/O (UART) mode can be selected by
clearing the serial I/O2 mode selection bit (b6) of the serial I/O2
control register (address 001D16) to “0”. Eight serial data transfer
formats can be selected and the transfer formats used by the
transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer (the
two buffers have the same address in memory). Since the shift
register cannot be wr itten to or read from directly, transmit data is
written to the transmit buffer, and receive data is read from the re-
ceive buffer. The tr ansmit buffer can also hold the next data to be
transmitted, and the receive buffer can receiv e 2-byte data con-
tinuously.
Fig. 39 Operation of UART serial I/O2 function
Fig. 38 Block diagram of UART serial I/O2
O
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q
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t
(
T
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d
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81
6
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h
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h
a
r
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r
l
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n
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t
h
s
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l
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c
t
i
o
n
b
i
t
7
b
i
t
8
b
i
t
S
e
r
i
a
l
I
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2
c
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n
t
r
o
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r
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g
i
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r
S
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r
i
a
l
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s
t
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g
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r
S
P
d
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c
t
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c
l
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k
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p
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t
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b
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c
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w
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h
b
i
t
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
ST
D
0
D
1
SP D
0
D
1
ST SP
TBE=1 TSC=1*
ST
D
0
D
1
SP D
0
D
1
ST SP
Transmit or receive clock
* Generated at 2nd bit in 2-stop
bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
Serial I/O2 input R
X
D
Write-in signal to
transmit buffer register
Serial I/O2 output T
X
D
Read-out signal from receive
buffer register
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
39
[Serial I/O2 Control Register] SIO2CON (001D16)
The serial I/O2 control register contains eight control bits for serial
I/O2 functions.
[UART Control Register] UARTCON (003816)
This is a 7 bit register containing four control bits, of which four
bits are valid when UART is selected, and of which three bits are
always valid.
Data format of serial data receive/transfer and the output structure
of the P65/TxD pin and others are set by this register.
[Serial I/O2 Status Register] SIO2STS (001E16)
The read-only serial I/O2 status register consists of seven flags
(b0 to b6) which indicate the operating status of the serial I/O2
function and various errors. Three of the flags (b4 to b6) are only
valid in the UART mode. The receive buffer full flag (b1) is cleared
to “0” when the receive buffer is read.
The error detection is performed at the same time data is trans-
ferred from the receive shift register to the receive buffer register,
and the receive buffer full flag is set. A writing to the ser ial I/O2
status register clears error flags OE, PE, FE, and SE (b3 to b6, re-
spectively). Writing “0” to the serial I/O2 enable bit (SIOE : b7 of
the serial I/O2 control register) also clears all the status flags, in-
cluding the error flags.
All bits of the serial I/O2 status register are initialized to “0” at re-
set, but if the transmit enable bit (b4) of the serial I/O2 control
register has been set to “1”, the transmit shift register shift comple-
tion flag (b2) and the transmit buffer empty flag (b0) become “1”.
[Serial I/O2 Transmit Buffer Register/Receive
Buffer Register] TB/RB (001F16)
The transmit buffer and the receive buffer are located in the same
address . The transmit buffer is wr ite-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored
in the receive buffer is “0”.
[Baud Rate Generator] BRG (003716)
The baud rate generator determines the baud rate for serial trans-
fer. With the 8-bit counter having a reload register, the baud rate
generator divides the frequency of the count source by 1/(n+1),
where n is the value written to the baud rate generator.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
40
Fig. 40 Structure of serial I/O2 related register
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O2 status register
(SIO2STS : address 001E
16
) Serial I/O2 control register
(SIO2CON : address 001D
16
)
b0 b0
b7
UART control register
(UARTCON : address 0038
16
)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P6
5
/T
X
D P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
BRG clock switch bit
0: X
IN
or X
CIN
(depends on internal system clock)
1: X
CIN
Serial I/O2 clock I/O pin selection bit
0: S
CLK21
(P6
7
/S
CLK22
pin is used as I/O port or S
RDY2
output pin.)
1: S
CLK22
(P6
6
/S
CLK21
pin is used as I/O port.)
Not used (return “1” when read)
b0
BRG count source selection bit (CSS)
0: f(X
IN
) or f(X
CIN
)/2 or f(X
CIN
)
1: f(X
IN
)/4 or f(X
CIN
)/8 or f(X
CIN
)/4
Serial I/O2 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
S
RDY2
output enable bit (SRDY)
0: P6
7
pin operates as ordinary I/O pin
1: P6
7
pin operates as S
RDY2
output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O2 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O2 enable bit (SIOE)
0: Serial I/O2 disabled
(pins P6
4
to P6
7
operate as ordinary I/O pins)
1: Serial I/O2 enabled
(pins P6
4
to P6
7
operate as serial I/O pins)
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
41
Serial I/O3
The serial I/O3 function can be used only for 8-bit clock synchro-
nous serial I/O.
All serial I/O pins are shared with port P9, which can be set with
the serial I/O3 control register (address 0EEC16).
[Serial I/O3 Control Register (SIO3CON)] 0EEC16
The serial I/O3 control register contains eight bits which control
various serial I/O functions.
● Serial I/O3 Operation
Either the internal clock or external clock can be selected as syn-
chronous clock for serial I/O3 transfer.
The internal clock can use a built-in dedicated divider where 6 dif-
ferent clocks are selected. In the case of the internal clock used,
transfer is started by a write signal to the serial I/O3 register (ad-
dress 0EED 16). When 8-bit data has been transferred, the SOUT3
pin goes to high impedance state.
In the case of the external clock used, the clock must be externally
controlled. It is because the contents of serial I/O3 register is kept
shifted while the clock is being input. Additionally, the function to
put the SOUT3 pin high impedance state at completion of data
transfer is not available.
The serial I/O3 interrupt request bit is set at completion of 8-bit
data transfer, regardless of use of the internal clock or external
clock.
Fig. 42 Structure of serial I/O3 control register
Fig. 41 Block diagram of serial I/O3
“
1
”
“
0
”
“
0
”
“
1
”
“
0
”
“
1
”
S
R
D
Y
3
S
C
L
K
3
“
0
”
“
1
”
1
/
4
1
/
8
1
/
1
6
1
/
3
2
1
/
6
4
1
/
1
2
8
D
a
t
a
b
u
s
S
e
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O
3
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p
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c
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b
i
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S
e
r
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a
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I
/
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3
c
o
u
n
t
e
r
(
3
)
S
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I
/
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3
s
h
i
f
t
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g
i
s
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r
(
8
)
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D
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r
P
92/
SC
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3
P
91/
SO
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P
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SI
N
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P
92
l
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h
P
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l
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h
P
93
l
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h
P
93/
SR
D
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3
XC
I
N
1
/
2
XI
N
“
0
”
“
1
”
I
n
t
e
r
n
a
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s
y
s
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m
c
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k
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c
t
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n
b
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S
e
r
i
a
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I
/
O
3
c
o
n
t
r
o
l
r
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g
i
s
t
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r
(
S
I
O
3
C
O
N
:
a
d
d
r
e
s
s
0
E
E
C
1
6
)
b
7
I
n
t
e
r
n
a
l
s
y
n
c
h
r
o
n
o
u
s
c
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c
k
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c
t
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b
i
t
s
0
0
0
:
f
(
X
I
N
)
/
4
(
f
(
X
C
I
N
)
/
8
)
0
0
1
:
f
(
X
I
N
)
/
8
(
f
(
X
C
I
N
)
/
1
6
)
0
1
0
:
f
(
X
I
N
)
/
1
6
(
f
(
X
C
I
N
)
/
3
2
)
0
1
1
:
f
(
X
I
N
)
/
3
2
(
f
(
X
C
I
N
)
/
6
4
)
1
1
0
:
f
(
X
I
N
)
/
6
4
(
f
(
X
C
I
N
)
/
1
2
8
)
1
1
1
:
f
(
X
I
N
)
/
1
2
8
(
f
(
X
C
I
N
)
/
2
5
6
)
S
e
r
i
a
l
I
/
O
3
p
o
r
t
s
e
l
e
c
t
i
o
n
b
i
t
(
P
9
1
,
P
9
2
)
0
:
I
/
O
p
o
r
t
1
:
S
O
U
T
3
,
S
C
L
K
3
s
i
g
n
a
l
o
u
t
p
u
t
S
R
D
Y
3
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
(
P
9
3
)
0
:
I
/
O
p
o
r
t
1
:
S
R
D
Y
3
s
i
g
n
a
l
o
u
t
p
u
t
T
r
a
n
s
f
e
r
d
i
r
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
0
:
L
S
B
f
i
r
s
t
1
:
M
S
B
f
i
r
s
t
S
e
r
i
a
l
I
/
O
3
s
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
0
:
E
x
t
e
r
n
a
l
c
l
o
c
k
1
:
I
n
t
e
r
n
a
l
c
l
o
c
k
P
9
1
/
S
O
U
T
3
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
(
P
9
1
)
0
:
C
M
O
S
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
1
:
N
-
c
h
a
n
n
e
l
o
p
e
n
d
r
a
i
n
o
u
t
p
u
t
(
i
n
o
u
t
p
u
t
m
o
d
e
)
b
0
b
2
b
1
b
0
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
42
Fig. 43 Timing of serial I/O3 (LSB first)
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
T
r
a
n
s
f
e
r
c
l
o
c
k
S
e
r
i
a
l
I
/
O
3
o
u
t
p
u
t
S
O
U
T
3
S
e
r
i
a
l
I
/
O
3
i
n
p
u
t
S
I
N
3
R
e
c
e
i
v
e
e
n
a
b
l
e
s
i
g
n
a
l
S
R
D
Y
3
S
e
r
i
a
l
I
/
O
3
r
e
g
i
s
t
e
r
w
r
i
t
e
s
i
g
n
a
l
S
e
r
i
a
l
I
/
O
3
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
i
t
s
e
t
N
o
t
e:
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
c
l
o
c
k
i
s
s
e
l
e
c
t
e
d
a
s
t
h
e
t
r
a
n
s
f
e
r
c
l
o
c
k
,
t
h
e
SO
U
T
3
p
i
n
g
o
e
s
t
o
h
i
g
h
i
m
p
e
d
a
n
c
e
a
f
t
e
r
t
r
a
n
s
f
e
r
c
o
m
p
l
e
t
i
o
n
.
S
y
n
c
h
r
o
n
o
u
s
c
l
o
c
k
(
N
o
t
e
)
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
43
FLD CONTROLLER
The M38B7 group has fluorescent display (FLD) drive and control
circuits.
Table 9 shows the FLD controller specifications.
Specifications
• 52 pins (20 pins can be switched to general-purpose ports)
• 4 pins (all 4 pins can be switched to general-purpose ports)
(A driver IC must be installed externally)
• Used FLD output
28 segment ✕ 28 digit (segment number + digit number ≤ 56)
• Used digit output
40 segment ✕ 16 digit (segment number ≤ 40, digit number ≤ 16)
• Connected to M35501
56 segment ✕ (connected number of M35501) digit
(segment number ≤ 56, digit number ≤ number of M35501 ✕ 16)
• Used P64 to P6 7 expansion
52 segment ✕ 16 digit (segment number ≤ 52, digit number ≤ 16)
• 4.0 µs to 1024 µs (count source XIN/16, 4 MHz)
• 16.0 µs to 4096 µs (count source X IN/64, 4 MHz)
• 4.0 µs to 1024 µs (count source XIN/16, 4 MHz)
• 16.0 µs to 4096 µs (count source X IN/64, 4 MHz)
• Digit interrupt
• FLD blanking interrupt
• Key-scan using digit
• Key-scan using segment
• Digit pulse output function
This function automatically outputs digit pulses.
• M35501 connection function
The number of digits can be increased easily by using the output of DIMOUT(P73) as CLK for the
M35501.
• Toff section generating/nothing function
This function does not generate Toff1 section when the connected outputs are the same.
• Gradation display function
This function allows each segment to be set for dark or bright display.
• P64 to P67 expansion function
This function provides 16 lines of digit outputs from four ports by attaching the decoder converting
4-bit data to 16-bit data.
Item
FLD
controller
port
High-breakdown-
voltage output port
CMOS port
Display pixel number
Period
Dimmer time
Interrupt
Key-scan
Expanded function
Table 9 FLD controller specifications
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
44
Fig. 44 Block diagram of FLD control circuit
P
20/
F
L
D0D
I
G
/
F
L
D
0
E
F
31
6
0
0
0
41
6
8
P
21/
F
L
D1D
I
G
/
F
L
D
P
22/
F
L
D2D
I
G
/
F
L
D
P
23/
F
L
D3
D
I
G
/
F
L
D
P
24/
F
L
D4
D
I
G
/
F
L
D
P
25/
F
L
D5
D
I
G
/
F
L
D
P
26/
F
L
D6
D
I
G
/
F
L
D
P
27/
F
L
D7
D
I
G
/
F
L
D
0
0
0
21
6
8
P
10/
F
L
D1
6
P
11/
F
L
D1
7
P
12/
F
L
D1
8
P
13/
F
L
D1
9
P
14/
F
L
D2
0
P
15/
F
L
D2
1
P
16/
F
L
D2
2
P
17/
F
L
D2
3
0
0
0
61
6
8
P
30/
F
L
D2
4
P
31/
F
L
D2
5
P
32/
F
L
D2
6
P
33/
F
L
D2
7
P
34/
F
L
D2
8
P
35/
F
L
D2
9
P
36/
F
L
D3
0
P
37/
F
L
D3
1
0
0
0
81
6
0
E
F
91
6
8
P
40/
F
L
D3
2
P
41/
F
L
D3
3
P
42/
F
L
D3
4
P
43/
F
L
D3
5
P
44/
F
L
D3
6
P
45/
F
L
D3
7
P
46/
F
L
D3
8
P
47/
F
L
D3
9
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
0
E
0
01
6
0
E
D
F1
6
P
00/
F
L
D8
D
I
G
/
F
L
D
0
E
F
21
6
0
0
0
01
6
8
P
01/
F
L
D9
D
I
G
/
F
L
D
P
02/
F
L
D1
0
D
I
G
/
F
L
D
P
03/
F
L
D1
1D
I
G
/
F
L
D
P
04/
F
L
D1
2D
I
G
/
F
L
D
P
05/
F
L
D1
3D
I
G
/
F
L
D
P
06/
F
L
D1
4D
I
G
/
F
L
D
P
07/
F
L
D1
5D
I
G
/
F
L
D
0
0
0
A1
6
0
E
F
A1
6
8
P
50/
F
L
D4
0
P
51/
F
L
D4
1
P
52/
F
L
D4
2
P
53/
F
L
D4
3
P
54/
F
L
D4
4
P
55/
F
L
D4
5
P
56/
F
L
D4
6
P
57/
F
L
D4
7
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
0
0
0
C1
6
0
E
F
B1
6
8
P
60/
F
L
D4
8
P
61/
F
L
D4
9
P
62/
F
L
D5
0
P
63/
F
L
D5
1
P
64/
F
L
D5
2
P
65/
F
L
D5
3
P
66/
F
L
D5
4
P
67/
F
L
D5
5
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
F
L
D
/
P
M
a
i
n
a
d
d
r
e
s
s
b
u
s
L
o
c
a
l
a
d
d
r
e
s
s
b
u
s
F
L
D
a
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
R
A
M
M
a
i
n
d
a
t
a
b
u
sL
o
c
a
l
d
a
t
a
b
u
s
F
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
(
0
E
F
41
6)
F
L
D
d
a
t
a
p
o
i
n
t
e
r
r
e
l
o
a
d
r
e
g
i
s
t
e
r
(
0
E
F
81
6)
F
L
D
d
a
t
a
p
o
i
n
t
e
r
(
0
E
F
81
6)
T
i
m
i
n
g
g
e
n
e
r
a
t
o
r
A
d
d
r
e
s
s
d
e
c
o
d
e
r
D
i
g
i
t
o
u
t
p
u
t
s
e
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
F
L
D
/
P
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
45
Fig. 45 Structure of FLDC related registers (1)
b
7b
6b
5b
4b3b
2b
1b0
F
L
D
C
m
o
d
e
r
e
g
i
s
t
e
r
(
F
L
D
M
:
a
d
d
r
e
s
s
0
E
F
41
6)
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
c
o
n
t
r
o
l
b
i
t
0
:
G
e
n
e
r
a
l
-
p
u
r
p
o
s
e
m
o
d
e
1
:
A
u
t
o
m
a
t
i
c
d
i
s
p
l
a
y
m
o
d
e
D
i
s
p
l
a
y
s
t
a
r
t
b
i
t
0
:
S
t
o
p
d
i
s
p
l
a
y
1
:
D
i
s
p
l
a
y
(
s
t
a
r
t
t
o
d
i
s
p
l
a
y
b
y
s
w
i
t
c
h
i
n
g
“
0
”
t
o
“
1
”
)
T
s
c
a
n
c
o
n
t
r
o
l
b
i
t
s
b
3
b
2
0
0
:
F
L
D
d
i
g
i
t
i
n
t
e
r
r
u
p
t
(
a
t
r
i
s
i
n
g
e
d
g
e
o
f
e
a
c
h
d
i
g
i
t
)
0
1
:
1
✕
T
d
i
s
p
1
0
:
2
✕
T
d
i
s
pF
L
D
b
l
a
n
k
i
n
g
i
n
t
e
r
r
u
p
t
1
1
:
3
✕
T
d
i
s
p(
a
t
f
a
l
l
i
n
g
e
d
g
e
o
f
t
h
e
l
a
s
t
d
i
g
i
t
)
T
i
m
i
n
g
n
u
m
b
e
r
c
o
n
t
r
o
l
b
i
t
0
:
1
6
t
i
m
i
n
g
m
o
d
e
1
:
3
2
t
i
m
i
n
g
m
o
d
e
G
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
s
e
l
e
c
t
i
o
n
c
o
n
t
r
o
l
b
i
t
0
:
N
o
t
s
e
l
e
c
t
i
n
g
1
:
S
e
l
e
c
t
i
n
g
(N
o
t
e)
T
d
i
s
p
c
o
u
n
t
e
r
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
XI
N)
/
1
6
1
:
f
(
XI
N)
/
6
4
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
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t
d
r
i
v
a
b
i
l
i
t
y
s
e
l
e
c
t
i
o
n
b
i
t
0
:
D
r
i
v
a
b
i
l
i
t
y
s
t
r
o
n
g
1
:
D
r
i
v
a
b
i
l
i
t
y
w
e
a
k
N
o
t
e
:
W
h
e
n
t
h
e
g
r
a
d
a
t
i
o
n
d
i
s
p
l
a
y
m
o
d
e
i
s
s
e
l
e
c
t
e
d
,
t
h
e
m
a
x
.
n
u
m
b
e
r
o
f
t
i
m
i
n
g
i
s
1
6
t
i
m
i
n
g
.
(
B
e
s
u
r
e
t
o
s
e
t
t
h
e
t
i
m
i
n
g
n
u
m
b
e
r
c
o
n
t
r
o
l
b
i
t
t
o
“
0
”
.
)
b
7b
6b
5b
4b3b
2b
1b0
F
L
D
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
F
L
D
C
O
N
:
a
d
d
r
e
s
s
0
E
F
C1
6)
P
64
t
o
P
67
o
u
t
p
u
t
r
e
v
e
r
s
e
b
i
t
0
:
O
u
t
p
u
t
n
o
r
m
a
l
l
y
1
:
R
e
v
e
r
s
e
o
u
t
p
u
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
;
(
D
o
n
o
t
w
r
i
t
e
“
1
”
.
)
P
64
t
o
P
67
T
o
f
f
i
n
v
a
l
i
d
b
i
t
0
:
O
p
e
r
a
t
i
o
n
n
o
r
m
a
l
l
y
1
:
T
o
f
f
i
n
v
a
l
i
d
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
;
(
D
o
n
o
t
w
r
i
t
e
“
1
”
.
)
P
73
d
i
m
m
e
r
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
D
i
m
m
e
r
o
u
t
p
u
t
G
e
n
e
r
a
t
i
n
g
/
N
o
t
o
f
C
M
O
S
p
o
r
t
T
o
f
f
s
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
0
:
T
o
f
f
s
e
c
t
i
o
n
n
o
t
g
e
n
e
r
a
t
e
d
1
:
T
o
f
f
s
e
c
t
i
o
n
g
e
n
e
r
a
t
e
d
G
e
n
e
r
a
t
i
n
g
/
N
o
t
o
f
h
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
T
o
f
f
s
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
0
:
T
o
f
f
s
e
c
t
i
o
n
n
o
t
g
e
n
e
r
a
t
e
d
1
:
T
o
f
f
s
e
c
t
i
o
n
g
e
n
e
r
a
t
e
d
T
o
f
f
2
S
E
T
/
R
E
S
E
T
s
w
i
t
c
h
b
i
t
0
:
T
o
f
f
2
R
E
S
E
T
;
T
o
f
f
1
S
E
T
1
:
T
o
f
f
2
S
E
T
;
T
d
i
s
p
R
E
S
E
T
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
46
Fig. 46 Structure of FLDC related registers (2)
b
7b
6b
5b
4b
3b
2b
1
b
0
P
o
r
t
P
4
F
L
D
/
P
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
(
P
4
F
P
R
:
a
d
d
r
e
s
s
0
E
F
91
6)
P
o
r
t
P
40
F
L
D
/
P
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
41
F
L
D
/
P
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
42
F
L
D
/
P
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
43
F
L
D
/
P
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
44
F
L
D
/
P
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
45
F
L
D
/
P
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
46
F
L
D
/
P
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
47
F
L
D
/
P
o
r
t
s
w
i
t
c
h
b
i
t
0
:
N
o
r
m
a
l
p
o
r
t
1
:
F
L
D
o
u
t
p
u
t
p
o
r
t
P
o
r
t
P
5
F
L
D
/
P
o
r
t
s
w
i
t
c
h
r
e
g
i
s
t
e
r
(
P
5
F
P
R
:
a
d
d
r
e
s
s
0
E
F
A1
6)
b
7b
6b
5b
4b
3b
2b
1
b
0
P
o
r
t
P
50
F
L
D
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P
o
r
t
s
w
i
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c
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b
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0
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N
o
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a
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p
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1
:
F
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p
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P
o
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P
51
F
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P
o
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s
w
i
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c
h
b
i
t
0
:
N
o
r
m
a
l
p
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1
:
F
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o
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t
p
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p
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P
o
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P
52
F
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P
o
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t
s
w
i
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c
h
b
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0
:
N
o
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m
a
l
p
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1
:
F
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p
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P
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P
53
F
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s
w
i
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c
h
b
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0
:
N
o
r
m
a
l
p
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1
:
F
L
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p
u
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p
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P
o
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P
54
F
L
D
/
P
o
r
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s
w
i
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c
h
b
i
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0
:
N
o
r
m
a
l
p
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1
:
F
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t
p
u
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p
o
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P
o
r
t
P
55
F
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P
o
r
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s
w
i
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c
h
b
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0
:
N
o
r
m
a
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p
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1
:
F
L
D
o
u
t
p
u
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p
o
r
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P
o
r
t
P
56
F
L
D
/
P
o
r
t
s
w
i
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c
h
b
i
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0
:
N
o
r
m
a
l
p
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1
:
F
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D
o
u
t
p
u
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p
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P
o
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P
57
F
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D
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P
o
r
t
s
w
i
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c
h
b
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0
:
N
o
r
m
a
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p
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1
:
F
L
D
o
u
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p
u
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p
o
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
47
Fig. 47 Structure of FLDC related registers (3)
b
7b
6b
5b
4b
3
b
2
b
1b
0
P
o
r
t
P
6
F
L
D
/
P
o
r
t
s
w
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c
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g
i
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r
(
P
6
F
P
R
:
a
d
d
r
e
s
s
0
E
F
B
1
6
)
P
o
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P
6
0
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P
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s
w
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c
h
b
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0
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1
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6
1
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0
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1
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2
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1
:
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6
3
F
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w
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c
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b
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0
:
N
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a
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p
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1
:
F
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4
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5
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6
6
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1
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P
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P
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6
7
F
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p
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1
:
F
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p
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p
o
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
48
Fig. 48 Structure of FLDC related registers (4)
b
7b
6b
5b
4b
3b
2
b
1b
0
P
o
r
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P
0
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(
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0
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R
:
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0
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21
6)
P
o
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P
00
F
L
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D
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g
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t
s
w
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t
c
h
b
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t
0
:
F
L
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t
p
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t
1
:
D
i
g
i
t
o
u
t
p
u
t
P
o
r
t
P
01
F
L
D
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D
i
g
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t
s
w
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t
c
h
b
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t
0
:
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1
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P
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02
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(
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2
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:
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F
31
6)
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P
22
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P
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P
27
F
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:
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1
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
49
Fig. 49 Segment/Digit setting example
FLD Automatic Display Pins
P0 to P6 are the pins capable of automatic display output for the
FLD. The FLD starts operating by setting the automatic display
control bit (bit 0 at address 0EF416) to “1”. There is the FLD output
function that outputs the RAM contents from the port every timing
or the digit output function that drives the port high with a digit tim-
Setting method
The individual bits of the digit output set switch registers (addresses 0EF216, 0EF316) can
set each pin to either an FLD port (“0”) or a digit port (“1”).
When the pins are set for the digit port, the digit pulse output function is enabled, so that the
digit pulses can always be output regardless the value of FLD automatic display RAM.
Setting the automatic display control bit (bit 0 of address 0EF416) to “1” can set these ports
to the FLD exclusive use port.
The individual bits of the FLD/Port switch register (addresses 0EF916 to 0EFB 16) can set
each pin to either an FLD port (“1”) or a general-purpose port (“0”).
The individual bits of the port P6 FLD/Port switch register (address 0EFB16) can set each
pin to either FLD port (“1”) or general-purpose port (“0”). A variety of output pulses can be
available by setting of the FLD output control register (address 0EFC16). The por t output
structure is the CMOS output. When using the port as a display pin, a driver IC must be in-
stalled exter nally.
ing. The FLD can be displayed using the FLD output for the seg-
ments and the digit or FLD output for the digits. When using the
FLD output for the digits, be sure to write digit display patterns to
the RAM in advance. The remaining segment and digit lines can
be used as general-purpose ports. Settings of each port are
shown below.
Table 10 Pins in FLD automatic display mode
Port
P0, P2 Automatic display pin
FLD0 to FLD15
P1, P3 FLD16 to FLD31
P4, P5,
P60 to P63
P64 to P67
FLD32 to FLD51
FLD52 to FLD55
P
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(
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.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
50
Fig. 50 FLD automatic display RAM assignment
FLD Automatic Display RAM
The FLD automatic display RAM uses the 224 bytes of addresses
0E0016 to 0EDF16. For FLD, the 3 modes of 16-timing•ordinary
mode, 16-timing•gradation display mode and 32-timing mode are
available depending on the number of timings and the use/not use
of gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timing•ordinary mode
This mode is used when the display timing is 16 or less. The 112
bytes of addresses 0E7016 to 0EDF16 are used as a FLD display
data store area. Because addresses 0E0016 to 0E6F16 are not
used as the automatic display RAM, they can be the ordinary
RAM.
(2) 16-timing•gradation display mode
This mode is used when the display timing is 16 or less, in which
mode each segment can be set for dark or bright display. The 224
bytes of addresses 0E0016 to 0EDF16 are used. The 112 bytes of
addresses 0E7016 to 0EDF16 are used as an FLD display data
store area, while the 112 bytes of addresses 0E0016 to 0E6F16 are
used as a gradation display control data store area.
(3) 32-timing mode
This mode is used when the display timing is 16 or greater. This
mode can be used for up to 32-timing.
The 224 bytes of addresses 0E0016 to 0EDF16 are used as an
FLD display data store area.
The FLD data pointer (address 0EF816) is a register to count dis-
play timings. This pointer has a reload register. When the pointer
underflow occurs, it starts counting over again after being re-
loaded with the initial value in the reload register. Make sure that
(the timing counts – 1) is set to the FLD data pointer. When writing
data to this address, the data is written to the FLD data pointer re-
load register; when reading data from this address, the value in
the FLD data pointer is read.
1
6
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d
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
51
Data Setup
(1) 16-timing•ordinary mode
The area of addresses 0E7016 to 0EDF16 are used as a FLD au-
tomatic display RAM.
When data is stored in the FLD automatic display RAM, the last
data of FLD port P6 is stored at address 0E7016, the last data of
FLD port P5 is stored at address 0E8016, the last data of FLD port
P4 is stored at address 0E90 16, the last data of FLD port P3 is
stored at address 0EA016, the last data of FLD port P1 is stored at
address 0EB016, the last data of FLD port P0 is stored at address
0EC016, and the last data of FLD port P2 is stored at address
0ED016, to assign in sequence from the last data respectively.
The first data of the FLD port P6, P5, P4, P3, P1, P0, and P2 is
stored at an address which adds the value of (the timing number –
1) to the corresponding addresses 0E7016, 0E8016, 0E9016,
0EA016, 0EB016, 0EC016 and 0ED016.
Set the FLD data pointer reload register to the value given by (the
timing number – 1).
Fig. 51 Example of using FLD automatic d isplay RAM in 16-timing•ordinary mode
(2) 16-timing•gradation display mode
Display data setting is performed in the same way as that of the
16-timing•ordinary mode. Gradation display control data is ar-
ranged at an address resulting from subtracting 007016 from the
display data store address of each timing and pin. Bright display is
performed by setting “0”, and dark display is performed by setting
“1” .
(3) 32-timing Mode
The area of addresses 0E0016 to 0EDF16 is used as a FLD auto-
matic display RAM.
When data is stored in the FLD automatic display RAM, the last
data of FLD port P6 is stored at address 0E0016, the last data of
FLD port P5 is stored at address 0E2016, the last data of FLD port
P4 is stored at address 0E4016, the last data of FLD port P3 is
stored at address 0E6016, the last data of FLD port P1 is stored at
address 0E8016, the last data of FLD port P0 is stored at address
0EA016, and the last data of FLD port P2 is stored at address
0EC016, to assign in sequence from the last data respectively.
The first data of the FLD port P6, P5, P4, P3, P1, P0, and P2 is
stored at an address which adds the value of (the timing number –
1) to the corresponding addresses 0E0016, 0E2016, 0E4016,
0E6016, 0E8016, 0EA016 and 0EC016.
Set the FLD data pointer reload register to the value given by (the
timing number – 1).
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
52
Fig. 52 Example of using FLD automatic display RAM in 16-timing•gradation display mode
N
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
53
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Fig. 53 Example of using FLD automatic display RAM in 32-timing mode
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
54
Timing Setting
Each timing is set by the FLDC mode register, Tdisp time set reg-
ister, Toff1 time set register, and Toff2 time set register.
(1) Tdisp time setting
The Tdisp time means the length of displa y timing. In non-g rada-
tion display mode, it consists of the FLD display output term and
the Toff1 time. In gradation display mode, it consists of the display
output term and the Toff1 time plus a low signal output term for
dark display. Set the Tdisp time by the Tdisp counter count source
selection bit of the FLDC mode register and the Tdisp time set
register. Supposing that the value of the Tdisp time set register is
n, the Tdisp time is represented as Tdisp = (n+1) ✕ t (t: count
source). When the Tdisp counter count source selection bit of the
FLDC mode register is “0” and the value of the Tdisp time set reg-
ister is 200 (C816), the Tdisp time is: Tdisp = (200 + 1) ✕ 4.0 µs (at
XIN = 4 MHz) = 804 µs. When reading the Tdisp time set register,
the counting value is read out.
(2) Toff1 time setting
The Toff1 time means a non-output (low signal output) time to pre-
vent blurring of FLD and for dimmer display. Use the Toff1 time set
register to set this Toff1 time. Make sure the value set to Toff1 is
smaller than Tdisp and Toff2. Supposing that the value of the Toff1
time set register is n1, the Toff1 time is represented as Toff1 =
n1 ✕ t. When the Tdisp counter count source selection bit of the
FLDC mode register is “0” and the value of the Toff1 time set reg-
ister is 30 (1E16), Toff1 = 30 ✕ 4.0 µs (at XIN = 4 MHz) = 120 µs.
Be sure to set the value of 0316 or more to the Toff1 time set reg-
ister (address 0EF616).
(3) Toff2 time setting
The Toff2 time is time for dar k display. For br ight display, the FLD
display output remains effective until the counter that is counting
Tdisp underflows. For dar k display, however, “L” (or “off”) signal is
output when the counter that is counting Toff2 underflows. This
Toff2 time setting is valid only for FLD ports which are in the g ra-
dation display mode and whose gradation display control RAM
value is “1” .
Set the Toff2 time by the Toff2 time set register. Make sure the
value set to Toff2 is smaller than Tdisp but larger than Toff1. Sup-
posing that the value of the Toff2 time set register is n2, the Toff2
time is represented as Toff2 = n2 ✕ t. When the Tdisp counter
count source selection bit of the FLDC mode register is “0” and
the value of the Toff2 time set register is 180 (B416), Toff2 = 180 ✕
4.0 µs (at XIN = 4 MHz) = 720 µs.
When bit 7 of the FLD output control register (address 0EFC16) is
set to “1”, be sure to set the value of 0316 or more to the Toff2 time
set register (address 0EF716).
Fig. 54 FLD and digit output timing
Toff1 T
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1T
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f
f
2
Tdis
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•Gradation display mode is not selected
(Address 0EF416 bit 5 = “0”)
•Gradation display mode is selected and set for bright display
(Address 0EF416 bit 5 = “1” and the corresponding gradation
dis
p
la
y
control data = “0”
)
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Low output term for
blurring prevention
•Gradation display mode is selected and set for dark display
(Address 0EF416 bit 5 = “1” and the corresponding gradation
display control data = “1”)
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
55
Fig. 55 Timing using digit interrupt
FLD Automatic Display Start
Automatic display starts by setting both the automatic display con-
trol bit (bit 0 of address 0EF4 16) and the display start bit (bit 1 of
address 0EF416) to “1”. The RAM contents at a location apart from
the start address of the automatic display RAM for each port by
(FLD data pointer (address 0EF816) – 1) are output to each port.
The FLD data pointer (address 0EF8 16) counts down in the Tdisp
interval. When the count results in “FF16”, the pointer is reloaded
and starts counting over again. Before setting the display start bit
(bit 1 of address 0EF416) to “1”, be sure to set the FLD/port switch
registers, digit output set switch registers, FLDC mode register,
Tdisp time set register, Toff1 time set register, Toff2 time set regis-
ter, and FLD data pointer.
During FLD automatic display, the display start bit always keeps
“1”, and FLD automatic display can be interrupted by writing “0” to
this bit.
Key-scan and Interrupt
Either the FLD digit interrupt or FLD blanking interrupt can be se-
lected using the Tscan control bits (bits 2, 3 of address 0EF416).
The FLD digit interrupt is generated when the Toff1 time in each
timing expires (at rising edge of digit output). Key scanning that
makes use of FLD digits can be achieved using each FLD digit in-
terrupt. To use FLD digit interrupts for key scanning, follow the
procedure described below:
(1) Read the port value each time the interrupt occurs.
(2) The key is fixed on the last digit interrupt.
The output digit positions can be determined by reading the FLD
data pointer (address 0EF816).
F
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
56
Fig. 56 Timing using FLD blanking interrupt
The FLD blanking interrupt is generated when the FLD data
pointer (address 0EF816) reaches “FF16”. The FLD automatic dis-
play output is tur ned off for a duration of 1 ✕ Tdisp, 2 ✕ Tdisp , or
3 ✕ Tdisp depending on post-interrupt settings. Dur ing this time,
key scanning that makes use of FLD segments can be achieved.
When the key scanning is performed with the segment during
key-scan blanking time Tscan, follow the procedure descr ibed
below:
(1) Write “0” to the automatic display control bit (bit 0 of address
0EF416).
(2) Set the port corresponding to the segment for key scanning to
the output port.
(3) Perform key scanning.
(4) Write “1” to the automatic display control bit.
■ Note
When performing a key-scan according to the above steps 1 to 4,
take the following points into consideration.
1. Do not set the display start bit (bit 1 of address 0EF416) to “0”.
2. Do not set “1” in the ports corresponding to digits.
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
57
P64 to P6 7 Expansion Function
Ports P64 to P67 are CMOS output structure. FLD digit outputs
can be increased as many as 16 lines by connecting a decoder
converting 4-bit to 16-bit data to these ports. P64 to P67 have the
function to allow for connection to a decoder converting 4-bit to
16-bit data.
(1) P64 to P67 Toff invalid function
This function disables the Toff1 time and Toff2 time and outputs
display data for the duration of Tdisp. (See Figure 57.) This can be
achieved by setting the P64 to P67 Toff invalid bit (bit 2 of address
0EFC16) to “1”.
(2) Dimmer signal output function
This function allows a dimmer signal creation signal to be output
from DIM OUT (P73). The dimmer function can be achieved by con-
trolling the decoder with this signal. (See Figure 57.) This function
can be set by setting P73 dimmer output control bit (bit 4 of ad-
dress 0EFC16) to “1”.
Unlike the Toff section generating/nothing function, this function
disables all display data.
Fig. 57 P64 to P67 FLD output pulses
(3) P64 to P67 FLD output reverse function
P64 to P67 have the function to reverse the polarity of the FLD out-
put. This function is useful in adjusting the polarity when using an
externally installed driver.
The output polarity can be reversed by setting the P64 to P67 out-
put reverse bit of the FLD output control register (bit 0 of address
0EFC16) to “1”.
■ Note
In the case of gradation display mode and dark display, P64 to P67
Toff in valid function is disabled.
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
58
Toff2 SET/RESET Switch Function
In gradation display mode, the values set by the Toff2 time set reg-
ister (TOFF2) are effective. When the Toff2 SET/RESET switch bit
of FLD output control register (bit 7 of address 0EFC16) is “0”,
RAM data is output to the FLD output ports (SET) at the time that
is set by TOFF1 and it is tur ned to “0” (RESET) at the time that is
set by TOFF2.
When Toff2 SET/RESET switch bit is “1”, RAM data is output
(SET) at the time that is set by TOFF2 and it is turned to “0” (RE-
SET) when the Tdisp time expires.
■ Note
In the case of gradation display mode and dark display, the Toff
section generate/nothing function is disabled.
Toff Section Generate/Nothing Function
The function is for reduction of useless noises which generated as
every switching of ports, because of the combined capacity of
among FLD ports. When the continuous data is output to each
FLD port, the Toff1 section of the continuous parts is not gener-
ated. (See Figure 58)
Fig. 58 Toff section generating/nothing function
If it needs Toff1 section on FLD pulses, set the generating /not of
CMOS por t Toff section selection bit (bit 5 of address 0EFC16) to
“1” and set the generating /not of high-breakdown-voltage port Toff
section selection bit to “1”.
High-breakdown-voltage ports (P2, P0, P1, P3, P4, P5, P63 to
P60, total 52 pins) generate Toff1 section by setting the generating
/not of high-breakdown-voltage port Toff section selection bit to
“1”.
The CMOS ports (P64 to P67, total 4 pins ) generate Toff1 section
by setting the generating /not of CMOS por t Toff section selection
bit to “1”.
P
1
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P
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P
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a
g
e
p
o
r
t
T
o
f
f
s
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
(
b
i
t
6
o
f
a
d
d
r
e
s
s
0
E
F
C
1
6
)
i
s
“
1
”
.
“
H
”
o
u
t
p
u
t
“
H
”
o
u
t
p
u
t
“
H
”
o
u
t
p
u
t“
H
”
o
u
t
p
u
t
“
H
”
o
u
t
p
u
t
“
H
”
o
u
t
p
u
t“
H
”
o
u
t
p
u
t
“
H
”
o
u
t
p
u
t
“
H
”
o
u
t
p
u
t
“
H
”
o
u
t
p
u
t
“
H
”
o
u
t
p
u
t
“
L
”
o
u
t
p
u
t
“
L
”
o
u
t
p
u
t
“
L
”
o
u
t
p
u
t
“
L
”
o
u
t
p
u
t
S
e
c
t
i
o
n
o
f
T
o
f
f
1
i
s
n
o
t
g
e
n
e
r
a
t
e
d
b
e
c
a
u
s
e
o
f
o
u
t
p
u
t
i
s
t
h
e
s
a
m
e
.
O
u
t
p
u
t
w
a
v
e
f
o
r
m
w
h
e
n
g
e
n
e
r
a
t
i
n
g
/
n
o
t
o
f
h
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
p
o
r
t
T
o
f
f
s
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
(
b
i
t
6
o
f
a
d
d
r
e
s
s
0
E
F
C
1
6
)
i
s
“
0
”
.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
59
Fig. 59 Digit pulses output function
Digit Pulses Output Function
P00 to P07 and P2 0 to P27 can output digit pulses by using the
digit output set switch registers. Set the digit output set switch reg-
isters by setting as many consecutive 1s as the timing count from
P20. The contents of FLD automatic display RAM for the por ts that
have been selected for digit output are disabled, and the pulse
sho wn in Figure 59 is output automatically.
The output timing consists of Tdisp time and Toff1 time , and Toff2
time does not exist.
Because the contents of FLD automatic display RAM are dis-
abled, the segment data can be changed easily even when
segment data and digit data coexist at the same address in the
FLD automatic display RAM.
This function is effective in 16-timing•ordinary mode and 16-timing
gradation display mode. If a value is set exceeding the timing
count (FLD data pointer reload register’s set value + 1) for any
port, the output of such port is “L”.
L
o
w
-
o
r
d
e
r
4
b
i
t
s
o
f
t
h
e
d
a
t
a
p
o
i
n
t
e
rFEDC
B
A 01
2
3
456
7
8
9
P
0
7
P
0
6
P
0
5
P
0
4
P
0
3
P
0
2
P
0
1
P
0
0
P
2
7
P
2
6
P
2
5
P
2
4
P
2
3
P
2
2
P
2
1
P
2
0
T
d
i
s
p
T
o
f
f
1
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
60
b
7
b
6b
5b
4b
3b
2b
1b
0A
D
/
D
A
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
21
6)
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
b
3
b
2
b
1
b
0
0
0
0
0
:
P
A0/
A
N0
0
0
0
1
:
P
A1/
A
N1
0
0
1
0
:
P
A2/
A
N2
0
0
1
1
:
P
A3/
A
N3
0
1
0
0
:
P
A4/
A
N4
0
1
0
1
:
P
A5/
A
N5
0
1
1
0
:
P
A6/
A
N6
0
1
1
1
:
P
A7/
A
N7
1
0
0
0
:
P
90/
SI
N
3/
A
N8
1
0
0
1
:
P
91/
SO
U
T
3/
A
N9
1
0
1
0
:
P
92/
SC
L
K
3/
A
N1
0
1
0
1
1
:
P
93/
SR
D
Y
3/
A
N1
1
1
1
0
0
:
P
94/
R
T
P1/
A
N1
2
1
1
0
1
:
P
95/
R
T
P0/
A
N1
3
1
1
1
0
:
P
96/
P
W
M0/
A
N1
4
1
1
1
1
:
P
97/
BU
Z
0
2/
A
N1
5
A
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
b
i
t
0
:
C
o
n
v
e
r
s
i
o
n
i
n
p
r
o
g
r
e
s
s
1
:
C
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
e
d
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
D
A
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
0
:
D
A
o
u
t
p
u
t
d
i
s
a
b
l
e
d
1
:
D
A
o
u
t
p
u
t
e
n
a
b
l
e
d
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
A
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
(
A
D
H
:
a
d
d
r
e
s
s
0
0
3
41
6)
b
7
b
0
b
7
b
6b
5b
4b
3
b
2
A
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
l
o
w
-
o
r
d
e
r
)
(
A
D
L
:
a
d
d
r
e
s
s
0
0
3
31
6)
b
7
b
0
b
1b
0
b
9b
8
N
o
t
e:
W
h
e
n
r
e
a
d
i
n
g
t
h
e
l
o
w
-
o
r
d
e
r
6
b
i
t
s
a
t
a
d
d
r
e
s
s
0
0
3
31
6,
“
0
”
i
s
r
e
a
d
o
u
t
.
D
a
t
a
b
u
s
AV
SS
V
REF
A
-
D
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
7b0
4
A
D
/
D
A
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
C
o
m
p
a
r
a
t
o
r
A-D control circuit
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
H
)
(Address 0034
16
)
(
A
d
d
r
e
s
s
0
0
3
3
1
6
)
R
e
s
i
s
t
o
r
l
a
d
d
e
r
P
A0/
A
N0
P
A1/
A
N1
P
A2/
A
N2
P
A3/
A
N3
P
A4/
A
N4
P
A5/
A
N5
P
A6/
A
N6
P
A7/
A
N7
P
90/
SI
N
3/
A
N8
P
91/
SO
U
T
3/
A
N9
P
92/
SC
L
K
3/
A
N1
0
P
93/
SR
D
Y
3/
A
N1
1
P
94/
R
T
P1/
A
N1
2
P
95/
R
T
P0/
A
N1
3
P
96/
P
W
M0/
A
N1
4
P
97/
BU
Z
0
2/
A
N1
5
A-D conversion register (L)
A-D CONVERTER
The 38B7 group has a 10-bit A-D conver ter. The A-D converter
performs successive approximation conversion.
[A-D Conversion Register] ADH, ADL
One of these registers is a high-order register, and the other is a
low-order register. The high-order 8 bits of a conversion result is
stored in the A-D conversion register (high-order) (address
003416), and the low-order 2 bits of the same result are stored in
bit 7 and bit 6 of the A-D conversion register (low-order) (address
003316).
During A-D conversion, do not read these registers.
[AD/DA Control Register] ADCON
This register controls A-D conver ter. Bits 3 to 0 are analog input
pin selection bits. Bit 4 is an AD conversion completion bit and “0”
during A-D conversion. This bit is set to “1” upon completion of A-
D conversion.
A-D conversion is started by writing “0” in this bit.
[Comparison V oltage Generator]
The comparison voltage generator divides the voltage between
AVss and VREF by 1024, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports PA7/AN7–PA0/
AN0, and P97/BUZ02/AN15 to P90/SIN3/AN8 and inputs it to the
comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog
inputvoltage with the comparison voltage and stores the result in
the A-D conversion register. When an A-D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD conversion interrupt request bit to “1”.
Note that the comparator is constructed linked to a capacitor, so
that set f(XIN) to at least 250 kHz during A-D conversion. Addition-
ally, bit 7 of the CPU mode register (address 003B16) must be set
to “0”.
Fig. 61 Block diagram of A-D converter
Fig. 60 Structure of AD/DA control register
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
61
D-A CONVERTER
The 38B7 group has one internal D-A converter with 8-bit resolu-
tion.
The D-A conversion is performed by setting the value in the D-A
conversion register. The result of D-A con version is output from
the DA pin by setting the DA output enable bit to “1”.
When using the D-A converter, the PB 0/DA port direction register
bit must be set to “0” (input status).
The output analog voltage V is determined by the value n (deci-
mal notation) in the D-A conversion register as follows:
V = V REF ✕ n/256 (n = 0 to 255)
Where VREF is the reference voltage.
At reset, the D-A conversion register is cleared to “0016”, and the
DA output enable bit is cleared to “0”, and PB0/DA pin becomes
high impedance.
The DA output does not have buffers. Accordingly, connect an ex-
ternal buffer when driving a low-impedance load.
Set VCC to 3.0 V or more when using the D-A converter.
Fig. 62 Block diagram of D-A converter
Fig. 63 Equivalent connection circuit of D-A converter
P
B0/
D
A
D
-
A
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
8
)
R
-
2
R
r
e
s
i
s
t
o
r
l
a
d
d
e
rD
A
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
D
a
t
a
b
u
s
A
V
S
S
V
R
E
F
“
0
”
“
1
”
M
S
B
“
0
”“
1
”
R
2
R
R
2
R
R
2
R
R
2
R
R
2
R
R
2
R
R
2
R2
R
L
S
B
2
R
P
B
0
/
D
A
D
-
A
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
D
A
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
62
1
4
1
/
2
XI
N
(
4
M
H
z
)
P
96/
P
W
M0
b
i
t
7b
i
t
0
b
i
t
5
M
S
B L
S
B
P
W
M
b
i
t
7
b
i
t
0
D
a
t
a
b
u
s
XC
I
N
“
1
”
“
0
”
P
W
M
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
(
a
d
d
r
e
s
s
0
0
3
51
6)
P
W
M
r
e
g
i
s
t
e
r
(
l
o
w
-
o
r
d
e
r
)
(
a
d
d
r
e
s
s
0
0
3
61
6)
I
t
i
s
s
e
t
t
o
“
1
”
w
h
e
n
w
r
i
t
e
.
P
W
M
l
a
t
c
h
(
1
4
-
b
i
t
)
1
4
-
b
i
t
P
W
M
c
i
r
c
u
i
t
W
h
e
n
t
h
e
i
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
i
s
s
e
t
t
o
“
0
”T
i
m
i
n
g
g
e
n
e
r
a
t
i
n
g
u
n
i
t
f
o
r
P
W
M
(
6
4
µs
c
y
c
l
e
)
(
4
0
9
6
µs
c
y
c
l
e
)
P
96/
P
W
M
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
P
96
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
96/
P
W
M
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
P
96
l
a
t
c
h
PWM (Pulse Width Modulation)
The 38B7 group has a PWM function with a 14-bit resolution. When
the oscillation frequency XIN is 4 MHz, the minimum resolution bit
width is 250 ns and the cycle period is 4096 µs. The PWM timing
generator supplies a PWM control signal based on a signal that is
the frequency of the X IN clock.
The explanation in the rest assumes XIN = 4 MHz.
Fig. 64 PWM block diagram
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
63
1
5
.
7
5
µs
6
4
µs6
4
µs6
4
µs6
4
µ
s
6
4
µs
m
=
0
m
=
7
m
=
8
m
=
9m
=
6
3
1
6
.
0
µs1
5
.
7
5
µs1
5
.
7
5
µs
1
5
.
7
5
µs1
5
.
7
5
µs1
5
.
7
5
µs
P
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
i
o
n
r
e
g
i
s
t
e
r
H
:
0
0
1
1
1
1
1
1
P
u
l
s
e
w
i
d
t
h
m
o
d
u
l
a
t
i
o
n
r
e
g
i
s
t
e
r
L
:
0
0
0
1
0
1
S
u
b
-
p
e
r
i
o
d
s
w
h
e
r
e
“
H
”
p
u
l
s
e
w
i
d
t
h
i
s
1
6
.
0
µs
:
m
=
8
,
2
4
,
3
2
,
4
0
,
5
6
S
u
b
-
p
e
r
i
o
d
s
w
h
e
r
e
“
H
”
p
u
l
s
e
w
i
d
t
h
i
s
1
5
.
7
5
µs
:
m
=
a
l
l
o
t
h
e
r
v
a
l
u
e
s
4
0
9
6
µs
Data Setup
The PWM output pin also function as port P96. Set port P96 to be
the PWM output pin by setting bit 0 of the PWM control register
(address 0026 16) to “1”. The high-order 8 bits of output data are
set in the high-order PWM register PWMH (address 003516) and
the low-order 6 bits are set in the low-order PWM register PWML
(address 0036 16).
PWM Operation
The timing of the 14-bit PWM function is shown in Figure 65.
The 14-bit PWM data is divided into the low-order 6 bits and the
high-order 8 bits in the PWM latch.
The high-order 8 bits of data determine how long an “H” level sig-
nal is output during each sub-period. There are 64 sub-periods in
each period, and each sub-period t is 256 ✕ τ (= 64 µs) long. The
signal’s “H” has a length equal to N times τ, and its minimum reso-
lution = 250 ns.
The last bit of the sub-period becomes the ADD bit which is speci-
fied either “H” or “L,” by the contents of PWML. As shown in Table
11, the ADD bit is decided either “H” or “L.”
That is, only in the sub-period tm shown in Table 11 in the PWM
cycle per iod T = 64 t, the “H” duration is lengthened during the
minimum resolution width τ period in comparison with the other
period.
For example, if the high-order eight bits of the 14-bit data are
“0316” and the low-order six bits are “0516,” the length of the “H”
level output in sub-periods t 8, t24, t32, t40 and t 56 is 4 τ, and its
length 3 τ in all other sub-periods.
Time at the “H” level of each sub-period almost becomes equal
because the time becomes length set in the high-order 8 bits or
becomes the value plus t, and this sub-period t (= 64 µs, approxi-
mate 15.6 kHz) becomes cycle period approximately.
Table 11 Relationship between low-order 6-bit data and setting
period of ADD bit
0 0 0 0 0 0 None
0 0 0 0 0 1 m = 32
0 0 0 0 1 0 m = 16, 48
0 0 0 1 0 0 m = 8, 24, 40, 56
0 0 1 0 0 0 m = 4, 12, 20, 28, 36, 44, 52, 60
0 1 0 0 0 0 m = 2, 6, 10, 14, 18, 22, 26, 30, 34, 38, 42, 46, 50, 54, 58, 62
1 0 0 0 0 0 m = 1, 3, 5, 7, .................................................., 57, 59, 61, 63
LSB
Sub-periods tm lengthened (m = 0 to 63)
Low-order
6-bit data
Transfer From Register to Latch
Data written to the PWML register is transferred to the PWM latch
once in each PWM period (every 4096 µs), and data written to the
PWMH register is transferred to the PWM latch once in each sub-
period (every 64 µs). Pulses output from the PWM output pin
correspond to this latch contents.
When the PWML register is read, the contents of the latch are
read. However, bit 7 of the PWML register indicates whether the
transfer to the PWM latch is completed: the transfer is completed
when bit 7 is “0”, it is not done when bit 7 is “1”.
Fig. 65 PWM timing
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
64
P
9
6
/
P
W
M
0
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
0
:
I
/
O
p
o
r
t
1
:
P
W
M
0
o
u
t
p
u
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
P
W
M
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
W
M
C
O
N
:
a
d
d
r
e
s
s
0
0
2
6
1
6
)
b
7b
0
6A 6A 6A 6A 6A 6B 6A 6A 6A 6A 6A 6A 6A 6A6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B 6B
5 5 5 5 55 5 5 5 5 5 5 5 5
6
A 6
A 6
B 6
B 6
B 6
A6B 6
B 6
B 6
A 6
B 6
B6B 6
A6
A 6
A 6
A 6
A6A 6A 6
A 6
A6A 6
A 6
A 6
A 6
A
4 3 4 4 3 4 4 3 4
6
B 6
A 6
9 6
8 6
7 0
2 0
1 6
A 6
968 6
702 0
1
0
2 0
1 0
0 F
F F
E F
D 9
7 9
6 9
502 0
100F
C F
F F
E F
D97 9
695F
C
A
D
D A
D
D
165316 1A9316 1AA416 1AA416 1EE416 1EF516
T
=
4
0
9
6
µs
t
=
6
4
µs
1
31
6A
41
62
41
63
51
6
7
B1
66
A1
65
91
6
Data 3516 stored at address 003616
t
=
6
4
µs
τ = 0.25 µs
“
H
”
p
e
r
i
o
d
l
e
n
g
t
h
s
p
e
c
i
f
i
e
d
b
y
P
W
M
H
1
2
B516
2
PWM register
(
hi
g
h-order
)
PWM register
(
low-order
)
PWM latch
(
14-bit
)
Data 6A16 stored at address 003516
D
a
t
a
2
41
6
s
t
o
r
e
d
a
t
a
d
d
r
e
s
s
0
0
3
61
6Bit 7 cleared after transfer
Transfer from registe r to la tch
Data 7B16 stored at address 003516
Transfer from registe r to la tch
W
h
e
n
b
i
t
7
o
f
P
W
M
L
i
s
“
0
,
”
t
r
a
n
s
f
e
r
f
r
o
m
r
e
g
i
s
t
e
r
t
o
l
a
t
c
h
i
s
d
i
s
a
b
l
e
d
.
PWM output
(Example 1)
Low-order 6-bits
output
H = 6A16
L = 2416 6
B1
6.
.
.
.
.
.
.
.
.
.
.
.
3
6
t
i
m
e
s
(
1
0
7
)
6
A1
6.
.
.
.
.
.
.
.
.
.
.
.
2
8
t
i
m
e
s
(
1
0
6
)
P
W
M
o
u
t
p
u
t
(Example 2)
L
o
w
-
o
r
d
e
r
6
b
i
t
s
o
u
t
p
u
t
H
=
6
A1
6
L
=
1
81
66
B1
6.
.
.
.
.
.
.
.
.
.
.
.
2
4
t
i
m
e
s6
A1
6.
.
.
.
.
.
.
.
.
.
.
.
4
0
t
i
m
e
s
PWM output
8
-
b
i
t
c
o
u
n
t
e
r
T
h
e
A
D
D
p
o
r
t
i
o
n
s
w
i
t
h
a
d
d
i
t
i
o
n
a
l τ a
r
e
d
e
t
e
r
m
i
n
e
d
e
i
t
h
e
r
“
H
”
o
r
“
L
”
b
y
l
o
w
-
o
r
d
e
r
6
-
b
i
t
d
a
t
a
.
M
i
n
i
m
u
m
b
i
t
w
i
d
t
h
(
6
4
6
4
µs
)
✕
1
0
6
✕
6
4 2
4
(256 0.25 µs)
2
5
6
(
6
4
µs
)
,
f
i
x
e
d
τ
1
0
6
✕
6
4 3
6
✕
Fig. 67 14-bit PWM timing
Fig. 66 Structure of PWM control register
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
65
f
(
X
I
N
)
/
1
2
8
f
(
X
C
I
N
)
1
/
4
1
/
2
1
/
1
f
(
X
C
I
N
)
C
o
u
n
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
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e
l
e
c
t
i
o
n
b
i
t
I
N
T
2
i
n
t
e
r
r
u
p
t
i
n
p
u
t
N
o
i
s
e
f
i
l
t
e
r
8
-
b
i
t
b
i
n
a
r
y
u
p
c
o
u
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t
e
r
I
n
t
e
r
r
u
p
t
i
n
t
e
r
v
a
l
d
e
t
e
r
m
i
n
a
t
i
o
n
r
e
g
i
s
t
e
r
a
d
d
r
e
s
s
0
0
3
0
1
6
D
a
t
a
b
u
s
D
i
v
i
d
e
r
O
n
e
-
s
i
d
e
d
/
b
o
t
h
-
s
i
d
e
d
e
d
g
e
d
e
t
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
N
o
i
s
e
f
i
l
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
C
o
u
n
t
e
r
o
v
e
r
f
l
o
w
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
o
r
r
e
m
o
t
e
c
o
n
t
r
o
l
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
D
i
v
i
d
e
r
1
/
1
1
/
2
f
(
X
I
N
)
/
3
2
I
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
I
n
t
e
r
n
a
l
s
y
s
t
e
m
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
INTERRUPT INTER VAL DETERMINATION FUNCTION
The 38B7 group has an interrupt interval determination circuit.
This interrupt interval determination circuit has an 8-bit binary up
counter. Using this counter, it determines a dur ation of time from
the rising edge (falling edge) of an input signal pulse on the P72/
INT2 pin to the rising edge (falling edge) of the signal pulse that is
input next.
How to determine the interrupt interval is described below.
1. Enable the INT2 interrupt by setting bit 2 of the interrupt control
register 1 (address 003E16). Select the rising interval or falling
interval by setting bit 2 of the interrupt edge selection register
(address 003A16).
2. Set bit 0 of the interrupt interval determination control register
(address 003116) to “1” (interr upt inter val determination operat-
ing).
3. Select the sampling clock of 8-bit binary up counter by setting
bit 1 of the interr upt interval deter mination control register.
4. When the signal of polarity which is set on the INT 2 pin (rising
or falling edge) is input, the 8-bit binary up counter starts count-
ing up of the selected counter sampling clock.
5. When the signal of polarity selected above is input again, the
value of the 8-bit binary up counter is transferred to the inter-
rupt interval determination register (address 003016), and the
remote control interrupt request occurs. Immediately after that,
the 8-bit binary up counter continues to count up again from
“0016”.
6. When count value reaches “FF16”, the 8-bit binary up counter
stops counting up. Then, simultaneously when the next counter
sampling clock is input, the counter sets value “FF16” to the in-
terrupt interval determination register to generate the counter
overflow interrupt request.
Fig. 68 Interrupt interval determination circuit block diagram
Noise Filter
The P72/INT2 pin builds in the noise filter.
The noise filter operation is described below.
1. Select the sampling clock of the input signal with bits 2 and 3 of
the interrupt inter val determination control register. When not
using the noise filter, set “0016”.
2. The P72/INT2 input signal is sampled in synchronization with
the selected clock. When sampling the same level signal in a
series of three sampling, the signal is recognized as the inter-
rupt signal, and the interrupt request occurs.
When setting bit 4 of interrupt interval determination control regis-
ter to “1”, the interrupt request can occur at both rising and falling
edges.
When using the noise filter, set the minimum pulse width of the
INT2 input signal to 3 cycles or more of the sample clock.
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
66
I
n
t
e
r
r
u
p
t
i
n
t
e
r
v
a
l
d
e
t
e
r
m
i
n
a
t
i
o
n
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
I
I
D
C
O
N
:
a
d
d
r
e
s
s
0
0
3
1
1
6
)
I
n
t
e
r
r
u
p
t
i
n
t
e
r
v
a
l
d
e
t
e
r
m
i
n
a
t
i
o
n
c
i
r
c
u
i
t
o
p
e
r
a
t
i
n
g
s
e
l
e
c
t
i
o
n
b
i
t
0
:
S
t
o
p
p
e
d
1
:
O
p
e
r
a
t
i
n
g
C
o
u
n
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
0
:
f
(
XI
N)
/
1
2
8
o
r
f
(
XC
I
N)
1
:
f
(
XI
N)
/
2
5
6
o
r
f
(
XC
I
N)
/
2
N
o
i
s
e
f
i
l
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
(
I
N
T2)
b
3
b
2
0
0
:
F
i
l
t
e
r
s
t
o
p
0
1
:
f
(
XI
N)
/
3
2
o
r
f
(
XC
I
N)
1
0
:
f
(
XI
N)
/
6
4
o
r
f
(
XC
I
N)
/
2
1
1
:
f
(
XI
N)
/
1
2
8
o
r
f
(
XC
I
N)
/
4
O
n
e
-
s
i
d
e
d
/
b
o
t
h
-
s
i
d
e
d
e
d
g
e
d
e
t
e
c
t
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
0
:
O
n
e
-
s
i
d
e
d
e
d
g
e
d
e
t
e
c
t
i
o
n
1
:
B
o
t
h
-
s
i
d
e
d
e
d
g
e
d
e
t
e
c
t
i
o
n
(
c
a
n
b
e
u
s
e
d
w
h
e
n
u
s
i
n
g
a
n
o
i
s
e
f
i
l
t
e
r
)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
.
)
b
7b
0
Remote control
interru
p
t re
q
uest
0123456
123
0
FE F
F
N
F
F
0
F
F
6
6
N
1
N
(
W
h
e
n
I
I
D
C
O
N
4
=
“
0
”
)
N
o
i
s
e
f
i
l
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
I
N
T
2
p
i
n
Accept ance of
interru
p
t
Counter sampling
clock
8
-
b
i
t
b
i
n
a
r
y
u
p
c
o
u
n
t
e
r
v
a
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I
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r
r
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p
t
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n
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a
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m
i
n
a
t
i
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r
e
g
i
s
t
e
r
v
a
l
u
eRemote control
interru
p
t re
q
uest C
o
u
n
t
e
r
o
v
e
r
f
l
o
w
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
011
0
F
EF
F
2
F
F
23
3
F
F
2
N
N
N
32
2
2
0
1
21
0
1
0
2
R
e
m
o
t
e
c
o
n
t
r
o
l
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
W
h
e
n
I
I
D
C
O
N
4
=
“
1
”
)
N
o
i
s
e
f
i
l
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
I
N
T
2
p
i
n
A
c
c
e
p
t
a
n
c
e
o
f
i
n
t
e
r
r
u
p
t
C
o
u
n
t
e
r
s
a
m
p
l
i
n
g
c
l
o
c
k
8
-
b
i
t
b
i
n
a
r
y
u
p
c
o
u
n
t
e
r
v
a
l
u
e
I
n
t
e
r
r
u
p
t
i
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e
r
v
a
l
d
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t
e
r
m
i
n
a
t
i
o
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g
i
s
t
e
r
v
a
l
u
eR
e
m
o
t
e
c
o
n
t
r
o
l
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
tC
o
u
n
t
e
r
o
v
e
r
f
l
o
w
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
R
e
m
o
t
e
c
o
n
t
r
o
l
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
tR
e
m
o
t
e
c
o
n
t
r
o
l
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Fig. 71 Interrupt interval determination operation example (at both-sided edge active)
Fig. 70 Interrupt interval determination operation example (at rising edge active)
Fig. 69 Structure of interrupt interval determination control register
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
67
XIN
Data bus
XCIN
“1”
“0”
Internal system clock
selection bit
(Note)
“0”
“1”
1/8
Watchdog timer H count
source selection bit
Reset
circuit
STP instruction disable bit
Watchdog timer H (8)
“FF16” is set
when watchdog
timer control
register is written
to.
Internal reset
RESET
Watchdog timer L (8)
Note: Either high-speed, middle-speed or low-speed mode is selected by bit 7 of CPU mode register.
STP instruction
“FF16” is set when
watchdog timer
control register is
written to.
1/2
(2) Watchdog timer H count source selection
bit operation
Bit 7 of the watchdog timer control register (address 0EEE16) per-
mits selecting a watchdog timer H count source. When this bit is
set to “0”, the underflow signal of watchdog timer L becomes the
count source. The detection time is set to 131.072 ms at f(XIN) = 4
MHz frequency, and 32.768 s at f(XCIN) = 32 kHz frequency.
When this bit is set to “1”, the count source becomes the signal di-
vided by 8 for f(XIN) or divided by 16 for f(XCIN). The detection
time in this case is set to 512 µs at f(XIN) = 4 MHz frequency, and
128 ms at f(XCIN) = 32 kHz frequency.
This bit is cleared to “0” after reset.
(3) Operation of STP instruction disable bit
Bit 6 of the watchdog timer control register (address 0EEE16) per-
mits disabling the STP instruction when the watchdog timer is in
operation.
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled.
If the STP instruction is executed, an internal resetting occurs.
When this bit is set to “1”, it cannot be rewritten to “0” by program.
This bit is cleared to “0” after reset.
■ Note
When releasing the stop mode, the watchdog timer performs its
count operation even in the stop release waiting time. Be careful
not to cause the watchdog timer H to underflow in the stop release
waiting time, for example, by writing any data in the watchdog
timer control register (address 0EEE16) before executing the STP
instruction.
W ATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software runa way). The watchdog timer consists of an
8-bit watchdog timer L and a 8-bit watchdog timer H.
Standard Operation Of Watchdog Timer
When any data is not written into the watchdog timer control reg-
ister (address 0EEE16) after reset, the watchdog timer is in the
stop state. The watchdog timer star ts to count down by wr iting an
optional value into the watchdog timer control register and an in-
ternal reset occurs at an underflow of the watchdog timer H.
Accordingly, programming is usually performed so that writing to
the watchdog timer control register may be started before an un-
derflow. When the watchdog timer control register is read, the
values of the high-order 6 bits of the watchdog timer H, STP in-
struction disable bit, and watchdog timer H count source selection
bit are read.
(1) Initial value of watchdog timer
At reset or writing to the watchdog timer control register (address
0EEE16), a watchdog timer H is set to “FF16” and a watchdog
timer L to “FF16”.
Fig. 73 Structure of watchdog timer control register
Fig. 72 Block diagram of watchdog timer
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer H count source selection bit
0: Watchdog timer L underflow
1: f(XIN)/8 or f(XCIN)/16
Watchdog timer H (for read-out of high-order 6 bits)
Watchdog timer control register
(WDTCON : address 0EEE16)
b7
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
68
BUZZER OUTPUT CIRCUIT
The 38B7 group has a buzzer output circuit. One of 1 kHz, 2 kHz
and 4 kHz (at XIN = 4.19 MHz) frequencies can be selected by the
buzzer output control register (address 0EFD16). Either P7 7/BUZ01
or P97/BUZ02/AN15 can be selected as a buzzer output port by the
output port selection bits (b2 and b3 of address 0EFD16).
The buzzer output is controlled by the buzzer output ON/OFF bit
(b4).
Fig. 74 Block diagram of buzzer output circuit
Fig. 75 Structure of buzzer output control register
Note: In the low-speed mode, a buzzer output is made OFF.
f(X
IN
)
1/1024
1/2048
1/4096
Port latch
Buzzer output
Buzzer output ON/OFF bit
Output port control signal
Port direction register
Divider
Buzzer output control register
(BUZCON: address 0EFD
16
)
Output frequency selection bits (XIN = 4.19 MHz)
b1b0
0 0 : 1 kHz (f(XIN)/4096)
0 1 : 2 kHz (f(XIN)/2048)
1 0 : 4 kHz (f(XIN)/1024)
1 1 : Not available
Output port selection bits
b3b2
0 0 : P77 and P97 function as ordinary ports.
0 1 : P77/BUZ01 functions as a buzzer output.
1 0 : P97/BUZ02/AN15 functions as a buzzer output.
1 1 : Not available
Buzzer output ON/OFF bit
b4
0 : Buzzer output OFF (“0” output)
1 : Buzzer output ON
Not used (returns “0” when read)
b7 b0
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
69
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is retur ned to an “H”
level (the power source voltage should be between 2.7 V and 5.5
V, and the oscillation should be stable), reset is released. After the
reset is completed, the program starts from the address contained
in address FFFD16 (high-order byte) and address FFFC16 (low-
order byte). Make sure that the reset input voltage is less than
0.54 V for Vcc of 2.7 V (switching to the high-speed mode, a
power source voltage must be between 4.0 V and 5.5 V).
Fig. 77 Reset sequence
Fig. 76 Reset circuit example
(Note)
0.2V
CC
0V
0V
Poweron
V
CC
RESET
V
CC
RESET
Power source
voltage detection
circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage ; Vcc=2.7 V
RESET
Internal
reset
Data
φ
Address
SYNC
XIN: about 4000 cycles
XIN
???? ?FFFC FFFD ADH, ADL
1: The frequency relation of f(XIN) and f(φ) is f(XIN)=4 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
Notes
ADLADH
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
70
Fig. 78 Internal status at reset
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6
F
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010010 00
0
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0
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0
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6
✕✕✕✕✕✕
0
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31
6
P
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6
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
71
CLOCK GENERATING CIRCUIT
The 38B7 group has two built-in oscillation circuits. An oscillation
circuit can be formed by connecting a resonator between X IN and
XOUT or XCIN and XCOUT. Use the circuit constants in accordance
with the resonator man ufacturer’s recommended values. No exter-
nal resistor is needed between X IN and X OUT since a feedback
resistor exists on-chip. However , an external feedback resistor is
needed between XCIN and XCOUT.
Immediately after power on, only the X IN oscillation circuit starts
oscillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Middle-speed mode
The internal system clock is the frequency of XIN divided by 4. Af-
ter reset, this mode is selected.
(2) High-speed mode
The internal system clock is the frequency of X IN.
(3) Low-speed mode
The internal system clock is the frequency of X CIN divided by 2.
■ Note
If you switch the mode between middle/high-speed and low-
speed, stabilize both XIN and XCIN oscillations. The sufficient time
is required for the sub clock to stabilize, especially immediately af-
ter power on and at returning from stop mode. When switching the
mode between middle/high-speed and low-speed, set the fre-
quency on condition that f(XIN) > 3 • f(XCIN).
(4) Low power consumption mode
The low power consumption operation can be realized by stopping
the main clock XIN in low-speed mode. To stop the main clock, set
the main clock stop bit (bit 5) of the CPU mode register to “1”.
When the main clock X IN is restarted (by setting the main clock
stop bit to “0”), set enough time for oscillation to stabilize.
Oscillation Control
(1) Stop mode
If the STP instruction is executed, the internal system clock stops
at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to
“FF16” and timer 2 is set to “0116”.
Either XIN divided by 8 or XCIN divided by 16 is input to timer 1 as
count source, and the output of timer 1 is connected to timer 2.
The bits of the timer 12 mode register are cleared to “0”. Set the
interrupt enable bits of the timer 1 and timer 2 to disabled (“0”) be-
fore executing the STP instruction. Oscillator restarts when an
external interrupt is received, but the internal system clock is not
supplied to the CPU until timer 2 underflows. This allows time for
the clock circuit oscillation to stabilize.
(2) Wait mode
If the WIT instruction is executed, the internal system clock stops
at an “H” level. The states of XIN and XCIN are the same as the
state before executing the WIT instruction. The inter nal system
clock restarts at reset or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted.
Fig. 79 Ceramic resonator circuit
Fig. 80 External clock input circuit
XCIN XCOUT XIN XOUT
CIN COUT
CCIN CCOUT
Rf Rd
X
IN
X
OUT
External oscillation circuit
V
CC
V
SS
open
X
CIN
X
COUT
External oscillation circuit
or external pulse
open
V
CC
V
SS
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
72
WIT instruction STP instruction
Timing φ (internal clock)
S
R
Q
STP instruction
S
R
Q
Main clock stop bit
(Note 3)
S
R
Q
1/4
XIN XOUT
XCOUT
XCIN
Interrupt request
Reset
Interrupt disable flag l
1/2
1/2
Port XC
switch bit (Note 3)
“1”“0”
“1”
Timer 1 count source
selection bit (Note 2)
Low-speed mode
High-speed or
middle-speed
mode
Middle-speed mode
High-speed or
low-speed mode
Internal system clock
selection bit (Notes 1, 3)
“1”
“0”
Timer 1 Timer 2
Timer 2 count source
selection bit (Note 2)
“0”
Main clock division ratio
selection bits (Note 3)
“1
”
“0
”
“1”
“0”
Notes 1: When low-speed mode is selected, set the port Xc switch bit (b4) to “1”.
2: Refer to the structure of the timer 12 mode register.
3: Refer to the structure of the CPU mode register.
Fig. 81 Clock generating circuit block diagram
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
73
C
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4
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1
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2
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3
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.
4
:
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5
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2
5
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6
:
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C
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p
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.
φ
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.
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φ
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1
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(
φ
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7
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(
4
M
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6
=
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(
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=
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(
X
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g
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φ
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m
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1
6
k
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7
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3
2
k
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6
=
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=
1
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3
2
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c
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a
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C
M
7
=
0
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4
M
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c
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d
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M
6
=
1
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m
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C
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5
=
0
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X
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N
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s
c
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l
l
a
t
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g
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C
M
4
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(
3
2
k
H
z
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s
c
i
l
l
a
t
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n
g
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C
M
7
=
1
(
3
2
k
H
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s
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c
t
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d
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C
M
6
=
1
(
m
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d
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M
5
=
0
(
X
I
N
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c
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l
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a
t
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C
M
4
=
1
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3
2
k
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c
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l
l
a
t
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L
o
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s
p
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e
d
m
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d
e
(
φ
=
1
6
k
H
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7
=
1
(
3
2
k
H
z
s
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c
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C
M
6
=
1
(
m
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d
d
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C
M
5
=
1
(
X
I
N
s
t
o
p
p
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d
)
C
M
4
=
1
(
3
2 k
H
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c
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l
l
a
t
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n
g
)
L
o
w
-
p
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w
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d
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s
s
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p
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t
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m
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(
=
1
6
k
H
z
)
φ
L
o
w
-
p
o
w
e
r
d
i
s
s
i
p
a
t
i
o
n
m
o
d
e
(
=
1
6
k
H
z
)
φ
N
o
t
e
s
Fig. 82 State transitions of system clock
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
74
MASK OPTION OF PULL-DOWN RESISTOR
(object product: mask ROM version)
Whether built-in pull-down resistors are connected or not to high-
breakdown voltage ports P40 to P47, P50 to P57, and P60 to P63
can be specified in ordering mask ROM. The option type can be
specified from among 7 types; A to G.
Notes 1: The electrical characteristics of high-breakdown voltage ports P40 to P47, P50 to P57, and P60 to P6 3’s built-in pull-down resistors
are the same as that of high-breakdown voltage ports P00 to P07.
2: The absolute maximum ratings of power dissipation may be exceed owing to the number of built-in pull-down resistor. After calcu-
lating the power dissipation, specify the option type.
3: The flash memory version cannot select whether built-in pull-down resistors are connected or not. This is the same as option type A.
4: Since mask options B to G are under development now, they cannot be specified.
Power Dissipation Calculating Method
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number a; digit number b; segment number c
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: d
• All segment number during repeat cycle: e (= a ✕ c)
• Total number of built-in resistor: for digit, f; for segment, g
• Digit pin current value h (mA)
• Segment pin current value i (mA)
A
B
C
D
E
F
G
P
4
0
P
4
1
P
4
2
P4
3
P4
4
P
4
5
P
4
6
P
4
7
P5
0
P
5
1
P
5
2
P5
3
P
5
4
P
5
5
P5
6
P
5
7
P
6
0
P
6
1
P
6
2
0000000000000000000
P6
3
0
1111000000000000000 0
1111111100000000000 0
1111111111110000000 0
1111111111111111000 0
1111111111111111110 0
1111111111111111111 1
(1) Digit pin power dissipation
{h ✕ b ✕ (1 – Toff / Tdisp) ✕ voltage} / a
(2) Segment pin power dissipation
{i ✕ d ✕ (1–Toff / Tdisp) ✕ voltage} / a
(3) Pull-down resistor power dissipation (digit)
{power dissipation per 1 digit ✕ (b ✕ f / b) ✕ (1–Toff / Tdisp) } / a
(4) Pull-down resistor power dissipation (segment)
{power dissipation per 1 segment ✕ (d ✕ g / c) ✕ (1–To f f /
Tdisp) } / a
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 190 mW
(1) + (2)+ (3) + (4) + (5) = X mW
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
75
Fig. 83 Digit timing waveform (1)
Power Dissipation Calculating Example 1
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µs = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing number 17; digit number 16; segment number 20
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number during repeat cycle: 31
• All segment n umber during repeat cycle: 340 (= 17 ✕ 20)
• Total number of built-in resistor : for digit, 16; for segment, 20
• Digit pin current value 18 (mA)
• Segment pin current value 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 16 ✕ (1 – 1 / 16) ✕ 2} / 17 = 31.77 mW
(2) Segment pin power dissipation
{3 ✕ 31 ✕ (1– 1 / 16) ✕ 2} / 17 = 10.26 mW
(3) Pull-down resistor power dissipation (digit)
[{45 – 2}2/ 48 ✕ (16 ✕ 16 / 16) ✕ (1 – 1 / 16)] / 17 = 33.94 mW
(4) Pull-down resistor power dissipation (segment)
[{45 – 2}2/ 48 ✕ (31 ✕ 20 / 20) ✕ (1 – 1 / 16)] / 17 = 65.86 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 75 mW
(1) + (2)+ (3) + (4) + (5) = 217 mW
DIG0
DIG1
DIG2
DIG3
DIG13
DIG14
DIG15
Timing
number 12 316 171514
Tscan
Repeat cycle
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
76
Power Dissipation Calculating Example 2
(2 or more digits turned ON at the same time)
(Fixed number depending on microcomputer’s standard)
• VOH output fall voltage of high-breakdown port
2 V (max.); | Current value | = at 18 mA
• Resistor value 43 V / 900 µs = 48 kΩ (min.)
• Power dissipation of internal circuit (CPU, ROM, RAM etc.)
= 5 V ✕ 15 mA = 75 mW
(Fixed number depending on use condition)
• Apply voltage to VEE pin: Vcc – 45 V
• Timing n umber 11; digit number 12; segment number 24
• Ratio of Toff time corresponding Tdisp time: 1/16
• Turn ON segment number dur ing repeat cycle: 114
• All segment number during repeat cycle: 264 (= 11 ✕ 24)
• Total number of built-in resistor: for digit, 10; for segment, 22
• Digit pin current value 18 (mA)
• Segment pin current value 3 (mA)
(1) Digit pin power dissipation
{18 ✕ 12 ✕ (1 – 1 / 16) ✕ 2} / 11 = 36.82 mW
(2) Segment pin power dissipation
{3 ✕ 114 ✕ (1– 1 / 16) ✕ 2} / 11 = 58.30 mW
(3) Pull-down resistor power dissipation (digit)
[{45 – 2}2/ 48 ✕ (12 ✕ 10 / 12) ✕ (1 – 1 / 16)] / 11 = 32.84 mW
(4) Pull-down resistor power dissipation (segment)
[{45 – 2}2/ 48 ✕ (114 ✕ 22 / 24) ✕ (1 – 1 / 16)] / 11 = 343.08 mW
(5) Internal circuit power dissipation (CPU, ROM, RAM etc.)
= 75 mW
(1) + (2)+ (3) + (4) + (5) = 547 mW
DIG0
DIG1
DIG2
DIG3
DIG7
DIG8
DIG9
Timing
number 12 34567 891011
DIG4
DIG5
DIG6
Tscan
Repeat cycle
Fig. 84 Digit timing waveform (2)
77
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
FLASH MEMORY MODE
The M38B79FF has the flash memory mode in addition to the nor-
mal operation mode (microcomputer mode). The user can use this
mode to perform read, program, and erase operations for the in-
ternal flash memory.
The M38B79FF has three modes the user can choose: the paral-
lel input/output and serial input/output mode, where the flash
memory is handled by using the external programmer, and the
CPU reprogramming mode, where the flash memory is handled by
the central processing unit (CPU). The following explains these
modes.
(1) Flash memory mode 1 (parallel I/O mode)
The parallel I/O mode can be selected by connecting wires as
shown in Figures 85 and supplying power to the VCC and VPP
pins. In this mode, the M38B79FF operates as an equivalent of
MITSUBISHI’s CMOS flash memory M5M28F101. However, be-
cause the M38B79FF’s internal memory has a capacity of 60
Kbytes, programming is available for addresses 0100016 to
0FFFF16, and make sure that the data in addresses 0000016 to
00FFF16 and addresses 1000016 to 1FFFF16 are FF16. Note also
that the M38B79FF does not contain a facility to read out a device
identification code by applying a high voltage to address input
(A9). Be careful not to erratically set program conditions when us-
ing a general-purpose PROM programmer.
Table 12 shows the pin assignments when operating in the paral-
lel input/output mode.
Table 12 Pin assignments of M38B79FF when operating in
the parallel input/output mode
VCC
VPP
VSS
Address input
Data I/O
__
CE
___
OE
___
WE
M38B79FF
VCC
CNVSS
VSS
Ports P0, P1, P31
Port P2
P36
P37
P33
M5M28F101
VCC
VPP
VSS
A0–A16
D0–D7
__
CE
__
OE
___
WE
Functional Outline (parallel input/output mode)
In the parallel input/output mode, the M38B79FF allow the user to
choose an operation mode between the read-only mode and the
read/write mode (software command control mode) depending on
the voltage applied to the VPP pin. When VPP = VPPL, the read-
only mode is selected, and the user can choose one of three
states (e.g., read, output disable, or standby) depending on inputs
___ ___ ___
to the CE, OE, and WE pins. When VPP = VPPH, the read/write
mode is selected, and the user can choose one of four states
(e.g., read, output disable, standby, or write) depending on inputs
__ __ ___
to the CE, OE, and WE pins. Table 13 shows assignment states of
control input and each state.
● Read
__
The microcomputer enters the read state by driving the CE, and
__ ___
OE pins low and the WE pin high; and the contents of memory
corresponding to the address to be input to address input pins
(A0–A16) are output to the data input/output pins (D0–D7).
● Output disable
The microcomputer enters the output disable state by driving the
__ ___ __
CE pin low and the WE and OE pins high; and the data input/out-
put pins enter the floating state.
● Standby
__
The microcomputer enters the standby state by driving the CE pin
high. The M38B79FF is placed in a power-down state consuming
only a minimal supply current. At this time, the data input/output
pins enter the floating state.
● Write
The microcomputer enters the write state by driving the VPP pin
___ __
high (VPP = VPPH) and then the WE pin low when the CE pin is
__
low and the OE pin is high. In this state, software commands can
be input from the data input/output pins, and the user can choose
program or erase operation depending on the contents of this soft-
ware command.
Pin
Mode Read
Output disable
Standby
Read
Output disable
Standby
Write
Read-only
Read/Write
__
CE
VIL
VIL
VIH
VIL
VIL
VIH
VIL
VIL
VIH
×
VIL
VIH
×
VIH
Table 13 Assignment states of control input and each state
__
OE
___
WE
VIH
VIH
×
VIH
VIH
×
VIL
VPPL
VPPL
VPPL
VPPH
VPPH
VPPH
VPPH
VPP
Output
Floating
Floating
Output
Floating
Floating
Input
Data I/O
Note: × can be VIL or VIH.
State
78
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to
5 V ± 10 %
in read-only mode, connect to 11.7 V to 12.6 V in read/write mode.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Connect to VSS.
Port P0 functions as 8-bit address input (A0–A7).
Port P1 functions as 8-bit address input (A8–A15).
Function as 8-bit data’s I/O pins (D0–D7).
Connect them to Vss through each resistor of 6.8 kΩ.
P3
7
, P3
6
and P3
3
function as the OE, CE and WE input pins respectively. P3
1
functions as
the A
16
input pin.
Connect P30 and P32 to VSS. Input “H” or “L” to P34, P35, or keep
them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Connect P64 and P66 to VSS. Input “H” or “L” to P60–P63, P65, P67, or keep them
open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Keep this open.
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Address input (A0–A7)
Address input (A8–A15)
Data I/O (D0–D7)
Control signal input
Input port P4
Input port P5
Input port P6
Input port P7
Input port P8
Input port P9
Input port PA
Input port PB
Pull-down power supply
Table 14 Pin description (flash memory parallel I/O mode)
Pin Name
—
Input
Input
Input
Output
—
Input
Input
Input
I/O
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
/Output
Functions
VCC, VSS
CNVSS
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
P30–P37
P40–P47
P50–P57
P60–P67
P70–P77
P80–P83
P90–P97
PA0–PA7
PB0–PB6
VEE
79
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Fig. 85 Pin connection of M38B79FF when operating in parallel input/output mode
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
38
39
40
41
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
6
5
6
6
6
7
6
8
6
9
7
0
7
1
7
2
7
3
7
4
7
5
7
6
7
7
7
8
7
9
8
0
81
82
8
3
84
85
86
8
7
8
8
8
9
9
0
9
1
9
2
9
3
94
95
96
9
7
9
8
9
9
10
0
M
3
8
B
7
9
F
F
F
P
*
P
4
7
/
F
L
D
3
9
*
P
0
0
/
F
L
D
8
*
P
0
3
/
F
L
D
1
1
*
P
0
4
/
F
L
D
1
2
*
P
0
5
/
F
L
D
1
3
*
P
0
6
/
F
L
D
1
4
*
P
0
7
/
F
L
D
1
5
*
P
1
1
/
F
L
D
1
7
*
P
1
2
/
F
L
D
1
8
*
P
1
3
/
F
L
D
1
9
*
P
1
4
/
F
L
D
2
0
*
P
1
5
/
F
L
D
2
1
*
P
1
6
/
F
L
D
2
2
*
P
1
7
/
F
L
D
2
3
*
P
1
0
/
F
L
D
1
6
*
P
0
1
/
F
L
D
9
*
P
0
2
/
F
L
D
1
0
V
E
E
*
P
4
6
/
F
L
D
3
8
*
P
4
3
/
F
L
D
3
5
*
P
4
2
/
F
L
D
3
4
*
P
4
1
/
F
L
D
3
3
*
P
4
0
/
F
L
D
3
2
*
P
3
7
/
F
L
D
3
1
*
P
3
6
/
F
L
D
3
0
*
P
3
5
/
F
L
D
2
9
*
P
3
4
/
F
L
D
2
8
*
P
3
3
/
F
L
D
2
7
*
P
3
2
/
F
L
D
2
6
*
P
3
1
/
F
L
D
2
5
*
P
3
0
/
F
L
D
2
4
*
P
4
5
/
F
L
D
3
7
*
P
4
4
/
F
L
D
3
6
P
B
5
/
S
O
U
T
1
P
B
4
/
S
C
L
K
1
1
P
B
3
/
S
S
T
B
1
P
A
6
/
A
N
6
P
A
7
/
A
N
7
V
REF
AV
SS
P
9
0
/
S
I
N
3
/
A
N
8
P
9
1
/
S
O
U
T
3
/
A
N
9
P
9
2
/
S
C
L
K
3
/
A
N
1
0
P
9
4
/
R
T
P
1
/
A
N
1
2
P
9
5
/
R
T
P
0
/
A
N
1
3
P
9
6
/
P
W
M
0
/
A
N
1
4
P
9
7
/
B
U
Z
0
2
/
A
N
1
5
P
B
2
/
S
B
U
S
Y
1
P
A
1
/
A
N
1
P
A
0
/
A
N
0
P
8
1
/
X
C
O
U
T
P
8
0
/
X
C
I
N
P
7
4
/
P
W
M
1
P
7
3
/
I
N
T
3
/
D
I
M
O
U
T
P
7
2
/
I
N
T
2
P7
1
/INT
1
P7
0
/INT
0
P
A
5
/
A
N
5
PB
0
/S
CLK12
/SV
IN
/DA
PB
1
/S
RDY1
P
7
5
/
T
1
O
U
T
X
I
N
X
O
U
T
V
C
C
P
7
6
/
T
3
O
U
T
V
S
S
P
7
7
/
I
N
T
4
/
B
U
Z
0
1
R
E
S
E
T
P
A
4
/
A
N
4
P
A
3
/
A
N
3
P
A
2
/
A
N
2
*P2
0
/FLD
0
*P2
1
/FLD
1
*P2
2
/FLD
2
*
P
2
3
/
F
L
D
3
*
P
2
4
/
F
L
D
4
*
P
2
5
/
F
L
D
5
*P2
6
/FLD
6
*
P
2
7
/
F
L
D
7
P
B
6
/
S
I
N
1
*
P
5
1
/
F
L
D
4
1
*
P
5
0
/
F
L
D
4
0
*
P
5
3
/
F
L
D
4
3
*
P
5
2
/
F
L
D
4
2
*
P
5
5
/
F
L
D
4
5
*
P
5
4
/
F
L
D
4
4
*P5
7
/FLD
47
*
P
5
6
/
F
L
D
4
6
*P6
1
/FLD
49
*P6
0
/FLD
48
*
P
6
3
/
F
L
D
5
1
*
P
6
2
/
F
L
D
5
0
P6
5
/TxD/FLD
53
P
6
4
/
R
x
D
/
F
L
D
5
2
P
6
7
/
S
R
D
Y
2
/
S
C
L
K
2
2
/
F
L
D
5
5
P6
6
/S
CLK21
/FLD
54
P
8
2
/
C
N
T
R
1
C
N
V
S
S
P
8
3
/
C
N
T
R
0
/
C
N
T
R
2
P
9
3
/
S
R
D
Y
3
/
A
N
1
1
A
1
6
W
E
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
1
0
A
1
1
A
1
2
A
1
3
A
1
4
A
1
5
O
E
C
E
V
p
p
V
c
c
D
7
D
6
D
5
D
4
D3
D
2
D1
D0
V
s
s
6
.
8
kΩ
✱
:
C
o
n
n
e
c
t
t
o
t
h
e
c
e
r
a
m
i
c
o
s
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Package type: 100P6S-A
80
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Read-only Mode
The microcomputer enters the read-only mode by applying VPPL
to the VPP pin. In this mode, the user can input the address of a
memory location to be read and the control signals at the timing
shown in Figure 86, and the M38B79FF will output the contents of
the user’s specified address from data I/O pin to the exter nal. In
this mode, the user cannot perform any operation other than read.
Fig. 86 Read timing
Read/Write Mode
The microcomputer enters the read/write mode by applying VPPH
to the VPP pin. In this mode, the user must first input a software
command to choose the operation (e. g., read, program, or erase)
to be performed on the flash memory (this is called the first cycle),
and then input the information necessary for execution of the com-
mand (e.g, address and data) and control signals (this is called
the second cycle). When this is done, the M38B79FF executes the
specified operation.
Table 15 shows the software commands and the input/output in-
formation in the first and the second cycles. The input address is
___
latched internally at the falling edge of the WE input; software
commands and other input data are latched internally at the rising
___
edge of the WE input.
The following explains each software command. Refer to Figures 87
to 89 for details about the signal input/output timings.
Table 15 Software command (parallel input/output mode)
Symbol
Read
Program
Program verify
Erase
Erase verify
Reset
Device identification
Address input
×
×
×
×
Verify address
×
×
First cycle Data input
0016
4016
C016
2016
A016
FF16
9016
Address input
Read address
Program address
×
×
×
×
ADI
Second cycle Data I/O
Read data (Output)
Program data (Input)
Verify data (Output)
2016 (Input)
Verify data (Output)
FF16 (Input)
DDI (Output)
Note: ADI = Device identification address : manufacturer’s code 0000016, device code 00001 16
DDI = Device identification data : manufacturer’s code 1C16, device code D0 16
× can be VIL or VIH.
Address Valid address
tRC
ta(CE)
tWRR tDF
ta(OE) tDH
tOLZ
Floating Floating
tCLZ
ta(AD)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CE
OE
WE
Data Dout
81
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● Read command
The microcomputer enters the read mode by inputting command
code “0016” in the first cycle. The command code is latched into
___
the internal command latch at the rising edge of the WE input.
When the address of a memory location to be read is input in the
second cycle, with control signals input at the timing shown in
Figure 87, the M38B79FF outputs the contents of the specified ad-
dress from the data I/O pins to the external.
The read mode is retained until any other command is latched into
the command latch. Consequently, once the M38B79FF enters the
read mode, the user can read out the successive memory contents
simply by changing the input address and executing the second
cycle only. Any command other than the read command must be in-
put beginning from its command code over again each time the user
execute it. The contents of the command latch immediately after
power-on is 0016.
Fig. 87 Timings during reading
Address Valid address
tWC
tCH
tCS
tRC
ta(CE)
tDFtWRRtWPtRRW
ta(OE)
tDHtDH
tVSC
tCLZ
tOLZ
tDS
ta(AD)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VPPH
VPPL
CE
OE
WE
Data
VPP
Dout0016
82
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● Program command
The microcomputer enters the program mode by inputting com-
mand code “4016” in the first cycle. The command code is latched
___
into the internal command latch at the rising edge of the WE input.
When the address which indicates a program location and data is
input in the second cycle, the M38B79FF internally latches the ad-
___
dress at the falling edge of the WE input and the data at the rising
___
edge of the WE input. The M38B79FF starts programming at the
___
rising edge of the WE input in the second cycle and finishes pro-
gramming within 10 µs as measured by its internal timer.
Programming is performed in units of bytes.
Note: A programming operation is not completed by executing the
program command once. Always be sure to execute a pro-
gram verify command after executing the program command.
When the failure is found in this verification, the user must re-
peatedly execute the program command until the pass. Refer
to Figure 90 for the programming flowchart.
● Program verify command
The microcomputer enters the program verify mode by inputting
command code “C016” in the first cycle. This command is used to
verify the programmed data after executing the program com-
mand. The command code is latched into the internal command
___
latch at the rising edge of the WE input. When control signals are
input in the second cycle at the timing shown in Figure 88, the
M38B79FF outputs the programmed address’s contents to the ex-
ternal. Since the address is internally latched when the program
command is executed, there is no need to input it in the second
cycle.
Fig. 88 Input/output timings during programming (Verify data is output at the same timing as for read.)
Address Program
Program verify
Program
address
tWC
tCS
tRRW
tWP tWPH tWP tDP
tDS
4016 DIN C016 Dout
tDS
tDH tDH Verify data output
tDH
tVSC
tDS
tWP tWRR
tCS tCS
tCH tCH tCH
tAS tAH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VPPH
VPPL
CE
OE
WE
Data
VPP
83
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● Erase command
The erase command is executed by inputting command code 2016
in the first cycle and command code 2016 again in the second
cycle. The command code is latched into the internal command
___
latch at the rising edges of the WE input in the first cycle and in
the second cycle, respectively. The erase operation is initiated at
___
the rising edge of the WE input in the second cycle, and the
memory contents are collectively erased within 9.5 ms as mea-
sured by the internal timer. Note that data 0016 must be wr itten to
all memory locations before executing the erase command.
Note: An erase operation is not completed by executing the erase
command once. Alw ays be sure to execute an erase verify
command after executing the erase command. When the fail-
ure is found in this verification, the user must repeatedly ex-
ecute the erase command until the pass. Refer to Figure 90
for the erase flowchart.
Fig. 89 Input/output timings during erasing (verify data is output at the same timing as for read.)
● Erase verify command
The user must verify the contents of all addresses after complet-
ing the erase command. The microcomputer enters the erase
verify mode by inputting the verify address and command code
A016 in the first cycle. The address is inter nally latched at the fall-
___
ing edge of the WE input, and the command code is internally
___
latched at the rising edge of the WE input. When control signals
are input in the second cycle at the timing shown in Figure 89, the
M38B79FF outputs the contents of the specified address to the
external.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the op-
eration of “erase → erase verify” over again. In this case,
ho we ver, the user does not need to write data 0016 to memory
locations before erasing.
Address Erase
Erase verify
Verify
address
tWC
tCS
tRRW
tWP tWPH tWP tDE
tDS
2016 2016 A016 Dout
tDS
tDH tDH
Verify data output
tDH
tVSC
tDS
tWP tWRR
tCS tCS
tCH tCH tCH
tAS tAH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VPPH
VPPL
CE
OE
WE
Data
VPP
84
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● Reset command
The reset command provides a means of stopping execution of
the erase or program command safely. If the user inputs command
code FF16 in the second cycle after inputting the erase or program
command in the first cycle and again input command code FF16 in
the third cycle, the erase or program command is disabled (i.e.,
reset), and the M38B79FF is placed in the read mode. If the reset
command is executed, the contents of the memory does not
change.
● Device identification code command
By inputting command code 9016 in the first cycle, the user can
read out the device identification code. The command code is
latched into the internal command latch at the rising edge of the
___
WE input. At this time, the user can read out manufacture’s code
1C16 (i.e., MITSUBISHI) by inputting 000016 to the address input
pins in the second cycle; the user can read out device code D016
(i. e., 1M-bit flash memory) by inputting 000116.
These command and data codes are input/output at the same tim-
ing as for read.
85
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Fig. 90 Programming/Erasing algorithm flow chart
START
VCC = 5 V, VPP = VPPH
ADRS = first location
X = 0
WRITE PROGRAM
COMMAND
WRITE PROGRAM
DATA
DURATION = 10 µs
X = X + 1
WRITE PROGRAM-VERIFY
COMMAND
4016
DIN
C016
0016
DURATION = 6 µs
X = 25 ?
LAST ADRS ?
NO
INC ADRS
WRITE READ COMMAND
VPP = VPPL
DEVICE
PASSED DEVICE
FAILED
VERIFY BYTE ? VERIFY BYTE ?
FAIL
FAIL
Program Erase
YES
YES
NO
PASS
PASS
START
VCC = 5 V, VPP = VPPH
ADRS = first location
X = 0
WRITE ERASE
COMMAND
PROGRAM
ALL BYTES = 0016
ALL
BYTES = 0016 ?
WRITE ERASE
COMMAND
DURATION = 9.5 ms
X = X + 1
WRITE ERASE-VERIFY
COMMAND
2016
2016
A016
0016
DURATION = 6 µs
X = 1000 ?
LAST ADRS ?
NO
INC ADRS
WRITE READ COMMAND
VPP = VPPL
DEVICE
PASSED DEVICE
FAILED
VERIFY BYTE ? VERIFY BYTE ?
FAIL
FAIL
YES
YES
NO
PASS
PASS
YES
NO
86
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Table 16 DC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Symbol Max.
1
100
15
15
15
10
100
100
30
30
0.2Vcc
VCC
VCC + 1.0
12.6
__
VCC = 5.5 V, CE = VIH
VCC = 5.5 V,
__
CE = VCC ± 0.2 V
__
VCC = 5.5 V, CE = VIL,
tRC = 150 ns, IOUT = 0 mA
VPP = VPPH
VPP = VPPH
0≤VPP≤VCC
VCC<VPP≤VCC + 1.0 V
VPP = VPPH
VPP = VPPH
VPP = VPPH
IOH = –400 µA
IOH = –100 µA
ISB1
ISB2
ICC1
ICC2
ICC3
IPP1
IPP2
IPP3
VIL
VIH
VOH1
VOH2
VPPL
VPPH
VCC supply current (at standby)
VCC supply current (at read)
VCC supply current (at program)
VCC supply current (at erase)
VPP supply current (at read)
VPP supply current (at program)
VPP supply current (at erase)
“L” input voltage
“H” input voltage
“H” output voltage
VPP supply voltage (read only)
VPP supply voltage (read/write)
Parameter Test conditions Typ.Min. Limits
mA
µA
mA
mA
mA
µA
µA
µA
mA
mA
V
V
V
V
V
V
Unit
0
0.52Vcc
2.4
VCC –0.4
VCC
11.7 12.0
AC ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC = 5 V ± 10 %, unless otherwise noted)
Table 17 Read-only mode
Symbol Max.
Parameter Min. Limits Unit
tRC
ta(AD)
ta(CE)
ta(OE)
tCLZ
tOLZ
tDF
tDH
tWRR
Read cycle time
Address access time
__
CE access time
__
OE access time
__
Output enable time (after CE)
__
Output enable time (after OE)
__
Output floating time (after OE)
__ __
Output valid time (after CE, OE, address)
Write recovery time (before read)
500
0
0
0
6
500
500
200
70
ns
ns
ns
ns
ns
ns
ns
ns
µs
Table 18 Read/Write mode
Symbol Max.
Parameter Min. Limits Unit
tWC
tAS
tAH
tDS
tDH
tWRR
tRRW
tCS
tCH
tWP
tWPH
tDP
tDE
tVSC
Write cycle time
Address set up time
Address hold time
Data setup time
Data hold time
Write recovery time (before read)
Read recovery time (before write)
__
CE setup time
__
CE hold time
Write pulse width
Write pulse waiting time
Program time
Erase time
VPP setup time
300
0
120
100
20
6
0
40
0
120
40
10
9.5
1
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
µs
ms
µs
Note: Read timing of Read/Write mode is same as Read-only mode.
87
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
(2) Flash memory mode 2 (serial I/O mode)
The M38B79FF has a function to serially input/output the software
commands, addresses, and data required for operation on the in-
ternal flash memory (e. g., read, program, and erase) using only a
few pins. This is called the ser ial I/O (input/output) mode. This
mode can be selected by driving the SDA (serial data input/out-
__
put), SCLK (serial clock input ), and OE pins high after connecting
wires as shown in Figures 91 and powering on the VCC pin and
then applying VPPH to the VPP pin.
In the serial I/O mode, the user can use six types of software com-
mands: read, program, program verify, erase, erase verify and
error check.
Serial input/output is accomplished synchronously with the clock,
beginning from the LSB (LSB first).
Fig. 91 Pin connection of M38B79FF when operating in serial I/O mode
M
3
8
B
7
9
F
F
F
P
*
P
47/
F
L
D3
9
*
P
00/
F
L
D8
*
P
03/
F
L
D1
1
*
P
04/
F
L
D1
2
*
P
05/
F
L
D1
3
*
P
06/
F
L
D1
4
*
P
07/
F
L
D1
5
*
P
11/
F
L
D1
7
*
P
12/
F
L
D1
8
*
P
13/
F
L
D1
9
*
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14/
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D2
0
*
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15/
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L
D2
1
*
P
16/
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D2
2
*
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17/
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L
D2
3
*
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10/
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D1
6
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L
D9
*
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D1
0
VE
E
*
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46/
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8
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43/
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D3
5
*
P
42/
F
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D3
4
*
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41/
F
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D3
3
*
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F
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D3
2
*
P
37/
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D3
1
*
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36/
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D3
0
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P
35/
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L
D2
9
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P
34/
F
L
D2
8
*
P
33/
F
L
D2
7
*
P
32/
F
L
D2
6
*
P
31/
F
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D2
5
*
P
30/
F
L
D2
4
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7
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6
P
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0
8
1
8
2
8
3
8
4
8
5
8
6
8
7
8
8
8
9
9
0
9
1
9
2
9
3
9
4
9
5
9
6
9
7
9
8
9
9
10
0
*
✱
P
a
c
k
a
g
e
t
y
p
e
:
1
0
0
P
6
S
-
A
88
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Table 19 Pin description (flash memory serial I/O mode)
VCC, VSS
CNVSS
_____
RESET
XIN
XOUT
AVSS
VREF
P00–P07
P10–P17
P20–P27
P30–P36
P37
P40–P47
P50–P57
P60–P63, P65
P64
P66
P67
P70–P77
P80–P83
P90–P97
PA0–PA7
PB0–PB6
VEE
Pin
Power supply
VPP input
Reset input
Clock input
Clock output
Analog supply input
Reference voltage input
Input port P0
Input port P1
Input port P2
Input port P3
Control signal input
Input port P4
Input port P5
Input port P6
SDA I/O
SCLK input
BUSY output
Input port P7
Input port P8
Input port P9
Input port PA
Input port PB
Pull-down power supply
Name
—
Input
Input
Input
Output
—
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Input
Output
Input
Input
Input
Input
Input
Input
/Output
Functions
Supply 5 V ± 10 % to VCC and 0 V to VSS.
Connect to 11.7 V to 12.6 V.
Connect to VSS.
Connect a ceramic resonator between XIN and XOUT.
Connect to VSS.
Input an arbitrary level between the range of VSS and VCC.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
__
OE input pin
Input “H” or “L” , or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L” to P60–P63, P65, or keep them open.
This pin is for serial data I/O.
This pin is for serial clock input.
This pin is for BUSY signal output.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Input “H” or “L”, or keep them open.
Keep this open.
89
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Functional Outline (serial I/O mode)
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
Data is transferred in units of eight bits.
In the first transfer, the user inputs the command code. This is fol-
lowed by address input and data input/output according to the
contents of the command. Table 20 shows the software com-
mands used in the serial I/O mode. The following explains each
software command.
Table 20 Software command (serial I/O mode)
Read
Program
Program verify
Erase
Erase verify
Error check
Number of transfers
Command First command
code input
0016
4016
C016
2016
A016
8016
Read address L (Input)
Program address L (Input)
Verify data (Output)
2016 (Input)
Verify address L (Input)
Error code (Output)
Second
Read address H (Input)
Program address H (Input)
—————
—————
Verify address H (Input)
—————
Third Fourth
Read data (Output)
Program data (Input)
—————
—————
Verify data (Output)
—————
● Read command
Input command code 0016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
__
pull the OE pin low. When this is done , the M38B79FF reads out
the contents of the specified address, and then latchs it into the in-
__
ternal data latch. When the OE pin is released back high and se-
rial clock is input to the SCLK pin, the read data that has been
latched into the data latch is serially output from the SDA pin.
Fig. 92 Timings during reading
“L”
SCLK
BUSY
OE
SDA
tCH
A0A7A8A15 D0D7
tCH
tCR
Command code input (0016) Read address input (L) Read address input (H) Read data output
tWR
Read
tRC
Note : When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
00000000
90
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● Program command
Input command code 4016 in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
then program data. Programming is initiated at the last rising edge
of the ser ial clock dur ing program data transfer. The BUSY pin is
driven high during program operation. Programming is completed
within 10 µs as measured by the internal timer, and the BUSY pin
is pulled low.
Note :A programming operation is not completed by executing the
program command once. Alw ays be sure to execute a pro-
gram verify command after executing the program command.
When the failure is found in the verification, the user must re-
peatedly execute the program command until the pass in the
verification. Refer to Figure 90 for the programming flowchart.
● Program verify command
Input command code C016 in the first transfer. Proceed and drive
__
the OE pin low. When this is done, The M38B79FF ver ify-reads
the programmed address’s contents, and then latchs it into the in-
__
ternal data latch. When the OE pin is released back high and se-
rial clock is input to the SCLK pin, the verify data that has been
latched into the data latch is serially output from the SDA pin.
Fig. 94 Timings during program verify
Fig. 93 Timings during programming
SCLK
BUSY
OE
SDA
tCH
A0
00000010
A7A8A15 D0D7
tCH tCH
tPC
Command code input (4016) Program address input (L) Program address input (H) Program data input
tWP
Program
SCLK
BUSY
OE
SDA D
0
D
7
t
CRPV
Command code input (C0
16
) Verify data output
t
WR
Verify read
t
RC
Note: When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th
(C-E)
after the last rising edge of SCLK (at the 8th bit).
00000011
“L”
91
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● Erase command
Input command code 2016 in the first transfer and command code
2016 again in the second transfer. When this is done, the
M38B79FF executes an erase command. Erase is initiated at the
last rising edge of the serial clock. The BUSY pin is driven high
during the erase operation. Erase is completed within 9.5 ms as
measured by the internal timer, and the BUSY pin is pulled low.
Note that data 0016 must be written to all memory locations before
executing the erase command.
Note: A erase operation is not completed by executing the erase
command once. Always be sure to execute a erase verify
command after executing the erase command. When the fail-
ure is found in the verification, the user must repeatedly ex-
ecute the erase command until the pass in the verification.
Refer to Figure 90 for the erase flowchart.
Fig. 95 Timings at erasing
● Erase verify command
The user must verify the contents of all addresses after complet-
ing the erase command. Input command code A016 in the first
transfer. Proceed and input the low-order 8 bits and the high-order
__
8 bits of the address and pull the OE pin low. When this is done,
the M38B79FF reads out the contents of the specified address,
__
and then latchs it into the internal data latch. When the OE pin is
released back high and serial clock is input to the SCLK pin, the
verify data that has been latched into the data latch is serially out-
put from the SDA pin.
Note: If any memory location where the contents have not been
erased is found in the erase verify operation, execute the op-
eration of “erase → erase verify” over again. In this case,
ho we ver, the user does not need to write data 0016 to memory
locations before erasing.
Fig. 96 Timings during erase verify
twE
SCLK
BUSY
OE
SDA
tCH
tEC
00000100 00000100
Command code input (2016) Command code input (2016)
Erase
“H”
“L”
SCLK
BUSY
OE
SDA
tCH
A0A7A8A15 D0D7
tCH
tCREV
Command code input (A016) Verify address input (L) Verify address input (H) Verify data output
tWR
Verify read
tRC
Note : When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of SCLK (at the 8th bit).
00000101
92
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● Error check command
Input command code 8016 in the first transfer, and the M38B79FF
outputs error information from the SDA pin, beginning at the next
falling edge of the serial clock. If the LSB bit of the 8-bit error infor-
mation is 1, it indicates that a command error has occurred. A
command error means that some invalid commands other than
commands shown in Table 20 has been input.
When a command error occurs, the serial communication circuit
sets the corresponding flag and stops functioning to avoid an erro-
neous programming or erase. When being placed in this state, the
serial communication circuit does not accept the subsequent serial
clock and data (even including an error check command). There-
fore, if the user wants to execute an error check command,
temporarily drop the VPP pin input to the VPPL level to terminate
the serial input/output mode. Then, place the M38B79FF into the
serial I/O mode back again. The serial communication circuit is re-
set by this operation and is ready to accept commands. The error
flag alone is not cleared by this operation, so the user can exam-
ine the serial communication circuit’s error conditions before reset.
This examination is done by the first execution of an error check
command after the reset. The error flag is cleared when the user
has executed the error check command. Because the error flag is
undefined immediately after power-on, always be sure to execute
the error check command.
Fig. 97 Timings at error checking
SCLK
BUSY
OE
SDA E0
tCH
Command code input (8016) Error flag output
00000001 ??????
Note: When outputting the error flag, the SDA pin is switched for output at the first falling edge of the serial clock. The SDA pin is placed
in the floating state during the period of th(C-E) after the last rising edge of the serial clock (at the 8th bit).
?
“H”
“L”
93
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
ns
ns
ns
ns
µs
µs
ns
µs
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DC ELECTRICAL CHARACTERISTICS
(Ta = 25 °C, V
CC
= 5 V ± 10 %, V
PP
= 11.7 to 12.6 V, unless otherwise noted)
ICC, IPP-relevant standards during read, program, and erase are the same as in the parallel input/output mode. VIH, VIL, VOH, VOL, IIH, and
__
IIL for the SCLK, SDA, BUSY, OE pins conform to the microcomputer modes.
Table 21 AC Electrical characteristics
(Ta = 25 °C, VCC = 5 V ± 10 %, VPP = 11.7 to 12.6 V, f(XIN) = 4 MHz, unless otherwise noted)
Symbol Max.
10
9.5
90
312.5
(Note 4)
tCH
tCR
tWR
tRC
tCRPV
tWP
tPC
tCREV
tWE
tEC
tc(CK)
tw(CKH)
tw(CKL)
tr(CK)
tf(CK)
td(C-Q)
th(C-Q)
th(C-E)
tsu(D-C)
th(C-D)
Serial transmission interval
Read waiting time after transmission
Read pulse width
Transfer waiting time after read
Waiting time before program verify
Programming time
Transfer waiting time after programming
Waiting time before erase verify
Erase time
Transfer waiting time after erase
SCLK input cycle time
SCLK high-level pulse width
SCLK low-level pulse width
SCLK rise time
SCLK fall time
SDA output delay time
SDA output hold time
SDA output hold time (only the 8th bit)
SDA input set up time
SDA input hold time
Parameter Unit
Min.
625(Note 1)
625(Note 1)
500(Note 2)
625(Note 1)
6
625(Note 1)
6
625(Note 1)
250
100
100
20
20
0
0
187.5(Note 3)
30
90
Limits
Notes 1: When f(X IN) = 4 MHz or less, calculate the minimum value according to formula 1.
Formula 1 : × 106
2: When f(X IN) = 4 MHz or less, calculate the minimum value according to formula 2.
Formula 2 : × 106
3: When f(X IN) = 4 MHz or less, calculate the minimum value according to formula 3.
Formula 3 : × 106
4: When f(X IN) = 4 MHz or less, calculate the minimum value according to formula 4
Formula 4 : × 106
2500
f(XIN)
2000
f(XIN)
1250
f(XIN)
750
f(XIN)
AC waveforms
SCLK
SDA input
Test conditions for AC characteristics
• Output timing voltage : V
OL
= 0.8 V, V
OH
= 2.0 V
• Input timing voltage : V
IL
= 0.2 V
CC
, V
IH
= 0.8 V
CC
SDA output
t
c(CK)
t
r(CK)
t
d(C-Q)
t
su(D-C)
t
h(C-D)
t
h(C-E)
t
h(C-Q)
t
f(CK)
t
w(CKL)
t
w(CKH)
94
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
(3) Flash memory mode 3 (CPU reprogramming
mode)
The M38B79FF has the CPU reprogramming mode where a built-
in flash memory is handled by the central processing unit (CPU).
In CPU reprogramming mode, the flash memory is handled by
writing and reading to/from the flash memory control register (see
Figure 98) and the flash command register (see Figure 99).
The CNVSS pin is used as the VPP power supply pin in CPU repro-
gramming mode. It is necessary to apply the power-supply voltage
of VPPH from the external to this pin.
Functional Outline (CPU reprogramming mode)
Figure 98 shows the flash memory control register bit configura-
tion. Figure 99 shows the flash command register bit
configuration.
Bit 0 of the flash memory control register is the CPU reprogram-
ming mode select bit. When this bit is set to “1” and VPPH is
applied to the CNVss/VPP pin, the CPU reprogramming mode is
selected. Whether the CPU reprogramming mode is realized or
not is judged by reading the CPU reprogramming mode monitor
flag (bit 2 of the flash memory control register).
Bit 1 is a busy flag which becomes “1” during erase and program
execution.
Whether these operations have been completed or not is judged
by checking this flag after each command of erase and the pro-
gram is executed.
Bits 4, 5 of the flash memory control register are the erase/pro-
gram area select bits. These bits specify an area where erase and
program is operated. When the erase command is executed after
an area is specified by these bits, only the specified area is
erased. Only for the specified area, programming is enabled; for
the other areas, programming is disabled.
Figure 100 shows the CPU mode register bit configuration in the
CPU reprogramming mode.
Fig. 98 Flash memory control register bit configuration
76543210
00 Flash memory control regsiter
(FCON : address 0EFE
16
)
CPU reprogramming mode select bit (Note)
0 : CPU reprogramming mode is invalid. (Normal operation mode)
1 : When applying 0 V or V
PP
L to CNV
SS
/V
PP
pin, CPU reprogramming mode is
invalid. When applying V
PP
H to CNV
SS
/V
PP
pin, CPU reprogramming mode is valid.
Erase/Program busy flag
0 : Erase and program are completed or not have been executed.
1 : Erase/program is being executed.
CPU reprogramming mode monitor flag
0 : CPU reprogramming mode is invalid.
1 : CPU reprogramming mode is valid.
Erase/Program area select bits
0 0 : Addresses 1000
16
to FFFF
16
(total 60 Kbytes)
0 1 : Addresses 1000
16
to 7FFF
16
(total 28 Kbytes)
1 0 : Addresses 8000
16
to FFFF
16
(total 32 Kbytes)
1 1 : Not available
Fix this bit to “0”.
Fix this bit to “0”.
Note: Bit 0 can be reprogrammed only when 0 V is applied to the CNV
SS
/V
PP
pin.
Not used (returns “0” when read)
95
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● CPU reprogramming mode operation procedure
The operation procedure in CPU reprogramming mode is de-
scribed below.
< Beginning procedure >
➀ Apply 0 V to the CNVss/VPP pin for reset release.
➁ Set the CPU mode register. (see Figure 100)
➂ After CPU reprogramming mode control program is transferred to
internal RAM, jump to this control program on RAM. (The follow-
ing operations are controlled by this control program).
➃ Set “1” to the CPU reprogramming mode select bit.
➄ Apply VPPH to the CNVSS/VPP pin.
➅ Wait till CNVSS/VPP pin becomes 12 V.
➆ Read the CPU reprogramming mode monitor flag to confirm
whether the CPU reprogramming mode is valid.
➇ The operation of the flash memory is executed by software-com-
mand-writing to the flash command register .
Note: The following are necessary other than this:
•Control for data which is input from the external (serial I/O
etc.) and to be programmed to the flash memory
•Initial setting for ports etc.
•Writing to the watchdog timer
< Release procedure >
➀ Apply 0V to the CNVSS/VPP pin.
➁ Wait till CNVSS/VPP pin becomes 0V.
➂ Set the CPU reprogramming mode select bit to “0”.
Each software command is explained as follows.
● Read command
When “0016” is written to the flash command register, the
M38B79FF enters the read mode. The contents of the corre-
sponding address can be read by reading the flash memory (For
instance, with the LDA instruction etc.) under this condition.
The read mode is maintained until another command code is written
to the flash command register. Accordingly, after setting the read
mode once, the contents of the flash memory can continuously be
read.
After reset and after the reset command is executed, the read
mode is set.
Fig. 99 Flash command register bit configuration Fig. 100 CPU mode register bit configuration in CPU rewriting
mode
Writing of software command
<Command code>
“0016”
“4016”
“C016”
“2016” + “2016”
“A016”
“FF16” + “FF16”
<Software command name>
• Read command
• Program command
• Program verify command
• Erase command
• Erase verify command
• Reset command
Note: The flash command register is write-only register.
Flash command register
(FCMD : address 0EFF16)
76543 210 C
P
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:
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b
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0
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:
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=
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(
XI
N)
(
h
i
g
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p
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d
m
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=
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(
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/
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(
m
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m
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/
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(
l
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1
:
N
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t
a
v
a
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l
a
b
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00
96
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
● Program command
When “4016” is written to the flash command register, the
M38B79FF enters the program mode.
Subsequently to this, if the instruction (for instance, STA
instruction) for writing byte data in the address to be programmed
is executed, the control circuit of the flash memory executes the
progr am. The erase/program busy flag of the flash memory control
register is set to “1” when the program starts, and becomes “0”
when the program is completed. Accordingly, after the write in-
struction is executed, CPU can recognize the completion of the
program by polling this bit.
The programmed area must be specified beforehand by the erase/
program area select bits.
During programming, watchdog timer stops with “FFFF16” set.
Note: A progr amming operation is not completed by executing the
program command once. Always be sure to execute a pro-
gram verify command after executing the program command.
When the failure is found in this verification, the user must re-
peatedly execute the program command until the pass. Refer
to Figure 101 for the flow chart of the programming.
● Program verify command
When “C016” is written to the flash command register, the
M38B79FF enters the program verify mode. Subsequently to this,
if the instruction (for instance, LDA instruction) for reading byte
data from the address to be verified (i.e., previously programmed
address), the contents which has been written to the address ac-
tually is read.
CPU compares this read data with data which has been written by
the previous program command. In consequence of the compari-
son, if not agreeing, the operation of “program → program verify”
must be executed again.
● Erase command
When writing “2016” twice continuously to the flash command reg-
ister, the flash memory control circuit performs erase to the area
specified beforehand by the erase/program area select bits.
Erase/program busy flag of the flash memory control register be-
comes “1” when erase begins, and it becomes “0” when erase
completes. Accordingly, CPU can recognize the completion of
erase by polling this bit.
Data “0016” must be written to all areas to be erased by the pro-
gram and the program verify commands before the erase
command is executed.
During erasing, watchdog timer stops with “FFFF16” set.
Note: The er asing oper ation is not completed by e xecuting the erase
command once. Always be sure to execute an erase ver ify
command after executing the erase command. When the fail-
ure is found in this verification, the user must repeatedly ex-
ecute the erase command until the pass. Refer to Figure 101
for the erasing flowchart.
● Erase verify command
When “A016” is written to the flash command register, the
M38B79FF enters the erase verify mode. Subsequently to this, if
the instruction (for instance, LDA instruction) for reading byte data
from the address to be verified, the contents of the address is
read.
CPU must erase and verify to all erased areas in a unit of ad-
dress.
If the address of which data is not “FF16” (i.e., data is not erased)
is found, it is necessary to discontinue erasure verification there,
and execute the operation of “erase → erase verify” again.
Note: By executing the operation of “erase → erase verify” again
when the memory not erased is found. It is unnecessary to
write data “0016” before erasing in this case.
● Reset command
The reset command is a command to discontinue the program or
erase command on the w ay. When “FF16” is written to the command
register two times continuously after “4016” or “2016” is written to the
flash command register, the program, or erase command becomes
invalid (reset), and the M38B79FF enters the reset mode.
The contents of the memory does not change even if the reset com-
mand is executed.
DC Electric Characteristics
Note: The character istic concerning the flash memory par t are the
same as the characteristic of the parallel I/O mode.
AC Electric Characteristics
Note: The characteristics are the same as the char acter istic of the
microcomputer mode.
97
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Fig. 101 Flowchart of program/erase operation at CPU reprogramming mode
ERASE PROGRAM
BUSY FLAG = 0
START
ADRS = first location
X = 0
WRITE PROGRAM
COMMAND
WRITE PROGRAM
DATA
WAIT 1µs
X = X + 1
WRITE PROGRAM-VERIFY
COMMAND
40
16
DIN
C0
16
00
16
DURATION = 6 µs
X = 25 ?
LAST ADRS ?
NO
INC ADRS
WRITE READ COMMAND
DEVICE
PASSED DEVICE
FAILED
VERIFY BYTE ? VERIFY BYTE ?
FAIL
FAIL
Program Erase
YES
YES
NO
PASS
PASS
START
ADRS = first location
X = 0
WRITE ERASE
COMMAND
PROGRAM
ALL BYTES = 00
16
ALL
BYTES = 00
16
?
WRITE ERASE
COMMAND
X = X + 1
WRITE ERASE-VERIFY
COMMAND
20
16
20
16
A0
16
00
16
DURATION = 6 µs
X = 1000 ?
LAST ADRS ?
NO
INC ADRS
WRITE READ COMMAND
DEVICE
PASSED DEVICE
FAILED
VERIFY BYTE ? VERIFY BYTE ?
FAIL
FAIL
YES
YES
NO
PASS
PASS
YES
NO
ERASE PROGRAM
BUSY FLAG = 0
WAIT 1µs
NO
YES
YES
NO
98
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” Af-
ter a reset, initialize flags which affect program execution. In
particular, it is essential to initialize the index X mode (T) and the
decimal mode (D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immedi-
ately after they have been written. After writing to an interrupt
request register, execute at least one instruction before perfor m-
ing a BBC or BBS instruction.
Decimal Calculations
•To calculate in decimal notation, set the decimal mode flag (D)
to “1”, then execute an ADC or SBC instr uction. After executing
an ADC or SBC instruction, execute at least one instruction be-
fore executing a SEC, CLC, or CLD instruction.
•In decimal mode, the values of the negative (N), overflow (V),
and zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the fre-
quency division ratio is 1/(n+1).
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not af-
fect the MUL and DIV instruction.
•The execution of these instructions does not change the con-
tents of the processor status register.
Ports
The contents of the port direction registers cannot be read. The
following cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The instruction with the addressing mode which uses the value
of a direction register as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to
a direction register.
Use instructions such as LDM and STA, etc., to set the port direc-
tion registers.
Serial I/O
•Using an external clock
When using an external clock, input “H” to the external clock input
pin and clear the serial I/O interrupt request bit before executing
serial I/O transfer and serial I/O automatic transfer.
•Using an internal clock
When using an internal clock, set the synchronous clock to the in-
ternal clock, then clear the serial I/O interrupt request bit before
executing ser ial I/O transfer and serial I/O automatic transfer.
Automatic Transf er Serial I/O
When using the automatic transfer serial I/O mode of the serial I/
O1, set an automatic transfer interval as the following.
Otherwise the serial data might be incorrectly transmitted/re-
ceived.
•Set an automatic transfer interval for each 1-byte data transfer as
the following:
(1) Not using FLD controller
Keep the interval for 5 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
(2) Using FLD controller
(a) Not using gradation display
Keep the interval for 17 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
(b) Using gradation display
Keep the interval for 27 cycles or more of internal system
clock from clock rising of the last bit of 1-byte data.
A-D Converter
The comparator uses capacitive coupling amplifier whose charge
will be lost if the clock frequency is too low.
Therefore, make sure that f(XIN) is at least on 250 kHz during an
A-D conversion.
Do not execute the STP or WIT instruction dur ing an A-D conver-
sion.
D-A Converter
The accuracy of the D-A converter becomes rapidly poor under
the VCC = 4.0 V or less condition; a supply voltage of VCC ≥ 4.0 V
is recommended. When a D-A converter is not used, set the value
of D-A conversion register to “0016”.
Instruction Execution Time
The instruction execution time is obtained by multiplying the pe-
riod of the internal clock φ by the number of cycles needed to
execute an instruction.
The number of cycles required to execute an instruction is shown
in the list of machine instructions.
The period of the internal clock φ is half of the XIN period in high-
speed mode.
99
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
NOTES ON USAGE
Handling of Power Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (VCC pin) and GND pin (VSS pin), between power
source pin (VCC pin) and analog power source input pin (AVSS
pin), and between program power source pin (CNVss/VPP) and
GND pin for flash memory version when on-board reprogramming
is executed. Besides, connect the capacitor to as close as pos-
sible. For bypass capacitor which should not be located too far
from the pins to be connected, a ceramic capacitor of 0.01 µF–0.1
µF is recommended.
Flash Memor y Version
The CNVSS pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNV SS
pin and VSS pin or VCC pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVSS pin has no operational in-
terference even if it is connected to Vss pin or Vcc pin via a
resistor.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Confirmation Form
2.Mark Specification Form
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or in one floppy disk.
100
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
ELECTRICAL CHARACTERISTICS
Table 22 Absolute maximum ratings
Power source voltages
Pull-down power source voltages
Input voltage P64–P67, P70–P77, P80–P83,
P90–P97, PA0–PA7, PB0–PB6
Input voltage P10–P17, P30–P37, P40–P47,
P50–P57, P60–P63
Input voltage RESET, XIN, CNVSS
Input voltage XCIN
Output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50–P57,
P60–P63
Output voltage P64–P67, P80–P83, P70–P77,
P90–P97, PA0–PA7, PB0–PB6,
XOUT, XCOUT
Power dissipation
Operating temperature
Storage temperature
VCC
VEE
VI
VI
VI
VI
VO
VO
Pd
Topr
Tstg
Symbol Parameter Conditions Ratings
–0.3 to 6.5
VCC –45 to VCC +0.3
–0.3 to VCC +0.3
VCC –45 to VCC +0.3
–0.3 to VCC +0.3
–0.3 to VCC +0.3
VCC –45 to VCC +0.3
–0.3 to VCC +0.3
800
800 –12.5 ✕ (Ta –65)
–20 to 85
–40 to 125
V
V
V
V
V
V
V
V
mW
mW
°C
°C
Unit
Ta = –20 to 65 °C
Ta = 65 to 85 °C
All voltages are based on VSS.
Output transistors are cut off.
5.5
5.5
5.5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.25VCC
0.16VCC
0.2VCC
0.2VCC
0.2VCC
High-speed mode
Middle/Low-speed mode
Power source voltage (flash memory version)
Power source voltage
Pull-down power source voltage
Analog reference voltage
Analog power source voltage
Analog input voltage AN0–AN15
“H” input voltage P70–P77, P80–P83, P9 0–P97, PA0–PA7, PB0–PB6
“H” input voltage P64–P67
“H” input voltage P10–P17, P30–P37, P4 0–P47, P50–P57, P6 0–P63
“H” input voltage RxD, SCLK21, SCLK22
“H” input voltage XIN, XCIN, RESET, CNVss
“L” input voltage P70–P77, P80–P83, P9 0–P97, PA0–PA7, PB0–PB6
“L” input voltage P64–P67
“L” input voltage P10–P17, P30–P37, P40–P47, P50–P57, P60–P63
“L” input voltage RxD, SCLK21, SCLK22
“L” input voltage XIN, XCIN, RESET, CNVss
VCC
VCC
VSS
VEE
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Symbol Parameter Limits
Min. V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Unit
Table 23 Recommended operating conditions
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
4.0
2.7
4.0
Vcc –43
2.0
3.0
0
0.75VCC
0.4VCC
0.52VCC
0.8VCC
0.8VCC
0
0
0
0
0
5.0
5.0
5.0
0
0
Typ. Max.
when A-D converter is used
when D-A converter is used
Power source voltage (mask ROM version)
101
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Table 24 Recommended operating conditions
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
–240
–60
100
60
–120
–30
50
–40
–10
10
–18
–5
5
250
4.2
50
“H” total peak output current
(Note 1) P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
7
, P7
0
–P7
7
“H” total peak output current
(Note 1) P8
0
–P8
3
, P9
0
–P9
7
, PA
0
–PA
7
, PB
0
–PB
6
“L” total peak output current (Note 1) P64–P67, P70–P77
“L” total peak output current (Note 1)
P8
0
–P8
3
, P9
0
–P9
7
, PA
0
–PA
7
, PB
0
–PB
6
“H” total average output current
(Note 1)
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
3
“H” total aver age output current
(Note 1)
P6
4
–P6
7
, P7
0
–P7
7
, P8
0
–P8
3
, P9
0
–P9
7
, PA
0
–PA
7
,
PB
0
–PB
6
“L” total average output current
(Note 1)
P6
4
–P6
7
, P7
0
–P7
7
, P8
0
–P8
3
, P9
0
–P9
7
, PA
0
–PA
7
,
PB
0
–PB
6
“H” peak output current
(Note 2)
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
3
“H” peak output current
(Note 2)
P6
4
–P6
7
, P7
0
–P7
7
, P8
0
–P8
3
, P9
0
–P9
7
, PA
0
–PA
7
,
PB
0
–PB
6
“L” peak output current
(Note 2)
P6
4
–P6
7
, P7
0
–P7
7
, P8
0
–P8
3
, P9
0
–P9
7
, PA
0
–PA
7
,
PB
0
–PB
6
“H” average output current
(Note 3)
P0
0
–P0
7
, P1
0
–P1
7
, P2
0
–P2
7
, P3
0
–P3
7
, P4
0
–P4
7
,
P5
0
–P5
7
, P6
0
–P6
3
“H” aver age output current
(Note 3)
P6
4
–P6
7
, P7
0
–P7
7
, P8
0
–P8
3
, P9
0
–P9
7
, PA
0
–PA
7
,
PB
0
–PB
6
“L” average output current
(Note 3)
P6
4
–P6
7
, P7
0
–P7
7
, P8
0
–P8
3
, P9
0
–P9
7
, PA
0
–PA
7
,
PB
0
–PB
6
Clock input frequency for timers 2, 4, and X (duty cycle 50 %)
Main clock input oscillation frequency
(Note 4)
Sub-clock input oscillation frequency
(Notes 4, 5)
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
f(CNTR)
f(XIN)
f(XCIN)
Symbol Parameter Limits
Min. mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
kHz
MHz
kHz
Unit
Typ. Max.
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports . The total average current is an aver-
age value measured over 100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current IOL(avg), IOH(avg) are average value measured over 100 ms.
4: When the oscillation frequency has a duty cycle of 50%.
5: When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that
f(XCIN) < f(XIN)/3.
32.768
102
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Table 25 Electrical characteristics
(VCC = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
“H” output voltage P00–P07, P10–P17, P20–P27,
P30–P37, P40–P47, P50-P57,
P60–P63
“H” output voltage P64–P67, P70–P77, P80–P83,
P90–P97, PA0–PA7, PB0–PB6
“L” output voltage P64–P67, P70–P77, P80–P83,
P90–P97, PA0–PA7, PB0–PB6
Hysteresis RxD, SCLK21, SCLK22, SRDY1, P70–
P73, P77, P82–P83, P9 0–P92, PB0,
PB2, PB4–PB6
Hysteresis RESET, XIN
Hysteresis XCIN
“H” input current P64–P67, P70–P77, P80–P83,
P90–P97, PA0–PA7, PB0–PB6
“H” input current P10–P17, P30–P37, P40–P47,
P50-P57, P60–P63 (Note)
“H” input current RESET, CNVss, XCIN
“H” input current X IN
“L” input current P64–P67, P70–P77, P80–P83,
P90–P97, PA0–PA7, PB0–PB6
“L” input current P10–P17, P30–P37, P40–P47,
P50–P57, P60–P63 (Note)
“L” input current RESET, CNVss, XCIN
“L” input current XIN
VOH
VOH
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIH
IIL
IIL
IIL
IIL
IOH = –18 mA
IOH = –10 mA
IOL = 10 mA
VI = VCC
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-up “off”
VCC = 5 V, VI = VSS
Pull-up “on”
VCC = 3 V, VI = VSS
Pull-up “on”
VI = VSS
VI = VSS
VI = VSS
Test conditions
VCC–2.0
VCC–2.0
–30
–6.0
2.0
5.0
5.0
5.0
–5.0
–140
–45
–5.0
–5.0
0.4
0.5
0.5
4.0
–70
–25
–4.0
Note: Except when reading ports P1, P3, P4, P5 or P6.
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
103
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Table 26 Electrical characteristics
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Power source current
Limits
Parameter Min. Typ. Max.
Symbol UnitTest conditions
900
–10
5.5
15
55
20
1
10
ICC
Ta = 25 °C
Ta = 85 °C
600
1
7.0
1
3
1
20
8
0.6
0.1
µA
µA
µA
V
mA
mA
mA
mA
µA
µA
mA
µA
µA
ILOAD
ILEAK
IREADH
VRAM
Output load current
P00–P07, P10–P17,
P20–P27, P30–P37,
(P40–P47, P50–P57,
P60–P63 at option)
Output leak current
P00–P07, P10–P17,
P20–P27, P30–P37,
P40–P47, P50–P57,
P60–P63
“H” read current
P10–P17, P30–P37,
P40–P47, P50–P57,
P60–P63
RAM hold voltage
VEE = VCC–43 V, VOL =VCC
Output tr ansistors “off”
VEE = V CC–43 V, VOL =VCC–43 V
Output tr ansistors “off”
VI = 5 V
When clock is stopped
High-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz
f(XCIN) = 32.768 kHz
Output tr ansistors “off”
High-speed mode, Vcc = 5 V,
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output tr ansistors “off”
Middle-speed mode , Vcc = 5 V,
f(XIN) = 4.2 MHz
f(XCIN) = stopped
Output tr ansistors “off”
Middle-speed mode , Vcc = 5 V,
f(XIN) = 4.2 MHz (in WIT state)
f(XCIN) = stopped
Output tr ansistors “off”
Low-speed mode, Vcc = 3 V,
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output tr ansistors “off”
Low-speed mode, Vcc = 3 V,
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output tr ansistors “off”
Increment when A-D con version is
executed
All oscillation stopped
(in STP state)
Output tr ansistors “off”
400
2
104
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Table 27 A-D converter characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to 85 °C, f(XIN) = 250 kHz to 4.2 MHz in high-speed mode, unless otherwise noted)
Note: Except ladder resistor for A-D converter
Table 28 D-A converter characteristics
(VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 to Vcc, Ta = –20 to 85 °C, unless otherwise noted)
Bits
%
%
µs
kΩ
mA
Resolution
Absolute accuracy
(excluding quantization error)
Setting time
Output resistor
Reference power source input current (Note)
Min.
1
Typ.
2.5
Max.
8
1.0
2.5
3
4
3.2
Unit
Limits
Parameter
–
–
tsu
RO
IVREF
Test conditions
VCC = 4.0–5.5 V
VCC = 3.0–5.5 V
Symbol
Min. Typ. Max.
Symbol Parameter Limits UnitTest conditions
—
—
TCONV
IVREF
IIA
RLADDER
Resolution
Absolute accuracy (excluding quantization error)
Conversion time
Reference input current
Analog port input current
Ladder resistor
VCC = VREF = 5.12 V
VREF = 5.0 V 61
50
±1
150
0.5
35
10
±2.5
62
200
5.0
Bits
LSB
tc(
φ
)
µA
µA
kΩ
105
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
TIMING REQUIREMENTS
Table 29 Timing requirements (1)
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time (XCIN input)
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
CNTR0–CNTR2 input cycle time
CNTR0–CNTR2 input “H” pulse width
CNTR0–CNTR2 input “L” pulse width
INT0–INT4 input “H” pulse width (INT2 when noise filter is not used)
(Note 1)
INT0–INT4 input “L” pulse width (INT2 when noise filter is not used)
(Note 1)
INT2 input “H” pulse width (when noise filter is used) (Notes 1, 2)
INT2 input “L” pulse width (when noise filter is used) (Notes 1, 2)
Serial I/O1 clock input cycle time
Serial I/O1 clock input “H” pulse width
Serial I/O1 clock input “L” pulse width
Serial I/O1 input setup time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input setup time
Serial I/O2 input hold time
Serial I/O3 clock input cycle time
Serial I/O3 clock input “H” pulse width
Serial I/O3 clock input “L” pulse width
Serial I/O3 input setup time
Serial I/O3 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(CNTR)
tWH(CNTR)
tWL(CNTR)
tWH(INT)
tWL(INT)
tWH(INT2)
tWL(INT2)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(SIN1-SCLK1)
th(SCLK1-SIN1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(RxD-SCLK2)
th(SCLK2-RxD)
tC(SCLK3)
tWH(SCLK3)
tWL(SCLK3)
tsu(SIN3-SCLK3)
th(SCLK3-SIN3)
Limits
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
CLKs
CLKs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2.0
238
60
60
20
5.0
5.0
4.0
1.6
1.6
80
80
3
3
950
400
400
200
200
800
370
370
220
100
1000
400
400
200
200
Typ. Max.
Symbol Unit
Notes 1: IIDCON2, IIDCON3 = “00” when noise filter is not used
IIDCON2, IIDCON3 = “01” or “10” when noise filter is used
2: Unit indicates sample clock number of noise filter.
106
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Table 30 Switching characteristics
(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Serial I/O clock output “H” pulse width
Serial I/O clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O3 output delay time (Note 3)
Serial I/O3 output valid time (Note 3)
Serial I/O clock output rising time
Serial I/O clock output falling time
P-channel high-breakdodwn-voltage output
rising time (Note 4)
P-channel high-breakdodwn-voltage output
rising time (Note 5)
tWH (SCLK)
tWL (SCLK)
td (SCLK1-SOUT1)
tV (SCLK1-SOUT1)
td (SCLK2-TxD)
tV (SCLK2-TxD)
td (SCLK3-SOUT3)
tV (SCLK3-SOUT3)
tr (SCLK)
tf (SCLK)
tr (Pch–strg)
tr (Pch–weak)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Parameter Min.
tC(SCLK)/2–160
tC(SCLK)/2–160
0
–30
0
Typ.
55
1.8
Max.
200
140
200
40
40
Symbol Unit
Notes 1: When the PB5/SOUT1 P-channel output disable bit of the serial I/O1 control register (bit 7 of address 001A16) is “0”.
2: When the P65/TxD P-channel output disable bit of the UART control register (bit 4 of address 003816) is “0”.
3: When the P91/SOUT3 P-channel output disable bit of the serial I/O3 control register (bit 7 of address 0EEC16) is “0”.
4: When the high-breakdown voltage port drivability selection bit of the FLDC mode register (bit 7 of address 0EF416) is “0”.
5: When the high-breakdown voltage port drivability selection bit of the FLDC mode register (bit 7 of address 0EF416) is “1”.
Te s t conditions
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
CL = 100 pF
VEE = Vcc –43 V
CL = 100 pF
VEE = Vcc –43 V
Fig. 102 Circuit for measuring output switching characteristics
P
66/
SC
L
K
2
1,
P
67/
SC
L
K
2
2,
P
92/
SC
L
K
3,P
0
,
P
1
,
P
2
,
P
3
,
P
4
,
P
5
,
P
60–
P
63
P
B4/
SC
L
K
1
1
P
B0/
SC
L
K
1
2
,
CLCL
V
E
E
S
e
r
i
a
l
I
/
O
c
l
o
c
k
o
u
t
p
u
t
p
o
r
t
H
i
g
h
-
b
r
e
a
k
d
o
w
n
v
o
l
t
a
g
e
P
-
c
h
a
n
n
e
l
o
p
e
n
-
d
r
a
i
n
o
u
t
p
u
t
p
o
r
t
(
N
o
t
e
)
N
o
t
e
:
P
o
r
t
s
P
4
,
P
5
,
P
60–
P
63
n
e
e
d
e
x
t
e
r
n
a
l
r
e
s
i
s
t
o
r
s
.
107
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
Fig. 103 Timing diagram
0.2V
CC
t
WL(X
CIN
)
0.8V
CC
t
WH(X
CIN
)
t
C(X
CIN
)
X
CIN
0.2V
CC
t
WL(X
IN
)
0.8V
CC
t
WH(X
IN
)
t
C(X
IN
)
X
IN
0.2V
CC
0.8V
CC
t
W(RESET)
RESET
0.2V
CC
t
WL(CNTR)
0.8V
CC
t
WH(CNTR)
t
C(CNTR)
CNTR
0
,CNTR
1
0.2V
CC
t
WL(INT)
0.8V
CC
t
WH(INT)
INT
0–
INT
4
0.2V
CC
t
d(S
CLK
-S
OUT
)
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su(S
IN
-S
CLK
)
t
h(S
CLK
-S
IN
)
t
v(S
CLK
-S
OUT
)
t
C(S
CLK
)
t
WL(S
CLK
)
t
WH(S
CLK
)
S
OUT
, TxD
S
IN
, RxD
S
CLK
t
f(S
CLK
)
t
d(S
CLK
-TxD)
t
v(S
CLK
-TxD)
t
h(S
CLK
-RxD)
t
su(RxD-S
CLK
)
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to
change.
© 2000 MITSUBISHI ELECTRIC CORP.
New publication, effective Apr. 2000.
Specifications subject to change without notice.
Notes regarding these materials
•These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer’s application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
•Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
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Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product
distributor for the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
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personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
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HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
PACKAGE OUTLINE
QFP100-P-1420-0.65 1.58
Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42
100P6S-A
Plastic 100pin 14✕20mm body QFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.35 ––
I
2
1.3 ––
M
D
14.6 ––
M
E
20.6
10°0°0.1
1.4 0.80.60.4 23.122.822.5 17.116.816.5 0.65 20.220.019.8 14.214.013.8 0.20.150.13 0.40.30.25 2.8
03.05
e
e
e
E
c
H
E
1
30
31
81
50
80
51
H
D
D
M
D
M
E
A
F
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
100
x––0.13
b
x
M
Rev. Rev.
No. date
1.0 First Edition 10/04/00
1.1 Page 74 Mask options B to G are shaded to show that they cannoto be specified. Note 4 added. 02/10/00
Page 100 Absolute maximum ratings
VEE VCC–45 to VCC +0.3
VIVCC–45 to VCC +0.3
VOVCC–45 to VCC +0.3
REVISION HISTORY 38B7 GROUP DATA SHEET
(1/1)
Revision Description
