This is information on a product in full production.
February 2017 DocID023128 Rev 7 1/43
A7985A
2 A step-down switching regulator for automotive applications
Datasheet - production data
Features
AEC-Q100 qualified (see PPAP
for more details)
2 A DC output current
4.5 V to 38 V input voltage
Output voltage adjustable from 0.6 V
250 kHz switching frequency, programmable
up to 1 MHz
Internal soft-start and enable
Low dropout operation: 100% duty cycle
Voltage feed-forward
Zero load current operation
Overcurrent and thermal protection
HSOP8 package
Applications
Dedicated to automotive applications
Automotive LED driving
Description
The A7985A is a step-down switching regulator
with a 2.5 A (minimum) current limited embedded
power MOSFET, so it is able to deliver up to 2 A
current to the load depending on the application
conditions.
The input voltage can range from 4.5 V to 38 V,
while the output voltage can be set starting from
0.6 V to VIN.
Requiring a minimum set of external components,
the device includes an internal 250 kHz switching
frequency oscillator that can be externally
adjusted up to 1 MHz.
The HSOP8 package with exposed pad allows
the reduction of Rth(JA) down to 40 °C/W.
Figure 1. Application circuit
HSOP8 exposed pad
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Contents A7985A
2/43 DocID023128 Rev 7
Contents
1 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Oscillator and synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
5.2 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Error amplifier and compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5 Enable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6 Hysteretic thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4.1 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.2 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.5 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.6 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7 Application ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.1 Positive buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7.2 Inverting buck-boost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DocID023128 Rev 7 3/43
A7985A Contents
43
8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.1 HSOP8 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
List of tables A7985A
4/43 DocID023128 Rev 7
List of tables
Table 1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Input MLCC capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 10. HSOP8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 11. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
DocID023128 Rev 7 5/43
A7985A List of figures
43
List of figures
Figure 1. Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4. Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Sawtooth: voltage and frequency feed-forward; external synchronization . . . . . . . . . . . . . 12
Figure 6. Oscillator frequency vs. the FSW pin resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Soft-start scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. The error amplifier, the PWM modulator and the LC output filter . . . . . . . . . . . . . . . . . . . . 21
Figure 10. Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Open loop gain: module Bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 12. Open loop gain Bode diagram with ceramic output capacitor . . . . . . . . . . . . . . . . . . . . . . 24
Figure 13. Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 14. Open loop gain: module Bode diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor . . . . . . . . . . . . . 27
Figure 16. Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 17. Layout example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Demonstration board application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 19. PCB layout: A7985A (component side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 20. PCB layout: A7985A (bottom side) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 21. PCB layout: A7985A (front side). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 22. Junction temperature vs. output current at VIN = 24 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 23. Junction temperature vs. output current at VIN = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 24. Junction temperature vs. output current at VIN = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 25. Efficiency vs. output current at VO = 1.8 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 26. Efficiency vs. output current at VO = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 27. Efficiency vs. output current at VO = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 28. Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 29. Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 30. Load transient: from 0.4 A to 2 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 31. Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 32. Short-circuit behavior at VIN = 12 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 33. Short-circuit behavior at VIN = 24 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 34. Positive buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 35. Maximum output current according to max. DC switch current (2.0 A): VO = 12 V. . . . . . . 37
Figure 36. Inverting buck-boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 37. Maximum output current according to switch max. peak current (2.0 A): VO = -5 V. . . . . . 38
Figure 38. HSOP8 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Pin settings A7985A
6/43 DocID023128 Rev 7
1 Pin settings
1.1 Pin connection
Figure 2. Pin connection (top view)
1.2 Pin description
Table 1. Pin description
No. Type Description
1 OUT Regulator output.
2 SYNCH
Master/slave synchronization. When it is left floating, a signal with
a phase shift of half a period in respect to the power turn-on is present at
the pin. When connected to an external signal at a frequency higher than
the internal one, the device is synchronized by the external signal, with
zero phase shift.
Connecting together the SYNCH pins of two devices, the one with the
higher frequency works as master and the other as slave; so the two
power turn-ons have a phase shift of half a period.
3EN
A logical signal (active high) enables the device. With EN higher than
1.2 V the device is ON and with EN lower than 0.3 V the device is OFF.
4 COMP Error amplifier output to be used for loop frequency compensation.
5FB
Feedback input. Connecting the output voltage directly to this pin the
output voltage is regulated at 0.6 V. To have higher regulated voltages an
external resistor divider is required from VOUT to the FB pin.
6FSW
The switching frequency can be increased connecting an external resistor
from the FSW pin and ground. If this pin is left floating the device works at
its free-running frequency of 250 KHz.
7 GND Ground.
8V
CC Unregulated DC input voltage.
DocID023128 Rev 7 7/43
A7985A Maximum ratings
43
2 Maximum ratings
3 Thermal data
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
Vcc Input voltage 45
V
OUT Output DC voltage -0.3 to VCC
FSW, COMP, SYNCH Analog pin -0.3 to 4
EN Enable pin -0.3 to VCC
FB Feedback voltage -0.3 to 1.5
PTOT Power dissipation at TA < 60 °C HSOP8 2 W
TJJunction temperature range -40 to 150 °C
Tstg Storage temperature range -55 to 150 °C
Table 3. Thermal data
Symbol Parameter Value Unit
Rth(JA) Maximum thermal resistance junction ambient(1) HSOP8 40 °C/W
1. Package mounted on demonstration board.
Electrical characteristics A7985A
8/43 DocID023128 Rev 7
4 Electrical characteristics
TJ = -40 °C to 125 °C, VCC = 12 V, unless otherwise specified.
Table 4. Electrical characteristics
Symbol Parameter Test conditions
Values
Unit
Min. Typ. Max.
VCC Operating input voltage range - 4.5 - 38
VVCCON Turn-on VCC threshold - - - 4.5
VCCHYS VCC UVLO hysteresis - 0.1 - 0.4
RDS(on) MOSFET on-resistance - - 200 400 m
ILIM Maximum limiting current - 2.5 - 3.5 A
Oscillator
FSW Switching frequency - 210 250 275 kHz
VFSW FSW pin voltage - - 1.254 - V
D Duty cycle - 0 - 100 %
FADJ Adjustable switching frequency RFSW = 33 k- 1000 - kHz
Dynamic characteristics
VFB Feedback voltage 4.5 V < VCC < 38 V 0.588 0.6 0.612 V
DC characteristics
IQQuiescent current Duty cycle = 0, VFB = 0.8 V - - 2.4 mA
IQST-BY Total standby quiescent current - 20 30 A
Enable
VEN EN threshold voltage
Device OFF level - - 0.3
V
Device ON level 1.2 - -
IEN EN current EN = VCC - 7.5 10 µA
Soft-start
TSS Soft-start duration
FSW pin floating 7.3 8.2 9.8
ms
FSW = 1 MHz, RFSW = 33 k-2-
Error amplifier
VCH High level output voltage VFB < 0.6 V 3 - -
V
VCL Low level output voltage VFB > 0.6 V - - 0.1
IO SOURCE Source COMP pin VFB = 0.5 V, VCOMP = 1 V - 19 - mA
IO SINK Sink COMP pin VFB = 0.7 V, VCOMP = 0.75 V - 30 - mA
GVOpen loop voltage gain (1) - 100 - dB
DocID023128 Rev 7 9/43
A7985A Electrical characteristics
43
Synchronization function
VS_IN,HI High input voltage - 2 - 3.3
V
VS_IN,LO Low input voltage - - - 1
tS_IN_PW Input pulse width
VS_IN,HI = 3 V, VS_IN,LO = 0 V 100 - -
ns
VS_IN,HI = 2 V, VS_IN,LO = 1 V 300 - -
ISYNCH,LO Slave sink current VSYNCH = 2.9 V - 0.7 1 mA
VS_OUT,HI Master output amplitude ISOURCE = 4.5 mA 2 - - V
tS_OUT_PW Output pulse width SYNCH floating - 110 - ns
Protection
TSHDN
Thermal shutdown - - 150 -
°C
Hysteresis - - 30 -
1. Guaranteed by design.
Table 4. Electrical characteristics (continued)
Symbol Parameter Test conditions
Values
Unit
Min. Typ. Max.
Functional description A7985A
10/43 DocID023128 Rev 7
5 Functional description
The A7985A device is based on a “voltage mode”, constant frequency control. The output
voltage VOUT is sensed by the feedback pin (FB) compared to an internal reference (0.6 V)
providing an error signal that, compared to a fixed frequency sawtooth, controls the ON and
OFF time of the power switch.
The main internal blocks are shown in the block diagram in Figure 3. They are:
A fully integrated oscillator that provides sawtooth to modulate the duty cycle and the
synchronization signal. Its switching frequency can be adjusted by an external resistor.
The voltage and frequency feed-forward are implemented
Soft-start circuitry to limit inrush current during the startup phase
Voltage mode error amplifier
Pulse width modulator and the relative logic circuitry necessary to drive the internal
power switch
High-side driver for embedded P-channel power MOSFET switch
Peak current limit sensing block, to handle overload and short-circuit conditions
A voltage regulator and internal reference. It supplies internal circuitry and provides
a fixed internal reference
A voltage monitor circuitry (UVLO) that checks the input and internal voltages
A thermal shutdown block, to prevent thermal runaway.
Figure 3. Block diagram
PEAK
CURRENT
LIMIT
OSCILLATOR
S
R
Q
THERMAL
SHUTDOWN
SOFT-
START
EN
TRIMMING UVLO
0.6V
REGULATOR
&
BANDGAP
1.254V 3.3V
SYNCH
&
PHASE SHIFT
EN
FB
COMP
FSW GND SYNCH
OUT
VCC
DRIVER
E/A PWM
PEAK
CURRENT
LIMIT
OSCILLATOR
S
R
Q
THERMAL
SHUTDOWN
SOFT-
START
EN
TRIMMING UVLOUVLO
0.6V
REGULATOR
&
BANDGAP
REGULATOR
&
BANDGAP
1.254V 3.3V
SYNCH
&
PHASE SHIFT
EN
FB
COMP
FSW GND SYNCH
OUT
VCC
DRIVER
E/A PWM
DocID023128 Rev 7 11/43
A7985A Functional description
43
5.1 Oscillator and synchronization
Figure 4 shows the block diagram of the oscillator circuit. The internal oscillator provides
a constant frequency clock. Its frequency depends on the resistor externally connected to
the FSW pin. If the FSW pin is left floating, the frequency is 250 kHz; it can be increased as
shown in Figure 6 by an external resistor connected to ground.
To improve the line transient performance, keeping the PWM gain constant versus the input
voltage, the voltage feed-forward is implemented by changing the slope of the sawtooth
according to the input voltage change (see Figure 5.a).
The slope of the sawtooth also changes if the oscillator frequency is increased by the
external resistor. In this way, a frequency feed-forward is implemented (Figure 5.b) in order
to keep the PWM gain constant versus the switching frequency (see Section 6.4 on page 20
for PWM gain expression).
On the SYNCH pin the synchronization signal is generated. This signal has a phase shift of
180 ° with respect to the clock. This delay is useful when two devices are synchronized
connecting the SYNCH pin together. When SYNCH pins are connected, the device with the
higher oscillator frequency works as master, so the slave device switches at the frequency
of the master but with a delay of half a period. This minimizes the RMS current flowing
through the input capacitor (see the L5988D datasheet).
Figure 4. Oscillator circuit block diagram
The device can be synchronized to work at a higher frequency feeding an external clock
signal. The synchronization changes the sawtooth amplitude, changing the PWM gain
(Figure 5.c). This change must be taken into account when the loop stability is studied. To
minimize the change of the PWM gain, the free-running frequency should be set (with
a resistor on the FSW pin) only slightly lower than the external clock frequency. This pre-
adjusting of the frequency changes the sawtooth slope in order to render negligible the
truncation of sawtooth, due to the external synchronization.
Clock
Generator
Ramp
Generator
FSW
Sawtooth
Clock
Synchronization
SYNCH
Clock
Generator
Ramp
Generator
FSW
Sawtooth
ClockClock
Synchronization
SYNCH
Functional description A7985A
12/43 DocID023128 Rev 7
Figure 5. Sawtooth: voltage and frequency feed-forward; external synchronization
Figure 6. Oscillator frequency vs. the FSW pin resistor
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DocID023128 Rev 7 13/43
A7985A Functional description
43
where:
Equation 1
FSW is desired switching frequency.
5.2 Soft-start
Soft-start is essential to assure the correct and safe startup of the step-down converter. It
avoids inrush current surge and makes the output voltage increase monothonically.
The soft-start is performed by a staircase ramp on the non inverting input (VREF) of the error
amplifier. So the output voltage slew rate is:
Equation 2
where SRVREF is the slew rate of the non inverting input, while R1and R2 is the resistor
divider to regulate the output voltage (see Figure 7). The soft-start staircase consists of 64
steps of 9.5 mV each, from 0 V to 0.6 V. The time base of one step is of 32 clock cycles. So
the soft-start time and then the output voltage slew rate depend on the switching frequency.
Figure 7. Soft-start scheme
Soft-start time results:
Equation 3
For example, with a switching frequency of 250 kHz, the SSTIME is 8 ms.
RFSW
28.5 109
FSW 250 103
–
----------------------------------------- 3.23 103
–=
SROUT SRVREF 1R1
R2
--------+


=
SSTIME
32 64
Fsw
-----------------=
Functional description A7985A
14/43 DocID023128 Rev 7
5.3 Error amplifier and compensation
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to
perform the pulse width modulation. Its non inverting input is internally connected to a 0.6 V
voltage reference, while its inverting input (FB) and output (COMP) are externally available
for feedback and frequency compensation. In this device the error amplifier is a voltage
mode operational amplifier, so with high DC gain and low output impedance.
The uncompensated error amplifier characteristics are shown in Table 5.
In continuous conduction mode (CCM), the transfer function of the power section has two
poles due to the LC filter and one zero due to the ESR of the output capacitor. Different
kinds of compensation networks can be used depending on the ESR value of the output
capacitor. In case the zero introduced by the output capacitor helps to compensate the
double pole of the LC filter, a Type II compensation network can be used. Otherwise, a Type
III compensation network must be used (see Section 6.4 on page 20 for details of the
compensation network selection).
The methodology to compensate the loop is to introduce zeroes to obtain a safe phase
margin.
5.4 Overcurrent protection
The A7985A implements the overcurrent protection sensing current flowing through the
power MOSFET. Due to the noise created by the switching activity of the power MOSFET,
the current sensing is disabled during the initial phase of the conduction time. This avoids
an erroneous detection of a fault condition. This interval is generally known as “masking
time” or “blanking time”. The masking time is about 200 ns.
If the overcurrent limit is reached, the power MOSFET is turned off, implementing the pulse-
by-pulse overcurrent protection. Under an overcurrent condition, the device can skip turn-on
pulses in order to keep the output current constant and equal to the current limit. If, at the
end of the “masking time”, the current is higher than the overcurrent threshold, the power
MOSFET is turned off and one pulse is skipped. If, at the following switching-on, when the
“masking time” ends, the current is still higher than the overcurrent threshold, the device
skips two pulses. This mechanism is repeated and the device can skip up to seven pulses.
While, if at the end of the “masking time” the current is lower than the over current threshold,
the number of skipped cycles is decreased by one unit (see Figure 8).
So the overcurrent/short-circuit protection acts by switching off the power MOSFET and
reducing the switching frequency down to one eighth of the default switching frequency, in
order to keep constant the output current around the current limit.
Table 5. Uncompensated error amplifier characteristics
Parameter Value
Low frequency gain 100 dB
GBWP 4.5 MHz
Slew rate 7 V/s
Output voltage swing 0 to 3.3 V
Maximum source/sink current 17 mA/25 mA
DocID023128 Rev 7 15/43
A7985A Functional description
43
This kind of overcurrent protection is effective if the output current is limited. To prevent the
current from diverging, the current ripple in the inductor during the ON-time must not be
higher than the current ripple during the OFF-time. That is:
Equation 4
If the output voltage is shorted, VOUT 0, IOUT = ILIM, D/FSW = TON_MIN, (1-D)/FSW 1/FSW.
So from the above equation the maximum switching frequency that guarantees to limit the
current results:
Equation 5
With RDS(on) = 300 m, DRC = 0.08 , the worst condition is with VIN = 38 V, ILIM = 2.5 A;
the maximum frequency to keep the output current limited during the short-circuit results
74 kHz.
Based on the pulse-by-pulse mechanism, that reduces the switching frequency down to one
eighth, the maximum FSW, adjusted by the FSW pin, that assures a full effective output
current limitation is 74 kHz * 8 = 592 kHz.
If, with VIN = 38 V, the switching frequency is set higher than 592 kHz, during short-circuit
condition the system finds a different equilibrium with higher current. For example, with
FSW = 700 kHz and the output shorted to ground, the output current is limited around:
Equation 6
where FSW* is 700 kHz divided by eight.
VIN V–OUT RDSON IOUT
DCR IOUT
––
LF
SW
------------------------------------------------------------------------------------------------------------ DVOUT VFRDSON IOUT
DCR IOUT
++ +
LF
SW
----------------------------------------------------------------------------------------------------------- 1D–=
Functional description A7985A
16/43 DocID023128 Rev 7
Figure 8. Overcurrent protection
5.5 Enable function
The enable feature allows the device to be put into standby mode. With the EN pin lower
than 0.3 V, the device is disabled and the power consumption is reduced to less than 30A.
With the EN pin lower than 1.2 V, the device is enabled. If the EN pin is left floating, an
internal pull-down ensures that the voltage at the pin reaches the inhibit threshold and the
device is disabled. The pin is also VCC compatible.
5.6 Hysteretic thermal shutdown
The thermal shutdown block generates a signal that turns off the power stage if the junction
temperature goes above 150 °C. Once the junction temperature goes back to about 120 °C,
the device restarts in normal operation. The sensing element is very close to the PDMOS
area, so ensuring an accurate and fast temperature detection.
DocID023128 Rev 7 17/43
A7985A Application information
43
6 Application information
6.1 Input capacitor selection
The capacitor connected to the input must be capable of supporting the maximum input
operating voltage and the maximum RMS input current required by the device. The input
capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR,
affecting the overall system efficiency.
So the input capacitor must have an RMS current rating higher than the maximum RMS
input current and an ESR value compliant with the expected efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
Equation 7
where Io is the maximum DC output current, D is the duty cycle,
is the efficiency.
Considering = 1, this function has a maximum at D = 0.5 and it is equal to Io/2.
In a specific application the range of possible duty cycles must be considered in order to find
out the maximum RMS input current. The maximum and minimum duty cycles can be
calculated as:
Equation 8
and
Equation 9
where VF is the forward voltage on the freewheeling diode and VSW is voltage drop across
the internal PDMOS.
The peak-to-peak voltage across the input capacitor can be calculated as:
Equation 10
where ESR is the equivalent series resistance of the capacitor.
Given the physical dimension, ceramic capacitors can well meet the requirements of the
input filter sustaining a higher input RMS current than electrolytic/tantalum types.
VPP
IO
CIN FSW
------------------------- 1D
----–


DD
----1D–+ESR IO
+=
Application information A7985A
18/43 DocID023128 Rev 7
In this case, the equation of CIN as a function of the target VPP can be written as follows:
Equation 11
neglecting the small ESR of ceramic capacitors.
Considering = 1, this function has its maximum in D = 0.5, therefore, given the maximum
peak-to-peak input voltage (VPP_MAX), the minimum input capacitor (CIN_MIN) value is:
Equation 12
Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage in the order of 1%
of VINMAX.
In Table 6, some multi-layer ceramic capacitors suitable for this device are reported.
A ceramic bypass capacitor, as close to the VCC and GND pins as possible, so that
additional parasitic ESR and ESL are minimized, is suggested in order to prevent instability
on the output voltage due to noise. The value of the bypass capacitor can go from 100 nF to
1 µF.
6.2 Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the
minimum inductance value in order to have the expected current ripple must be selected.
The rule to fix the current ripple value is to have a ripple at 20% - 40% of the output current.
In continuous current mode (CCM), the inductance value can be calculated by the following
equation:
Equation 13
where TON is the conduction time of the internal high-side switch and TOFF is the conduction
time of the external diode [in CCM, FSW = 1/(TON + TOFF)]. The maximum current ripple, at
fixed VOUT
, is obtained at maximum TOFF
, that is at minimum duty cycle (see Section 6.1 to
calculate minimum duty). So by fixing IL = 20% to 30% of the maximum output current, the
minimum inductance value can be calculated:
Table 6. Input MLCC capacitors
Manufacturer Series Cap value (F) Rated voltage (V)
Taiyo Yuden
UMK325BJ106MM-T 10 50
GMK325BJ106MN-T 10 35
muRata GRM32ER71H475K 4.7 50
CIN
IO
VPP FSW
---------------------------1D
----–


DD
----1D–+=
CIN_MIN
IO
2V
PP_MAX FSW

------------------------------------------------=
IL
VIN VOUT
–
L
------------------------------TON
VOUT VF
+
L
----------------------------TOFF
==
DocID023128 Rev 7 19/43
A7985A Application information
43
Equation 14
where FSW is the switching frequency, 1/(TON + TOFF).
For example, for VOUT = 5 V, VIN = 24 V, IO = 2 A and FSW = 250 kHz, the minimum
inductance value to have IL= 30% of IO is about 28 H.
The peak current through the inductor is given by:
Equation 15
So if the inductor value decreases, then the peak current (that must be lower than the
minimum current limit of the device) increases. According to the maximum DC output
current for this product family (2 A), the higher the inductor value, the higher the average
output current that can be delivered, without triggering the overcurrent protection.
In Table 7 some inductor part numbers are listed.
6.3 Output capacitor selection
The current in the capacitor has a triangular waveform which generates a voltage ripple
across it. This ripple is due to the capacitive component (charge or discharge of the output
capacitor) and the resistive component (due to the voltage drop across its ESR). So the
output capacitor must be selected in order to have a voltage ripple compliant with the
application requirements.
The amount of the voltage ripple can be calculated starting from the current ripple obtained
by the inductor selection.
Equation 16
Usually the resistive component of the ripple is much higher than the capacitive one, if the
output capacitor adopted is not a multi-layer ceramic capacitor (MLCC) with very low ESR
value.
Table 7. Inductors
Manufacturer Series Inductor value (H) Saturation current (A)
Coilcraft
MSS1038 3.8 to 10 3.9 to 6.5
MSS1048 12 to 22 3.84 to 5.34
Wurth
PD Type L 8.2 to 15 3.75 to 6.25
PD Type M 2.2 to 4.7 4 to 6
SUMIDA
CDRH6D226/HP 1.5 to 3.3 3.6 to 5.2
CDR10D48MN 6.6 to 12 4.1 to 5.7
LMIN
VOUT VF
+
IMAX
----------------------------1D
MIN
–
FSW
-----------------------=
ILPKIO
IL
2
--------+=
VOUT ESR IMAX
IMAX
8C
OUT fSW

-------------------------------------+=
Application information A7985A
20/43 DocID023128 Rev 7
The output capacitor is important also for loop stability: it fixes the double LC filter pole and
the zero due to its ESR. In Section 6.4, how to consider its effect in the system stability is
illustrated.
For example, with VOUT = 5 V, VIN = 24 V, IL = 0.9 A (resulting by the inductor value), in
order to have a VOUT = 0.01 · VOUT
, if the multi-layer ceramic capacitors are adopted,
10 µF are needed and the ESR effect on the output voltage ripple can be neglected. In case
of not-negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into
account its ESR value. So, in the case of 330 µF with ESR = 70 mthe resistive
component of the drop dominates and the voltage ripple is 43 mV
The output capacitor is also important to sustain the output voltage when a load transient
with high slew rate is required by the load. When the load transient slew rate exceeds the
system bandwidth the output capacitor provides the current to the load. So if the high slew
rate load transient is required by the application, the output capacitor and system bandwidth
must be chosen in order to sustain the load transient.
In Table 8 below some capacitor series are listed.
6.4 Compensation network
The compensation network must assure stability and good dynamic performance. The loop
of the A7985A is based on the voltage mode control. The error amplifier is
a voltage operational amplifier with high bandwidth. So by selecting the compensation
network the E/A is considered as ideal, that is, its bandwidth is much larger than the system
one.
The transfer functions of the PWM modulator and the output LC filter are studied (see
Figure 10). The transfer function of the PWM modulator, from the error amplifier output
(COMP pin) to the OUT pin, results:
Equation 17
where VS is the sawtooth amplitude. As seen in Section 5.1 on page 11, the voltage feed-
forward generates a sawtooth amplitude directly proportional to the input voltage, that is:
Equation 18
Table 8. Output capacitors
Manufacturer Series Cap value (F) Rated voltage (V) ESR (m)
muRata
GRM32 22 to 100 6.3 to 25 < 5
GRM31 10 to 47 6.3 to 25 < 5
PANASONIC
ECJ 10 to 22 6.3 < 5
EEFCD 10 to 68 6.3 15 to 55
SANYO TPA/B/C 100 to 470 4 to 16 40 to 80
TDK C3225 22 to 100 6.3 < 5
GPW0
VIN
Vs
---------=
VSKV
IN
=
DocID023128 Rev 7 21/43
A7985A Application information
43
In this way the PWM modulator gain results constant and equal to:
Equation 19
The synchronization of the device with an external clock provided through the SYNCH pin
can modify the PWM modulator gain (see Section 5.1 on page 11 to understand how this
gain changes and how to keep it constant in spite of the external synchronization).
Figure 9. The error amplifier, the PWM modulator and the LC output filter
The transfer function on the LC filter is given by:
Equation 20
where:
Equation 21
Equation 22
As seen in Section 5.3 on page 14, two different kinds of network can compensate the loop.
In the two following paragraphs the guidelines to select the Type II and Type III
compensation network are illustrated.
GPW0
VIN
Vs
---------1
K
----18===
FB COMP
V
REF
E/A
PWM
V
S
OUT
V
CC
C
OUT
ESR
L
G
PW0
G
LC
FB COMP
V
REF
E/A
PWM
V
S
OUT
V
CC
C
OUT
ESR
L
G
PW0
G
LC
GLC s
1s
2fzESR
--------------------------+
1s
2QfLC
---------------------------- s
2fLC
-------------------


2
++
-------------------------------------------------------------------------=
fLC
1
2LC
OUT
1ESR
ROUT
---------------+
------------------------------------------------------------------------= fzESR
1
2ESR COUT

--------------------------------------------=
QROUT LC
OUT ROUT ESR+
LC
OUT ROUT ESR+
------------------------------------------------------------------------------------------ ROUT
VOUT
IOUT
--------------=,=
Application information A7985A
22/43 DocID023128 Rev 7
6.4.1 Type III compensation network
The methodology to stabilize the loop consists in placing two zeroes to compensate the
effect of the LC double pole, thereby increasing phase margin; then to place one pole in the
origin to minimize the DC error on the regulated output voltage; finally to place other poles
far from the zero dB frequency.
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency higher than the desired bandwidth (that is: 2ESR COUT < 1 / BW), the Type
III compensation network is needed. Multi-layer ceramic capacitors (MLCC) have very low
ESR (< 1 m), with very high frequency zero, so a Type III network is adopted to
compensate the loop.
In Figure 10, the Type III compensation network is shown. This network introduces two
zeroes (fZ1, fZ2) and three poles (fP0, fP1, fP2). They are expressed as:
Equation 23
Equation 24
Figure 10. Type III compensation network
fZ1
1
2C3R1R3
+
------------------------------------------------=fZ2
1
2R4C4

------------------------------=
fP0 0=fP1
1
2R3C3

------------------------------= fP2
1
2R4
C4C5
C4C5
+
--------------------
--------------------------------------------=
DocID023128 Rev 7 23/43
A7985A Application information
43
In Figure 11 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]
and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEIII(f)] are drawn.
Figure 11. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1. Choose a value for R1, usually between 1 k and 5 k.
2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 25
where K is the feed-forward constant and 1/K is equal to 18.
3. Calculate C4 by placing the zero at 50% of the output filter double pole frequency (fLC):
Equation 26
4. Calculate C5 by placing the second pole at four times the system bandwidth (BW):
Equation 27
5. Set also the first pole at four times the system bandwidth and also the second zero at
the output filter double pole:
Equation 28
R4
BW
fLC
----------KR
1
=
C4
1
R4fLC

---------------------------=
C5
C4
2R4C44BW1–
--------------------------------------------------------------=
Application information A7985A
24/43 DocID023128 Rev 7
The suggested maximum system bandwidth is equal to the switching frequency divided by
3.5 (FSW/3.5), so lower than 100 kHz if the FSW is set higher than 500 kHz.
For example, with VOUT = 5 V, VIN = 24 V, IO = 2 A, L = 22 H, COUT = 22 F, and
ESR < 1 m, the Type III compensation network is:
Equation 29
In Figure 12 the module and phase of the open loop gain is shown. The bandwidth is about
32 kHz and the phase margin is 51 °.
Figure 12. Open loop gain Bode diagram with ceramic output capacitor
R14.99k=R2680=R3270=R41.1k=C34.7nF=C447nF=C51pF=
DocID023128 Rev 7 25/43
A7985A Application information
43
6.4.2 Type II compensation network
If the equivalent series resistance (ESR) of the output capacitor introduces a zero with
a frequency lower than the desired bandwidth (that is: 2ESR COUT > 1 / BW), this zero
helps stabilize the loop. Electrolytic capacitors show not-negligible ESR (> 30 m), so with
this kind of output capacitor the Type II network combined with the zero of the ESR allows
the stabilizing of the loop.
In Figure 13 the Type II network is shown.
Figure 13. Type II compensation network
The singularities of the network are:
Equation 30
fZ1
1
2R4C4

------------------------------= fP0 0=fP1
1
2R4
C4C5
C4C5
+
--------------------
--------------------------------------------=
Application information A7985A
26/43 DocID023128 Rev 7
In Figure 14 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]
and the open loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)] are drawn.
Figure 14. Open loop gain: module Bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component
values can be summarized as follows:
1. Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4
and C5 not comparable with parasitic capacitance of the board.
2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:
Equation 31
where fESR is the ESR zero:
Equation 32
and VS is the sawtooth amplitude. The voltage feed-forward keeps the ratio VS/VIN constant.
3. Calculate C4 by placing the zero one decade below the output filter double pole:
Equation 33
4. Then calculate C3 in order to place the second pole at four times the system bandwidth
(BW):
Equation 34
R4
fESR
fLC
------------


2BW
fESR
------------VS
VIN
---------R1
=
fESR
1
2ESR COUT

--------------------------------------------=
C4
10
2R4fLC

-------------------------------=
C5
C4
2R4C44BW1–
--------------------------------------------------------------=
DocID023128 Rev 7 27/43
A7985A Application information
43
For example, with VOUT = 5 V, VIN = 24 V, IO = 2 A, L = 22 H, COUT = 330 F, and
ESR = 70 m the Type II compensation network is:
Equation 35
In Figure 15 the module and phase of the open loop gain is shown. The bandwidth is about
36 kHz and the phase margin is 53 °.
Figure 15. Open loop gain Bode diagram with electrolytic/tantalum output capacitor
R11.1k=R2150=R44.99k=C4180nF=C5180pF=
Application information A7985A
28/43 DocID023128 Rev 7
6.5 Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if the junction
temperature goes above 150 °C. The three different sources of losses within the device are:
a) conduction losses due to the not-negligible RDS(on) of the power switch; these are
equal to:
Equation 36
where D is the duty cycle of the application and the maximum RDS(on) overtemperature is
220 m. Note that the duty cycle is theoretically given by the ratio between VOUT and VIN,
but actually it is quite higher to compensate the losses of the regulator. So the conduction
losses increase compared with the ideal case.
b) switching losses due to power MOSFET turn-on and turn-off; these can be
calculated as:
Equation 37
where TRISE and TFALL are the overlap times of the voltage across the power switch (VDS)
and the current flowing into it during turn-on and turn-off phases, as shown in Figure 16.
TSW is the equivalent switching time. For this device the typical value for the equivalent
switching time is 40 ns.
c) Quiescent current losses, calculated as:
Equation 38
where IQ is the quiescent current (IQ = 2.4 mA).
The junction temperature TJ can be calculated as:
Equation 39
where TA is the ambient temperature and PTOT is the sum of the power losses just seen.
Rth(JA) is the equivalent thermal resistance junction to ambient of the device; it can be
calculated as the parallel of many paths of heat conduction from the junction to the ambient.
For this device the path through the exposed pad is the one conducting the largest amount
of heat. The Rth(JA) measured on the demonstration board described in the following
paragraph is about 40 °C/W for the HSOP8 package.
PON RDS on IOUT

2D=
PSW VIN IOUT
TRISE TFALL
+
2
-------------------------------------------Fsw VIN IOUT TSW FSW
==
PQVIN IQ
=
TJTARthJA PTOT
+=
DocID023128 Rev 7 29/43
A7985A Application information
43
Figure 16. Switching losses
6.6 Layout considerations
The PC board layout of the switching DC/DC regulator is very important to minimize the
noise injected in high impedance nodes and interference generated by the high switching
current loops.
In a step-down converter, the input loop (including the input capacitor, the power MOSFET
and the freewheeling diode) is the most critical one. This is due to the fact that the high
value pulsed current is flowing through it. In order to minimize the EMI, this loop must be as
short as possible.
The feedback pin (FB) connection to the external resistor divider is a high impedance node,
so the interference can be minimized by placing the routing of the feedback node as far as
possible from the high current paths. To reduce the pick-up noise, the resistor divider must
be placed very close to the device.
To filter the high frequency noise, a small bypass capacitor (220 nF -1 µF) can be added as
close as possible to the input voltage pin of the device.
Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal
resistance junction to ambient; so a large ground plane enhances the thermal performance
of the converter allowing high power conversion.
Application information A7985A
30/43 DocID023128 Rev 7
In Figure 17 a layout example is shown.
Figure 17. Layout example
DocID023128 Rev 7 31/43
A7985A Application information
43
6.7 Application circuit
In Figure 18 the demonstration board application circuit is shown.
Figure 18. Demonstration board application circuit
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Table 9. Component list
Reference Part number Description Manufacturer
C1 UMK325BJ106MM-T 10 F, 50 V Taiyo Yuden
C2 GRM32ER61E226KE15 22 F, 25 V muRata
C3 - 3.3 nF, 50 V -
C4 - 33 nF, 50 V -
C5 - 100 pF, 50 V -
C6 - 470 nF, 50 V -
R1 - 4.99 k, 1%, 0.1 W 0603 -
R2 - 1.1 k, 1%, 0.1 W 0603 -
R3 - 330 , 1%, 0.1 W 0603 -
R4 - 1.5 k, 1%, 0.1 W 0603 -
R5 - 150 k1%, 0.1 W 0603 -
D1 STPS3L40 3 A DC, 40 V STMicroelectronics
L1 MSS1038-103NL 10 H, 30%, 3.9 A, DCRMAX = 35 mCoilcraft
Application information A7985A
32/43 DocID023128 Rev 7
Figure 19. PCB layout: A7985A (component side)
Figure 20. PCB layout: A7985A (bottom side)
Figure 21. PCB layout: A7985A (front side)
DocID023128 Rev 7 33/43
A7985A Application information
43
Figure 22. Junction temperature vs. output
current at VIN = 24 V
Figure 23. Junction temperature vs. output
current at VIN = 12 V
V
OUT
=1.8V
V
OUT
=3.3V
V
OUT
=5V
HSOPVQFN
V
IN
=24V
F
SW
=250KHz
T
AMB
=25 C
V
OUT
=1.8V
V
OUT
=3.3V
V
OUT
=5V
HSOPVQFN
VIN=12V
FSW=250KHz
TAMB=25 C
Figure 24. Junction temperature vs. output
current at VIN = 5 V
Figure 25. Efficiency vs. output current
at VO = 1.8 V
V
OUT
=1.2V
V
OUT
=1.8V
V
OUT
=3.3V
HSOPVQFN
V
IN
=5V
F
SW
=250KHz
T
AMB
=25 C
40
45
50
55
60
65
70
75
80
85
0.100 0.600 1.100 1.600 2.100
Eff [%]
Io [A]
Vin=5V
Vin=12V
Vin=24V
Vo=1.8V
FSW=250kHz
Figure 26. Efficiency vs. output current
at VO =5V
Figure 27. Efficiency vs. output current
at VO = 3.3 V
60
65
70
75
80
85
90
95
0.100 0.600 1.100 1.600 2.100
Eff [%]
Io [A]
Vin=12V
Vin=18V
Vin=24V
Vo=5.0V
FSW=250kHz
50
55
60
65
70
75
80
85
90
95
0.100 0.600 1.100 1.600 2.100
Eff [%]
Io [A]
Vin=5V
Vin=12V
Vin=24V
Vo=3.3V
FSW=250kHz
Application information A7985A
34/43 DocID023128 Rev 7
Figure 28. Load regulation Figure 29. Line regulation
3.310
3.315
3.320
3.325
3.330
3.335
3.340
3.345
0.00 0.50 1.00 1.50 2.00
V
OUT
[V]
Io [A]
Vin=5V
Vin=12V
Vin=24V
3.3200
3.3250
3.3300
3.3350
3.3400
3.3450
3.3500
5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0
V
OUT
[V]
V
IN
[V]
Io=1A
Io=2A
Figure 30. Load transient: from 0.4 A to 2 A Figure 31. Soft-start
V
OUT
100mV/div
AC coupled
I
L
500mA/div
Time base 100us/div
V
IN
=24V
V
OUT
=3.3V
C
OUT
=47uF
L=10uH
F
SW
=520k
V
OUT
100mV/div
AC coupled
I
L
500mA/div
Time base 100us/div
V
IN
=24V
V
OUT
=3.3V
C
OUT
=47uF
L=10uH
F
SW
=520k
V
OUT
500mV/div
V
FB
200mV/div
I
L
500mA/div
Time base 1ms/div
Figure 32. Short-circuit behavior at VIN = 12 V Figure 33. Short-circuit behavior at VIN = 24 V
OUT
5V/div
I
L
1A/div
V
OUT
1V/div
SYNCH
5V/div
Timebase 10us/div
OUT
5V/div
I
L
0.5A/div
V
OUT
1V/div
SYNCH
5V/div
Timebase 10us/div
DocID023128 Rev 7 35/43
A7985A Application ideas
43
7 Application ideas
7.1 Positive buck-boost
The A7985A can implement the step-up/down converter with a positive output voltage.
Figure 34 shows the schematic: one power MOSFET and one Schottky diode are added to
the standard buck topology to provide a 12 V output voltage with input voltage from 4.5 V to
38 V.
Figure 34. Positive buck-boost regulator
The relationship between input and output voltage is:
Equation 40
so the duty cycle is:
Equation 41
The output voltage isn’t limited by the maximum operating voltage of the device (38 V),
because the output voltage is sensed only through the resistor divider. The external power
MOSFET maximum drain to source voltage, must be higher than output voltage; the
maximum gate to source voltage must be higher than the input voltage (in Figure 34, if VIN is
higher than 16 V, the gate must be protected through a Zener diode and resistor).
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Application ideas A7985A
36/43 DocID023128 Rev 7
The current flowing through the internal power MOSFET is transferred to the load only
during the OFF time, so according to the maximum DC switch current (2.0 A), the maximum
output current for the buck boost topology can be calculated from Equation 42.
Equation 42
where ISW is the average current in the embedded power MOSFET in the ON time.
To chose the right value of the inductor and to manage transient output current, which, for
a short time, can exceed the maximum output current calculated by Equation 42, also the
peak current in the power MOSFET must be calculated. The peak current, shown in
Equation 43, must be lower than the minimum current limit (2.5 A).
Equation 43
where r is defined as the ratio between the inductor current ripple and the inductor DC
current.
Therefore, in the buck boost topology the maximum output current depends on the
application conditions (firstly input and output voltage, secondly switching frequency and
inductor value).
In Figure 35 the maximum output current for the above configuration is depicted, varying the
input voltage from 4.5 V to 38 V.
The dashed line considers a more accurate estimation of the duty cycles given Equation 44,
where power losses across diodes, the external power MOSFET, and the internal power
MOSFET are taken into account.
ISW,PK
IOUT
1D–
------------- 1r
2
---+ 2.5A=
rVOUT
IOUT LF
SW

------------------------------------ 1D–
2
=
DocID023128 Rev 7 37/43
A7985A Application ideas
43
Figure 35. Maximum output current according to max. DC switch current (2.0 A):
VO = 12 V
Equation 44
where VD is the voltage drop across the diodes, VSW and VSWE across the internal and
external power MOSFET.
7.2 Inverting buck-boost
The A7985A device can implement the step-up/down converter with a negative output
voltage.
Figure 34 shows the schematic to regulate -5 V: no further external components are added
to the standard buck topology.
The relationship between input and output voltage is:
Equation 45
so the duty cycle is:
Equation 46
As in the positive one, in the inverting buck-boost the current flowing through the power
MOSFET is transferred to the load only during the OFF time. So according to the maximum
DC switch current (2.0 A), the maximum output current can be calculated from Equation 42,
where the duty cycle is given by Equation 46.
Application ideas A7985A
38/43 DocID023128 Rev 7
Figure 36. Inverting buck-boost regulator
The GND pin of the device is connected to the output voltage so, given the output voltage,
the input voltage range is limited by the maximum voltage the device can withstand across
VCC and GND (38 V). Therefore, if the output is -5 V, the input voltage can range from 4.5 V
to 33 V.
As in the positive buck-boost, the maximum output current according to application
conditions is shown in Figure 37. The dashed line considers a more accurate estimation of
the duty cycles given by Equation 47, where power losses across diodes and the internal
power MOSFET are taken into account.
Equation 47
Figure 37. Maximum output current according to switch max. peak current (2.0 A): VO = -5 V
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DocID023128 Rev 7 39/43
A7985A Package information
43
8 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
8.1 HSOP8 package information
Figure 38. HSOP8 package outline
Package information A7985A
40/43 DocID023128 Rev 7
Table 10. HSOP8 package mechanical data
Symbol
Dimensions
mm inch
Min. Typ. Max. Min. Typ. Max.
A - - 1.70 - - 0.0669
A1 0.00 - 0.10 - 0.00 0.0039
A2 1.25 - - 0.0492 - -
b 0.31 - 0.51 0.0122 - 0.0201
c 0.17 - 0.25 0.0067 - 0.0098
D 4.80 4.90 5.00 0.1890 0.1929 0.1969
D1 3 3.1 3.2 0.118 0.122 0.126
E 5.80 6.00 6.20 0.2283 - 0.2441
E1 3.80 3.90 4.00 0.1496 - 0.1575
E2 2.31 2.41 2.51 0.091 0.095 0.099
e - 1.27 - - - -
h 0.25 - 0.50 0.0098 - 0.0197
L 0.40 - 1.27 0.0157 - 0.0500
k0° (min), 8° (max.)
ccc - - 0.10 - - 0.0039
DocID023128 Rev 7 41/43
A7985A Ordering information
43
9 Ordering information
Table 11. Ordering information
Order code Package Packaging
A7985A HSOP8 Tube
A7985ATR HSOP8 Tape and reel
Revision history A7985A
42/43 DocID023128 Rev 7
10 Revision history
Table 12. Document revision history
Date Revision Changes
19-Apr-2012 1 Initial release.
08-Oct-2012 2 Document status promoted from preliminary data to production data.
In Section 5.6 changed temperature value from 130 to 120 °C.
04-Jul-2013 3 Updated values for VFB parameter in Table 4: Electrical
characteristics.
12-Aug-2013 4 Changed VFB parameter in Table 4: Electrical characteristics from
0.594 to 0.588.
17-Mar-2014 5
Updated Figure 34: Positive buck-boost regulator on page 36
(replaced by a new figure).
Updated Section 8: Package information on page 40 (reversed order
of Figure 38 and Tab le 1 0 , minor modifications).
Updated cross-references throughout document.
Minor modifications throughout document.
30-Sep-2016 6
Updated Table 1 on page 6 [replaced 0.63 V by 0.3 V (EN pin)].
Updated Figure 18 on page 31, Figure 36 on page 38 and Figure 38
on page 39 (replaced by new figures).
Updated Equation 43 on page 36 (replaced 3.7 A by 2.5 A).
Updated Table 10 on page 40 (replaced by new table).
Minor modifications throughout document.
14-Feb-2017 7
Updated Section : Features on page 1(replaced “Qualified following
AEC-Q100 requirements” by “AEC-Q100 qualified”).
Minor modifications throughout document.
DocID023128 Rev 7 43/43
A7985A
43
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