HD4074459 - Renesas Technology / Hitachi Semiconductor

Regarding the change of names mentioned in the document, such as Hitachi

Electric and Hitachi XX, to Renesas Technology Corp.

The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas

Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog

and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.)

Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand

names are mentioned in the document, these names have in fact all been changed to Renesas

Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and

corporate statement, no changes whatsoever have been made to the contents of the document, and

these changes do not constitute any alteration to the contents of the document itself.

Renesas Technology Home Page: http://www.renesas.com

Renesas Technology Corp.

Customer Support Dept.

April 1, 2003

To all our customers

Cautions

Keep safety first in your circuit designs!

1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better

and more reliable, but th ere is always the possibility that trouble may occur with them. Trouble with

semiconductors may lead to personal injury, fire or property damage.

Remember to give due consideration to safety when making your circuit designs, with appropriate

measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or

(iii) prevention against any malfunction or mishap.

Notes regar ding these materials

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contained therein.

HD404459 Series

Rev. 6.0

Sept. 1998

Description

The HD404459 Series is a member of the 4-bit HMCS400-series microcomputers with large-capacity

memory and architecture providing high program productivity. Each microcomputer has a 32-kHz

oscillator for clock, low-voltage (1.8 V) operating mode, and four low-power dissipation modes.

The HD404459 Series includes three chips: the HD404458 with an 8-kword ROM; the HD404459 with a

16-kword ROM; and the HD4074459 with a 16-kword PROM (ZTATTM version).

The HD4074459 is a PROM version (ZTATTM microcomputer). A program can be written to the PROM by

a PROM writer, thus dramatically shortening system development periods and turnaround time (ZTAT TM

versions are 27256-compatible).

ZTATTM: Zero Turn Around Time ZTAT is a trademark of Hitachi, Ltd.

Features

• 8,192-word × 10-bit ROM (HD404458)

16,384-word × 10-bit ROM (HD404459 and HD4074459)

• 512-digit × 4-bit RAM (HD404458)

768-digit × 4-bit RAM (HD404459 and HD4074459)

• 56 I/O pins, including seven input pins

• Four timer/counters

• 1-channel × 8-bit input capture circuit

• Three timer outputs (including two PWM outputs)

• Two event counter inputs (including one double-edge function)

• 8-bit clock-synchronous serial interface

• Eight wakeup inputs

• Four-channel voltage comparator (external or internal reference power supply can be selected)

• Built-in oscillators

 Main clock: 4-MHz ceramic or crystal oscillator (an external clock is also possible)

 Subclock: 32.768-kHz crystal

HD404459 Series

• Ten interrupt sources

 Five by external sources, including two double-edge function

 Five by internal sources

• Subroutine stack up to 16 levels, including interrupts

• Four low-power dissipation modes (transition time shortened)

 Stop mode

 Standby mode

 Watch mode

 Subactive mode (optional)

• One external input for transition from stop mode to active mode

• Instruction cycle time

 For HD404458/HD404459:

1, 2, 4, 8 µs (fOSC = 4 MHz; 1/4, 1/8, 1/16, 1/32 division ratio)

 For HD4074459:

1, 2, 4, 8 µs (fOSC = 4 MHz; 1/4, 1/8, 1/16, 1/32 division ratio; power voltage of 2.7 V or higher)

2, 4, 8, 16 µs (fOSC = 2 MHz; 1/4, 1/8, 1/16, 1/32 division ratio; power voltage of 2.2 V or higher)

• Two general operating conditions

 MCU or PROM mode for HD4074459

 MCU mode only for HD404458/HD404459

Ordering Information

Type Product Name Model Name ROM (Words) RAM (Digits) Package

Mask ROM HD404458 HD404458H 8,192 512 64-pin plastic

QFP (FP-64A)

HD404459 HD404459H 16,384 768 64-pin plastic

QFP (FP-64A)

ZTATTM HD4074459 HD4074459H 16,384 768 64-pin plastic

QFP (FP-64A)

HD404459 Series

Pin Arrangement

FP-64A

R53 (WU3)

R52 (WU2)

R51 (WU1)

R50 (WU0)

R43/SO

R42/SI

R41/SCK

R40/EVND

R33/EVNB

R32/TOD

R31/TOC

R30/TOB

R23

R22

R21

R20

RA0/COMP0

RA1/COMP1

RA2/COMP2

RA3/COMP3

TEST

OSC1

OSC2

GND

RESET

R93/VCref

R92

R91

R90

R83

R82

R81

R80

R73

R72

R71

R70

R63 (WU7)

R62 (WU6)

R61 (WU5)

R60 (WU4)

D10

D11/STOPC

VCC

R00/INT0

R01/INT1

R02/INT2

R03/INT3

R10

R11

R12

R13

HD404459 Series

Pin Description

Pin Number

Item Symbol FP-64A I/O Function

Power supply VCC 24 Power voltage

GND 8 Ground

Test TEST 5 I Used for factory testing only: Connect this pin to VCC

Reset RESET 11 I Resets the MCU

Oscillator OSC16 I Input/output pins for the internal oscillator circuit:

Connect them to a ceramic, crystal, or connect only

OSC1 to an external oscillator circuit

OSC27O

X1 10 I Used for a 32.768-kHz crystal for clock purposes. If

not to be used, fix the X1 pin to VCC and leave the X2

pin open.

X2 9 O

Ports D0–D912–21 I/O Input/output pins addressable by individual bits

D10, D11 22, 23 I Input pins addressable by individual bits

R00–R9325–64 I/O Input/output pins addressable in 4-bit units. The R93

port is an input-only pin.

RA0–RA31–4 I Input pins addressable in 4-bit units

Interrupts INT0, INT1,

INT2, INT3,

WU0–WU7

25–28, 45–52 I Input pins for external interrupts

Stop clear STOPC 23 I Input pin for transition from stop mode to active mode

Serial

interface SCK 42 I/O Serial clock input/output pin

SI 43 I Serial receive data input pin

SO 44 O Serial transmit data output pin

Timers TOB, TOC,

TOD 37–39 O Timer output pins

EVNB,

EVND 40, 41 I Event count input pins

Voltage

comparator COMP0 –

COMP3

1–4 I Analog input pins for voltage comparator

VCref 64 I Standard voltage pin for inputting the threshold

voltage of analog input pins

HD404459 Series

Block Diagram

System control

External

interrupt

Timer

Serial

interface

Compa-

rator

Internal data bus

Internal address bus

RAM

(512 × 4 bits)

(768 × 4 bits)

(2 bits)

(4 bits)

SPX

(4 bits)

(1 bit) CA

(1 bit)

(4 bits)

(10 bits)

(14 bits)

Instruction

decoder

CPU

RESET

TEST

STOPC

OSC

GND

TOC

EVND

TOD

INT

VCref

COMP

R0 portR1 portR2 portR3 portR4 port

R5 portR6 portR7 portR8 portR9 portRA port

SCK

ROM

(8,192 × 10 bits)

(16,384 × 10 bits)

D port

EVNB

TOB

SPY

(4 bits)

ALU

HD404459 Series

Memory Map

ROM Memory Map

See the ROM memory map of figure 1.

Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses

of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the

vector address.

Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a

subroutine in this area in response to the CAL instruction.

Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction.

Program Area ($0000–$1FFF for HD404458, $0000–$3FFF for HD404459/HD4074459): Used for

program coding.

Vector address

Zero-page subroutine

(64 words)

Pattern

(4,096 words)

HD404458 program

(8,192 words)

HD404459, HD4074459 program

(16,384 words)

$0000

$000F

$0010

$0FFF

$1000

$1FFF

$2000

$3FFF

$003F

$0040

$0000

$0001

$0002

$0003

$0004

$0005

$0006

$0007

$0008

$0009

$000A

$000B

$000C

$000D

$000E

$000F

JMPL instruction

(jump to RESET, STOPC routine)

JMPL instruction

(jump to INT routine)

JMPL instruction

(jump to timer D routine)

JMPL instruction

(jump to timer A, INT

routine)

JMPL instruction

(jump to timer B, INT

routine)

JMPL instruction

(jump to timer C, serial routine)

JMPL instruction

(jump to wakeup routine)

JMPL instruction

(jump to INT routine)

Figure 1 ROM Memory Map

HD404459 Series

RAM Memory Map

The HD404458 MCU contains a 512-digit × 4-bit RAM area. The HD404459 and HD4074459 MCUs

contain 768-digit × 4-bit RAM areas. Both of these RAM areas consist of a memory register area, a data

area, and a stack area. In addition, an interrupt control bits area, special register area, and register flag area

are mapped onto the same RAM memory space labeled as the RAM-mapped register area. See the RAM

memory map of figure 2.

RAM-Mapped Register Area ($000–$03F):

• Interrupt control bits area ($000–$003)

This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit

manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the

instructions can be used for each bit. For limitations on using the instructions, refer to figure 4.

• Special function register area ($004–$01F, $024–$03F)

This area is used as mode registers and data registers for external interrupts, serial interface,

timer/counters, and as data control registers for I/O ports. See figures 2 and 5. These registers can be

classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation

instructions cannot be used for these registers.

• Register flag area ($020–$023)

This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3).

These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and

TM/TMD). However, note that not all the instructions can be used for each bit. For limitations on using

the instructions, refer to figure 4.

Memory Register (MR) Area ($040–$04F): Consisting of 16 addresses, this area (MR0–MR15) can be

accessed by register-register instructions (LAMR and XMRA). See figure 6.

Data Area ($050–$1FF for HD404458, $050–$2FF for HD404459/HD4074459)

Stack Area ($3C0–$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and

carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a

16-level nesting subroutine stack in which one level requires four digits. See figure 6 for the data to be

saved and the save conditions.

The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can

only be restored by the RTNI instruction. Any unused space in this area can be used for data storage.

HD404459 Series

$000

$001

$002

$003

$004

$005

$006

$007

$008

$009

$00A

$00B

$00C

$00D

$00E

$00F

$010

$011

$012

$013

$014

$015

$016

$017

$018

$019

$01A

$01B

$01C

$01D

$01E

$01F

$020

$021

$022

$023

$024

$025

$026

$027

$028

$029

$02A

$02B

$02C

$02D

$02E

$02F

$030

$031

$032

$033

$034

$035

$036

$037

$038

$039

$03A

$03B

$03C

$03D

$03E

$03F

11 $00A

$00B

Timer read register B lower

Timer read register B upper (TRBL)

(TRBU) R

RTimer write register B lower

Timer write register B upper (TWBL)

(TWBU) W

15 $00E

$00F

Timer read register C lower

Timer read register C upper (TRCL)

(TRCU) R

RTimer write register C lower

Timer write register C upper (TWCL)

(TWCU) W

18 $011

$012

Timer read register D lower

Timer read register D upper (TRDL)

(TRDU) R

RTimer write register D lower

Timer write register D upper (TWDL)

(TWDU) W

512

768

960

$000

$040

$050

$200

$300

$3C0

1023 $3FF

Note: *Two registers are mapped

onto the same address

($00A, $00B, $00E, $00F,

$011, and $012).

R/W:

Read only

Write only

Read/write

Interrupt control bits area

Port mode register A

Serial mode register A

Serial data register lower

Serial data register upper

Timer mode register A

Timer mode register B1

Miscellaneous register

Timer mode register C1

Timer mode register D1

Timer mode register B2

Timer mode register C2

Timer mode register D2

Comparator control register

Comparator enable register

Wakeup select register

Port mode register B

Port mode register C

Detection edge select register 1

Detection edge select register 2

Serial mode register B

System clock select register 1

System clock select register 2

Port D

to D

DCR

Port D

to D

DCR

Port D

to D

DCR

Port R

DCR

Port R

DCR

Port R

DCR

Port R

DCR

Port R

DCR

Port R

DCR

Port R

DCR

Port R

DCR

Port R

DCR

Port R

DCR

(PMRA)

(SMRA)

(SRL)

(SRU)

(TMA)

(TMB1)

(TRBL/TWBL)

(TRBU/TWBU)

(MIS)

(TMC1)

(TRCL/TWCL)

(TRCU/TWCU)

(TMD1)

(TRDL/TWDL)

(TRDU/TWDU)

(TMB2)

(TMC2)

(TMD2)

(CCR)

(CER)

(WSR)

(PMRB)

(PMRC)

(ESR1)

(ESR2)

(SMRB)

(SSR1)

(SSR2)

(DCD0)

(DCD1)

(DCD2)

(DCR0)

(DCR1)

(DCR2)

(DCR3)

(DCR4)

(DCR5)

(DCR6)

(DCR7)

(DCR8)

(DCR9)

R/W

Not used

RAM-mapped register

Memory register (MR)

HD404458

Data (432 digits)

HD404459, HD4074459

Data (688 digits)

Stack (64 digits)

Not used

Timer B

Timer C

Timer D

Figure 2 RAM Memory Map

HD404459 Series

Bit 3 Bit 2 Bit 1 Bit 0

IMTD

(IM of timer D) IFTD

(IF of timer D) IM1

(IM of INT

)IF1

(IF of INT

)

IMTB

(IM of timer B) IFTB

(IF of timer B) IMTA

(IM of timer A) IFTA

(IF of timer A)

IMWU

(IM of wakeup) IMTC

(IM of timer C) IFTC

(IF of timer C)

$000

$001

$002

$003

Interrupt control bits area

IM0

(IM of INT

)IF0

(IF of INT

)RSP

(Reset SP bit) IE

(Interrupt

enable flag)

ICSF

(Input capture

status flag)

IM3

(IM of INT

)IF3

(IF of INT

)IM2

(IM of INT

)IF2

(IF of INT

)

IMS

(IM of serial) IFS

(IF of serial)

$020

$021

$022

$023

DTON

(Direct transfer

on flag)

CMSF

(Comparator

start flag)

WDON

(Watchdog

on flag)

LSON

(Low speed

on flag)

ICEF

(Input capture

error flag)

RAME

(RAM enable

flag) Not used

IF:

IM:

SP:

Interrupt request flag

Interrupt mask

Stack pointer

Bit 3 Bit 2 Bit 1 Bit 0

IFWU

(IF of wakeup)

Not used Not used

Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas

LSON

ICSF

ICEF

RAME

RSP

WDON

CMSF

Not used

DTON

SEM/SEMD REM/REMD TM/TMD

Allowed Allowed Allowed

Not executed Allowed Allowed

Not executed Allowed Inhibited

Allowed Not executed Inhibited

Allowed Inhibited Allowed

Not executed in active mode Allowed Allowed

Used in subactive mode

Not executed Not executed Inhibited

Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation.

The REM or REMD instuction must not be executed for CMSF during comparator

operation. DTON is always reset in active mode.

If the TM or TMD instruction is executed for the inhibited bits or non-existing bits,

the value in ST becomes undefined.

Figure 4 Usage Limitations of RAM Bit Manipulation Instructions

HD404459 Series

$000

$003

PMRA $004

SMRA $005

SRL $006

SRU $007

TMA $008

TMB1 $009

TRBL/TWBL $00A

TRBU/TWBU $00B

MIS $00C

TMC1 $00D

TRCL/TWCL$00E

TRCU/TWCU $00F

TMD1 $010

TRDL/TWDL $011

TRDU/TWDU $012

TMB2 $013

TMC2 $014

TMD2 $015

CCR $016

CER $017

WSR $018

$020

$023

PMRB $024

PMRC $025

ESR1 $026

ESR2 $027

SMRB $028

SSR1 $029

SSR2 $02A

DCD0 $02C

DCD1 $02D

DCD2 $02E

DCR0 $030

DCR1 $031

DCR2 $032

DCR3 $033

DCR4 $034

DCR5 $035

DCR6 $036

DCR7 $037

DCR8 $038

DCR9 $039

$03F

Not used

Interrupt control bits area

/SI R4

/SO

/SCK Serial transmit clock speed selection

Serial data register (lower digit)

Serial data register (upper digit)

Timer-A/timer-base

Auto-reload on/off Clock source selection (timer A)

Clock source selection (timer B)

Timer B register (lower digit)

Timer B register (upper digit)

Pull-up MOS control

Auto-reload on/off

SO PMOS control Interrupt frame period selection

Clock source selection (timer C)

Timer C register (lower digit)

Timer C register (upper digit)

Clock source selection (timer D)

Timer D register (lower digit)

Timer D register (upper digit) Timer B output mode selection

Timer C output mode selection

Timer D output mode selection

Internal reference voltage level selection

Voltage comparison result

enable WU

to WU

enable WU

to WU

enable

/INT

/STOPC R4

/EVND R3

/EVNB

INT

detection edge selection

EVND detection edge selection INT

detection edge selection

SO output level control in idle states

32-kHz oscillation sampling selection

Serial clock source selection

32-kHz oscillation stop

32-kHz oscillation division ratio selection

OSC division ratio selection

Port D3 DCR

Port D7 DCR Port D2 DCR

Port D6 DCR Port D1 DCR

Port D5 DCR

Port D9 DCR

Port D0 DCR

Port D4 DCR

Port D8 DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R8

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R8

DCR

Port R9

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R8

DCR

Port R9

DCR

Port R0

DCR

Port R1

DCR

Port R2

DCR

Port R3

DCR

Port R4

DCR

Port R5

DCR

Port R6

DCR

Port R7

DCR

Port R8

DCR

Port R9

DCR

Not used Not used

Not used

Not used Not used

Not used

Not usedNot used

Not used

Reference power supply selection

COMP

to COMP

selection

Bit 3 Bit 2 Bit 1 Bit 0

Input capture selection

Figure 5 Special Function Register Area

HD404459 Series

Memory registers

$040

$041

$042

$043

$044

$045

$046

$047

$048

$049

$04A

$04B

$04C

$04D

$04E

$04F

960 $3C0

1023 $3FF

MR(0)

MR(1)

MR(2)

MR(3)

MR(4)

MR(5)

MR(6)

MR(7)

MR(8)

MR(9)

Level 16

Level 15

Level 14

Level 13

Level 12

Level 11

Level 10

Level 9

Level 8

Level 7

Level 6

Level 5

Level 4

Level 3

Level 2

Level 1

MR(10)

MR(11)

MR(12)

MR(13)

MR(14)

MR(15)

Bit 3 Bit 2 Bit 1 Bit 0

$3FC

$3FD

$3FE

$3FF

1020

1021

1022

1023

Stack area

PC –PC :

ST: Status flag

CA: Carry flag

Program counter

13 0

Figure 6 Configuration of Memory Registers, Stack Area, and Stack Position

HD404459 Series

Functional Description

Registers and Flags

The MCU has nine registers and two flags for CPU operations (figure 7).

(B)

(A)

(W)

(X)

(Y)

(SPX)

(SPY)

(CA)

(ST)

(PC)

(SP)

1111

Accumulator

B register

W register

X register

Y register

SPX register

SPY register

Carry

Status

Program counter

Initial value: 0,

no R/W

Stack pointer

Initial value: $3FF, no R/W

Initial value: Undefined, R/W

Initial value: 1, no R/W

Figure 7 Registers and Flags

Accumulator (A), B Register (B): Four-bit registers used to hold the results from the arithmetic logic unit

(ALU) and transfer data between memory, I/O, and other registers.

W Register (W), X Register (X), Y Register (Y): Two-bit (W) and four-bit (X and Y) registers used for

indirect RAM addressing. The Y register is also used for D-port addressing.

HD404459 Series

SPX Register (SPX), SPY Register (SPY): Four-bit registers used to supplement the X and Y registers.

Carry Flag (CA): One-bit flag that stores any ALU overflow generated by an arithmetic operation. CA is

affected by the SEC, REC, ROTL, and ROTR instructions. A carry is pushed onto the stack during an

interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.

Status Flag (ST): One-bit flag that latches any overflow generated by an arithmetic or compare instruction,

not-zero decision from the ALU, or result of a bit test. ST is used as a branch condition of the BR, BRL,

CAL, and CALL instructions. The contents of ST remain unchanged until the next arithmetic, compare, or

bit test instruction is executed, but become 1 after the BR, BRL, CAL, or CALL instruction is read,

regardless of whether the instruction is executed or skipped. The contents of ST are pushed onto the stack

during an interrupt and popped from the stack by the RTNI instruction—but not by the RTN instruction.

Program Counter (PC): 14-bit binary counter that points to the ROM address of the instruction being

executed.

Stack Pointer (SP): Ten-bit pointer that contains the address of the stack area to be used next. The SP is

initialized to $3FF by MCU reset. It is decremented by 4 when data is pushed onto the stack, and

incremented by 4 when data is popped from the stack. The top four bits of the SP are fixed at 1111, so a

stack can be used up to 16 levels.

The SP can be initialized to $3FF also by resetting the RSP bit with the REM or REMD instruction.

Reset

The MCU is reset by inputting a high-level voltage to the RESET pin. At power-on or when stop mode is

cancelled, RESET must be high for at least one tRC to enable the oscillator to stabilize. During operation,

RESET must be high for at least two instruction cycles.

See table 1 for initial values after MCU reset.

Interrupts

The MCU has 10 interrupt sources: four external signals (INT0, I NT1, INT2, INT3), four timer/counters

(timers A, B, C, and D), serial interface, and wakeup.

An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt

source, and an interrupt enable flag (IE) controls the entire interrupt process.

Some vector addresses are shared by two different interrupts. They are timer A and INT2, timer B and INT3,

timer C and serial interface. So the type of request that has occurred must be checked at the beginning of

interrupt processing.

Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are

reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions.

The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE)

and the IF to 0 and the interrupt mask (IM) to 1.

HD404459 Series

Refer to figure 8 for the block diagram of the interrupt control circuit, table 2 for interrupt priorities and

vector addresses, and table 3 for interrupt processing conditions for the 10 interrupt sources.

An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the

interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to

that interrupt source.

For the interrupt processing sequence, see figure 9, and figure 10 for an interrupt processing flowchart.

After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset

in the second cycle, the carry, status, and program counter values are pushed onto the stack during the

second and third cycles, and the program jumps to the vector address to execute the instruction in the third

cycle.

Program the JMPL instruction at each vector address, to branch the program to the start address of the

interrupt program, and reset the IF by a software instruction within the interrupt program.

HD404459 Series

Table 1 Initial Values After MCU Reset

Item Abbr. Initial

Value Contents

Program counter (PC) $0000 Indicates program execution point from start

address of ROM area

Status flag (ST) 1 Enables conditional branching

Stack pointer (SP) $3FF Stack level 0

Interrupt

flags/mask Interrupt enable flag (IE) 0 Inhibits all interrupts

Interrupt request flag (IF) 0 Indicates there is no interrupt request

Interrupt mask (IM) 1 Prevents (masks) interrupt requests

I/O Port data register (PDR) All bits 1 Enables output at level 1

Data control register (DCD0,

DCD1) All bits 0 Turns output buffer off (to high impedance)

(DCD2) - - 00

(DCR0–

DCR8) All bits 0

(DCR9) - 000

Port mode register A (PMRA) - - 00 Refer to description of port mode register A

Port mode register B (PMRB) 0000 Refer to description of port mode register B

Port mode register C bits

2, 1, 0 (PMRC2,

PMRC1,

PMRC0)

- 000 Refer to description of port mode register C

Detection edge select

Timers/

counters,

serial

interface

Timer mode register A (TMA) 0000 Refer to description of timer mode register A

Timer mode register B1 (TMB1) 0000 Refer to description of timer mode register B1

Timer mode register B2 (TMB2) - - 00 Refer to description of timer mode register B2

Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1

Timer mode register C2 (TMC2) - 000 Refer to description of timer mode register C2

Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1

Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2

Serial mode register A (SMRA) 0000 Refer to description of serial mode register A

Serial mode register B (SMRB) - - 00 Refer to description of serial mode register B

HD404459 Series

Item Abbr. Initial

Value Contents

Timers/

counters,

serial

interface

Prescaler S (PSS) $000 —

Prescaler W (PSW) $00 —

Timer counter A (TCA) $00 —

Timer counter B (TCB) $00 —

Timer counter C (TCC) $00 —

Timer counter D (TCD) $00 —

Timer write register B (TWBU,

TWBL) $X0 —

Timer write register C (TWCU,

TWCL) $X0 —

Timer write register D (TWDU,

TWDL) $X0 —

Octal counter 000 —

I/O Wakeup set register (WSR) 0000 —

Voltage

comparator Comparator enable

Comparator control

Bit register Low speed on flag (LSON) 0 Refer to description of operating modes

Watchdog timer on flag (WDON) 0 Refer to description of timer C

Comparator start flag (CMSF) 0 Refer to description of voltage comparator

Direct transfer on flag (DTON) 0 Refer to description of operating modes

Input capture status flag (ICSF) 0 Refer to description of timer D

Input capture error flag (ICEF) 0 Refer to description of timer D

Others Miscellaneous register (MIS) 0000 Refer to description of operating modes, and

oscillator circuit

System clock select

SSR11) 00 Refer to description of operating modes, and

oscillator circuit

System clock select

Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table.

2. X indicates invalid value. - indicates that the bit does not exist.

HD404459 Series

Item Abbr.

Status After

Cancellation of Stop

Mode by STOPC Input

Status After

Cancellation of Stop

Mode by MCU Reset Status After all Other

Types of Reset

Carry flag (CA) Pre-stop-mode values are not guaranteed;

values must be initialized by program Pre-MCU-reset values

are not guaranteed;

values must be

initialized by program

Accumulator (A)

B register (B)

W register (W)

X/SPX register (X/SPX)

Y/SPY register (Y/SPY)

Serial data register (SRL, SRU)

RAM Pre-stop-mode values are retained

RAM enable flag (RAME) 1 0 0

Port mode register

C bit 2 (PMRC) Pre-stop-mode values

are retained 00

System clock select

register1 bit 3 (SSR13)

Table 2 Vector Addresses and Interrupt Priorities

Reset/Interrupt Priority Vector Address

RESET, STOPC*— $0000

INT01 $0002

INT12 $0004

Timer D 3 $0006

Timer A, INT24 $0008

Timer B, INT35 $000A

Timer C, Serial 6 $000C

Wakeup 7 $000E

Note: *The STOPC interrupt request is valid only in stop mode.

HD404459 Series

$000,2

IF0

$000,3

IM0

INT0 interrupt

$001,0

IF1

$001,1

IM1

INT1 interrupt

$001,2

IFTD

$001,3

IMTD

Timer D interrupt

$002,0

IFTA

$002,1

IMTA

Timer A interrupt

$002,2

IFTB

$002,3

IMTB

Timer B interrupt

$003,0

IFTC

$003,1

IMTC

Timer C interrupt

$003,2

IFWU

$003,3

IMWU

Wakeup interrupt

$022,0

$022,1

IM2

INT2 interrupt

$022,2

$022,3

IM3

INT3 interrupt

$023,0

IFS

$023,1

IMS

Serial interrupt

$000,0

IF2

IF3

Priority control PLA

Vector

address

Sequence control

• Push PC/CA/ST

• Reset IE

• Jump to vector

address

Figure 8 Interrupt Control Circuit

HD404459 Series

Table 3 Interrupt Processing and Activation Conditions

Interrupt Source

Interrupt

Control Bit INT0INT1Timer D Timer A or

INT2

Timer B or

INT3

Timer C or

Serial Wakeup

IE 1111111

IF0 · IM0 1000000

IF1 · IM1 *100000

IFTD · IMTD **10000

IFTA · IMTA

+ IF2 · IM2

***1000

IFTB · IMTB

+ IF3 · IM3

****100

IFTC · IMTC

+ IFS · IMS

*****10

IFWU · IMWU ******1

Note: Bits marked by * can be either 0 or 1. Their values have no effect on operation.

Instruction cycles

123456

Instruction

execution*

IE reset

Interrupt

acceptance

Execution of JMPL

instruction at vector address

Execution of

instruction at

start address

of interrupt

routine

Vector address

generation

Note: *The stack is accessed and the IE reset after the instruction

is executed, even if it is a two-cycle instruction.

Stacking

Figure 9 Interrupt Processing Sequence

HD404459 Series

Power on

RESET = 1?

Reset MCU

Interrupt

request?

Execute instruction

PC ←(PC) + 1

PC ←$0002

PC ←$0004

PC ←$0006

PC ←$0008

PC ←$000A

PC ←$000E

IE = 1?

Interrupt accept

IE 0

Stack (PC)

Stack (CA)

Stack (ST)

←

INT

interrupt?

INT

interrupt?

Timer D

interrupt?

Timer-A/INT

interrupt?

Yes

←

(wakeup interrupt)

PC ←$000C Timer-C/serial

interrupt?

Yes

Timer-B/INT

interrupt?

Figure 10 Interrupt Processing Flowchart

HD404459 Series

Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt

processing and set by the RTNI instruction. Refer to table 4.

Table 4 Interrupt Enable Flag (IE: $000, Bit 0)

IE Interrupt Enabled/Disabled

0 Disabled

1 Enabled

External Interrupts (INT0 , INT1, INT2, INT3, WU0–WU7): Five external interrupt signals.

External Interrupt Request Flags (IF0, IF1, IF2, IF3, IFWU: $000, $001, $003, $022): IF0, IF1, and

IFWU are set at the falling edge of input signals, and IF2 and IF3 are set at the rising or falling edge or both

rising and falling edges of input signals (table 5). INT2 and INT3 interrupt edges are selected by the

detection edge select register (ESR1: $026) (figure 11).

Table 5 External Interrupt Request Flags (IF0–IF3, IFWU: $000, $001, $003, $022)

IF0–IF3, IFWU Interrupt Request

0No

1 Yes

Bit

Initial value

Read/Write

Bit name

ESR13

ESR12

ESR10

ESR11

Detection edge selection register 1 (ESR1: $026)

ESR11

ESR10

INT2 detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection*

ESR13

ESR12

INT3 detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection*

Note: *Both falling and rising edges are detected.

Figure 11 Detection Edge Selection Register 1 (ESR1)

HD404459 Series

External Interrupt Masks (IM0, IM1, IM2, IM3, IMWU: $000, $001, $003, $022): Prevent (mask)

interrupt requests caused by the corresponding external interrupt request flags (table 6).

Table 6 External Interrupt Masks (IM0–1M3, IMWU: $000, $001, $003, $022)

IM0–IM3, IMWU Interrupt Request

0 Enabled

1 Disabled (masked)

Timer A Interrupt Request Flag (IFTA: $002, Bit 0): Set by overflow output from timer A (table 7).

Table 7 Timer A Interrupt Request Flag (IFTA: $002, Bit 0)

IFTA Interrupt Request

0No

1 Yes

Timer A Interrupt Mask (IMTA: $002, Bit 1): Prevents (masks) an interrupt request caused by the timer

A interrupt request flag (table 8).

Table 8 Timer A Interrupt Mask (IMTA: $002, Bit 1)

IMTA Interrupt Request

0 Enabled

1 Disabled (masked)

Timer B Interrupt Request Flag (IFTB: $002, Bit 2): Set by overflow output from timer B (table 9).

Table 9 Timer B Interrupt Request Flag (IFTB: $002, Bit 2)

IFTB Interrupt Request

0No

1 Yes

Timer B Interrupt Mask (IMTB: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer

B interrupt request flag (table 10).

Table 10 Timer B Interrupt Mask (IMTB: $002, Bit 3)

IMTB Interrupt Request

0 Enabled

1 Disabled (masked)

HD404459 Series

Timer C Interrupt Request Flag (IFTC: $003, Bit 0): Set by overflow output from timer C (table 11).

Table 11 Timer C Interrupt Request Flag (IFTC: $003, Bit 0)

IFTC Interrupt Request

0No

1 Yes

Timer C Interrupt Mask (IMTC: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer

C interrupt request flag (table 12).

Table 12 Timer C Interrupt Mask (IMTC: $003, Bit 1)

IMTC Interrupt Request

0 Enabled

1 Disabled (masked)

Timer D Interrupt Request Flag (IFTD: $001, Bit 2): Set by overflow output from timer D, or by the

rising or falling edge of signals input to EVND when the input capture function is used (table 13).

Table 13 Timer D Interrupt Request Flag (IFTD: $001, Bit 2)

IFTD Interrupt Request

0No

1 Yes

Timer D Interrupt Mask (IMTD: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer

D interrupt request flag (table 14).

Table 14 Timer D Interrupt Mask (IMTD: $001, Bit 3)

IMTD Interrupt Request

0 Enabled

1 Disabled (masked)

HD404459 Series

Serial Interrupt Request Flags (IFS: $023, Bit 0): Set when data transfer is completed or when data

transfer is suspended (table 15).

Table 15 Serial Interrupt Request Flag (IFS: $023, Bit 0)

IFS Interrupt Request

0No

1 Yes

Serial Interrupt Mask (IMS: $023, Bit 1): Prevents (masks) an interrupt request caused by the serial

interrupt request flag (table 16).

Table 16 Serial Interrupt Mask (IMS: $023, Bit 1)

IMS Interrupt Request

0 Enabled

1 Disabled (masked)

Wakeup Interrupt Request Flag (IFWU: $003, Bit 2): Set by the falling edge of signals input to wakeup

(table 17).

Table 17 Wakeup Interrupt Request Flag (IFWU: $003, Bit 2)

IFWU Interrupt Request

0No

1 Yes

Wakeup Interrupt Mask (IMWU: $003, Bit 3): Prevents (masks) an interrupt request caused by the

wakeup interrupt request flag (table 18).

Table 18 Wakeup Interrupt Mask (IMWU: $003, Bit 3)

IMWU Interrupt Request

0 Enabled

1 Disabled (masked)

HD404459 Series

Wakeup Function: Detects the falling edge of wakeup input signals and sets the wakeup interrupt request

flag (IFWU: $003, bit 2). Refer to figure 12 for a block diagram showing the wakeup interrupt. The wakeup

select register (WSR: $018) can select from one to eight wakeup inputs (WU0–WU7) (figure 13). The

wakeup function can operate in any mode other than stop mode. When the wakeup interrupt is received, the

CPU generates an independent vector address ($000E).

Note: The wakeup select register (WSR: $018) controls whether the wakeup input is to be valid or

invalid, but it can not switch the pin inputs between the R ports and wakeup. When using the pins

only as R ports, nullify wakeup input or set the wakeup interrupt mask (IMWU: $003, bit 3).

R50/WU0

R51/WU1

R52/WU2

R53/WU3

R60/WU4

R61/WU5

R62/WU6

R63/WU7

Internal bus

Falling-edge

detection Wakeup

interrupt

request flag

WSR (4 bits)

Wakeup selection

Figure 12 Wakeup Interrupt

HD404459 Series

Bit

Initial value

Read/Write

Bit name

WSR3

WSR2

WSR0

WSR1

WSR0

WU0 to WU3 control

Invalid

Valid

WSR1

WU4 to WU5 control

Invalid

Valid

WSR2

WU6 control

Invalid

Valid

WSR3

WU7 control

Invalid

Valid

Figure 13 Wakeup Select Register (WSR)

HD404459 Series

Operating Modes

The MCU has five operating modes (table 19). Refer to tables 20 and 21 for the operations in each mode,

and figure 14 for the transitions between operating modes.

Active Mode: All MCU functions operate according to the clock generated by the system oscillators OSC1

and OSC2.

Table 19 Operating Modes and Clock Status

Mode Name

Active Standby Stop Watch Subactive*2

Activation method RESET

cancellation,

interrupt

request, STOPC

cancellation in

stop mode,

STOP/SBY

instruction in

subactive mode

(when direct

transfer is

selected)

SBY instruction STOP

instruction when

TMA3 = 0

STOP

instruction when

TMA3 = 1

INT0, timer A or

wakeup interrupt

request from

watch mode

Status System

oscillator OP OP Stopped Stopped Stopped

Subsystem

oscillator OP OP OP*1OP OP

Cancellation

method RESET input,

STOP/SBY

instruction

RESET input,

interrupt request RESET input,

STOPC input in

stop mode

RESET input,

INT0, timer A or

wakeup interrupt

request

RESET input,

STOP/SBY

instruction

Note: OP implies in operation

1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select

2. Subactive mode is an optional function; specify it on the function option list.

HD404459 Series

Table 20 Operations in Low-Power Dissipation Modes

Function Stop Mode Watch Mode Standby Mode Subactive Mode*2

CPU Reset Retained Retained OP

RAM Retained Retained Retained OP

Timer A Reset OP OP OP

Timer B Reset Stopped OP OP

Timer C Reset Stopped OP OP

Timer D Reset Stopped OP OP

SCI Reset Stopped*3OP OP

Comparator Reset Stopped OP Stopped

I/O Reset*1Retained Retained OP

Note: OP implies in operation

1. Output pins are at high impedance.

2. Subactive mode is an optional function to be specified on the function option list.

3. Transmission/reception is activated if a clock is input in external clock mode. However, all

interrupts stop.

Table 21 I/O Status in Low-Power Dissipation Modes

Output Input

Standby Mode,

Watch Mode Stop Mode Active Mode,

Subactive Mode

D0–D9Retained High impedance Input enabled

D10–D11 — — Input enabled

R0–R8

R90, R91, R92

Retained or output of

peripheral functions High impedance Input enabled

R93, RA — — Input enabled

HD404459 Series

Reset by

RESET input or

by watchdog timer

fOSC:

fX:

øCPU:

øCLK:

øPER:

Oscillate

Stop

fcyc

fOSC:

fX:

øCPU:

øCLK:

øPER:

Oscillate

Stop

fcyc

fOSC:

fX:

øCPU:

øCLK:

øPER:

Oscillate

fcyc

fOSC:

fX:

øCPU:

øCLK:

øPER:

Oscillate

fcyc

fOSC:

fX:

øCPU:

øCLK:

øPER:

Stop

Oscillate

fSUB

fOSC:

fX:

øCPU:

øCLK:

øPER:

Stop

fOSC:

fX:

øCPU:

øCLK:

øPER:

Stop

Oscillate

Stop

fOSC:

fX:

øCPU:

øCLK:

øPER:

Stop

Oscillate

Stop

Standby mode

Stop mode

(TMA3 = 0, SSR13 = 1)

Watch mode

Subactive

mode

(TMA3 = 1) (TMA3 = 1, LSON = 0)

(TMA3 = 1, LSON = 1)

SBY

Interrupt

SBY

Interrupt

STOP

1. Interrupt source

2. STOP/SBY (DTON = 1, LSON = 0)

3. STOP/SBY (DTON = 0, LSON = 0)

4. STOP/SBY (DTON = Don’t care, LSON = 1)

fOSC:

fX:

fcyc:

fSUB:

fW:

LSON:

DTON:

Main oscillation frequency

Suboscillation frequency

for time-base

fOSC/4, fOSC/8, fOSC/16,

fOSC/32 (software

selectable)

fX/8 or fX/4

(software selectable)

fX/8

System clock

Clock for time-base

Clock for other

peripheral functions

Low speed on flag

Direct transfer on flag

Active

mode

Notes:

øCPU:

øCLK:

øPER:

fOSC:

fX:

øCPU:

øCLK:

øPER:

Stop

Oscillate

Stop

(TMA3 = 0, SSR13 = 0)

RESET1 RESET2

RAME = 0 RAME = 1

(TMA3 = 0)

STOPC

STOP

INT0, WU0 to

WU7, timer A

INT0, WU0 to

WU7, timer A*1

STOPC

STOP

Figure 14 MCU Status Transitions

HD404459 Series

Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction

execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the

D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and

serial interface continue to operate. The power dissipation in this mode is lower than in active mode since

the CPU halts.

The MCU enters standby mode when the SBY instruction is executed in active mode.

Standby mode is terminated by RESET input or an interrupt request. If it is terminated by RESET, the

MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next

instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is

0, the interrupt request is left pending and normal instruction execution continues. See figure 15 for the

flowchart of operation in standby mode.

Standby

Oscillator: Active

Peripheral clocks: Active

All other clocks: Stop

Yes No

Yes

(SBY

only)

Watch

Oscillator: Stop

Suboscillator: Active

Peripheral clocks: Stop

All other clocks: Stop

Restart

processor clocks

Reset MCU Execute

next instruction Accept interrupt

Restart

processor clocks

Yes

RESET = 1?

IF0 • IM0 = 1?

IF1 • IM1 = 1?

IFTD • IMTD

= 1?

IFTA •

IMTA + IF2 •

IM2 = 1?

IFTB •

IMTB + IF3 •

IM3 = 1?

Yes

Stop

Oscillator: Stop

Suboscillator: Active/Stop

Peripheral clocks: Stop

All other clocks: Stop

RESET = 1?

STOPC = 0?

RAME = 1 RAME = 0

Yes

(SBY

only) (SBY

only)

Execute

next instruction

IF = 1,

IM = 0, and

IE = 1?

Note:

The INT

interrupt

is valid only by

standby mode

cancellation.

IFWU • IMWU

= 1?

IFTC •

IMTC + IFS •

IMS = 1?

Figure 15 MCU Operation Flowchart

HD404459 Series

Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power

dissipation in this mode is the least of all modes. The OSC1 and OSC2 oscillator stops. Operation of the X1

and X2 oscillator can be selected by setting bit 3 of the system clock select register (SSR1: $029; operating:

SSR13 = 0, stop: SSR13 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is executed in

active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 40).

Stop mode is terminated by RESET input or STOPC input (figure 16). RESET or STOPC must be applied

for at least one tRC to stabilize oscillation (refer to the AC Characteristics section). When the MCU restarts

after stop mode is cancelled, all RAM contents before entering stop mode are retained, but the accuracy of

the contents of the accumulator, B register, W register, X/SPX register, Y/SPY register, carry flag, and

serial data register cannot be guaranteed.













,













Stop mode

Oscillator

Internal

clock

STOP instruction execution tres ≥tRC (stabilization period)

tres







RESET

STOPC

Figure 16 Timing of Stop Mode Cancellation

Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator operate but

other function operations stop. Therefore, the power dissipation in this mode is the second least to stop

mode, and is also convenient when only clock display is used. In this mode, the OSC1 and OSC2 oscillator

stops, but the X1 and X2 oscillator operates. The MCU enters watch mode if the STOP instruction is

executed in active mode when TMA3 = 1, or if the STOP or SBY instruction is executed in subactive

mode.

Watch mode is terminated by a RESET input, timer A interrupt request, INT0 interrupt request, or wakeup

interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer

A interrupt request, an INT0 nterrupt request, or wakeup interrupt request, the MCU enters active mode if

LSON is 0 or subactive mode if LSON is 1. After an interrupt request is generated, the time required to

enter active mode is tRC for a timer A interrupt, and TX (where T + tRC < TX < 2T + tRC) for an INT0

interrupt, as shown in figure 17.

Operation during mode transition is the same as that at standby mode cancellation (figure 15).

HD404459 Series

Active mode Watch mode Active mode

Oscillation

stabilization period

Interrupt strobe

Inte, rupt, trobe

INT , WU – WU

Interrupt request

generation

(During the transition

from watch mode to

active mode only)



TTt

t :

Interrupt frame length

Oscillation stabilization period

T + < Tx < 2T +

tRC tRC

Figure 17 Interrupt Frame

Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by

the X1 and X2 oscillator. In this mode, functions other than the voltage comparator operate. However,

because the operating clock is slow, the power dissipation becomes low, next to watch mode.

The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR12) of the

system clock select register (SSR1: $029). Note that the SSR12 value must be changed in active mode. If

the value is changed in subactive mode, the MCU may malfunction.

When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active

mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on

flag (DTON: $020, bit 3).

Subactive mode is an optional function that the user must specify on the function option list.

Interrupt Frame: In watch and subactive modes, ø CLK is applied to timer A and the INT0 and WU0–WU7

circuits. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt

frame. Three interrupt frame lengths (T) can be selected by setting the miscellaneous register (MIS: $00C)

(figure 18).

In watch and subactive modes, a timer A/ INT0 wakeup interrupt is generated synchronously with the

interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except

during transition to active mode. The falling edge of the INT0 and WU0–WU7 signals is input asynchro-

nously with the interrupt frame timing, but it is regarded as input synchronously with the second interrupt

strobe clock after the falling edge. An overflow and interrupt request in timer A is generated synchronously

with the interrupt strobe timing.

HD404459 Series

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1

MIS0 T*1

0 0.24414 ms

tRC*1

0.12207 ms

0.24414 ms*2

7.8125 ms

62.5 ms

Oscillation circuit conditions

External clock input

Ceramic or crystal oscillator

15.625 ms

125 ms

Not used —

Notes: 1.

2. The values of T and tRC are applied when a 32.768-kHz crystal oscillator is used.

The value is applied only when direct transfer operation is used.

Buffer control.

Refer to figure 39.

MIS3 MIS2

Figure 18 Miscellaneous Register (MIS)

Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on

flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described

below:

1. Set LSON to 0 and DTON to 1 in subactive mode.

2. Execute the STOP or SBY instruction.

3. The MCU automatically enters active mode from subactive mode after waiting for the MCU internal

processing time and oscillation stabilization time (figure 19).

Notes: The DTON flag ($020, bit 3) can be set only in subactive mode. It is always reset in active mode.

The transition time (TD) from subactive mode to active mode is:

tRC < TD < T + tRC

HD404459 Series

Subactive mode

Interrupt strobe

Direct transfer

completion timing

MCU internal

processing period

Oscillation

stabilization

time Active mode

TtRC

t :

STOP/SBY instruction execution

(Set LSON = 0, DTON = 1)

Interrupt frame length

Oscillation stabilization period

Figure 19 Direct Transition Timing

Stop Mode Cancellation by STOPC : The MCU enters active mode from stop mode by a STOPC input as

well as by RESET. In either case, the MCU starts instruction execution from the starting address (address

0) of the program. However, the value of the RAM enable flag (RAME: $021, bit 3) differs between

cancellation by STOPC and by RESET. When stop mode is cancelled by RESET, RAME = 0; when

cancelled by STOPC, RAME = 1. RESET can cancel all modes, but STOPC is valid only in stop mode;

STOPC input is ignored in other modes. Therefore, when the program requires to confirm that stop mode

has been cancelled by STOPC (i.e., when the RAM contents before entering stop mode are used after

transition to active mode), execute the TEST instruction on the RAM enable flag (RAME) at the beginning

of the program.

MCU Operation Sequence: See figures 20 to 22 for the MCU operation sequences. It is reset by an

asynchronous RESET input, regardless of its status.

The low-power mode operation sequence is shown in figure 22. With the IE flag cleared and an interrupt

flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is

cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY

instruction, make sure all interrupt flags are cleared or all interrupts are masked.

HD404459 Series

Power on

RESET = 1?

RAME = 0

Reset MCU

MCU

operation

cycle

Yes

Figure 20 MCU Operating Sequence (Power On)

HD404459 Series

MCU operation

cycle

IF = 1?

Instruction

execution

SBY, STOP

instruction?

PC Next

location PC Vector

address

Low-power mode

operation cycle

IE 0

Stack (PC),

(CA),

(ST)

IM = 0 and

IE = 1?

←

←←

Yes

No No

Yes

IF:

IM:

IE:

PC:

CA:

ST:

←

Interrupt request flag

Interrupt mask

Interrupt enable flag

Program counter

Carry flag

Status flag

Figure 21 MCU Operating Sequence (MCU Operation Cycle)

HD404459 Series

Low-power mode

operation cycle

IF = 1 and

IM = 0?

Hardware NOP

execution

←

PC Next

Iocation

MCU operation

cycle

Standby/Watch

mode

IF = 1 and

IM = 0?

Hardware NOP

execution

PC Next

Iocation

←

Instruction

execution

Stop mode

Yes

Note: * For IF and IM operation, refer to figure 15.

STOPC = 0?

RAME = 1

Reset MCU

Yes

Figure 22 MCU Operating Sequence (Low-Power Mode Operation)

HD404459 Series

Notes on Use:

• When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of

INT0 and WU0–WU7 is shorter than the interrupt frame, INT0 and WU0–WU7 will not be detected.

Also, if the low level period after the falling edge of INT0 and WU0–WU7 is shorter than the interrupt

frame, INT0 and WU0–WU7 will not be detected.

Edge detection is shown in figure 23. The level of the INT0 and WU0–WU7 signals are sampled by a

sampling clock. When this sampled value changes from high to low, a falling edge is detected.

In figure 24, the level of the INT0 and WU0–WU7 signals are sampled by an interrupt frame. In (a) the

sampled value is low at point A, and also low at point B. Therefore, a falling edge will not be detected.

In (b), the sampled value is high at point A, and also high at point B. A falling edge will not be detected

in this case either.

When the MCU is in watch mode or subactive mode, keep the high level and low level periods of INT0

and WU0–WU7 longer than interrupt frame.

High Low

INT0,

WU0–WU7

Sampling

Low

Figure 23 Edge Detection

A: Low B: Low

INT0,

WU0–WU7

Interrupt

frame A: High B: High

INT0,

WU0–WU7

Interrupt

frame

a. High level period b. Low level period

Figure 24 Sampling Example

HD404459 Series

Internal Oscillator Circuit

Clock Generation Circuit

See figure 25 for a block diagram of the clock generation circuit. A ceramic oscillator or crystal oscillator

can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2 (table

22). The system oscillator can also be operated by an external clock. Bit 1 (SSR11) of system clock select

and OSC2(figure 26).

Note: If the system clock select register 1 (SSR1: $029) setting does not match the oscillator frequency,

subsystems using the 32.768-kHz oscillation will malfunction.

OSC2

OSC1

System

oscillator

Sub-

system

oscillator

1/4, 1/8,

1/16, or

1/32

division

circuit*1

Timing

generator

circuit System

clock

selection

circuit

CPU with ROM,

RAM, registers,

flags, and I/O

Peripheral

function

interrupt

Time-base

interrupt

Time-base

clock

selection

circuit

1/8 or 1/4

division

circuit*2

Timing

generator

circuit

Timing

generator

circuit

1/8

division

circuit fW

fSUB

LSON

TMA3

fcyc

tcyc

fOSC

tWcyc

øCPU

PER

øCLK

Notes: 1.

1/4, 1/8, 1/16, or 1/32 division ratio can be selected by setting bits 0 and 1 of system clock

select register 2 (SSR2).

1/8 or 1/4 division ratio can be selected by setting bit 2 of system clock select register 1

(SSR1).

subcyc

Figure 25 Clock Generation Circuit

HD404459 Series

Selection of Division Ratio

Division Ratio of the System Clock: 1/4, 1/8, 1/16, or 1/32 division ratio of the system clock can be

selected by setting bits 0 and 1 (SSR20 and SSR21) of system clock select register 2 (SSR2: $02A). The

values of SSR20 and SSR21 become valid when entering the watch mode after making the ratio selection.

(However, the value of SSR2 becomes valid immediately after the selection.) Therefore, when changing the

division ratio, the system clock must be stopped. There are two methods for selecting the division ratio of

the system clock as follows.

• Division ratio is selected by writing to SSR20 and SSR21 in active mode. The selected values of SSR20

and SSR21 are valid before the MCU enters watch mode. The division ratio of the system clock

becomes the written value when the MCU returns to the active mode from the watch mode.

• Division ratio is selected by writing to SSR20 and SSR21 in subactive mode. The division ratio of the

system clock becomes the selected value when the MCU returns to active mode after entering watch

mode.

Note: SSR2 is cleared in the reset and stop modes. Therefore, 1/4 division ratio of the system clock is

selected when the MCU returns from stop mode after reset.

Division Ratio of the Subsystem Clock: 1/4 or 1/8 division ratio of the subsystem clock can be selected

by setting bit 2 (SSR12) of system clock select register 1 (SSR1: $029). The value of SSR12 becomes valid

immediately after the ratio selection. When the value of SSR12 is changed, the MCU must be in active

mode. If the value of SSR12 is changed in subactive mode, the MCU may malfunction.

HD404459 Series

SSR11

System oscillation frequency selection

1.6 to 4.0 MHz

0.4 to 1.0 MHz

Bit

Initial value

Read/Write

Bit name

SSR13*

SSR12

—

Not used

SSR11

System clock select register 1 (SSR1: $029)

SSR13

32-kHz oscillation stop

Oscillation operates in stop mode

Oscillation stops in stop mode

SSR12

32-kHz oscillation division ratio selection

fsub = fx/8

fsub = fx/4

Note: *SSR13 is reset to 0 only by RESET input. When STOPC is input in stop mode, SSR13

is not reset but retains its value. SSR13 is not reset in stop mode.

Figure 26 System Clock Select Register 1 (SSR1: $029)

Bit

Initial value

Read/Write

Bit name

—

Not used

—

Not used

SSR20

SSR21

System clock select register 2 (SSR2: $02A)

SSR21

System clock division ratio selection

1/4

1/8

1/16

1/32

SSR20

Figure 27 System Clock Select Register 2 (SSR2: $02A)

HD404459 Series

RESET

GND

OSC2

OSC1

TEST

GND

Figure 28 Typical Layout of Crystal and Ceramic Oscillators

HD404459 Series

Table 22 Oscillator Circuit Examples

Circuit Configuration Circuit Constants

External clock

operation External

oscillator OSC

Open

OSC2

Ceramic oscillator

(OSC1, OSC2)OSC

COSC

Ceramic

GND

Ceramic oscillator: CSA4.00MG (Murata)

Rf = 1 MΩ ± 20%

C1 = C2 = 30 pF

Crystal oscillator

(OSC1, OSC2)C1

Crystal

GND LS

CRS

OSC1

OSC2

OSC1

Rf = 1 MΩ ± 20%

C1 = C2 = 10–22 pF ± 20%

Crystal: Equivalent to circuit shown below

C0: 7 pF max.

RS: 100 Ω max.

Crystal oscillator

(X1, X2) X1

CX2

Crystal

GND LS

CRS

X1 X2

Crystal: 32.768 kHz: MX38T

(Nippon Denpa Kogyo)

C1 = C2 = 15 pF ± 5%

RS: 14 kΩ

C0: 1.5 pF

Notes: 1. Since the circuit constants change depending on the crystal or ceramic resonator and stray

capacitance of the board, the user should consult with the crystal or ceramic oscillator

manufacturer to determine the circuit parameters.

2. Wiring among OSC1, OSC2, X1, X2, and elements should be as short as possible, and must not

cross other wiring (figure 28).

3. If the 32.768-kHz crystal oscillator is not used, the X1 pin must be fixed to GND and X2 must be

open.

HD404459 Series

Input/Output

The MCU has 49 input/output pins (D0–D9, R0–R8, R90–R92) and 7 input pins (D 10, D11, R93, RA). The

features are described as follows.

• The D11, R0, R3–R6, R93, and RA pins are multiplexed with peripheral function pins such as those for

timers or the serial interface. See table 24. For these pins, the peripheral function setting is done prior to

the D or R port setting. Therefore, when a peripheral function is selected for a pin, the pin function and

input/output selection are automatically switched according to the setting. However, pins input to the

wakeup function are not switched. Only the valid/invalid statuses of wakeup input are controlled.

• Peripheral function output pins are CMOS out-put pins. See table 23. Only the SO pin and R43 port can

be set to NMOS open-drain output by software.

• In stop mode, the MCU is reset, and therefore peripheral function selection is cancelled. Input/output

pins are set at high-impedance.

• Each input/output pin has a built-in pull-up MOS (figure 29), which can be individually turned on or off

by software.

HD404459 Series

Table 23 Programmable I/O Circuits

MIS3 (Bit 3 of MIS) 0 1

DCD, DCR 0 1 0 1

PDR 01010101

CMOS buffer PMOS ———On———On

NMOS — — On — — — On —

Pull-up MOS —————On—On

Note: — indicates off status.

MIS3

Input control signal

VCC

Pull-up

MOS

DCD, DCR

PDR

Input data

VCC

HLT

Pull-up control signal

Buffer control signal

Output data

Figure 29 I/O Buffer Configuration

HD404459 Series

Table 24 Circuit Configurations of I/O Pins

I/O Pin Type Circuit Pins

Input/output pins VCC VCC Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

DCD, DCR

PDR

Input control signal

D0–D9, R00–R03,

R10–R13, R20–R23,

R30–R33, R40–R42,

R50–R53, R60–R63,

R70–R73, R80–R83,

R90–R92

VCC VCC Pull-up control signal

Buffer control

signal

Output data

Input data

HLT

MIS3

DCR

PDR

Input control signal

MIS2

R43

Input pins Input data

Input control signal

D10, D11,

R93, RA0–RA3

Peripheral

function

pins

Input/

output pins VCC VCC Pull-up control signal

Output data

Input data

HLT

MIS3

SCK

Output

pins VCC VCC Pull-up control signal

PMOS control

signal

Output data

HLT

MIS3

MIS2

VCC VCC Pull-up control signal

Output data

HLT

MIS3

TOB, TOC, TOD

HD404459 Series

I/O Pin Type Circuit Pins

Peripheral

function

pins

Input pins VCC

INT0, etc

HLT

MIS3

PDR

SI, INT0, INT1,

INT2, INT3,

WU0–WU7,

EVNB, EVND

Input data STOPC STOPC

Notes: 1. In stop mode, the MCU is reset and peripheral function selection is cancelled. The HLT signal

becomes low, and input/output pins enter high-impedance state.

2. The HLT signal is 1 in watch and subactive modes.

D Port (D0–D11): Consist of 10 input/output pins and 2 input pins addressed by one bit. D0–D9 are

input/output pins, and D10 and D11 are input-only pins.

Pins D0–D9 are set by the SED and SEDD instructions, and reset by the RED and REDD instructions.

Output data is stored in the port data register (PDR) for each pin. All pins D0–D11 are tested by the TD and

TDD instructions.

The on/off statuses of the output buffers are controlled by D-port data control registers (DCD0–DCD2:

$02C–$02E) that are mapped to memory addresses (figure 30).

Pin D11 is multiplexed with peripheral function pin STOPC. The peripheral function mode of this pin is

selected by bit 2 (PMRC2) of port mode register C (PMRC: $025) (figure 35).

HD404459 Series

R Ports (R0–RA): 39 input/output pins and 5 input pins addressed in 4-bit units. Data is input to these

ports by the LAR and LBR instructions, and output from them by the LRA and LRB instructions. Output

data is stored in the port data register (PDR) for each pin. The on/off statuses of the output buffers of the R

ports are controlled by R-port data control registers (DCR0–DCR9: $030–$039) that are mapped to

memory addresses (figure 30).

Bit

Initial value

Read/Write

Bit name

DCD03,

DCD02,

DCD00,

DCD01,

DCD0, DCD1

Data control register (DCD0 to DCD2: $02C to $02E)

(DCR0 to DCR9: $030 to $039)

DCD13 DCD12 DCD10DCD11

Bit

Initial value

Read/Write

Bit name

—

Not used

—

Not used

DCD20

DCD21

DCD2

Bit

Initial value

Read/Write

Bit name

DCR03–

DCR02–

DCR00–

DCR01–

DCR0 to DCR8

DCR83 DCR82 DCR80DCR81

Bit

Initial value

Read/Write

Bit name

—

Not used

DCR92

DCR90

DCR91

DCR9

Correspondence between ports and DCD/DCR bits

DCD0

DCD1

DCD2

DCR0

DCR1

DCR2

DCR3

DCR4

DCR5

DCR6

DCR7

DCR8

DCR9

Off (high-impedance)

All Bits CMOS Buffer On/Off Selection

—

Bit 3

—

Bit 2

Bit 1

Bit 0

Figure 30 Data Control Registers (DCD, DCR)

HD404459 Series

Pins R00–R03 are multiplexed with peripheral pins INT0–INT3, respectively. The peripheral function modes

of these pins are selected by bits 0–3 (PMRB0–PMRB3) of port mode register B (PMRB: $024) (figure

31).

/INT

Bit

Initial value

Read/Write

Bit name

PMRB3

PMRB2

PMRB0

PMRB1

PMRB0

R00/INT0 mode selection

R00

INT0

Port mode register B (PMRB: $024)

PMRB1

mode selection

R01/INT1 mode selection

R01

INT1

PMRB2

mode selection

R02/INT

R02

INT2

PMRB3

R03

INT3

Figure 31 Port Mode Register B (PMRB)

HD404459 Series

Pins R30–R32 are multiplexed with peripheral pins TOB, TOC, and TOD, respectively. The peripheral

function modes of these pins are selected by bits 0 and 1 (TMB20, TMB21) of timer mode register B2

(TMB2: $013), bits 0–2 (TMC20–TMC22) of timer mode register C2 (TMC2: $014), and bits 0–3

(TMD20–TMD23) of timer mode register D2 (TMD2: $015) (figures 32, 33, and 34).

Bit

Initial value

Read/Write

Bit name

—

Not used

—

Not used

R/W

TMB20

R/W

TMB21

Timer mode register B2 (TMB2: $013)

TMB21

TMB20

R30/TOB mode selection

R30

TOB

R30 port

Toggle output

0 output

1 output

Figure 32 Timer Mode Register B2 (TMB2)

Bit

Initial value

Read/Write

Bit name

—

Not used

R/W

TMC22

R/W

TMC20

R/W

TMC21

Timer mode register C2 (TMC2: $014)

TMC20

TOC

R31/TOC mode selectionTMC21

TMC22

R31 port

Toggle output

0 output

1 output

Not used

PWM output

Figure 33 Timer Mode Register C2 (TMC2)

HD404459 Series

Bit

Initial value

Read/Write

Bit name

R/W

TMD23

R/W

TMD22

R/W

TMD20

R/W

TMD21

Timer mode register D2 (TMD2: $015)

TMD20

Don't care

TOD

R32

R32/TOD mode selectionTMD21

Don't care

TMD22

Don't care

R32 port

Toggle output

0 output

1 output

Not used

PWM output

Input capture (R32 port)

TMD23

Figure 34 Timer Mode Register D2 (TMD2)

HD404459 Series

Pins R33 and R40 are multiplexed with peripheral pins EVNB and EVND, respectively. The peripheral

function modes of these pins are selected by bits 0 and 1 (PMRC0, PMRC1) of port mode register C

(PMRC: $025) (figure 35).

Bit

Initial value

Read/Write

Bit name

—

Not used

PMRC2*

PMRC0

PMRC1

Port mode register C (PMRC: $025)

PMRC0

R33

PMRC1

R40/EVND mode selection

R40

EVND

R33/EVNB mode selection

EVNB

PMRC2

D11

STOPC

D11/STOPC mode selection

Note: *PMRC2 is reset to 0 only by RESET input. When STOPC is input in stop mode,

PMRC2 is not reset but retains its value.

Figure 35 Port Mode Register C (PMRC)

HD404459 Series

Pins R41–R43 are multiplexed with peripheral pins SCK, SI, and SO, respectively. The peripheral function

modes of these pins are selected by bit 3 (SMRA3) of serial mode register A (SMRA: $005), and bits 0 and

1 (PMRA0, PMRA1) port mode register A (PMRA: $004) (figures 36 and 37).

PMRA0

/SO mode selection

Bit

Initial value

Read/Write

Bit name

—

Not used

—

Not used

PMRA0

PMRA1

Port mode register A (PMRA: $004)

PMRA1

/SI mode selection

Figure 36 Port Mode Register A (PMRA)

Bit

Initial value

Read/Write

Bit name

SMRA3

SMRA2

SMRA0

SMRA1

Serial mode register A (SMRA: $005)

Output

Input

Prescaler

System clock

External clock

÷2048

÷512

÷128

÷32

÷8

÷2

—

Prescaler

division

ratio

SMRA2 SMRA0SMRA1 Clock source

SMRA3

/SCK

mode selection SCK

port

SCK

Figure 37 Serial Mode Register A (SMRA)

HD404459 Series

Ports R5 and R6 are multiplexed with pins WU0–WU7. The wakeup modes of these pins can be selected by

the wakeup select register (WSR: $018). Even if wakeup input is valid, the R port functions normally

(figure 38).

Bit

Initial value

Read/Write

Bit name

WSR3

WSR2

WSR0

WSR1

WSR0

WU0 to WU3 control

Invalid

Valid

Wakeup select register (WSR: $018)

WSR1

WU4 to WU5 control

Invalid

Valid

WSR2

WU6 control

Invalid

Valid

WSR3

WU7 control

Invalid

Valid

Figure 38 Wakeup Select Register (WSR)

HD404459 Series

Pull-Up MOS Transistor Control: A program-controlled pull-up MOS transistor is provided for each

input/output pin other than input-only pins D10, D11, R93, and RA0–RA3. The on/off status of all these

transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of

an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin—

enabling on/off control of that pin alone (table 23 and figure 39).

The on/off status of each transistor and the peripheral function mode of each pin can be set independently.

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

MIS2

CMOS buffer

on/off selection

for pin R43/SO

Miscellaneous register (MIS: $00C)

Off Refer to figure 18 in the

operation modes section.

tRC selection.

MIS3

Pull-up MOS

on/off selection

Off

MIS1 MIS0

Figure 39 Miscellaneous Register (MIS)

How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (those that remain

floating) must be connected to VCC to prevent LSI malfunctions due to noise. These pins must either be

pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 kΩ.

HD404459 Series

Prescalers

The MCU has two prescalers, S and W. See table 25 and figure 40.

Both the timers A–D input clocks except external events and the serial transmit clock except the external

clock are selected from the prescaler outputs, depending on corresponding mode registers.

32-kHz

crystal

oscillator

System

clock

Prescaler W

Prescaler S

Timer A

Timer B

Timer C

Timer D

Serial

Clock

selector

fX/8

fX/4 or fX/8

Figure 40 Prescaler Output Supply

Prescaler Operation

Prescaler S: 11-bit counter that inputs a system clock signal. After being reset to $000 by MCU reset,

prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes and at

MCU reset.

Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided.

After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by

software.

Table 25 Prescaler Operating Conditions

Prescaler Input Clock Reset Conditions Stop Conditions

Prescaler S System clock

(in active and standby

mode),

Subsystem clock

(in subactive mode)

MCU reset MCU reset,

stop mode,

watch mode

Prescaler W 32-kHz crystal oscillation MCU reset, software MCU reset,

stop mode

HD404459 Series

Timers

The MCU has four timer/counters (A to D).

 Timer A: Free-running timer

 Timer B: Multifunction timer

 Timer C: Multifunction timer

 Timer D: Multifunction timer

Timer A is an 8-bit free-running timer. Timers B–D are 8-bit multifunction timers (table 26). The operating

modes are selected by software.

Table 26 Timer Functions

Functions Timer A Timer B Timer C Timer D

Clock source Prescaler S Available Available Available Available

Prescaler W Available — — —

External event — Available — Available

Timer functions Free-running Available Available Available Available

Time-base Available — — —

Event counter — Available — Available

Reload — Available Available Available

Watchdog — — Available —

Input capture — — — Available

Timer outputs Toggle — Available Available Available

0 output — Available Available Available

1 output — Available Available Available

PWM — — Available Available

Note: — means not available.

HD404459 Series

Timer A

Timer A Functions: Timer A (figure 41) has the following functions.

• Free-running timer

• Clock time-base

1/4 1/2

32.768-kHz

oscillator

System

clock

Prescaler W

(PSW)

Selector

Prescaler S (PSS)

Selector

Internal data bus

Timer A interrupt

request flag

(IFTA)

Clock

Overflow

Timer

counter A

(TCA)

Timer mode

(TMA)

2 f

1/2 tWcyc

tWcyc

øPER

128

512

1024

2048

Figure 41 Block Diagram of Timer A

Timer A Operations:

• Free-running timer operation: The input clock for timer A is selected by timer mode register A (TMA:

$008).

Timer A is reset to $00 by MCU reset and incremented at each input clock. If an input clock is applied

to timer A after it has reached $FF, an overflow is generated, and timer A is reset to $00. The overflow

sets the timer A interrupt request flag (IFTA: $002, bit 0). Timer A continues to be incremented after

reset to $00, and therefore it generates regular interrupts every 256 clocks.

• Clock time-base operation: Timer A is used as a clock time-base by setting bit 3 (TMA3) of timer mode

interrupts at the correct timing based on the 32.768-kHz crystal oscillation. In this case, prescaler W and

timer A can be reset to $00 by software.

HD404459 Series

Registers for Timer A Operation: Timer A operating modes are set by the following registers.

• Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A’s operating mode

and input clock source (figure 42).

Bit

Initial value

Read/Write

Bit name

TMA3

TMA2

TMA0

TMA1

Timer mode register A (TMA: $008)

PSS

PSW

Operating mode

Timer A mode

TMA3 TMA1TMA2 TMA0 Source

prescaler

2048tcyc

1024tcyc

512tcyc

128tcyc

32tcyc

8tcyc

4tcyc

2tcyc

Input clock

frequency

32tWcyc

16tWcyc

8tWcyc

2tWcyc

1/2tWcyc

Time-base

mode

Not used

PSW and TCA reset

Don't

care

Note: 1.

tWcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used)

Timer counter overflow output period (seconds) = input clock period (seconds) 256.

The division ratio must not be modified during time-base mode operation, otherwise

an overflow cycle error will occur.

Figure 42 Timer Mode Register A (TMA)

HD404459 Series

Timer B

Timer B Functions: Timer B (figure 43) has the following functions.

• Free-running/reload timer

• External event counter

• Timer output operation (toggle, 0, and 1 outputs)

System

clock

EVNB

TOB

Timer output control

Selector

Prescaler S (PSS)

Clock

Timer read register BU (TRBU)

Timer read

(TRBL)

Timer/event

counter B

(TCB)

Timer write

(TWBU)

Timer write

(TWBL)

Timer mode

(TMB1)

Timer mode

(TMB2)

Timer B interrupt

request flag

(IFTB)

øPER

Internal data bus

128

512

2048

Free-running/

Reload control

Overflow

Timer output

control logic

Figure 43 Block Diagram of Timer B

HD404459 Series

Timer B Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and

prescaler division ratio are selected by timer mode register B1 (TMB1: $009).

Timer B is initialized to the value set in timer write register B (TWBL: $00A, TWBU: $00B) by

software and incremented by one at each clock input. If an input clock is applied to timer B after it has

reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer B is

initialized to its initial value set in timer write register B; if the free-running timer function is enabled,

the timer is initialized to $00 and then incremented again.

The overflow sets the timer B interrupt request flag (IFTB: $002, bit 2). IFTB can be reset by software

or MCU reset. Refer to figure 3 and table 1 for details.

• External event counter operation: Timer B is used as an external event counter by selecting external

event input as the input clock source. In this case, pin R33/EVNB must be set to EVNB by port mode

Timer B is incremented by one at each falling edge of signals input to pin EVNB. The other operations

are basically the same as the free-running/ reload timer operation.

• Timer output operation: The following three output modes can be selected for timer B by setting timer

mode register B2 (TMB2: $013).

 Toggle

 0 output

 1 output

By selecting the timer output mode, pin R30/TOB is set to TOB. The output from TOB is reset low by

MCU reset.

 Toggle output: When toggle output mode is selected, the output level is inverted if a clock is input

after timer B has reached $FF. By using this function and reload timer function, clock signals can be

output at a required frequency for a buzzer. Refer to figure 44 for the output waveform.

 0 output: When 0 output mode is selected, the output level is pulled low if a clock is input after

timer B has reached $FF. Note that this function must be used only when the output level is high.

 1 output: When 1 output mode is selected, the output level is set high if a clock is input after timer B

has reached $FF. Note that this function must be used only when the output level is low.

HD404459 Series

T (N + 1)

T 256

T (256 – N)

TMC13 = 0

The waveform is always fixed low when N = $FF.

TMC13 = 1

Input clock period to counter (figures 45, 53, and 60)

The value of the timer write register (figures 55, 56, 62, and 63)

Note:

TMD13 = 0

TMD13 = 1

256 clock cycles 256 clock cycles

Free-running timer

Toggle output waveform (timers B, C, and D)

PWM output waveform (timers C and D)

(256 – N) clock cycles (256 – N) clock cycles

Reload timer

Figure 44 Timer Output Waveform

Registers for Timer B Operation: By using the following registers, timer B operation modes are selected

and the timer B count is read and written.

 Timer mode register B1 (TMB1: $009)

 Timer mode register B2 (TMB2: $013)

 Timer write register B (TWBL: $00A, TWBU: $00B)

 Timer read register B (TRBL: $00A, TRBU: $00B)

 Port mode register C (PMRC: $025)

• Timer mode register B1 (TMB1: $009): Four-bit write-only register that selects the free-running/reload

timer function, input clock source, and the prescaler division ratio (figure 45). It is reset to $0 by MCU

reset.

HD404459 Series

The mode change of this register is valid from the second instruction execution cycle after the execution

of the previous timer mode register B1 write instruction. Setting timer B’s initialization by writing to

timer write register B (TWBL: $00A, TWBU: $00B) must be done after a mode change becomes valid.

Bit

Initial value

Read/Write

Bit name

TMB13

TMB12

TMB10

TMB11

Timer mode register B1 (TMB1: $009)

2048tcyc

512tcyc

128tcyc

32tcyc

8tcyc

4tcyc

2tcyc

TMB12 TMB10TMB11 Input clock period and input

clock source

R33/EVNB (external event input)

TMB13

Free-running/reload

timer selection

Free-running timer

Reload timer

Figure 45 Timer Mode Register B1 (TMB1)

HD404459 Series

• Timer mode register B2 (TMB2: $013): Two-bit read/write register that selects the timer B output mode

(figure 46). It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

—

Not used

—

Not used

R/W

TMB20

R/W

TMB21

Timer mode register B2 (TMB2: $013)

TMB21

TMB20

R30/TOB mode selection

R30

TOB

R30 port

Toggle output

0 output

1 output

Figure 46 Timer Mode Register B2 (TMB2)

• Timer write register B (TWBL: $00A, TWBU: $00B): Write-only register consisting of a lower digit

(TWBL) and an upper digit (TWBU) (figures 47 and 48). The lower digit is reset to $0 by MCU reset,

but the upper digit value is undefined.

Timer B is initialized by writing to timer write register B (TWBL: $00A, TWBU: $00B). In this case,

the lower digit (TWBL) must be written to first, but writing only to the lower digit does not change the

timer B value. Timer B is initialized to the value in timer write register B at the same time the upper

digit (TWBU) is written to. When timer write register B is written to again and if the lower digit value

needs no change, writing only to the upper digit initializes timer B.

Bit

Initial value

Read/Write

Bit name

TWBL3

TWBL2

TWBL0

TWBL1

Timer write register B (lower digit) (TWBL: $00A)

Figure 47 Timer Write Register B Lower Digit (TWBL)

HD404459 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWBU3

Undefined

TWBU2

Undefined

TWBU0

Undefined

TWBU1

Timer write register B (upper digit) (TWBU: $00B)

Figure 48 Timer Write Register B Upper Digit (TWBU)

• Timer read register B (TRBL: $00A, TRBU: $00B): Read-only register consisting of a lower digit

(TRBL) and an upper digit (TRBU) that holds the count of the timer B upper digit.

The upper digit (TRBU) must be read first, which will result in the count of the timer B upper digit to

be obtained and the count of the timer B lower digit to be latched to the lower digit (TRBL). Then by

reading TRBL, the count of timer B can be obtained when TRBU is read.

Bit

Initial value

Read/Write

Bit name

Undefined

TRBL3

Undefined

TRBL2

Undefined

TRBL0

Undefined

TRBL1

Timer read register B (lower digit) (TRBL: $00A)

Figure 49 Timer Read Register B Lower Digit (TRBL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRBU3

Undefined

TRBU2

Undefined

TRBU0

Undefined

TRBU1

Timer read register B (upper digit) (TRBU: $00B)

Figure 50 Timer Read Register B Upper Digit (TRBU)

HD404459 Series

• Port mode register C (PMRC: $025): Write-only register that selects the R33/EVNB pin function (figure

51). It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

—

Not used

PMRC2

PMRC0

PMRC1

R40/EVND mode selection

R40

EVND

Port mode register C (PMRC: $025)

PMRC0

R33/EVNB mode selection

R33

EVNB

PMRC2

D11/STOPC mode selection

D11

STOPC

Figure 51 Port Mode Register C (PMRC)

HD404459 Series

Timer C

Timer C Functions: Timer C (figure 52) has the following functions.

 Free-running/reload timer

 Watchdog timer

 Timer output operation (toggle, 0, 1, and PWM outputs)

Watchdog on

flag (WDON)

System

reset signal Timer C interrupt

request flag

(IFTC)

Timer output

control logic Timer read register CU (TRCU)

Timer output

control Timer read

(TRCL)

Clock Timer counter C

(TCC)

Selector

System

clock Prescaler S (PSS)

Overflow

Internal data bus

Timer write

(TWCU) Timer write

(TWCL)

Timer mode

(TMC1)

Timer mode

(TMC2)

Free-running

/reload control

Watchdog timer

control logic

TOC

øPER

÷2

÷4

÷8

÷32

÷128

÷512

÷1024

÷2048

Figure 52 Block Diagram of Timer C

HD404459 Series

Timer C Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and

prescaler division ratio are selected by timer mode register C1 (TMC1: $00D).

Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by

software and incremented by one at each clock input. If an input clock is applied to timer C after it has

reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is

initialized to its initial value set in timer write register C; if the free-running timer function is enabled,

the timer is initialized to $00 and then incremented again.

The overflow sets the timer C interrupt request flag (IFTC: $003, bit 0). IFTC can be reset by software

or MCU reset. Refer to figure 3 and table 1 for details.

• Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program

routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of

control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing

timer C by software before it reaches $FF.

• Timer output operation: The following four output modes can be selected for timer C by setting timer

mode register C2 (TMC2: $014).

 Toggle

 0 output

 1 output

 PWM output

By selecting the timer output mode, pin R31/TOC is set to TOC. The output from TOC is reset low by

MCU reset.

 Toggle output: The operation is basically the same as that of timer-B’s toggle output.

 0 output: The operation is basically the same as that of timer-B’s 0 output.

 1 output: The operation is basically the same as that of timer-B’s 1 output.

 PWM output (figure 44): When PWM output mode is selected, timer C provides the variable-duty

pulse output function. The output waveform differs depending on the contents of timer mode

Registers for Timer C Operation: By using the following registers, timer C operation modes are selected

and the timer C count is read and written.

 Timer mode register C1 (TMC1: $00D)

 Timer mode register C2 (TMC2: $014)

 Timer write register C (TWCL: $00E, TWCU: $00F)

 Timer read register C (TRCL: $00E, TRCU: $00F)

• Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/ reload

timer function, input clock source, and prescaler division ratio (figure 53). It is reset to $0 by MCU

reset.

HD404459 Series

The mode change of this register is valid from the second instruction execution cycle after the execution

of the previous timer mode register C1 write instruction. Setting timer C’s initialization by writing to

timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid.

Bit

Initial value

Read/Write

Bit name

TMC13

TMC12

TMC10

TMC11

Timer mode register C1 (TMC1: $00D)

2048tcyc

1024tcyc

512tcyc

128tcyc

32tcyc

8tcyc

4tcyc

2tcyc

TMC12 TMC10TMC11

TMC13

Free-running/reload timer selection

Free-running timer

Reload timer

Input clock period

Figure 53 Timer Mode Register C1 (TMC1)

HD404459 Series

• Timer mode register C2 (TMC2: $014): Three-bit read/write register that selects the timer C output

mode (figure 54). It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

—

Not used

R/W

TMC22

R/W

TMC20

R/W

TMC21

Timer mode register C2 (TMC2: $014)

TMC22

TMC21 R31/TOC mode selection

R31

TOC

R31 port

Toggle output

0 output

1 output

Not used

PWM output

TMC20

Figure 54 Timer Mode Register C2 (TMC2)

• Timer write register C (TWCL: $00E, TWCU: $00F): Write-only register consisting of a lower digit

(TWCL) and an upper digit (TWCU) (figures 55 and 56). The operation of timer write register C is

basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).

Bit

Initial value

Read/Write

Bit name

TWCL3

TWCL2

TWCL0

TWCL1

Timer write register C (lower digit) (TWCL: $00E)

Figure 55 Timer Write Register C Lower Digit (TWCL)

HD404459 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWCU3

Undefined

TWCU2

Undefined

TWCU0

Undefined

TWCU1

Timer write register C (upper digit) (TWCU: $00F)

Figure 56 Timer Write Register C Upper Digit (TWCU)

• Timer read register C (TRCL: $00E, TRCU: $00F): Read-only register consisting of a lower digit

(TRCL) and an upper digit (TRCU) that holds the count of the timer C upper digit(figures 57 and 58).

The operation of timer read register C is basically the same as that of timer read register B (TRBL:

$00A, TRBU:$00B).

Bit

Initial value

Read/Write

Bit name

Undefined

TRCL3

Undefined

TRCL2

Undefined

TRCL0

Undefined

TRCL1

Timer read register C (lower digit) (TRCL: $00E)

Figure 57 Timer Read Register C Lower Digit (TRCL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRCU3

Undefined

TRCU2

Undefined

TRCU0

Undefined

TRCU1

Timer read register C (upper digit) (TRCU: $00F)

Figure 58 Timer Read Register C Upper Digit(TRCU)

Timer D

Timer D Functions: Timer D (figures 59 (A) and (B)) has the following functions.

 Free-running/reload timer

 External event counter

 Timer output operation (toggle, 0, 1, and PWM outputs)

 Input capture timer

HD404459 Series

Timer D interrupt

request flag (IFTD)

Timer output

control logic Timer read

Timer output

control Timer read

(TRDL)

Clock Timer counter D

(TCD)

Selector

System

clock Prescaler S (PSS)

Overflow

Internal data bus

Timer write

(TWDU) Timer write

(TWDL)

Timer mode

(TMD1)

Timer mode

(TMD2)

Free-running/

Reload control

TOD

Edge

detection

logic

Edge detection

selection register

2 (ESR2)

Edge detection control

øPER

÷2

÷4

÷8

÷32

÷128

÷512

÷2048

EVND

Figure 59(A) Block Diagram of Timer D (Free-Running/Reload Timer)

HD404459 Series

Selector

÷2

÷4

÷8

÷32

÷128

÷512

÷2048

PER

Input capture

status flag (ICSF) Input capture

error flag (ICEF) Timer D interrupt

request flag (IFTD)

Error

control

logic

Edge

detection

logic

Timer read

(TRDU) Timer read

(TRDL)

Read signal

Clock Timer counter D

(TCD) Overflow

System

clock

Edge detection control

Prescaler S (PSS)

Input capture

timer control

Timer mode

(TMD1)

Timer mode

(TMD2)

Edge detection

selection register

2 (ESR2)

EVND

Internal data bus

Figure 59(B) Block Diagram of Timer D (Input Capture Timer)

HD404459 Series

Timer D Operations:

• Free-running/reload timer operation: The free-running/reload operation, input clock source, and

prescaler division ratio are selected by timer mode register D1 (TMD1: $010).

Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by

software and incremented by one at each clock input. If an input clock is applied to timer D after it has

reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is

initialized to its initial value set in timer write register D; if the free-running timer function is enabled,

the timer is initialized to $00 and then incremented again.

The overflow sets the timer D interrupt request flag (IFTD: $001, bit 2). IFTD can be reset by software

or MCU reset. Refer to figure 3 and table 1 for details.

• External event counter operation: Timer D is used as an external event counter by selecting the external

event input as an input clock source. In this case, pin R40/EVND must be set to EVND by port mode

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the

external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and

falling edges detection is selected, the time between the falling edge and rising edge of input signals

must be 2tcyc or longer.

Timer D is incremented by one at each detection edge selected by detection edge select register 2

(ESR2: $027). The other operation is basically the same as the free-running/reload timer operation.

• Timer output operation: The following four output modes can be selected for timer D by setting timer

mode register D2 (TMD2: $015).

 Toggle

 0 output

 1 output

 PWM output

By selecting the timer output mode, pin R32/TOD is set to TOD. The output from TOD is reset low by

MCU reset.

 Toggle output: The operation is basically the same as that of timer-B’s toggle output.

 0 output: The operation is basically the same as that of timer-B’s 0 output.

 1 output: The operation is basically the same as that of timer-B’s 1 output.

 PWM output: The operation is basically the same as that of timer-C’s PWM output.

• Input capture timer operation: The input capture timer counts the clock cycles between trigger edges

input to pin EVND.

Either falling or rising edge, or both falling and rising edges of input signals can be selected as the

trigger input edge by detection edge select register 2 (ESR2: $027).

HD404459 Series

When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL:

$011, TRDU: $012), and the timer D interrupt request flag (IFTD: $001, bit 2) and the input capture

status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF

is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture

error flag (ICEF: $021, bit 1) is set. ICSF and ICEF can be reset to 0 by MCU reset or by writing 0.

By selecting the input capture operation, pin R32/TOD is set to R32 and timer D is reset to $00.

Registers for Timer D Operation: By using the following registers, timer D operation modes are selected

and the timer D count is read and written.

 Timer mode register D1 (TMD1: $010)

 Timer mode register D2 (TMD2: $015)

 Timer write register D (TWDL: $011, TWDU: $012)

 Timer read register D (TRDL: $011, TRDU: $012)

 Port mode register C (PMRC: $025)

 Detection edge select register 2 (ESR2: $027)

• Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload

timer function, input clock source, and the prescaler division ratio (figure 60). It is reset to $0 by MCU

reset.

The mode change of this register is valid from the second instruction execution cycle after the execution

of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D’s initialization

by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change

becomes valid.

When selecting the input capture timer operation, select the internal clock as the input clock source.

HD404459 Series

Bit

Initial value

Read/Write

Bit name

TMD13

TMD12

TMD10

TMD11

Timer mode register D1 (TMD1: $010)

2048tcyc

512tcyc

128tcyc

32tcyc

8tcyc

4tcyc

2tcyc

TMD12 TMD10TMD11 Input clock period and

input clock source

R40/EVND (external event input)

TMD13

Free-running/reload

timer selection

Free-running timer

Reload timer

Figure 60 Timer Mode Register D1 (TMD1)

HD404459 Series

• Timer mode register D2 (TMD2: $015): Four-bit read/write register that selects the timer D output

mode and input capture operation (figure 61). It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

R/W

TMD23

R/W

TMD22

R/W

TMD20

R/W

TMD21

Timer mode register D2 (TMD2: $015)

TMD22 TMD20

TMD21

R32/TOD mode selection

R32

TOD

R32

R32 port

Toggle output

0 output

1 output

Not used

PWM output

Input capture (R32 port)

TMD23

Don't care Don't careDon't care

Figure 61 Timer Mode Register D2(TMD2)

• Timer write register D (TWDL: $011, TWDU: $012): Write-only register consisting of a lower digit

(TWDL) and an upper digit (TWDU) (figures 62 and 63). The operation of timer write register D is

basically the same as that of timer write register B (TWBL: $00A, TWBU: $00B).

Bit

Initial value

Read/Write

Bit name

TWDL3

TWDL2

TWDL0

TWDL1

Timer write register D (lower digit) (TWDL: $011)

Figure 62 Timer Write Register D Lower Digit (TWDL)

HD404459 Series

Bit

Initial value

Read/Write

Bit name

Undefined

TWDU3

Undefined

TWDU2

Undefined

TWDU0

Undefined

TWDU1

Timer write register D (upper digit) (TWDU: $012)

Figure 63 Timer Write Register D Upper Digit (TWDU)

• Timer read register D (TRDL: $011, TRDU: $012): Read-only register consisting of a lower digit

(TRDL) and an upper digit (TRDU) (figures 64 and 65). The operation of timer read register D is

basically the same as that of timer read register B (TRBL: $00A, TRBU: $00B).

When the input capture timer operation is selected and if the count of timer D is read after a trigger is

input, either the lower or upper digit can be read first.

Bit

Initial value

Read/Write

Bit name

Undefined

TRDL3

Undefined

TRDL2

Undefined

TRDL0

Undefined

TRDL1

Timer read register D (lower digit) (TRDL: $011)

Figure 64 Timer Read Register D Lower Digit (TRDL)

Bit

Initial value

Read/Write

Bit name

Undefined

TRDU3

Undefined

TRDU2

Undefined

TRDU0

Timer read register D (upper digit) (TRDU: $012)

Undefined

TRDU1

Figure 65 Timer Read Register D Upper Digit (TRDU)

• Port mode register C (PMRC: $025): Write-only register that selects R40/EVND pin function (figure

51). It is reset to $0 by MCU reset.

HD404459 Series

• Detection edge select register 2 (ESR2: $027): Write-only register that selects the detection edge of

signals input to pin EVND (figure 66). It is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

ESR23

ESR22

—

Not used

—

Not used

Detection edge register 2 (ESR2: $027)

ESR23

ESR22

EVND detection edge

No detection

Falling-edge detection

Rising-edge detection

Double-edge detection*

Note: * Both falling and rising edges are detected.

Figure 66 Detection Edge Select Register 2 (ESR2)

HD404459 Series

Notes on Use

When using the timer output as PWM output, note the following point. From the update of the timer write

settings, as shown in table 27. The PWM output should therefore not be used until after the overflow

interrupt following the update of the timer write register. After the overflow, the PWM output will have the

set period and duty cycle.

Table 27 PWM Output following Update of Timer Write Register

PWM Output

Mode Timer Write Register is Updated during

High PWM Output Timer Write Register is Updated during

Low PWM Output

Free running

Timer write

updated to

value N Interrupt

request

T × (255 – N) T × (N + 1)

Timer write

updated to

value N Interrupt

request

T × (N' + 1)

T × (255 – N) T × (N + 1)

Reload

Timer write

updated to

value N Interrupt

request

TT × (255 – N)T

Timer write

updated to

value N Interrupt

request

TT × (255 – N)

HD404459 Series

Serial Interface

The MCU has a serial interface (figure 67). The serial interface serially transfers or receives 8-bit data, and

includes the following features.

• Multiple transmit clock sources

 External clock

 Internal prescaler output clock

 System clock

• Output level control in idle states

Five registers, an octal counter, and a multiplexer are also configured for the serial interface as follows.

 Serial data register (SRL: $006, SRU: $007)

 Serial mode register A (SMRA: $005)

 Serial mode register B (SMRB: $028)

 Port mode register A (PMRA: $004)

 Miscellaneous register (MIS: $00C)

 Octal counter (OC)

 Selector

HD404459 Series

Internal data bus

÷2

÷8

÷32

÷128

÷512

÷2048

Serial mode

(SMRB)

SCK

Selector

System

clock φPER Prescaler S (PSS)

Idle

controller

3Serial mode

(SMRA)

Clock Serial data

Serial interrupt

request flag

(IFS)

Selector

1/2 1/2

SO Octal

counter (OC)

I/O

controller

Transfer

control

signal

Figure 67 Serial Interface Block Diagram

Serial Interface Operation

Selecting and Changing the Operating Mode: To select an operating mode, use one of these

combinations of port mode register A (PMRA: $004) and serial mode register A (SMRA: $005) settings

(table 28); to change the operating mode of the serial interface, always initialize the serial interface

internally by writing data to serial mode register A. Note that the serial interface is initialized by writing

data to serial mode register A. Refer to the following section, Registers for Serial Interface, for details.

Pin Setting: The R41/SCK pin is controlled by writing data to serial mode register A (SMRA: $005). Pins

R42/SI and R43/SO are controlled by writing data to port mode register A (PMRA: $004). Refer to the

following section, Registers for Serial Interface, for details.

Transmit Clock Source Setting: The transmit clock source of the serial interface is set by writing data to

serial mode register A (SMRA: $005) and serial mode register B (SMRB: $028). Refer to the following

section, Registers for Serial Interface, for details.

Data Setting: Transmit data of the serial interface is set by writing data to the serial data register (SRL:

$006, SRU: $007). Receive data of the serial interface is obtained by reading the contents of the serial data

external system.

HD404459 Series

The output level of the SO pins is undefined until the first data of each serial interface is output after MCU

reset, or until the output level control in idle states is performed.

Transfer Control: The serial interface is activated by the STS instruction. The octal counter is reset to 000

by the STS instruction and is incremented at the rising edge of the transmit clock for the serial interface.

When the eighth transmit clock signal is input or when serial transmission/reception is discontinued, the

octal counter is reset to 000, the serial interrupt request flag (IFS: $023, bit 0) for serial interface is set, and

the transfer stops.

When the prescaler output is selected as the transmit clock of the serial interface, the transmit clock

frequency is selected as 4tcyc to 8192t cyc by setting bits 0 to 2 (SMRA0–SMRA2) of serial mode register A

(SMRA: $005) and bit 0 (SMRB0) of serial mode register B (SMRB: $028) (table 29).

Table 28 Serial Interface Operating Mode

SMRA PMRA

Bit 3 Bit 1 Bit 0 Operating Mode

1 0 0 Continuous clock output mode

1 Transmit mode

1 0 Receive mode

1 Transmit/receive mode

Table 29 Serial Transmit Clock (Prescaler Output)

SMRB SMRA

Bit 0 Bit 2 Bit 1 Bit 0 Prescaler Division Ratio Transmit Clock Frequency

0000÷ 2048 4096tcyc

1÷ 512 1024tcyc

10÷ 128 256tcyc

1÷ 32 64tcyc

100÷ 8 16tcyc

1÷ 24t

cyc

1000÷ 4096 8192tcyc

1÷ 1024 2048tcyc

10÷ 256 512tcyc

1÷ 64 128tcyc

100÷ 16 32tcyc

1÷ 48t

cyc

HD404459 Series

Operating States: The serial interface has the following operating states, which allow transitions to occur

between them (figure 68).

 STS wait state

 Transmit clock wait state

 Transfer state

Continuous clock output state (only in internal clock mode)

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000) Transfer state

(Octal counter = 000)

MCU reset

SMRA write 04 STS instruction

Transmit clock

8 transmit clocks

03 STS instruction (IFS 1)

05 ←

SMRA write (IFS 1)

06 ←

External clock mode

STS wait state

(Octal counter = 000,

transmit clock disabled)

Transmit clock wait state

(Octal counter = 000) Transfer state

(Octal counter = 000)

SMRA write 14 STS instruction

Transmit clock

STS instruction (IFS 1)

←

8 transmit clocks

Internal clock mode

Continuous clock output state

(PMRA 0, 1 = 0, 0)

SMRA write

Transmit clock 17

Note: Refer to the Operating States section for the explanations on the corresponding encircled numbers.

MCU reset10

←

SMRA write (IFS 1)

Figure 68 Serial Interface State Transitions

• STS wait state: The serial interface enters STS wait state by MCU reset (00 and 10 in figure 68). In STS

wait state, the serial interface is initialized and the transmit clock is ignored. If the STS instruction is

then executed (01 and 11), the serial interface enters transmit clock wait state.

HD404459 Series

• Transmit clock wait state: Transmit clock wait state is the period between the STS execution and the

falling edge of the first transmit clock. In transmit clock wait state, input of the transmit clock (02 and

12) increments the octal counter, shifts the serial data register (SRL: $006, SRU: $007), and enters the

serial interface in transfer state. However, note that if continuous clock output state is selected in

internal clock mode, the serial interface does not enter transfer state but enters continuous clock output

state (17).

The serial interface enters STS wait state by writing data to serial mode register A (SMRA: $005) (04

and 14) in transmit clock wait state.

• Transfer state: Transfer state is the period between the falling edge of the first clock and the rising edge

of the eighth clock. In transfer state, the input of eight clocks or the execution of the STS instruction

sets the octal counter to 000, and the serial interface enters another state. When the STS instruction is

executed (05 and 15), transmit clock wait state is entered. When eight clocks are input, transmit clock

wait state is entered (03) in external clock mode, or STS wait state is entered (13) in internal clock

mode. In internal clock mode, the transmit clock stops after outputting eight clocks.

In transfer state, writing data to serial mode register A (SMRA: $005) (06 and 16) initializes the serial

interface, and STS wait state is entered.

If the state changes from transfer to another state, the serial interrupt request flag (IFS: $023, bit 0) is set

by the octal counter that is reset to 000.

• Continuous clock output state (only in internal clock mode): Continuous clock output state is entered

only in internal clock mode. In this state, the serial interface does not transmit/receive data but only

outputs the transmit clock from the SCK pin.

When bits 0 and 1 (PMRA0, PMRA1) of port mode register A (PMRA: $004) are 00 in transmit clock

wait state and if the transmit clock is input (17), the serial interface enters continuous clock output state.

If serial mode register A (SMRA: $005) is written to in continuous clock output mode (18), STS wait

state is entered.

Output Level Control in Idle States: When the serial interface is in STS instruction wait state and

transmit clock wait state, the output of serial output pin SO can be controlled by setting bit 1 (SMRB1) of

serial mode register B (SMRB: $028) to 0 or 1. See figure 69 for an output level control example of the

serial interface. Note that the output level cannot be controlled in transfer state.

HD404459 Series

,



State

MCU reset

PMRA write

SMRA write

SMRB write

SRL, SRU

write

STS instruction

SCK pin (input)

SO pin

IFS

STS wait state

Transmit clock

wait state

Transfer state

Transmit clock

wait state

STS wait state

Port selection

External clock selection

Output level control in

idle states

Dummy write for

state transition

Output level control in

idle states

Data write for transmission

Undefined LSB MSB

Flag reset at transfer completion

External clock mode



State

MCU reset

PMRA write

SMRA write

SMRB write

SRL, SRU

write

STS instruction

SCK pin (output)

SO pin

IFS

STS wait state Transfer state

Transmit clock

wait state

STS wait state

Port selection

Internal clock selection

Output level control in

idle states

Data write for transmission

Output level control in

idle states

Undefined LSB MSB

Flag reset at transfer completion

Internal clock mode

Figure 69 Example of Serial Interface Operation Sequence

HD404459 Series

Transmit Clock Error Detection (In External Clock Mode): The serial interface will malfunction if a

spurious pulse caused by external noise conflicts with a normal transmit clock during transfer. A transmit

clock error of this type can be detected (figure 70).

If more than eight transmit clocks are input in transfer state, at the eighth clock including a spurious pulse

by noise, the octal counter reaches 000, the serial interrupt request flag (IFS: $023, bit 0) is set, and

transmit clock wait state is entered. At the falling edge of the next normal clock signal, the transfer state is

again entered. After the transfer is completed and IFS is reset, writing to serial mode register A (SMRA:

$005) then changes the state from transfer to STS wait. However, during the time the serial interface was in

the transfer state with the serial interrupt request flag (IFS: $023, bit 0) being set again, the error can be

detected.

Notes on Use:

• Initialization after writing to registers: If port mode register A (PMRA: $004) is written to in transmit

clock wait state or in transfer state, the serial interface must be initialized by writing to serial mode

• Serial interrupt request flag (IFS: $023, bit 0) set: For the serial interface, if the state is changed from

transfer state to another by writing to serial mode register A (SMRA: $005) or executing the STS

instruction during the first low pulse of the transmit clock, the serial interrupt request flag (IFS: $023,

bit 0) is not set. To set the serial interrupt request flag (IFS: $023, bit 0), a serial mode register A

(SMRA: $005) write or STS instruction execution must be programmed to be executed after confirming

that the SCK pin is at 1, that is, after executing the input instruction to port R4.

HD404459 Series

Transfer completion

(IFS ←1)

Interrupts inhibited

IFS ←0

SMRA write

IFS = 1? Transmit clock

error processing

Normal

termination

Yes

Transmit clock error detection flowchart



Transmit clock error detection procedures

State

Transmit clock

wait state Transfer state Transfer state

Transmit clock wait state

Noise

Transfer state has been

entered by the transmit clock

error. When SMRA is written,

IFS is set.

Flag set because octal

counter reaches 000. Flag reset at

transfer completion.

SMRA

write

12345678

SCK pin

(input)

IFS

Figure 70 Transmit Clock Error Detection

HD404459 Series

Registers for Serial Interface

The serial interface operation is selected, and serial data is read and written by the following registers.

 Serial mode register A (SMRA: $005)

 Serial mode register B (SMRB: $028)

 Serial data register (SRL: $006, SRU: $007)

 Port mode register A (PMRA: $004)

 Miscellaneous register (MIS: $00C)

Serial Mode Register A (SMRA: $005): This register has the following functions (figure 71).

• R41/SCK pin function selection

• Transmit clock selection

• Prescaler division ratio selection

• Serial interface initialization

Serial mode register A (SMRA: $005) is a 4-bit write-only register. It is reset to $0 by MCU reset.

A write signal input to serial mode register A (SMRA: $005) discontinues the input of the transmit clock to

the serial data register (SRL: $006, SRU: $007) and octal counter, and the octal counter is reset to 000.

Therefore, if a write is performed during data transfer, the serial interrupt request flag (IFS: $023, bit 0) is

set.

Written data is valid from the second instruction execution cycle after the write operation, so the STS

instruction must be executed at least two cycles after that.

HD404459 Series

Bit

Initial value

Read/Write

Bit name

SMRA3

SMRA2

SMRA0

SMRA1

Serial mode register A (SMRA: $005)

SMRA2 SMRA0SMRA1

SMRA3

R41/SCK

mode selection

R41

SCK

Output

Input

Clock source

Prescaler

System clock

External clock

—

Prescaler

division ratio

Refer to

table 29

Figure 71 Serial Mode Register A (SMRA)

Serial Mode Register B (SMRB: $028): This register has the following functions (figure 72).

• Prescaler division ratio selection

• Output level control in idle states

Serial mode register B (SMRB: $028) is a 2-bit write-only register. It cannot be written during data

transfer.

By setting bit 0 (SMRB0) of this register, the prescaler division ratio is selected. Only bit 0 (SMRB0) can

be reset to 0 by MCU reset. By setting bit 1 (SMRB1), the output level of the SO pin is controlled in idle

states of the serial interface. The output level changes at the same time that SMRB1 is written to.

HD404459 Series

Bit

Initial value

Read/Write

Bit name

—

Not used

—

Not used

SMRB0

Undefined

SMRB1

SMRB0

Serial clock division ratio

Prescaler output divided by 2

Prescaler output divided by 4

Serial mode register B (SMRB: $028)

SMRB1

Output level control in idle states

Low level

High level

Figure 72 Serial Mode Register B (SMRB)

Serial Data Register (SRL: $006, SRU: $007): This register has the following functions (figures 73 and

74).

• Transmission data write and shift

• Receive data shift and read

Writing data in this register is output from the SO pin, LSB first, synchronously with the falling edge of the

transmit clock (figure 75); data is input, LSB first, through the SI pin at the rising edge of the transmit

clock.

Data cannot be read or written during serial data transfer. If a read/write occurs during transfer, the

accuracy of the resultant data cannot be guaranteed.

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR3

Undefined

R/W

SR2

Undefined

R/W

SR0

Undefined

R/W

SR1

Serial data register (lower digit) (SRL: $006)

Figure 73 Serial Data Register Lower Digit (SRL)

HD404459 Series

Bit

Initial value

Read/Write

Bit name

Undefined

R/W

SR7

Undefined

R/W

SR6

Undefined

R/W

SR4

Undefined

R/W

SR5

Serial data register (upper digit) (SRU: $007)

Figure 74 Serial Data Register Upper Digit (SRU)

LSB MSB

12345678

Transmit clock

Serial output

data

Serial input data

latch timing

Figure 75 Serial Interface Output Timing

HD404459 Series

Port Mode Register A (PMRA: $004): This register has the following functions (figure 76).

• R42/SI pin function selection

• R43/SO pin function selection

Port mode register A (PMRA: $004) is a 2-bit write-only register, and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

—

Not used

—

Not used

PMRA0

PMRA1

Port mode register A (PMRA: $004)

PMRA0

R43/SO mode selection

R43

PMRA1

R42/SI mode selection

R42

Figure 76 Port Mode Register A (PMRA)

HD404459 Series

Miscellaneous Register (MIS: $00C): This register has the following functions (figure 77).

• R43/SO pin PMOS control

Miscellaneous register (MIS: $00C) is a 4-bit write-only register and is reset to $0 by MCU reset.

Bit

Initial value

Read/Write

Bit name

MIS3

MIS2

MIS0

MIS1

Miscellaneous register (MIS: $00C)

MIS1 MIS0

tRC

0.12207 ms

7.8125 ms

62.5 ms

Not used

MIS2

R43/SO PMOS on/off selection

Off

MIS3

Pull-up MOS on/off selection

Off

Figure 77 Miscellaneous Register (MIS)

HD404459 Series

Comparator

The comparator (figure 78) compares an analog input voltage with a reference voltage. Either a 16-level

internal or external reference power supply can be selected.

The voltage comparison is started by writing 1 to the comparator start flag (CMSF: $020, bit 2), and is

completed after 4tcyc. The comparison result is stored into bit 3 (CER: $017, bit 3) of the comparator enable

confirming that the comparator start flag (CMSF: $020, bit 2) is at 0 (figure 79).

COMP

Comparator

control register

(CCR)

Comparator

start flag

(CMSF)

Comparator

enable register

(CER)

Internal data bus

R93/VCref

RA0/COMP0

RA1/COMP1

RA2/COMP2

RA3/COMP3

Selector

Figure 78 Block Diagram of Comparator

HD404459 Series

4tcyc

(RA port must not be used)

Comparator

start flag

Write cycle

Internal system clock

Comparator start flag

(CMSF)

Voltage comparison result

(CER3)

Figure 79 Comparator Operation Timing

HD404459 Series

Comparator Control Register (CCR: $016): Four-bit write-only register which selects a 16-level internal

reference power supply (figure 80). The comparator control register (CCR: $016) is reset to $0 by MCU

reset.

Bit

Initial value

Read/Write

Bit name

CCR3

CCR2

CCR0

CCR1

Comparator control register (CCR: $016)

CCR0

Reference power supply selection

1/17 VCC

2/17 VCC

3/17 VCC

4/17 VCC

5/17 VCC

6/17 VCC

7/17 VCC

8/17 VCC

9/17 VCC

10/17 VCC

11/17 VCC

12/17 VCC

13/17 VCC

14/17 VCC

15/17 VCC

16/17 VCC

CCR1

CCR2

CCR3

Figure 80 Comparator Control Register (CCR)

Comparator Enable Register (CER: $017): This register consists of a 3-bit write-only register and a 1-bit

read-only register. It selects the analog input pins and reference voltage, and indicates the voltage

comparison result. The comparison result output is 0 when an analog input voltage is lower than the

reference voltage, and is 1 when an analog input voltage is higher than the reference voltage. The

comparison result is read by the bit test instruction (TM or TMD). The comparator enable register (CER:

$017) is reset to $0 by MCU reset.

HD404459 Series

Bit

Initial value

Read/Write

Bit name

CER3

CER2

CER0

CER1

Comparator enable register (CER: $017)

CER1

Analog input mode selection

COMP0

COMP1

COMP2

COMP3

CER2

External reference power supply

Internal reference power supply

CER0

CER3 Voltage comparison result

Analog input voltage is lower than

reference voltage

Analog input voltage is higher than

reference voltage

Reference power supply selection

Figure 81 Comparator Enable Register (CER)

Comparator Start Flag (CMSF: $020, Bit 2): Starts the comparator operation. The comparator starts the

voltage comparison by writing 1 to the comparator start flag (CMSF: $020, bit 2), and automatically

completes the voltage comparison after 4tcyc. The comparator start flag is then reset to 0. The comparison

result must be read after confirming that the comparator start flag is at 0. The comparator start flag is reset

to 0 by MCU reset.

Notes on Use: RA0/COMP0–RA3/COMP3 pins are used only for the comparator during voltage comparison.

These pins cannot be used for R ports.

The comparator operates only in the active and standby modes.

The switch for the internal power supply is turned on when the internal power supply is selected. The

switch is turned off except in active and standby modes.

When the external power supply is used for a reference voltage, R93/VCref must not be used as an R port.

HD404459 Series

Notes on Mounting

Assemble all parts including the HD404458/HD404459 on a board, noting the points described below.

Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits.

An example connection is described in figure 82.

No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in

parallel.

The capacitors are a large capacitance C1 and a small capacitance C2.

GND

CC V

GND

C1C2

Figure 82 Example of Connections

HD404459 Series

100

Programmable ROM (HD4074459)

The HD4074459 is a ZTAT TM microcomputer with a built-in PROM that can be programmed in PROM

mode.

PROM Mode Pin Description

Pin No. MCU Mode PROM Mode Pin No. MCU Mode PROM Mode

FP-64A Pin Name I/O Pin Name I/O FP-64A Pin Name I/O Pin Name I/O

1RA0/COMP0I29R1

I/O A5I

2RA

/COMP1I30R1

I/O A6I

3RA

/COMP2I31R12I/O A7I

4RA

/COMP3I32R1

I/O A8I

5TEST ITEST I33 R2

0I/O A0I

6 OSC1IV

CC 34 R21I/O A10 I

7 OSC2O35R2

I/O A11 I

8 GND — GND — 36 R23I/O A12 I

9 X2 O 37 R30/TOB I/O

10 X1 I GND 38 R31/TOC I/O

11 RESET I RESET I 39 R32/TOD I/O

12 D0I/O O0I/O 40 R33/EVNB I/O

13 D1I/O O1I/O 41 R40/EVND I/O

14 D2I/O O2I/O 42 R41/SCK I/O

15 D3I/O O3I/O 43 R42/SI I/O

16 D4I/O O4I/O 44 R43/SO I/O

17 D5I/O O5I/O 45 R50/(WU0) I/O

18 D6I/O O6I/O 46 R51/(WU1) I/O

19 D7I/O O7I/O 47 R52/(WU2) I/O

20 D8I/O A13 I48 R5

/(WU3) I/O

21 D9I/O A14 I49 R6

/(WU4) I/O CE I

22 D10 IV

PP I50 R6

/(WU5) I/O OE I

23 D11/STOPC IA

9I51 R6

/(WU6) I/O VCC

24 VCC —V

CC 52 R63/(WU7) I/O VCC

25 R00/INT0I/O M 0 I53 R7

0I/O A1I

26 R01/INT1I/O M1I54 R7

1I/O A2I

27 R02/INT2I/O 55 R72I/O A3I

28 R03/INT3I/O 56 R73I/O A4I

HD404459 Series

101

Pin No. MCU Mode PROM Mode Pin No. MCU Mode PROM Mode

FP-64A Pin Name I/O Pin Name I/O FP-64A Pin Name I/O Pin Name I/O

57 R80I/O O4I/O 61 R90I/O O0I/O

58 R81I/O O3I/O 62 R91I/O VCC

59 R82I/O O2I/O 63 R92I/O

60 R83I/O O1I/O 64 R93/VCref I

Notes: 1. I/O: Input/output pin, I: Input pin, O: Output pin

2. Each of O0–O4 has two pins; before using them, each pair must be connected together.

HD404459 Series

102

Programming the Built-In PROM

The MCU’s built-in PROM is programmed in PROM mode. This PROM mode is set by pulling TEST, M0,

and M1 low, and RESET high (figure 83). In PROM mode, the MCU does not operate, but it can be

programmed in the same way as any other commercial 27256-type EPROM using a standard PROM

programmer and a 64-to-28-pin socket adapter. Refer to table 31 for the Recommended PROM

programmers and socket adapters of the HD4074459.

Since an HMCS400-series instruction is ten bits long, the HMCS400-series MCU has a built-in conversion

circuit to enable the use of a general-purpose PROM programmer. This circuit splits each instruction into

five lower bits and five upper bits that are read from or written to consecutive addresses. This means that if,

for example, 16 kwords of built-in PROM are to be programmed by a general-purpose PROM programmer,

a 32-kbyte address space ($0000–$7FFF) must be specified.

Warnings

1. Always specify addresses $0000 to $7FFF when programming with a PROM programmer. If address

$8000 or higher is accessed, the PROM may not be programmed or verified correctly. Set all data in

unused addresses to $FF.

Note that the plastic-package versions cannot be erased or reprogrammed.

2. Make sure that the PROM programmer, socket adapter, and LSI are aligned correctly (their pin 1

positions match), otherwise overcurrents may damage the LSI. Before starting programming, make sure

that the LSI is firmly fixed in the socket adapter and the socket adapter is firmly fixed onto the

programmer.

3. PROM programmers have two voltages (VPP): 12.5 V and 21 V. Remember that ZTATTM devices

require a VPP of 12.5 V—the 21-V setting will damage them. 12.5 V is the Intel 27256 setting.

Programming and Verification

The built-in PROM of the MCU can be program med at high speed without risk of voltage stress or damage

to data reliability.

Refer to table 30 for programming and verification modes.

For details of PROM programming, refer to the preface section, Notes on PROM Programming.

Table 30 PROM Mode Selection

Mode CE OE VPP O0–O7

Programming Low High VPP Data input

Verification High Low VPP Data output

Programming inhibited High High VPP High impedance

HD404459 Series

103

Table 31 Recommended PROM Programmers and Socket Adapters

PROM Programmer Socket Adapter

Manufacturer Model Name Package Model Name Manufacturer

DATA I/O Corp. 121B FP-64A HS4459ESH01H Hitachi

AVAL Corp. PKW-1000 FP-64A HS4459ESH01H Hitachi

Address

A0 to A14

Data

O0 to O7

VCC

VPP

GND

VCC

O0 to O7

A0 to A14

VPP

RESET

TEST

VCC

OSC1

R62

R63

R91

HD4074459H

Figure 83 PROM Mode Connections

HD404459 Series

104

Addressing Modes

RAM Addressing Modes

The MCU has three RAM addressing modes (figure 84).

for RAM addressing.

Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains

the opcode, and the contents of the second word (10 bits) are used for RAM addressing.

Memory Register Addressing Mode: The memory registers (MR), which are located in 16 addresses from

$040 to $04F, are accessed with the LAMR and XMRA instructions.

AP9AP0

W1Y0

W register X register Y register

RAM address

AP9AP0

RAM address

Direct Addressing

d9d0

2nd word of Instruction

Opcode

1st word of Instruction

AP9AP0

RAM address

Memory Register Addressing

Opcode

Instruction

000100

AP8AP7AP AP5AP46 AP3AP2AP1

AP AP AP AP AP AP AP AP

87654321

AP8AP7AP6AP5AP4AP3AP2AP1

W0X3X2X1X0Y3Y2Y1

m2m1m0

Figure 84 RAM Addressing Modes

HD404459 Series

105

ROM Addressing Modes and the P Instruction

The MCU has four ROM addressing modes (figure 85).

Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the

JMPL, BRL, or CALL instruction. Each of these instructions replaces the 14 program counter bits (PC 13–

PC0) with 14-bit immediate data.

Current Page Addressing Mode: The MCU has 64 pages of ROM with 256 words per page. A program

can branch to any address in the current page by executing the BR instruction. This instruction replaces the

eight low-order bits of the program counter (PC7–PC0) with eight-bit immediate data. If the BR instruction

is on a page boundary (address 256n + 255), executing that instruction transfers the PC contents to the next

physical page (figure 87). This means that the execution of the BR instruction on a page boundary will

make the program branch to the next page.

Note that the HMCS400-series cross macroassembler has an automatic paging feature for ROM pages.

Zero-Page Addressing Mode: A program can branch to the zero-page subroutine area located at $0000–

$003F by executing the CAL instruction. When the CAL instruction is executed, 6 bits of immediate data

are placed in the six low-order bits of the program counter (PC5–PC0), and 0s are placed in the eight high-

order bits (PC13–PC6).

Table Data Addressing Mode: A program can branch to an address determined by the contents of four-bit

immediate data, the accumulator, and the B register by executing the TBR instruction.

P Instruction: ROM data addressed in table data addressing mode can be referenced with the P instruction

(figure 86). If bit 8 of the ROM data is 1, eight bits of ROM data are written to the accumulator and the B

and 9 are 1, ROM data is written to the accumulator and the B register, and also to the R1 and R2 port

output registers at the same time.

The P instruction has no effect on the program counter.

HD404459 Series

106

2nd word of instruction

Opcode

1st word of instruction

[JMPL]

[BRL]

[CALL]

PCPCPCPC

10111213

Program counter

Direct Addressing

Zero Page Addressing

Instruction

[CAL] Opcode

PCPC

10111213

Program counter

00000000

PCPC PC PC PC PC

Accumulator

Program counter

Table Data Addressing

PCPCPC

10111213

B register

[TBR]

Instruction

Opcode

Opcode b

Instruction

PCPCPC

111213

Program counter

Current Page Addressing

[BR]

10 7

PCPC

Figure 85 ROM Addressing Modes

HD404459 Series

107

Accumulator

Referenced ROM address

Address Designation

RARARA

10111213

B register

[P]

Instruction

Opcode p

BBBBAA A

3210 3210

If RO = 1

Accumulator, B register

ROM data

Pattern Output

ROM data

32103210

If RO = 1

Output registers R1, R2 R2 R2 R2 R1 R1 R1 R1

Figure 86 P Instruction

BR AAA

AAA NOP

256 (n – 1) + 255

256n

BR AAA

BR BBB 256n + 254

256n + 255

256 (n + 1)

BBB NOP

Figure 87 Branching when the Branch Destination is on a Page Boundary

HD404459 Series

108

Absolute Maximum Ratings (HD404458/HD404459)

Item Symbol Value Unit Notes

Supply voltage VCC –0.3 to +4.0 V

Pin voltage VT–0.3 to (VCC + 0.3) V

Total permissible input current ∑Io50 mA 2

Total permissible output current –∑Io50 mA 3

Maximum input current Io4 mA 4, 5

Maximum output current –Io4 mA 5, 6

Operating temperature Topr –20 to +75 °C

Storage temperature Tstg –55 to +125 °C

Absolute Maximum Ratings (HD4074459)

Item Symbol Value Unit Notes

Supply voltage VCC –0.3 to +4.0 V

Programming voltage VPP –0.3 to +14.0 V 1

Pin voltage VT–0.3 to (VCC + 0.3) V

Total permissible input current ∑Io50 mA 2

Total permissible output current –∑Io50 mA 3

Maximum input current Io4 mA 4, 5

Maximum output current –Io4 mA 5, 6

Operating temperature Topr –20 to +75 °C7

Storage temperature Tstg –55 to +125 °C

Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation

must be under the conditions stated in the electrical characteristics tables. If these conditions are

exceeded, the LSI may malfunction or its reliability may be affected.

1. Applies to D10 (VPP) of the HD4074459.

2. The total permissible input current is the total of input currents simultaneously flowing in from all

the I/O pins to ground.

3. The total permissible output current is the total of output currents simultaneously flowing out from

VCC to all I/O pins.

4. The maximum input current is the maximum current flowing from each I/O pin to ground.

5. Applies to D0–D9, R0–R8, and R90–R92.

6. The maximum output current is the maximum current flowing out from VCC to each I/O pin.

7. Depends on the supply voltage.

HD404459 Series

109

Electrical Characteristics

DC Characteristics

HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = –20 to +75°C, fOSC = 0.4 to 4.0 MHz

HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = –5 to +60°C, fOSC = 0.4 to 2.0 MHz;

VCC = 2.7 to 3.6 V, GND = 0 V, Ta = –20 to +75°C, fOSC = 0.4 to 4.0 MHz, unless otherwise specified.

Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes

Input high

voltage VIH RESET, STOPC,

INT0, INT1, INT2, INT3,

SCK, SI, WU0–WU7,

EVNB, EVND

0.9VCC —V

CC + 0.3 V —

OSC1VCC – 0.3 — VCC + 0.3 V External clock

operation

Input low

voltage VIL RESET, STOPC,

INT0, INT1, INT2, INT3,

SCK, SI, WU0–WU7,

EVNB, EVND

–0.3 — 0.1VCC V—

OSC1–0.3 — 0.3 V External clock

operation

Output high

voltage VOH SCK, SO,

TOB, TOC, TOD VCC – 0.5 — — V –IOH = 0.3 mA

Output low

voltage VOL SCK, SO,

TOB, TOC, TOD — — 0.4 V IOL = 0.4 mA

I/O leakage

current | IIL | RESET, STOPC,

INT0, INT1, INT2, INT3,

SCK, SI, WU0–WU7,

SO, EVNB,

EVND, OSC1,

TOB, TOC, TOD

— — 1.0 µAV

in = 0 V to VCC 1

Current

dissipation

in active

mode

ICC VCC — 3 6 mA HD404458,

HD404459:

VCC = 3.0 V,

fOSC = 4 MHz

— 5 9 mA HD4074459:

VCC = 3.0 V,

fOSC = 4 MHz

HD404459 Series

110

Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes

Current

dissipation

in standby

mode

ISBY VCC — 1.2 3 mA VCC = 3.0 V,

fOSC = 4 MHz 3

Current

dissipation

in subactive

mode

ISUB VCC —3570µA HD404458,

HD404459:

VCC = 3.0 V,

32-kHz oscillator

— 70 150 µA HD4074459:

VCC = 3.0 V,

32-kHz oscillator

Current

dissipation

in watch

mode

IWTC VCC —815µAV

CC = 3.0 V,

32-kHz oscillator 4

Current

dissipation

in stop

mode

ISTOP VCC —110µAV

CC = 3.0 V,

no 32-kHz oscillator 4

Stop mode

retaining

voltage

VSTOP VCC 1.5 — — V No 32-kHz oscillator 5

Notes: 1. Output buffer current is excluded.

2. ICC is the source current when no I/O current is flowing while the MCU is in reset state.

Test conditions: MCU: Reset

Pins: RESET at VCC (0.9VCC to VCC)

TEST at VCC (0.9VCC to VCC)

3. ISBY is the source current when no I/O current is flowing while the MCU timer is operating.

Test conditions: MCU: I/O reset

Serial interface stopped

Standby mode

Pins: RESET at GND (0 V to 0.3 V)

TEST at VCC (0.9VCC to VCC)

4. These are the source currents when no I/O current is flowing.

Test conditions: Pins: RESET at GND (0 V to 0.3 V)

TEST at VCC (0.9VCC to VCC)

D10* at VCC (0.9VCC to VCC)

Note: * Applies to HD4074459

5. RAM data retention is the voltage required for retaining RAM data.

HD404459 Series

111

I/O Characteristics for Standard Pins

HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = –20 to +75°C, fOSC = 0.4 to 4.0 MHz

HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = –5 to +60°C, fOSC = 0.4 to 2.0 MHz;

VCC = 2.7 to 3.6 V, GND = 0 V, Ta = –20 to +75°C, fOSC = 0.4 to 4.0 MHz, unless otherwise specified.

Item Symbol Pin(s) Min Typ Max Unit Test Condition Note

Input high voltage VIH D0–D11,

R0–RA 0.7VCC —V

CC + 0.3 V —

Input low voltage VIL D0–D11,

R0–RA –0.3 — 0.3VCC V—

Output high

voltage VOH D0–D9,

R0–R8,

R90–R92

VCC – 0.5 — — V –IOH = 0.3 mA

Output low voltage VOL D0–D9,

R0–R8,

R90–R92

— — 0.4 V IOL = 0.4 mA

I/O leakage

current | IIL |D

–D11,

R0–RA ——1 µA HD404458,

HD404459:

Vin = 0 V to VCC

D0–D9, D11,

R0–RA ——1 µA HD4074459:

Vin = 0 V to VCC

D10 ——1 µA HD4074459:

Vin = VCC – 0.3 to VCC

——20µA HD4074459:

Vin = 0 V to 0.3 V 1

Pull-up MOS

current –IPU D0–D9,

R0–R8,

R90–R92

54090µAV

CC = 3.0 V,

Vin = 0 V

Note: 1. Output buffer current is excluded.

HD404459 Series

112

Voltage Comparator Characteristics

HD404458, HD404459: VCC = 2.0 to 3.6 V, GND = 0 V, Ta = –10 to +75°C, fOSC = 0.4 to 4.0 MHz

HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = –5 to +60°C, fOSC = 0.4 to 2.0 MHz;

VCC = 2.7 to 3.6 V, GND = 0 V, Ta = –10 to +75°C, fOSC = 0.4 to 4.0 MHz,unless otherwise specified.

Item Symbol Pin(s) Min Typ Max Unit Test Condition Note

Input high voltage VIHA COMP0–

COMP3

Vref + 0.17 — — V — 1

Input low voltage VILA COMP0–

COMP3

——V

ref – 0.03 V — 1

Analog input

standard voltage

range

VCref VCref 0—V

CC V—

Note: 1. When an internal reference voltage is selected, the standard voltage is an expected voltage of

internal Vref specified by the comparator control register (CCR).

HD404459 Series

113

AC Characteristics

HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = –20 to +75°C, fOSC = 0.4 to 4.0 MHz

HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = –5 to +60°C, fOSC = 0.4 to 2.0 MHz;

VCC = 2.7 to 3.6 V, GND = 0 V, Ta = –20 to +75°C, fOSC = 0.4 to 4.0 MHz, unless otherwise specified.

Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes

Clock oscillation

frequency fOSC OSC1, OSC20.4 — 4.0 MHz HD404458, HD404459:

1/4division,

VCC = 1.8 V to 3.6 V

HD4074459:

1/4 division,

VCC = 2.7 V to 3.6 V

0.4 — 2.0 MHz HD4074459:

1/4 division,

VCC = 2.2 V to 2.7 V

X1, X2 — 32.768 — kHz —

Instruction cycle

time tcyc — 1.0 — 10 µs HD404458, HD404459:

1/4 division,

VCC = 1.8 V to 3.6 V

HD4074459:

1/4 division,

VCC = 2.7 V to 3.6 V

2.0 — 10 µs HD4074459:

1/4 division,

VCC = 2.2 V to 2.7 V

tsubcyc — — 244.14 — µs 32-kHz oscillator,

1/8 division

— 122.07 — µs 32-kHz oscillator,

1/4 division

Oscillation

stabilization time

(ceramic oscillator)

tRC OSC1, OSC2— — 60 ms — 1

Oscillation

stabilization time

(crystal oscillator)

tRC OSC1, OSC2— — 60 ms — 1

X1, X2 — — 3 s Ta = –10°C to+60°C2

External clock high

width tCPH OSC1105 — — ns fOSC = 4 MHz 3

External clock low

width tCPL OSC1105 — — ns fOSC = 4 MHz 3

HD404459 Series

114

Item Symbol Pin(s) Min Typ Max Unit Test Condition Notes

External clock rise

time tCPr OSC1— — 20 ns — 3

External clock fall

time tCPf OSC1— — 20 ns — 3

INT0–INT3, EVNB,

WU0–WU7, EVND

high widths

tIH INT0–INT3,

WU0–WU7,

EVNB, EVND

2— —t

cyc/

tsubcyc

— 4, 7

INT0–INT3, EVNB,

WU0–WU7, EVND

low widths

tIL INT0–INT3,

WU0–WU7,

EVNB, EVND

2— —t

cyc/

tsubcyc

— 4, 7

RESET high width tRSTH RESET 2 — — tcyc —5

STOPC low width tSTPL STOPC 1— —t

RC —6

RESET fall time tRSTf RESET — — 20 ms — 5

STOPC rise time tSTPr STOPC — — 20 ms — 6

Input capacitance Cin All pins except

for D10

— — 15 pF f = 1 MHz, Vin = 0 V

D10 — — 15 pF HD404458, HD404459:

f = 1MHz, Vin = 0 V

— — 180 pF HD4074459:

f = 1 MHz, Vin = 0 V

Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC

reaches 1.8 V (2.2 V: HD4074459) at power-on, or after RESET input goes high or STOPC input

goes low when stop mode is cancelled. At power-on or when stop mode is cancelled, RESET or

STOPC must be input for at least tRC to ensure the oscillation stabilization time. If using a

ceramic or crystal oscillator, contact its manufacturer to determine the required stabilization time,

since it will depend on the circuit constants and stray capacitances. Set bits 0 and 1 (MIS0,

MIS1) of the miscellaneous register (MIS: $00C) according to the oscillation stabilization time of

the system oscillation.

2. The oscillation stabilization time is the period required for the oscillator to stabilize after VCC

reaches 1.8 V (2.2 V: HD4074459) at power-on, or after RESET input goes high or STOPC input

goes low when stop mode is cancelled. If using a crystal oscillator, contact its manufacturer to

determine the required stabilization time, since it will depend on the circuit constants and stray

capacitances.

3. Refer to figure 88.

4. Refer to figure 89. The tcyc unit applies when the MCU is in standby or active mode. The tsubcyc

unit applies when the MCU is in watch or subactive mode.

5. Refer to figure 90.

6. Refer to figure 91.

7. In watch or subactive mode, the periods when the INT0 and WU0–WU7 signals are high and when

these signals are low must be equal to the interrupt frame period or longer.

HD404459 Series

115

Serial Interface Timing Characteristics

HD404458, HD404459: VCC = 1.8 to 3.6 V, GND = 0 V, Ta = –20 to +75°C, fOSC = 0.4 to 4.0 MHz

HD4074459: VCC = 2.2 to 2.7 V, GND = 0 V, Ta = –5 to +60°C, fOSC = 0.4 to 2.0 MHz;

VCC = 2.7 to 3.6 V, GND = 0 V, Ta = –20 to +75°C, fOSC = 0.4 to 4.0 MHz, unless otherwise specified.

During Transmit Clock Output

Item Symbol Pin Min Typ Max Unit Test Condition Note

Transmit clock cycle

time tScyc SCK 1.0 — — tcyc Load shown in figure 93 1

Transmit clock high

width tSCKH SCK 0.4 — — tScyc Load shown in figure 93 1

Transmit clock low

width tSCKL SCK 0.4 — — tScyc Load shown in figure 93 1

Transmit clock rise time tSCKr SCK — — 200 ns Load shown in figure 93 1

Transmit clock fall time tSCKf SCK — — 200 ns Load shown in figure 93 1

Serial output data delay

time tDSO SO — — 500 ns Load shown in figure 93 1

Serial input data setup

time tSSI SI 300 — — ns — 1

Serial input data hold

time tHSI SI 300 — — ns — 1

Note: 1. Refer to figure 92.

During Transmit Clock Input

Item Symbol Pin Min Typ Max Unit Test Condition Note

Transmit clock cycle

time tScyc SCK 1.0 — — tcyc —1

Transmit clock high

width tSCKH SCK 0.4 — — tScyc —1

Transmit clock low

width tSCKL SCK 0.4 — — tScyc —1

Transmit clock rise time tSCKr SCK — — 200 ns — 1

Transmit clock fall time tSCKf SCK — — 200 ns — 1

Serial output data delay

time tDSO SO — — 500 ns Load shown in figure 93 1

Serial input data setup

time tSSI SI 300 — — ns — 1

Serial input data hold

time tHSI SI 300 — — ns — 1

Note: 1. Refer to figure 92.

HD404459 Series

116

OSC1

1/fCP

tCPL

tCPf

tCPH

tCPr

VCC – 0.3 V

0.3 V

Figure 88 External Clock Timing

tIL

0.9VCC

0.1VCC

tIH

WU0 to WU7,

INT0 to INT3,

EVNB, EVND

Figure 89 Interrupt Timing

0.1VCC

0.9VCC tRSTH

tRSTf

RESET

Figure 90 Reset Timing

HD404459 Series

117

0.1VCC

0.9VCC tSTPL

tSTPr

STOPC

Figure 91 STOPC Timing

0.9V

0.1V

tDSO

tSCKf tSCKL

tSSI tHSI

tScyc

tSCKr

0.4 V

V – 0.5 V

V – 0.5 V (0.9V )*

CC 0.4 V (0.1V )*

SCK

Note: * VCC – 0.5 V and 0.4 V are the threshold voltages for transmit clock output, and

0.9VCC and 0.1VCC are the threshold voltages for transmit clock input.

CC tSCKH

Figure 92 Serial Interface Timing

RL = 2.6 kΩ

VCC

1S2074 H

or equivalent

R =

12 kΩ

Test

point C =

30 pF

Figure 93 Timing Load Circuit

HD404459 Series

118

Notes on ROM Out

Please pay attention to the following items regarding ROM out.

On ROM out, fill the ROM area indicated below with 1s to create the same data size as a 16-kword version

(HD404459). A 16-kword data size is required to change ROM data to mask manufacturing data since the

program used is for a 16-kword version.

This limitation applies when using an EPROM or a data base.

Vector address

Zero-page subroutine

(64 words)

Pattern & program

(8,192 words)

Not used

ROM 8-kword version:

HD404458

Address $2000–$3FFF

$0000

$000F

$0010

$003F

$0040

$1FFF

$2000

$3FFF Fill this area with 1s

HD404459 Series

119

HD404458, HD404459 Option List

Please check off the appropriate applications and enter the necessary information.

3. ROM code media

Date of order

Customer

Department

Name

ROM code name

LSI number

EPROM:

Ceramic oscillator

Crystal oscillator

External clock

f = MHz

4. Oscillator for OSC1 and OSC2

The upper bits and lower bits are mixed together. The upper five bits and lower five bits

are programmed to the same EPROM in alternating order (i.e., LULULU...).

EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are

programmed to different EPROMS.

HD404458

HD404459

8-kword

16-kword

1. ROM size

FP-64A

6. Package

Please specify the first type listed below (the upper bits and lower bits are mixed together), when using

the EPROM on-package microcomputer type (including ZTAT™ version).

Used

Not used

5. Stop mode

With 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, with time-base for clock

Without 32-kHz CPU operation, without time-base

2. Optional Functions

Note: * Options marked with an asterisk require a subsystem crystal oscillator (X1, X2).

HD404459 Series

120

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,

Hitachi bears no responsibility for problems that may arise with third party’s rights, including

intellectual property rights, in connection with use of the information contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you have

received the latest product standards or specifications before final design, purchase or use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,

contact Hitachi’s sales office before using the product in an application that demands especially high

quality and reliability or where its failure or malfunction may directly threaten human life or cause risk

of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,

traffic, safety equipment or medical equipment for life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly

for maximum rating, operating supply voltage range, heat radiation characteristics, installation

conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used

beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable

failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-

safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other

consequential damage due to operation of the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without

written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor

products.