Single Port VDSL2
Line Driver with Shutdown
AD8398A
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2010 Analog Devices, Inc. All rights reserved.
FEATURES
Voltage feedback
Wide output swing
18.4 V p-p differential, RLOAD, DIFF = 20 Ω from 12 V supply
High output current
Linear output current of 450 mA peak
Low distortion
−65 dBc for Profile 8b @ 20.4 dBm
−55 dBc for Profile 17a @ 14.5 dBm
High speed
85 MHz bandwidth (AV DIFF = 5)
APPLICATIONS
ADSL2+/VDSL2 CO/CPE line drivers
PLC line drivers
Consumer xDSL modems
Twisted pair line drivers
FUNCTIONAL BLOCK DIAGRAM
NC = NO CONNECT
1NC
2−IN A
3+IN A
4GND
11 −IN B
12 NC
10 +IN B
9PD1
5
NC
6
NC
7
V
EE
8
PD0
15 NC
16 OUT A
14 V
CC
13 OUT
B
07760-001
–
+
–
+
Figure 1. Thermally Enhanced, 4 mm × 4 mm, 16-Lead LFCSP_WQ
TYPICAL APPLICATION DIAGRAM
V
MID
*
TIP
RING
AD8398A
AD8398A
1/2
1/2
*V
MID =
V
CC +
V
EE
2
07760-002
Figure 2. Typical VDSL2 Application
GENERAL DESCRIPTION
The AD8398A comprises two high speed, voltage feedback
operational amplifiers. When configured as a differential line
driver, the AD8398A is an ideal choice for ADSL2+, VDSL2, and
power line communications (PLC) applications. It has high
output current, high bandwidth, and fast slew rate, combined
with exceptional multitone power ratio (MTPR) and common-
mode stability. The AD8398A is available in a thermally enhanced
4 mm × 4 mm, 16-lead LFCSP.
The AD8398A incorporates power management functionality
via two CMOS-compatible control pins, PD0 and PD1. These
pins select one of four operating modes: full power, medium
power, low power, or complete power-down. In the power-down
mode, the quiescent current drops to 0.7 mA.
The AD8398A operates in the industrial temperature range of
−40°C to +85°C.
AD8398A
Rev. D | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Typical Application Diagram.......................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
Maximum Power Dissipation ..................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ..............................................6
Applications Information.................................................................8
Power Control Modes of Operation ...........................................8
Exposed Thermal Pad Connections ...........................................8
Power Supply Bypassing...............................................................8
Board Layout..................................................................................8
Multitone Power Ratio..................................................................9
Lightning and AC Power Fault....................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
REVISION HISTORY
9/10—Rev. C to Rev. D
Change to General Description Section........................................ 1
3/10—Rev. B to Rev. C
Changes to Figure 14........................................................................ 9
12/09—Rev. A to Rev. B
Changes to Figure 13, Figure 14, and Figure 15 ........................... 9
10/09—Rev. Sp0 to Rev. A
Changed RLOAD to RLOAD, Diff Throughout........................................ 1
Changes to DC Performance, Differential Input Offset
Voltage Parameter, Table 1 .............................................................. 3
Changes to Figure 4.......................................................................... 5
Changes to Figure 8 and Figure 9................................................... 6
Changes to Exposed Thermal Pad Connections Section............ 8
11/08—Revision Sp0: Initial Version
AD8398A
Rev. D | Page 3 of 12
SPECIFICATIONS
VS = 12 V, ±6 V at TA = 25°C, AV DIFF = 5, RLOAD, DIFF = 20 Ω, PD1 = 0, PD0 = 0, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE
−3 dB Bandwidth AV DIFF = 5, VOUT = 2 V peak, measured differentially
PD1 = 0, PD0 = 0 85 MHz
PD1 = 0, PD0 = 1 85 MHz
PD1 = 1, PD0 = 0 75 MHz
Slew Rate VOUT = 4 V peak, measured differentially 600 V/μs
NOISE/DISTORTION PERFORMANCE
MTPR Profile 8b at 20.4 dBm in VDSL2 application −65 dBc
Profile 17a at 14.5 dBm in VDSL2 application −55 dBc
Off Isolation PD1 = 1, PD0 = 1 −80 dBc
Input Voltage Noise f = 100 kHz 4.8 nV/√Hz
Input Current Noise f = 100 kHz 0.9 pA/√Hz
Differential Output Voltage Noise f = 100 kHz in VDSL2 application 120 nV/√Hz
DC PERFORMANCE
Differential Input Offset Voltage −2 ±0.1 +2 mV
Input Offset Voltage 16 55 mV
Input Bias Current 0.5 1 μA
Open-Loop Gain 63 dB
Common-Mode Rejection Measured differentially −100 −74 dB
INPUT CHARACTERISTICS
Input Resistance f < 100 kHz 1.9 MΩ
OUTPUT CHARACTERISTICS
Differential Swing 17.6 18.4 V p-p
Linear Peak Output Current VDSL2 at 20.4 dBm, MTPR = −65 dBc 450 mA peak
POWER SUPPLY
Operating Range Dual supply ±6 V
Single supply 12 V
Supply Current PD1 = 0, PD0 = 0 29 33.2 37 mA
PD1 = 0, PD0 = 1 20 22.9 25.5 mA
PD1 = 1, PD0 = 0 12 13.3 14.5 mA
PD1 = 1, PD0 = 1 0.7 1.1 mA
Power Supply Rejection Measured differentially −94 −74 dB
POWER-DOWN PINS
PD1, PD0 VIL Referenced to GND 0.8 V
PD1, PD0 VIH Referenced to GND 2 V
PD1, PD0 Bias Current PD1, PD0 = 0 V 15 30 μA
PD1, PD0 = 3 V 6 17 μA
Enable Time PD1, PD0 = (1, 1) − (0, 0) 60 μs
Disable Time PD1, PD0 = (0, 0) − (1, 1) 600 μs
AD8398A
Rev. D | Page 4 of 12
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Power Supplies (VCC − VEE) 13.2 V
Power Dissipation (TJ MAX − TA)/θJA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the AD8398A is limited
by its junction temperature (TJ) on the die. The maximum safe
TJ of plastic encapsulated devices, as determined by the glass
transition temperature of the plastic, is 150°C. Temporarily
exceeding this limit may cause a shift in the parametric
performance due to a change in the stresses exerted on the
die by the package. Exceeding this limit for an extended period
can result in device failure.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 16-lead LFCSP_WQ
on a 4-layer board with six vias connecting the exposed pad to
the GND plane layer.
AMBIENT TEMPERATURE (°C)
MAXIMUM POWER DISSIPATION (W)
0
5
07760-003
4
3
2
1
T
J
= 150°C
6
–40 –30 –20 –10 0 10 20 30 40 50 60 8070
THERMAL RESISTANCE
θJA is specified with the device soldered on a JEDEC circuit
board and the thermal pad connected to the GND plane layer
using six vias.
Table 3. Thermal Resistance
Package Type θJA Unit
16-Lead LFCSP_WQ 35.6 °C/W
Figure 3. Maximum Safe Power Dissipation vs. Ambient Temperature,
4-Layer JEDEC Board with Six Thermal Vias
ESD CAUTION
AD8398A
Rev. D | Page 5 of 12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC
−IN A
+IN A
GND
NC
NC
V
EE
PD0
12
11
10
1
3
4
NC
−IN B
+IN B
9PD1
2
6
5
7
8
16 OUT A
15 NC
14 V
CC
13 OUT B
TOP VIEW
(Not to Scale)
AD8398A
NOTES
1. NC = NO CONNEC
T
2. EXPOSED PADDLE (EPAD) IS
FLOATING, NOT ELECTRICALLY
CONNECTED INTERNALLY.
07760-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 5, 6, 12, 15 NC No Connect.
2 −IN A Amplifier A Inverting Input.
3 +IN A Amplifier A Noninverting Input.
4 GND Ground.
7 VEE Negative Power Supply Input.
8 PD0 Power Mode Control.
9 PD1 Power Mode Control.
10 +IN B Amplifier B Noninverting Input.
11 −IN B Amplifier B Inverting Input.
13 OUT B Amplifier B Output.
14 VCC Positive Power Supply Input.
16 OUT A Amplifier A Output.
EPAD Exposed Paddle (EPAD) The exposed paddle is electrically isolated.
AD8398A
Rev. D | Page 6 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
VCC = 6 V, VEE = −6 V, unless otherwise stated.
07760-017
CLOSED-LOOP GAIN (dB)
0.1 1000100101
FREQUENCY (MHz)
–12
–9
–6
–3
0
3
6
9
12
15
18
21
DIFFERENTIAL
COMMON-MODE
PD1 = 0, PD0 = 0
PD1 = 0, PD0 = 1
PD1 = 1, PD0 = 0
Figure 5. Small Signal Differential and Common-Mode Frequency Response;
AV DIFF = 5 (See the Application Circuit in Figure 8)
07760-018
CLOSED-LOOP GAIN (dB)
0.1 1000100101
FREQUENCY (MHz)
–21
–18
–15
–12
–9
–6
–3
0
3
6
9
12
15
18
DIFFERENTIAL
COMMON-MODE
PD1 = 0, PD0 = 0
PD1 = 0, PD0 = 1
PD1 = 1, PD0 = 0
Figure 6. Small Signal Differential and Common-Mode Frequency Response
(See the Application Circuit in Figure 9)
07760-019
CLOSED-LOOP GAIN (dB)
0.1 1000100101
FREQUENCY (MHz)
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
DIFFERENTIAL
COMMON-MODE
PD1 = 0, PD0 = 0
PD1 = 0, PD0 = 1
PD1 = 1, PD0 = 0
Figure 7. Small Signal Differential and Common-Mode Frequency Response
(See the Application Circuit in Figure 10)
V
MID
*
AD8398A
AD8398A
1/2
1/2
*V
MID =
V
CC +
V
EE
2
07760-014
R
LOAD, DIFF
= 20Ω
Figure 8. Typical Differential Application Circuit
RLOAD, DIFF = 20 Ω
V
MID
*
AD8398A
AD8398A
1/2
1/2
R
LOAD, DIFF
= 20Ω
*V
MID =
V
CC +
V
EE
2
07760-015
Figure 9. Typical Differential Application Circuit with Positive Feedback
RLOAD, DIFF = 20 Ω
VMID*
TIP
RING
AD8398A
AD8398A
1/2
1/2
*V
MID = VCC + VEE
2
07760-016
Figure 10. Typical VDSL2 Application Circuit
AD8398A
Rev. D | Page 7 of 12
400
500
600
700
800
900
1000
10 12 14 16 18 20
07760-005
OUTPUT POWER (dBm)
INTERNAL POWER DISSIPATION (mW)
VDSL2 PROFILE 17a
PD1 = 0, PD0 = 0 VDSL2 PROFILE 8b
PD1 = 0, PD0 = 1
Figure 11. Internal Power Dissipation vs. Output Power
1
10
100
1000
0.01 0.1 1 10 100
07760-007
FREQUENCY (MHz)
VOLTAGE NOISE (nV/√Hz)
Figure 12. Differential Output Voltage Noise vs. Frequency in a
Typical VDSL2 Application
AD8398A
Rev. D | Page 8 of 12
APPLICATIONS INFORMATION
POWER CONTROL MODES OF OPERATION
The AD8398A features four power modes: full power, medium
power, low power, and complete power-down. Two CMOS-
compatible logic pins (PD0 and PD1) select the power mode.
The power modes and associated logic states are listed in Table 5.
Table 5. Power Modes
PD1 PD0 Power Mode Total Supply Current (mA)
0 0 Full power 33.2
0 1 Medium power 22.9
1 0 Low power 13.3
1 1 Power-down 0.7
EXPOSED THERMAL PAD CONNECTIONS
To ensure adequate heat transfer away from the die, connect
the exposed thermal pad to a solid plane layer with low thermal
resistance. To maximize the operating life of the AD8398A, the
thermal design of the system should be kept below the junction
temperature of 125°C.
Although it is electrically isolated, the thermal pad typically
connects to the ground plane layer.
POWER SUPPLY BYPASSING
The AD8398A typically operates on ±6 V or +12 V supplies.
Power the AD8398A circuit with a well-regulated, properly
decoupled power supply. To minimize supply voltage ripple
and power dissipation, use high quality capacitors with low
equivalent series resistance (ESR), such as multilayer ceramic
capacitors (MLCCs). Place a decoupling 0.1 μF MLCC no
more than ⅛ inch away from each of the power supply pins.
In addition, a 10 μF tantalum capacitor is recommended to
provide good decoupling for lower frequency signals and to
supply current for fast, large signal changes at the AD8398A
outputs. Lay out bypass capacitors to keep return currents away
from the inputs of the amplifiers. This layout minimizes any
voltage drops that can develop due to ground currents flowing
through the ground plane.
BOARD LAYOUT
As is the case with all high speed applications, careful attention
to printed circuit board (PCB) layout details prevents associated
board parasitics from becoming problematic. Proper RF design
technique is mandatory.
The PCB has a ground plane covering all unused portions of the
component side of the board to provide a low impedance return
path. Removing the ground plane on all layers from the area
near the input and output pins of the AD8398A reduces stray
capacitance.
Signal lines connecting the feedback and gain resistors should
be as short as possible to minimize the inductance and stray
capacitance associated with these traces. Place termination resistors
and loads as close as possible to their respective inputs and outputs.
To minimize coupling (crosstalk) through the board, keep input
and output traces as far apart as possible. Wherever there are
complementary signals, provide a symmetrical layout to maximize
balanced performance.
AD8398A
Rev. D | Page 9 of 12
MULTITONE POWER RATIO
The discrete multitone (DMT) signal used in xDSL systems
carries data in discrete tones or bins that appear in the frequency
domain in evenly spaced 4.3125 kHz intervals. In applications
using this type of waveform, multitone power ratio (MTPR) is
a commonly used measure of linearity. Generally, designers are
concerned with two types of MTPR: in band and out of band.
In-band MTPR is defined as the measured difference from the
peak of one tone that is loaded with data to the peak of an adjacent
tone that is intentionally left empty. Out-of-band MTPR is
defined as the spurious emissions that occur in the receive bands.
Transmit band power and receive band MTPR are shown in
Figure 13, Figure 14, and Figure 15 for Profile 17a, Profile 8b,
and ADSL2+, respectively.
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
07760-010
FREQUENCY (MHz)
OUTPUT POWER (dB)
042861210 1614 2018
Figure 13. MTPR of a Typical VDSL2 Profile 17a DMT Test Signal,
VS = ±6 V, Output Power = 14.5 dBm
07760-020
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
012345678910
OUTPUT POWER (dBm/Hz)
FREQUENCY (MHz)
Figure 14. MTPR of a Typical VDSL2 Profile 8b DMT Test Signal,
VS = ±6 V, Output Power = 20.4 dBm
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
07760-012
FREQUENCY (MHz)
OUTPUT POWER (dB)
0 0.5 1.0 1.5 2.0 2.5 3.0
Figure 15. MTPR of a Typical ADSL2+ DMT Test Signal,
VS = ±6 V, Output Power = 20.4 dBm
LIGHTNING AND AC POWER FAULT
DSL line drivers are transformer-coupled to the twisted pair
telephone line. In this environment, the AD8398A may be
subject to large line transients resulting from events such as
lightning strikes or downed power lines. Additional circuitry
is required to protect the AD8398A from possible damage due
to these events.
AD8398A
Rev. D | Page 10 of 12
OUTLINE DIMENSIONS
101408-A
1
0.65
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
EXPOSED
PAD
PIN 1
INDICATOR
2.40
2.35 S Q
2.30
4.10
4.00 SQ
3.90
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70 0.05 MA X
0.02 NOM
0.20 RE F
0.20 M IN
COPLANARITY
0.08
PIN 1
INDI
C
ATOR
0.35
0.30
0.25
FOR PRO PE R CONNECT ION OF
THE EX P O SE D PAD, REF E R TO
THE PIN CONFI GURATI ON AND
FUNCT ION DESCRIP TIONS
SECTION OF THIS DATA SHEET .
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD
Figure 16. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD8398AACPZ-R2 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-20
AD8398AACPZ-R7 −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-20
AD8398AACPZ-RL −40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-16-20
1 Z = RoHS Compliant Part.
AD8398A
Rev. D | Page 11 of 12
NOTES
AD8398A
Rev. D | Page 12 of 12
NOTES
©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07760-0-9/10(D)
