APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs Product Features Frequency Table * FS2 0 0 0 0 1 1 1 1 Supports Power PC CPU's * Supports simultaneous PCI and Fast PCI Buses. * Uses external buffer to reduce EMI and Jitter * PCI synchronous clock * Fast PCI synchronous clock * Separated 3.3 volt power supplies for reduced Jitter * <500 pS skew between CPU and PCI clocks * Programmable features: FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU 90 94.5(90+5%) 66.6* 70(66+5%)* 100.0(99.6)* 105.0** 120.0(119.9) 133.0** PCI 30.0 31.5 33.3* 35** 33.3* 35.0** 30.0 33.3** PCIF 60.0 63 66.6* 70** 66.6* 69.9** 60.0 66.6** * Indicates 0.5% down spread spectrum capable ** See Test Mode table for functional definition when SSON is low. - Frequency selection - Margin testing frequency increases - Output enable for board level testing - CPU to PCI clock offset selection * Independent VDD supplies for all output clocks * 28 pin SOP 209 mil package * Spread Spectrum Technology for EMI reduction * Internal Crystal Load Capacitors for 20pF parallel (TEST MODE FUNCTIONALITY NOT GUARANTEED OVER FULL TEMPERATURE AND VOLTAGE) resonant crystal support. VDD REF 14.318 XIN REF VDDR XIN XOUT VSS XOUT VDD FS0 VDDCPU PLL1 CPU FS1 FS2 VDD VDDPF OE PCIF FS(0:2) VSS NC SSON VSS VDDP PCI SSON OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SG500 Pin Configuration Block Diagram 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDDR REF VSS VDDC CPU VSS VDDP PCI VSS VDDPF PCIF VDDPF 48M VSS VDDF PLL2 48MHz Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com 28 pin SSOP Document#: 38-07015 Rev. ** 7/12/1998 Page 1 of 9 APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs Pin Description Pin Number Pin Name PWR I/O 2 XIN VDD I 3 XOUT VDD O 18 PCIF VDDP O 21 PCI VDDP O 17 VDDF - PWR 19 VDDPF - PWR 22 VDDP - PWR 24 CPU VDDC O 13 SSON VDD I PU 16 48M VDDF O 14 OE VDD I 27 REF VDD O 6,7,8 FS(0:2) VDDPU I 4,10,12,15,20,23,26 1,5,9 25 28 VSS VDD VDDC VDDR - PWR PWR PWR PWR Description These pins form an on-chip reference oscillator when connected to terminals o an external parallel resonant crystal (nominally 14.318 MHz). XIN may also serve as input for an externally generated reference signal. If the external input is used, Pin 3 is left unconnected. 66.6 Mhz FAST PCI clock rising edge synchronized to the CPU Clock 33.3 MHz PCI clock rising edge synchronized to the CPU clock. Power for 48 Mhz fixed clock buffer Power for Fast PCI (66Mhz) clock buffer and PCIF (66 Mhz) clock buffer Power for PCI (33 Mhz) clock buffer and PCIF ( 66 Mhz) clock buffer CPU clock output. See table on page 1 for frequencies. Spread Spectrum clock modulation pin. Enables Spread Spectrum EMI reduction when at logic low (0) level. Has an internal pull-up resistor. This pin is a fixed frequency 48 Mhz clock output. Output enable. When at logic level low causes all clock outputs to be in a Tri-State mode. Has internal pull-up resistor. This pin is a buffered output copy of the crystal reference frequency. Frequency selection input pins. See table on page 1 for functionality. Contain internal pull-up resistors. Ground pins for the chip. Power supply pins for analog circuit and core logic. Power supply for CPU clock output buffer. Power supply for reference clock output buffer. A bypass capacitor (0.1F) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance's of the traces. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07015 Rev. ** 7/12/1998 Page 2 of 9 APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs Spread Spectrum Clock Generation (SSCG) Spread Spectrum is a modulation technique applied here for maximum efficiency in minimizing Electro-Magnetic Interference radiation generated from repetitive digital signals mainly clocks. A clock accumulates EM energy at the center frequency it is generating. Spread Spectrum distributes this energy over a small frequency bandwidth therefore spreading the same amount of energy over a spectrum. This technique is achieved by modulating the clock down from its resting frequency by a certain percentage (which also determines the energy distribution bandwidth). In this product, the modulation is 1.0% down from the resting frequency. Down Spread Amplitude (dB) Without Spectrum Spread With Spectrum Spread Modular Center Frequency (MHz) Frequency Test Mode Control Table SSON 0 0 0 0 0 0 0 0 FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 CPU 90.0 94.5 66.6 Tri State 100SS T2* 120 XIN/2 PCI 30.0 31.5 33.3 Tri State 33.3 SS T2* 30 XIN/6 PCIF 60.0 63 66.6 Tri State 66.6 SS T2* 60 XIN/3 48M 48 48 48 Tri State 49 T2* 48 XIN REF 14.318 14.318 140318 Tri State 14.318 T2* 14.318 XIN Note: (All frequencies are in Mhz, XIN defines the clock applied to the XIN pin for testing purposes, and SS= Spread Spectrum_. T2 is a device test mode and is not intended for customers. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07015 Rev. ** 7/12/1998 Page 3 of 9 APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs Maximum Ratings Voltage Relative to VSS: -0.3V Voltage Relative to VDD: 0.3V Storage Temperature: Operating Temperature: This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS<(Vin or Vout)<VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). -65C to + 150C 0C to +70C Maximum Power Supply: 7V Electrical Characteristics Characteristics Input Low Voltage Input High Voltage Input Low Current Input High Current Tri-State leakage current Dynamic Supply Current Static Supply Current Short Circuit Current Symbol VIL VIH IIL IIH Ioz Idd Issd ISC Min 2.0 Typ - 25 - Max 0.8 -66 5 10 TBD TBD - Units Vdc Vdc A A A mA mA mA Conditions - CPU = 100 Mhz OE= 0 (logic low) 1output at a time-30 seconds Switching Characteristics Characteristics Symbol Min Typ Max Units Conditions Output Duty Cycle 45 50 55 % Measured at 1.5V Skew (CPU to CPU) TSKEW1 pS 30 pF Load Measured at 1.5 pF 250 Skew ( CPU to PCI or PCIF) TSKEW1 pS 30 pF Load Measured at 1.5 pF 375 Skew (PCI or PCIF to PCI) TSKEW2 pS 30 pF Load Measured at 1.5 pF 250 pS Period Adjacent Cycles PA 250 Jitter Spectrum Long Term pS Measured over 10 seconds PL 500 VDD = VDDC =CVDDP = VDDPF = VDDF = VDDR = 3.15-3.45V, TA = 0c TO +70C Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07015 Rev. ** 7/12/1998 Page 4 of 9 APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs TB4L1 BUFFER CHARACTERISTICS FOR CPU, PCI, PCIF, REF and 48M Characteristics Symbol Min Typ Max Units Conditions Pull-Up Current Min IOHmin -33 mA Vout = 1.0 V Pull-Up Current Max IOHmax -33 mA Vout = 3.135 V Pull-Down Current Min IOLmin 30 mA Vout = 1.95 V Pull-Down Current Max IOLmax 38 mA Vout = .4 V Rise/Fall Time Min TRFmin 0.5 nS 15 pF Load between 0.4V and 2.4V Rise/Fall Time Max TRFmax 2.0 nS 30 pF Load between 0.4V and 2.4V VDD = VDDC =CVDDP = VDDPF = VDDF = VDDR = 3.15-3.45V, TA = 0c TO +70C Crystal and Reference Oscillator Parameters Characteristics Frequency Tolerance Mode Pin Capacitance DC Bias Voltage Start up time Load Capacitance Effective Series Resistance (ESR) Power Dissipation Shunt Capacitance Symbol Fo TC TS TA OM CP Min 12.0 - Typ 14.31818 36 Max 16.00 +/-100 +/-100 5 - VBias Ts CL R1 DL CO Units MHz PPM PPM PPM 0.3Vdd - Vdd/2 20 - 0.7Vdd 30 40 V S pF Ohms - - 0.10 8 mW pF pF Conditions Calibration note 1 Stability (Ta-10 to +60C) Note1 Aging ( First year@ 25C) note 1 Parallel Resonant Capacitance of XIN and XOUT pins to ground ( Each) The crystals rated load note 1 Note 1 Crystals internal package capacitance ( total) For maximum accuracy, the total circuit loading capacitance should be equal to CL. This loading capacitance is the effective capacitance across the crystal pins and includes the device pin capacitance (CP) in parallel with any circuit traces, the clock generator and any onboard discrete load capacitors. Budgeting Calculations: Typical trace capacitance, ( <half inch) is 4 pF, Load to the crystal is therefore = 2.0 pF Clock generator internal pin capacitance of 36 pF, load to the crystal is therefore = 18.0 pF The total parasitic capacitance would therefore be = 20.0 pF Note 1. It is recommended but not mandatory that a crystal meets these specifications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07015 Rev. ** 7/12/1998 Page 5 of 9 APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs PCB Layout Suggestion VCC1 C1 FB1 + C9 C2 6.6 to 22F C3 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 C8 Via to VDD Island Via to GND Plane Via to VCC Plane C7 C6 C5 FB2 VCC2 C4 + C10 6.8 to 22F This is only a layout recommendation for best performance and lower EMI. The designer may choose a different approach but C3, C4, C35, C36, C37, C38, C39 and C40 (all are 1.0f) should always be used and placed as close as possible to their VDD pins. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07015 Rev. ** 7/12/1998 Page 6 of 9 APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs Package Drawing and Dimensions 28 Pin SSOP Outline Dimensions C INCHES L H E D a A2 A SYMBOL MILLIMETERS MIN NOM MAX MIN NOM MAX A 0.068 0.073 0.078 1.73 1.86 1.99 A1 0.002 0.005 0.008 0.05 0.13 0.21 A2 0.066 0.068 0.070 1.68 1.73 1.78 B 0.010 0.012 0.015 0.25 0.30 0.38 C 0.005 0.006 0.009 0.13 0.15 0.22 D 0.397 0.402 0.407 10.07 10.20 10.33 E 0.205 0.209 0.212 5.20 5.30 5.38 A1 e e B 0.0256 BSC 0.65 BSC H 0.301 0.307 0.311 7.65 7.80 7.90 a 0 4 8 0 4 8 L 0.022 0.030 0.037 0.55 0.75 0.95 Ordering Information Part Number Package Type SG500CYB 28 PIN SSOP Note: Production Flow Commercial, 0C to +70C The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress SG500CYB Date Code, Lot # SG500CYB Flow B = Commercial, 0C to + 70C Package Y = SSOP Revision Device Number Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07015 Rev. ** 7/12/1998 Page 7 of 9 APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs Notice Cypress Semiconductor Corporation reserves the right to change or modify the information contained in this datasheet, without notice. Cypress Semiconductor Corporation does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress Semiconductor Corporation does not convey any license under its patent rights nor the rights of others. Cypress Semiconductor Corporation does not authorize its products for use as critical components in life-support systems or critical medical instruments, where a malfunction or failure may reasonably be expected to result in significant injury to the user. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07015 Rev. ** 7/12/1998 Page 8 of 9 APPROVED PRODUCT SG500 Low Jitter Spectrum Clock Generator for Power PC Designs Document Title: SG500 Low Jitter Spectrum Clock Generator for Power PC Designs Document Number: 38-07015 Rev. ** ECN No. 106943 Issue Date 06/29/01 Orig. of Change IKA Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Description of Change Convert from IMI to Cypress Document#: 38-07015 Rev. ** 7/12/1998 Page 9 of 9